199 files changed, 3 insertions, 208848 deletions

diff --git a/c/src/aclocal/check-networking.m4 b/c/src/aclocal/check-networking.m4
index 69265ac478..250d669705 100644
--- a/c/src/aclocal/check-networking.m4
+++ b/c/src/aclocal/check-networking.m4
@@ -8,7 +8,7 @@ AC_CACHE_CHECK([whether BSP supports networking],
   [dnl
     case "$RTEMS_CPU" in
     # do not have address space to hold BSD TCP/IP stack
-    avr*|m32c*)
+    m32c*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
     *)
diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4
index 5f10bda188..9202495154 100644
--- a/c/src/aclocal/rtems-cpu-subdirs.m4
+++ b/c/src/aclocal/rtems-cpu-subdirs.m4
@@ -10,7 +10,6 @@ AC_DEFUN([RTEMS_CPU_SUBDIRS],
 [
 ## EDIT: If adding a new cpu to RTEMS, add it to the case block below.
 case $RTEMS_CPU in
-_RTEMS_CPU_SUBDIR([arm],[$1]);;
 _RTEMS_CPU_SUBDIR([bfin],[$1]);;
 _RTEMS_CPU_SUBDIR([epiphany],[$1]);;
 _RTEMS_CPU_SUBDIR([avr],[$1]);;
diff --git a/c/src/lib/libbsp/avr/Makefile.am b/c/src/lib/libbsp/avr/Makefile.am
deleted file mode 100644
index f504c03a19..0000000000
--- a/c/src/lib/libbsp/avr/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-## Descend into the @RTEMS_BSP_FAMILY@ directory
-SUBDIRS = @RTEMS_BSP_FAMILY@
-
-EXTRA_DIST =
-
-include $(top_srcdir)/../../../automake/subdirs.am
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libbsp/avr/acinclude.m4 b/c/src/lib/libbsp/avr/acinclude.m4
deleted file mode 100644
index 296a6f7882..0000000000
--- a/c/src/lib/libbsp/avr/acinclude.m4
+++ /dev/null
@@ -1,8 +0,0 @@
-# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
-AC_DEFUN([RTEMS_CHECK_BSPDIR],
-[
-  case "$1" in
-  *)
-    AC_MSG_ERROR([Invalid BSP]);;
-  esac
-])
diff --git a/cpukit/aclocal/check-networking.m4 b/cpukit/aclocal/check-networking.m4
index 50982f3869..e15cf05aca 100644
--- a/cpukit/aclocal/check-networking.m4
+++ b/cpukit/aclocal/check-networking.m4
@@ -9,7 +9,7 @@ AC_CACHE_CHECK([whether CPU supports networking],
   [dnl
     case "$host" in
     # do not have address space to hold BSD TCP/IP stack
-    avr*|m32c*)
+    m32c*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
     *-*-rtems*)
diff --git a/cpukit/configure.ac b/cpukit/configure.ac
index c5bbee8511..3ec966ff04 100644
--- a/cpukit/configure.ac
+++ b/cpukit/configure.ac
@@ -452,7 +452,6 @@ score/Makefile
 score/cpu/Makefile
 score/cpu/arm/Makefile
 score/cpu/bfin/Makefile
-score/cpu/avr/Makefile
 score/cpu/epiphany/Makefile
 score/cpu/i386/Makefile
 score/cpu/lm32/Makefile
diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c
index 74d0bbc6b4..4c58720e2a 100644
--- a/cpukit/librpc/src/xdr/xdr_float.c
+++ b/cpukit/librpc/src/xdr/xdr_float.c
@@ -73,7 +73,6 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
     defined(__sparc__) || \
     defined(__ppc__) || defined(__PPC__) || \
     defined(__sh__) || \
-    defined(__AVR__) || \
     defined(__BFIN__) || \
     defined(__m32c__) || \
     defined(__v850)
diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index a973a8265d..1f57984105 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -2,7 +2,6 @@ SUBDIRS = @RTEMS_CPU@
 
 DIST_SUBDIRS =
 DIST_SUBDIRS += arm
-DIST_SUBDIRS += avr
 DIST_SUBDIRS += bfin
 DIST_SUBDIRS += epiphany
 DIST_SUBDIRS += i386
diff --git a/cpukit/score/cpu/avr/Makefile.am b/cpukit/score/cpu/avr/Makefile.am
deleted file mode 100644
index 10ab19b195..0000000000
--- a/cpukit/score/cpu/avr/Makefile.am
+++ /dev/null
@@ -1,170 +0,0 @@
-include $(top_srcdir)/automake/compile.am
-
-include_rtemsdir = $(includedir)/rtems
-include_rtems_HEADERS = rtems/asm.h
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = rtems/score/cpu.h
-include_rtems_score_HEADERS += rtems/score/avr.h
-include_rtems_score_HEADERS += rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += rtems/score/types.h
-include_rtems_score_HEADERS += rtems/score/cpuatomic.h
-
-include_rtems_avrdir = $(includedir)/avr
-include_rtems_avr_HEADERS = avr/boot.h
-include_rtems_avr_HEADERS += avr/common.h
-include_rtems_avr_HEADERS += avr/crc16.h
-include_rtems_avr_HEADERS += avr/delay.h
-include_rtems_avr_HEADERS += avr/eeprom.h
-include_rtems_avr_HEADERS += avr/fuse.h
-include_rtems_avr_HEADERS += avr/interrupt.h
-include_rtems_avr_HEADERS += avr/io1200.h
-include_rtems_avr_HEADERS += avr/io2313.h
-include_rtems_avr_HEADERS += avr/io2323.h
-include_rtems_avr_HEADERS += avr/io2333.h
-include_rtems_avr_HEADERS += avr/io2343.h
-include_rtems_avr_HEADERS += avr/io43u32x.h
-include_rtems_avr_HEADERS += avr/io43u35x.h
-include_rtems_avr_HEADERS += avr/io4414.h
-include_rtems_avr_HEADERS += avr/io4433.h
-include_rtems_avr_HEADERS += avr/io4434.h
-include_rtems_avr_HEADERS += avr/io76c711.h
-include_rtems_avr_HEADERS += avr/io8515.h
-include_rtems_avr_HEADERS += avr/io8534.h
-include_rtems_avr_HEADERS += avr/io8535.h
-include_rtems_avr_HEADERS += avr/io86r401.h
-include_rtems_avr_HEADERS += avr/io90pwm1.h
-include_rtems_avr_HEADERS += avr/io90pwm216.h
-include_rtems_avr_HEADERS += avr/io90pwm2b.h
-include_rtems_avr_HEADERS += avr/io90pwm316.h
-include_rtems_avr_HEADERS += avr/io90pwm3b.h
-include_rtems_avr_HEADERS += avr/io90pwm81.h
-include_rtems_avr_HEADERS += avr/io90pwmx.h
-include_rtems_avr_HEADERS += avr/io90scr100.h
-include_rtems_avr_HEADERS += avr/ioa6289.h
-include_rtems_avr_HEADERS += avr/ioat94k.h
-include_rtems_avr_HEADERS += avr/iocan128.h
-include_rtems_avr_HEADERS += avr/iocan32.h
-include_rtems_avr_HEADERS += avr/iocan64.h
-include_rtems_avr_HEADERS += avr/iocanxx.h
-include_rtems_avr_HEADERS += avr/io.h
-include_rtems_avr_HEADERS += avr/iom103.h
-include_rtems_avr_HEADERS += avr/iom1280.h
-include_rtems_avr_HEADERS += avr/iom1281.h
-include_rtems_avr_HEADERS += avr/iom1284p.h
-include_rtems_avr_HEADERS += avr/iom128.h
-include_rtems_avr_HEADERS += avr/iom128rfa1.h
-include_rtems_avr_HEADERS += avr/iom161.h
-include_rtems_avr_HEADERS += avr/iom162.h
-include_rtems_avr_HEADERS += avr/iom163.h
-include_rtems_avr_HEADERS += avr/iom164.h
-include_rtems_avr_HEADERS += avr/iom165.h
-include_rtems_avr_HEADERS += avr/iom165p.h
-include_rtems_avr_HEADERS += avr/iom168.h
-include_rtems_avr_HEADERS += avr/iom168p.h
-include_rtems_avr_HEADERS += avr/iom169.h
-include_rtems_avr_HEADERS += avr/iom169p.h
-include_rtems_avr_HEADERS += avr/iom16.h
-include_rtems_avr_HEADERS += avr/iom16hva.h
-include_rtems_avr_HEADERS += avr/iom16m1.h
-include_rtems_avr_HEADERS += avr/iom16u4.h
-include_rtems_avr_HEADERS += avr/iom2560.h
-include_rtems_avr_HEADERS += avr/iom2561.h
-include_rtems_avr_HEADERS += avr/iom323.h
-include_rtems_avr_HEADERS += avr/iom324.h
-include_rtems_avr_HEADERS += avr/iom3250.h
-include_rtems_avr_HEADERS += avr/iom325.h
-include_rtems_avr_HEADERS += avr/iom328p.h
-include_rtems_avr_HEADERS += avr/iom3290.h
-include_rtems_avr_HEADERS += avr/iom329.h
-include_rtems_avr_HEADERS += avr/iom32c1.h
-include_rtems_avr_HEADERS += avr/iom32.h
-include_rtems_avr_HEADERS += avr/iom32hvb.h
-include_rtems_avr_HEADERS += avr/iom32m1.h
-include_rtems_avr_HEADERS += avr/iom32u4.h
-include_rtems_avr_HEADERS += avr/iom32u6.h
-include_rtems_avr_HEADERS += avr/iom406.h
-include_rtems_avr_HEADERS += avr/iom48.h
-include_rtems_avr_HEADERS += avr/iom48p.h
-include_rtems_avr_HEADERS += avr/iom640.h
-include_rtems_avr_HEADERS += avr/iom644.h
-include_rtems_avr_HEADERS += avr/iom6450.h
-include_rtems_avr_HEADERS += avr/iom645.h
-include_rtems_avr_HEADERS += avr/iom6490.h
-include_rtems_avr_HEADERS += avr/iom649.h
-include_rtems_avr_HEADERS += avr/iom64c1.h
-include_rtems_avr_HEADERS += avr/iom64.h
-include_rtems_avr_HEADERS += avr/iom64m1.h
-include_rtems_avr_HEADERS += avr/iom8515.h
-include_rtems_avr_HEADERS += avr/iom8535.h
-include_rtems_avr_HEADERS += avr/iom88.h
-include_rtems_avr_HEADERS += avr/iom88p.h
-include_rtems_avr_HEADERS += avr/iom8.h
-include_rtems_avr_HEADERS += avr/iom8hva.h
-include_rtems_avr_HEADERS += avr/iomx8.h
-include_rtems_avr_HEADERS += avr/iomxx0_1.h
-include_rtems_avr_HEADERS += avr/iomxx4.h
-include_rtems_avr_HEADERS += avr/iomxxhva.h
-include_rtems_avr_HEADERS += avr/iotn11.h
-include_rtems_avr_HEADERS += avr/iotn12.h
-include_rtems_avr_HEADERS += avr/iotn13a.h
-include_rtems_avr_HEADERS += avr/iotn13.h
-include_rtems_avr_HEADERS += avr/iotn15.h
-include_rtems_avr_HEADERS += avr/iotn167.h
-include_rtems_avr_HEADERS += avr/iotn22.h
-include_rtems_avr_HEADERS += avr/iotn2313.h
-include_rtems_avr_HEADERS += avr/iotn24.h
-include_rtems_avr_HEADERS += avr/iotn25.h
-include_rtems_avr_HEADERS += avr/iotn261.h
-include_rtems_avr_HEADERS += avr/iotn26.h
-include_rtems_avr_HEADERS += avr/iotn28.h
-include_rtems_avr_HEADERS += avr/iotn43u.h
-include_rtems_avr_HEADERS += avr/iotn44.h
-include_rtems_avr_HEADERS += avr/iotn45.h
-include_rtems_avr_HEADERS += avr/iotn461.h
-include_rtems_avr_HEADERS += avr/iotn48.h
-include_rtems_avr_HEADERS += avr/iotn84.h
-include_rtems_avr_HEADERS += avr/iotn85.h
-include_rtems_avr_HEADERS += avr/iotn861.h
-include_rtems_avr_HEADERS += avr/iotn87.h
-include_rtems_avr_HEADERS += avr/iotn88.h
-include_rtems_avr_HEADERS += avr/iotnx4.h
-include_rtems_avr_HEADERS += avr/iotnx5.h
-include_rtems_avr_HEADERS += avr/iotnx61.h
-include_rtems_avr_HEADERS += avr/iousb1286.h
-include_rtems_avr_HEADERS += avr/iousb1287.h
-include_rtems_avr_HEADERS += avr/iousb162.h
-include_rtems_avr_HEADERS += avr/iousb646.h
-include_rtems_avr_HEADERS += avr/iousb647.h
-include_rtems_avr_HEADERS += avr/iousb82.h
-include_rtems_avr_HEADERS += avr/iousbxx2.h
-include_rtems_avr_HEADERS += avr/iousbxx6_7.h
-include_rtems_avr_HEADERS += avr/iox128a1.h
-include_rtems_avr_HEADERS += avr/iox128a3.h
-include_rtems_avr_HEADERS += avr/iox16a4.h
-include_rtems_avr_HEADERS += avr/iox16d4.h
-include_rtems_avr_HEADERS += avr/iox256a3b.h
-include_rtems_avr_HEADERS += avr/iox256a3.h
-include_rtems_avr_HEADERS += avr/iox32a4.h
-include_rtems_avr_HEADERS += avr/iox32d4.h
-include_rtems_avr_HEADERS += avr/iox64a1.h
-include_rtems_avr_HEADERS += avr/iox64a3.h
-include_rtems_avr_HEADERS += avr/lock.h
-include_rtems_avr_HEADERS += avr/parity.h
-include_rtems_avr_HEADERS += avr/pgmspace.h
-include_rtems_avr_HEADERS += avr/portpins.h
-include_rtems_avr_HEADERS += avr/power.h
-include_rtems_avr_HEADERS += avr/sfr_defs.h
-include_rtems_avr_HEADERS += avr/signal.h
-include_rtems_avr_HEADERS += avr/sleep.h
-include_rtems_avr_HEADERS += avr/version.h
-include_rtems_avr_HEADERS += avr/wdt.h
-
-noinst_LIBRARIES = libscorecpu.a
-libscorecpu_a_SOURCES = cpu.c cpu_asm.S
-libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
-libscorecpu_a_SOURCES += avr-exception-frame-print.c
-libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
-
-include $(srcdir)/preinstall.am
-include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/avr/README b/cpukit/score/cpu/avr/README
deleted file mode 100644
index 20ac7cc023..0000000000
--- a/cpukit/score/cpu/avr/README
+++ /dev/null
@@ -1,5 +0,0 @@
-WARNING
-=======
-
-This is just a stub and not a complete and functional port.
-
diff --git a/cpukit/score/cpu/avr/avr-exception-frame-print.c b/cpukit/score/cpu/avr/avr-exception-frame-print.c
deleted file mode 100644
index 71e7e1c516..0000000000
--- a/cpukit/score/cpu/avr/avr-exception-frame-print.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-  #include "config.h"
-#endif
-
-#include <rtems/score/cpu.h>
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
-{
-  /* TODO */
-}
diff --git a/cpukit/score/cpu/avr/avr/boot.h b/cpukit/score/cpu/avr/avr/boot.h
deleted file mode 100644
index 863143b226..0000000000
--- a/cpukit/score/cpu/avr/avr/boot.h
+++ /dev/null
@@ -1,687 +0,0 @@
-/**
- * @file
- *
- * @brief Bootloader Support Utilities
- *
- *  The macros in this module provide a C language interface to the
- *  bootloader support functionality of certain AVR processors. These
- *  macros are designed to work with all sizes of flash memory.
- *
- *  Global interrupts are not automatically disabled for these macros. It
- *  is left up to the programmer to do this. See the code example below.
- *  Also see the processor datasheet for caveats on having global interrupts
- *  enabled during writing of the Flash.
- *
- *  \note Not all AVR processors provide bootloader support. See your
- *  processor datasheet to see if it provides bootloader support.
- *
- *  From email with Marek: On smaller devices (all except ATmega64/128),
- *  __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
- *  instructions - since the boot loader has a limited size, this could be an
- *  important optimization.
- *
- *  API Usage Example
- *  The following code shows typical usage of the boot API.
- *
- *
- *  #include <inttypes.h>
- *  #include <avr/interrupt.h>
- *  #include <avr/pgmspace.h>
- *
- *  void boot_program_page (uint32_t page, uint8_t *buf)
- *  {
- *      uint16_t i;
- *      uint8_t sreg;
- *
- *      // Disable interrupts.
- *
- *      sreg = SREG;
- *      cli();
- *
- *      eeprom_busy_wait ();
- *
- *      boot_page_erase (page);
- *      boot_spm_busy_wait ();      // Wait until the memory is erased.
- *
- *      for (i=0; i<SPM_PAGESIZE; i+=2)
- *      {
- *          // Set up little-endian word.
- *
- *          uint16_t w = *buf++;
- *          w += (*buf++) << 8;
- *
- *          boot_page_fill (page + i, w);
- *      }
- *
- *      boot_page_write (page);     // Store buffer in flash page.
- *      boot_spm_busy_wait();       // Wait until the memory is written.
- *
- *      // Reenable RWW-section again. We need this if we want to jump back
- *      // to the application after bootloading.
- *
- *      boot_rww_enable ();
- *
- *      // Re-enable interrupts (if they were ever enabled).
- *
- *      SREG = sreg;
- *  }
- */
-
-/*
- *   Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009  Eric B. Weddington
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_BOOT_H_
-#define _AVR_BOOT_H_    1
-
-/**
- *  @defgroup avr_boot Bootloader Support Utilities
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/eeprom.h>
-#include <avr/io.h>
-#include <inttypes.h>
-#include <limits.h>
-
-/* Check for SPM Control Register in processor. */
-#if defined (SPMCSR)
-#  define __SPM_REG    SPMCSR
-#elif defined (SPMCR)
-#  define __SPM_REG    SPMCR
-#else
-#  error AVR processor does not provide bootloader support!
-#endif
-
-
-/* Check for SPM Enable bit. */
-#if defined(SPMEN)
-#  define __SPM_ENABLE  SPMEN
-#elif defined(SELFPRGEN)
-#  define __SPM_ENABLE  SELFPRGEN
-#else
-#  error Cannot find SPM Enable bit definition!
-#endif
-
-/** \ingroup avr_boot
-    \def BOOTLOADER_SECTION
-
-    Used to declare a function or variable to be placed into a
-    new section called .bootloader. This section and its contents
-    can then be relocated to any address (such as the bootloader
-    NRWW area) at link-time. */
-
-#define BOOTLOADER_SECTION    __attribute__ ((section (".bootloader")))
-
-/* Create common bit definitions. */
-#ifdef ASB
-#define __COMMON_ASB    ASB
-#else
-#define __COMMON_ASB    RWWSB
-#endif
-
-#ifdef ASRE
-#define __COMMON_ASRE   ASRE
-#else
-#define __COMMON_ASRE   RWWSRE
-#endif
-
-/* Define the bit positions of the Boot Lock Bits. */
-
-#define BLB12           5
-#define BLB11           4
-#define BLB02           3
-#define BLB01           2
-
-/** \ingroup avr_boot
-    \def boot_spm_interrupt_enable()
-    Enable the SPM interrupt. */
-
-#define boot_spm_interrupt_enable()   (__SPM_REG |= (uint8_t)_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_spm_interrupt_disable()
-    Disable the SPM interrupt. */
-
-#define boot_spm_interrupt_disable()  (__SPM_REG &= (uint8_t)~_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_is_spm_interrupt()
-    Check if the SPM interrupt is enabled. */
-
-#define boot_is_spm_interrupt()       (__SPM_REG & (uint8_t)_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_rww_busy()
-    Check if the RWW section is busy. */
-
-#define boot_rww_busy()          (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
-
-/** \ingroup avr_boot
-    \def boot_spm_busy()
-    Check if the SPM instruction is busy. */
-
-#define boot_spm_busy()               (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
-
-/** \ingroup avr_boot
-    \def boot_spm_busy_wait()
-    Wait while the SPM instruction is busy. */
-
-#define boot_spm_busy_wait()          do{}while(boot_spm_busy())
-
-#define __BOOT_PAGE_ERASE         (_BV(__SPM_ENABLE) | _BV(PGERS))
-#define __BOOT_PAGE_WRITE         (_BV(__SPM_ENABLE) | _BV(PGWRT))
-#define __BOOT_PAGE_FILL          _BV(__SPM_ENABLE)
-#define __BOOT_RWW_ENABLE         (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
-#if defined(BLBSET)
-#define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(BLBSET))
-#elif defined(RFLB)  /* Some devices have RFLB defined instead of BLBSET. */
-#define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(RFLB))
-#endif
-
-#define __boot_page_fill_normal(address, data)   \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %3\n\t"                       \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "z" ((uint16_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0"                                   \
-    );                                           \
-}))
-
-#define __boot_page_fill_alternate(address, data)\
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %3\n\t"                       \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "z" ((uint16_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0"                                   \
-    );                                           \
-}))
-
-#define __boot_page_fill_extended(address, data) \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %4\n\t"                       \
-        "movw r30, %A3\n\t"                      \
-        "sts %1, %C3\n\t"                        \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "r" ((uint32_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0", "r30", "r31"                     \
-    );                                           \
-}))
-
-#define __boot_page_erase_normal(address)        \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_erase_alternate(address)     \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_erase_extended(address)      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw r30, %A3\n\t"                      \
-        "sts  %1, %C3\n\t"                       \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "r" ((uint32_t)(address))              \
-        : "r30", "r31"                           \
-    );                                           \
-}))
-
-#define __boot_page_write_normal(address)        \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_write_alternate(address)     \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_write_extended(address)      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw r30, %A3\n\t"                      \
-        "sts %1, %C3\n\t"                        \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "r" ((uint32_t)(address))              \
-        : "r30", "r31"                           \
-    );                                           \
-}))
-
-#define __boot_rww_enable()                      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
-    );                                           \
-}))
-
-#define __boot_rww_enable_alternate()            \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
-    );                                           \
-}))
-
-/* From the mega16/mega128 data sheets (maybe others):
-
-     Bits by SPM To set the Boot Loader Lock bits, write the desired data to
-     R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
-     after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
-     that may prevent the Application and Boot Loader section from any
-     software update by the MCU.
-
-     If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
-     will be programmed if an SPM instruction is executed within four cycles
-     after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
-     don't care during this operation, but for future compatibility it is
-     recommended to load the Z-pointer with $0001 (same as used for reading the
-     Lock bits). For future compatibility It is also recommended to set bits 7,
-     6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
-     Lock bits the entire Flash can be read during the operation. */
-
-#define __boot_lock_bits_set(lock_bits)                    \
-(__extension__({                                           \
-    uint8_t value = (uint8_t)(~(lock_bits));               \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "ldi r30, 1\n\t"                                   \
-        "ldi r31, 0\n\t"                                   \
-        "mov r0, %2\n\t"                                   \
-        "sts %0, %1\n\t"                                   \
-        "spm\n\t"                                          \
-        :                                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "r" (value)                                      \
-        : "r0", "r30", "r31"                               \
-    );                                                     \
-}))
-
-#define __boot_lock_bits_set_alternate(lock_bits)          \
-(__extension__({                                           \
-    uint8_t value = (uint8_t)(~(lock_bits));               \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "ldi r30, 1\n\t"                                   \
-        "ldi r31, 0\n\t"                                   \
-        "mov r0, %2\n\t"                                   \
-        "sts %0, %1\n\t"                                   \
-        "spm\n\t"                                          \
-        ".word 0xffff\n\t"                                 \
-        "nop\n\t"                                          \
-        :                                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "r" (value)                                      \
-        : "r0", "r30", "r31"                               \
-    );                                                     \
-}))
-
-/*
-   Reading lock and fuse bits:
-
-     Similarly to writing the lock bits above, set BLBSET and SPMEN (or
-     SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
-     LPM instruction.
-
-     Z address:       contents:
-     0x0000           low fuse bits
-     0x0001           lock bits
-     0x0002           extended fuse bits
-     0x0003           high fuse bits
-
-     Sounds confusing, doesn't it?
-
-     Unlike the macros in pgmspace.h, no need to care for non-enhanced
-     cores here as these old cores do not provide SPM support anyway.
- */
-
-/** \ingroup avr_boot
-    \def GET_LOW_FUSE_BITS
-    address to read the low fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_LOW_FUSE_BITS           (0x0000)
-/** \ingroup avr_boot
-    \def GET_LOCK_BITS
-    address to read the lock bits, using boot_lock_fuse_bits_get
- */
-#define GET_LOCK_BITS               (0x0001)
-/** \ingroup avr_boot
-    \def GET_EXTENDED_FUSE_BITS
-    address to read the extended fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_EXTENDED_FUSE_BITS      (0x0002)
-/** \ingroup avr_boot
-    \def GET_HIGH_FUSE_BITS
-    address to read the high fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_HIGH_FUSE_BITS          (0x0003)
-
-/** \ingroup avr_boot
-    \def boot_lock_fuse_bits_get(address)
-
-    Read the lock or fuse bits at \c address.
-
-    Parameter \c address can be any of GET_LOW_FUSE_BITS,
-    GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
-
-    \note The lock and fuse bits returned are the physical values,
-    i.e. a bit returned as 0 means the corresponding fuse or lock bit
-    is programmed.
- */
-#define boot_lock_fuse_bits_get(address)                   \
-(__extension__({                                           \
-    uint8_t __result;                                      \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "sts %1, %2\n\t"                                   \
-        "lpm %0, Z\n\t"                                    \
-        : "=r" (__result)                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "z" ((uint16_t)(address))                        \
-    );                                                     \
-    __result;                                              \
-}))
-
-/** \ingroup avr_boot
-    \def boot_signature_byte_get(address)
-
-    Read the Signature Row byte at \c address.  For some MCU types,
-    this function can also retrieve the factory-stored oscillator
-    calibration bytes.
-
-    Parameter \c address can be 0-0x1f as documented by the datasheet.
-    \note The values are MCU type dependent.
-*/
-
-#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
-
-#define boot_signature_byte_get(addr) \
-(__extension__({                      \
-      uint8_t __result;                         \
-      __asm__ __volatile__                      \
-      (                                         \
-        "sts %1, %2\n\t"                        \
-        "lpm %0, Z" "\n\t"                      \
-        : "=r" (__result)                       \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),       \
-          "r" ((uint8_t)(__BOOT_SIGROW_READ)),  \
-          "z" ((uint16_t)(addr))                \
-      );                                        \
-      __result;                                 \
-}))
-
-/** \ingroup avr_boot
-    \def boot_page_fill(address, data)
-
-    Fill the bootloader temporary page buffer for flash
-    address with data word.
-
-    \note The address is a byte address. The data is a word. The AVR
-    writes data to the buffer a word at a time, but addresses the buffer
-    per byte! So, increment your address by 2 between calls, and send 2
-    data bytes in a word format! The LSB of the data is written to the lower
-    address; the MSB of the data is written to the higher address.*/
-
-/** \ingroup avr_boot
-    \def boot_page_erase(address)
-
-    Erase the flash page that contains address.
-
-    \note address is a byte address in flash, not a word address. */
-
-/** \ingroup avr_boot
-    \def boot_page_write(address)
-
-    Write the bootloader temporary page buffer
-    to flash page that contains address.
-
-    \note address is a byte address in flash, not a word address. */
-
-/** \ingroup avr_boot
-    \def boot_rww_enable()
-
-    Enable the Read-While-Write memory section. */
-
-/** \ingroup avr_boot
-    \def boot_lock_bits_set(lock_bits)
-
-    Set the bootloader lock bits.
-
-    \param lock_bits A mask of which Boot Loader Lock Bits to set.
-
-    \note In this context, a 'set bit' will be written to a zero value.
-    Note also that only BLBxx bits can be programmed by this command.
-
-    For example, to disallow the SPM instruction from writing to the Boot
-    Loader memory section of flash, you would use this macro as such:
-
-    \code
-    boot_lock_bits_set (_BV (BLB11));
-    \endcode
-
-    \note Like any lock bits, the Boot Loader Lock Bits, once set,
-    cannot be cleared again except by a chip erase which will in turn
-    also erase the boot loader itself. */
-
-/* Normal versions of the macros use 16-bit addresses.
-   Extended versions of the macros use 32-bit addresses.
-   Alternate versions of the macros use 16-bit addresses and require special
-   instruction sequences after LPM.
-
-   FLASHEND is defined in the ioXXXX.h file.
-   USHRT_MAX is defined in <limits.h>. */
-
-#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
-    || defined(__AVR_ATmega323__)
-
-/* Alternate: ATmega161/163/323 and 16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
-#define boot_page_erase(address)      __boot_page_erase_alternate(address)
-#define boot_page_write(address)      __boot_page_write_alternate(address)
-#define boot_rww_enable()             __boot_rww_enable_alternate()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
-
-#elif (FLASHEND > USHRT_MAX)
-
-/* Extended: >16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
-#define boot_page_erase(address)      __boot_page_erase_extended(address)
-#define boot_page_write(address)      __boot_page_write_extended(address)
-#define boot_rww_enable()             __boot_rww_enable()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
-
-#else
-
-/* Normal: 16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
-#define boot_page_erase(address)      __boot_page_erase_normal(address)
-#define boot_page_write(address)      __boot_page_write_normal(address)
-#define boot_rww_enable()             __boot_rww_enable()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
-
-#endif
-
-/** \ingroup avr_boot
-
-    Same as boot_page_fill() except it waits for eeprom and spm operations to
-    complete before filling the page. */
-
-#define boot_page_fill_safe(address, data) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_fill(address, data);              \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_page_erase() except it waits for eeprom and spm operations to
-    complete before erasing the page. */
-
-#define boot_page_erase_safe(address) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_erase (address);                  \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_page_write() except it waits for eeprom and spm operations to
-    complete before writing the page. */
-
-#define boot_page_write_safe(address) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_write (address);                  \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_rww_enable() except waits for eeprom and spm operations to
-    complete before enabling the RWW mameory. */
-
-#define boot_rww_enable_safe() \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_rww_enable();                          \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_lock_bits_set() except waits for eeprom and spm operations to
-    complete before setting the lock bits. */
-
-#define boot_lock_bits_set_safe(lock_bits) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_lock_bits_set (lock_bits);             \
-} while (0)
-
-/**@}*/
-#endif /* _AVR_BOOT_H_ */
diff --git a/cpukit/score/cpu/avr/avr/common.h b/cpukit/score/cpu/avr/avr/common.h
deleted file mode 100644
index 1acfe26889..0000000000
--- a/cpukit/score/cpu/avr/avr/common.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/**
- * @file
- *
- * @brief Common Symbols and Define Undefined Registers
- *
- * This purpose of this header is to define registers that have not been
- * previously defined in the individual device IO header files, and to define
- * other symbols that are common across AVR device families.
- *
- * This file is designed to be included in <avr/io.h> after the individual
- * device IO header files, and after <avr/sfr_defs.h>
- */
-
-/*
- *  Copyright (c) 2007 Eric B. Weddington
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-#ifndef _AVR_COMMON_H
-#define _AVR_COMMON_H
-
-/**
- *  @defgroup Avr_common Common Data
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/sfr_defs.h>
-
-/*------------ Registers Not Previously Defined ------------*/
-
-/*
-These are registers that are not previously defined in the individual
-IO header files, OR they are defined here because they are used in parts of
-avr-libc even if a device is not selected but a general architecture has
-been selected.
-*/
-
-
-/*
-Stack pointer register.
-
-AVR architecture 1 has no RAM, thus no stack pointer.
-
-All other architectures do have a stack pointer.  Some devices have only
-less than 256 bytes of possible RAM locations (128 Bytes of SRAM
-and no option for external RAM), thus SPH is officially "reserved"
-for them.
-*/
-#if __AVR_ARCH__ >= 100
-#  ifndef SPL
-#    define SPL _SFR_MEM8(0x3D)
-#  endif
-#  ifndef SPH
-#    define SPH _SFR_MEM8(0x3E)
-#  endif
-#  ifndef SP
-#    define SP _SFR_MEM16(0x3D)
-#  endif
-#elif __AVR_ARCH__ != 1
-#  ifndef SPL
-#    define SPL _SFR_IO8(0x3D)
-#  endif
-#  if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__)
-#    ifndef SP
-#      define SP  _SFR_IO8(0x3D)
-#    endif
-#  else
-#    ifndef SP
-#      define SP  _SFR_IO16(0x3D)
-#    endif
-#    ifndef SPH
-#      define SPH _SFR_IO8(0x3E)
-#    endif
-#  endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */
-#endif /* __AVR_ARCH__ != 1 */
-
-
-/* Status Register */
-#ifndef SREG
-#  if __AVR_ARCH__ >= 100
-#    define SREG _SFR_MEM8(0x3F)
-#  else
-#    define SREG _SFR_IO8(0x3F)
-#  endif
-#endif
-
-
-/* SREG bit definitions */
-#ifndef SREG_C
-#  define SREG_C  (0)
-#endif
-#ifndef SREG_Z
-#  define SREG_Z  (1)
-#endif
-#ifndef SREG_N
-#  define SREG_N  (2)
-#endif
-#ifndef SREG_V
-#  define SREG_V  (3)
-#endif
-#ifndef SREG_S
-#  define SREG_S  (4)
-#endif
-#ifndef SREG_H
-#  define SREG_H  (5)
-#endif
-#ifndef SREG_T
-#  define SREG_T  (6)
-#endif
-#ifndef SREG_I
-#  define SREG_I  (7)
-#endif
-
-
-#if defined(__COMPILING_AVR_LIBC__)
-
-/* AVR 6 Architecture */
-#  if __AVR_ARCH__ == 6
-#    ifndef EIND
-#      define EIND  _SFR_IO8(0X3C)
-#    endif
-/* XMEGA Architectures */
-#  elif __AVR_ARCH__ >= 100
-#    ifndef EIND
-#      define EIND  _SFR_MEM8(0x3C)
-#    endif
-#  endif
-
-/*
-Only few devices come without EEPROM.  In order to assemble the
-EEPROM library components without defining a specific device, we
-keep the EEPROM-related definitions here.
-*/
-
-/* EEPROM Control Register */
-#  ifndef EECR
-#    define EECR   _SFR_IO8(0x1C)
-#  endif
-
-/* EEPROM Data Register */
-#  ifndef EEDR
-#    define EEDR   _SFR_IO8(0x1D)
-#  endif
-
-/* EEPROM Address Register */
-#  ifndef EEAR
-#    define EEAR   _SFR_IO16(0x1E)
-#  endif
-#  ifndef EEARL
-#    define EEARL  _SFR_IO8(0x1E)
-#  endif
-#  ifndef EEARH
-#    define EEARH  _SFR_IO8(0x1F)
-#  endif
-
-/* EEPROM Control Register bits */
-#  ifndef EERE
-#    define EERE   (0)
-#  endif
-#  ifndef EEWE
-#    define EEWE   (1)
-#  endif
-#  ifndef EEMWE
-#    define EEMWE  (2)
-#  endif
-#  ifndef EERIE
-#    define EERIE  (3)
-#  endif
-
-#endif /* __COMPILING_AVR_LIBC__ */
-
-
-
-/*------------ Common Symbols ------------*/
-
-/*
-Generic definitions for registers that are common across multiple AVR devices
-and families.
-*/
-
-/* Pointer registers definitions */
-#if __AVR_ARCH__ != 1  /* avr1 does not have X and Y pointers */
-#  define XL  r26
-#  define XH  r27
-#  define YL  r28
-#  define YH  r29
-#endif /* #if __AVR_ARCH__ != 1 */
-#define ZL  r30
-#define ZH  r31
-
-
-/* Status Register */
-#if defined(SREG)
-#  define AVR_STATUS_REG   SREG
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STATUS_ADDR  _SFR_MEM_ADDR(SREG)
-#  else
-#    define AVR_STATUS_ADDR  _SFR_IO_ADDR(SREG)
-#  endif
-#endif
-
-/* Stack Pointer (combined) Register */
-#if defined(SP)
-#  define AVR_STACK_POINTER_REG   SP
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_ADDR  _SFR_MEM_ADDR(SP)
-#  else
-#    define AVR_STACK_POINTER_ADDR  _SFR_IO_ADDR(SP)
-#  endif
-#endif
-
-/* Stack Pointer High Register */
-#if defined(SPH)
-#  define _HAVE_AVR_STACK_POINTER_HI 1
-#  define AVR_STACK_POINTER_HI_REG   SPH
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_HI_ADDR  _SFR_MEM_ADDR(SPH)
-#  else
-#    define AVR_STACK_POINTER_HI_ADDR  _SFR_IO_ADDR(SPH)
-#  endif
-#endif
-
-/* Stack Pointer Low Register */
-#if defined(SPL)
-#  define AVR_STACK_POINTER_LO_REG   SPL
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_LO_ADDR  _SFR_MEM_ADDR(SPL)
-#  else
-#    define AVR_STACK_POINTER_LO_ADDR  _SFR_IO_ADDR(SPL)
-#  endif
-#endif
-
-/* RAMPD Register */
-#if defined(RAMPD)
-#  define AVR_RAMPD_REG   RAMPD
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPD_ADDR  _SFR_MEM_ADDR(RAMPD)
-#  else
-#    define AVR_RAMPD_ADDR  _SFR_IO_ADDR(RAMPD)
-#  endif
-#endif
-
-/* RAMPX Register */
-#if defined(RAMPX)
-#  define AVR_RAMPX_REG   RAMPX
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPX_ADDR  _SFR_MEM_ADDR(RAMPX)
-#  else
-#    define AVR_RAMPX_ADDR  _SFR_IO_ADDR(RAMPX)
-#  endif
-#endif
-
-/* RAMPY Register */
-#if defined(RAMPY)
-#  define AVR_RAMPY_REG   RAMPY
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPY_ADDR  _SFR_MEM_ADDR(RAMPY)
-#  else
-#    define AVR_RAMPY_ADDR  _SFR_IO_ADDR(RAMPY)
-#  endif
-#endif
-
-/* RAMPZ Register */
-#if defined(RAMPZ)
-#  define AVR_RAMPZ_REG   RAMPZ
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPZ_ADDR  _SFR_MEM_ADDR(RAMPZ)
-#  else
-#    define AVR_RAMPZ_ADDR  _SFR_IO_ADDR(RAMPZ)
-#  endif
-#endif
-
-/* Extended Indirect Register */
-#if defined(EIND)
-#  define AVR_EXTENDED_INDIRECT_REG   EIND
-#  if __AVR_ARCH__ >= 100
-#    define AVR_EXTENDED_INDIRECT_ADDR  _SFR_MEM_ADDR(EIND)
-#  else
-#    define AVR_EXTENDED_INDIRECT_ADDR  _SFR_IO_ADDR(EIND)
-#  endif
-#endif
-
-/*------------ Workaround to old compilers (4.1.2 and earlier)  ------------*/
-
-#ifndef __AVR_HAVE_MOVW__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_MOVW__ 1
-# endif
-#endif
-
-#ifndef __AVR_HAVE_LPMX__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_LPMX__ 1
-# endif
-#endif
-
-#ifndef __AVR_HAVE_MUL__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_MUL__ 1
-# endif
-#endif
-
-/**@}*/
-#endif /* _AVR_COMMON_H */
diff --git a/cpukit/score/cpu/avr/avr/crc16.h b/cpukit/score/cpu/avr/avr/crc16.h
deleted file mode 100644
index fe6dfd4346..0000000000
--- a/cpukit/score/cpu/avr/avr/crc16.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * @file
- *
- * @brief Moved to <util/crc16.h>
- */
-
-/*
- *  Copyright (c) 2005 Joerg Wunsch
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_CRC16_H_
-#define _AVR_CRC16_H_
-
-/**
- *  @defgroup Avr_crc16 crc16
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#warning "This file has been moved to <util/crc16.h>."
-#include <util/crc16.h>
-
-/**@}*/
-#endif /* _AVR_CRC16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/delay.h b/cpukit/score/cpu/avr/avr/delay.h
deleted file mode 100644
index ad9db108eb..0000000000
--- a/cpukit/score/cpu/avr/avr/delay.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file
- *
- * @brief Moved to <util/delay.h>
- */
-
-/*
- * Copyright (c) 2005 Joerg Wunsch
- * All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_DELAY_H_
-#define _AVR_DELAY_H_
-
-/**
- * @defgroup AvrDelay Delay
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#warning "This file has been moved to <util/delay.h>."
-#include <util/delay.h>
-
-/** @} */
-#endif /* _AVR_DELAY_H_ */
diff --git a/cpukit/score/cpu/avr/avr/eeprom.h b/cpukit/score/cpu/avr/avr/eeprom.h
deleted file mode 100644
index 448248dc37..0000000000
--- a/cpukit/score/cpu/avr/avr/eeprom.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/**
- * @file
- *
- * @brief Data EEPROM Contained in the AVR Microcontrollers
- *
- * This header file declares the interface to some simple library
- * routines suitable for handling the data EEPROM contained in the
- * AVR microcontrollers.  The implementation uses a simple polled
- * mode interface.  Applications that require interrupt-controlled
- * EEPROM access to ensure that no time will be wasted in spinloops
- * will have to deploy their own implementation.
- *
- *  \par Notes:
- *
- *  - In addition to the write functions there is a set of update ones.
- *  This functions read each byte first and skip the burning if the
- *  old value is the same with new.  The scaning direction is from
- *  high address to low, to obtain quick return in common cases.
- *
- *  - All of the read/write functions first make sure the EEPROM is
- *  ready to be accessed.  Since this may cause long delays if a
- *  write operation is still pending, time-critical applications
- *  should first poll the EEPROM e. g. using eeprom_is_ready() before
- *  attempting any actual I/O.  But this functions are not wait until
- *  SELFPRGEN in SPMCSR becomes zero.  Do this manually, if your
- *  softwate contains the Flash burning.
- *
- *  - As these functions modify IO registers, they are known to be
- *  non-reentrant.  If any of these functions are used from both,
- *  standard and interrupt context, the applications must ensure
- *  proper protection (e.g. by disabling interrupts before accessing
- *  them).
- *
- *  - All write functions force erase_and_write programming mode.
- *
- *  - For Xmega the EEPROM start address is 0, like other architectures.
- *  The reading functions add the 0x2000 value to use EEPROM mapping into
- *  data space.
- */
-
-/*
- * Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
- * Copyright (c) 2005, 2006 Bjoern Haase
- * Copyright (c) 2008 Atmel Corporation
- * Copyright (c) 2008 Wouter van Gulik
- * Copyright (c) 2009 Dmitry Xmelkov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_EEPROM_H_
-#define _AVR_EEPROM_H_ 1
-
-#include <avr/io.h>
-
-#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__)
-# warning "Device does not have EEPROM available."
-#else
-
-#ifndef	__DOXYGEN__
-
-#if defined (__AVR_AT94K__)
-# define _EEPROM_SUFFIX _at94k
-#elif defined (__AVR_AT43USB320__)
-# define _EEPROM_SUFFIX _43u320
-#elif defined (__AVR_AT43USB355__)
-# define _EEPROM_SUFFIX _43u355
-#elif defined (__AVR_AT76C711__)
-# define _EEPROM_SUFFIX _76c711
-#elif defined (__AVR_AT86RF401__)
-# define _EEPROM_SUFFIX _86r401
-#elif defined (__AVR_AT90PWM1__)
-# define _EEPROM_SUFFIX _90pwm1
-#elif defined (__AVR_AT90PWM2__)
-# define _EEPROM_SUFFIX _90pwm2
-#elif defined (__AVR_AT90PWM2B__)
-# define _EEPROM_SUFFIX _90pwm2b
-#elif defined (__AVR_AT90PWM3__)
-# define _EEPROM_SUFFIX _90pwm3
-#elif defined (__AVR_AT90PWM3B__)
-# define _EEPROM_SUFFIX _90pwm3b
-#elif defined (__AVR_AT90PWM216__)
-# define _EEPROM_SUFFIX _90pwm216
-#elif defined (__AVR_AT90PWM316__)
-# define _EEPROM_SUFFIX _90pwm316
-#elif defined (__AVR_AT90PWM81__)
-# define _EEPROM_SUFFIX _90pwm81
-#elif defined (__AVR_ATmega16M1__)
-# define _EEPROM_SUFFIX  _m16m1
-#elif defined (__AVR_ATmega8U2__)
-# define _EEPROM_SUFFIX  _m8u2
-#elif defined (__AVR_ATmega16U2__)
-# define _EEPROM_SUFFIX  _m16u2
-#elif defined (__AVR_ATmega16U4__)
-# define _EEPROM_SUFFIX  _m16u4
-#elif defined (__AVR_ATmega32C1__)
-# define _EEPROM_SUFFIX  _m32c1
-#elif defined (__AVR_ATmega32M1__)
-# define _EEPROM_SUFFIX  _m32m1
-#elif defined (__AVR_ATmega32U2__)
-# define _EEPROM_SUFFIX  _m32u2
-#elif defined (__AVR_ATmega32U4__)
-# define _EEPROM_SUFFIX  _m32u4
-#elif defined (__AVR_ATmega32U6__)
-# define _EEPROM_SUFFIX  _m32u6
-#elif defined (__AVR_ATmega64C1__)
-# define _EEPROM_SUFFIX  _m64c1
-#elif defined (__AVR_ATmega64M1__)
-# define _EEPROM_SUFFIX  _m64m1
-#elif defined (__AVR_ATmega128__)
-# define _EEPROM_SUFFIX  _m128
-#elif defined (__AVR_ATmega1280__)
-# define _EEPROM_SUFFIX  _m1280
-#elif defined (__AVR_ATmega1281__)
-# define _EEPROM_SUFFIX  _m1281
-#elif defined (__AVR_ATmega1284P__)
-# define _EEPROM_SUFFIX  _m1284p
-#elif defined (__AVR_ATmega128RFA1__)
-# define _EEPROM_SUFFIX  _m128rfa1
-#elif defined (__AVR_ATmega2560__)
-# define _EEPROM_SUFFIX  _m2560
-#elif defined (__AVR_ATmega2561__)
-# define _EEPROM_SUFFIX  _m2561
-#elif defined (__AVR_AT90CAN32__)
-# define _EEPROM_SUFFIX _can32
-#elif defined (__AVR_AT90CAN64__)
-# define _EEPROM_SUFFIX _can64
-#elif defined (__AVR_AT90CAN128__)
-# define _EEPROM_SUFFIX _can128
-#elif defined (__AVR_AT90USB82__)
-# define _EEPROM_SUFFIX _usb82
-#elif defined (__AVR_AT90USB162__)
-# define _EEPROM_SUFFIX _usb162
-#elif defined (__AVR_AT90USB646__)
-# define _EEPROM_SUFFIX _usb646
-#elif defined (__AVR_AT90USB647__)
-# define _EEPROM_SUFFIX _usb647
-#elif defined (__AVR_AT90USB1286__)
-# define _EEPROM_SUFFIX _usb1286
-#elif defined (__AVR_AT90USB1287__)
-# define _EEPROM_SUFFIX _usb1287
-#elif defined (__AVR_ATmega64__)
-# define _EEPROM_SUFFIX  _m64
-#elif defined (__AVR_ATmega640__)
-# define _EEPROM_SUFFIX  _m640
-#elif defined (__AVR_ATmega644__)
-# define _EEPROM_SUFFIX  _m644
-#elif defined (__AVR_ATmega644A__)
-# define _EEPROM_SUFFIX  _m644a
-#elif defined (__AVR_ATmega644P__)
-# define _EEPROM_SUFFIX  _m644p
-#elif defined (__AVR_ATmega644PA__)
-# define _EEPROM_SUFFIX  _m644pa
-#elif defined (__AVR_ATmega645__)
-# define _EEPROM_SUFFIX  _m645
-#elif defined (__AVR_ATmega645A__)
-# define _EEPROM_SUFFIX  _m645a
-#elif defined (__AVR_ATmega645P__)
-# define _EEPROM_SUFFIX  _m645p
-#elif defined (__AVR_ATmega6450__)
-# define _EEPROM_SUFFIX  _m6450
-#elif defined (__AVR_ATmega6450A__)
-# define _EEPROM_SUFFIX  _m6450a
-#elif defined (__AVR_ATmega6450P__)
-# define _EEPROM_SUFFIX  _m6450p
-#elif defined (__AVR_ATmega649__)
-# define _EEPROM_SUFFIX  _m649
-#elif defined (__AVR_ATmega649A__)
-# define _EEPROM_SUFFIX  _m649a
-#elif defined (__AVR_ATmega649P__)
-# define _EEPROM_SUFFIX  _m649p
-#elif defined (__AVR_ATmega6490__)
-# define _EEPROM_SUFFIX  _m6490
-#elif defined (__AVR_ATmega6490A__)
-# define _EEPROM_SUFFIX  _m6490a
-#elif defined (__AVR_ATmega6490P__)
-# define _EEPROM_SUFFIX  _m6490p
-#elif defined (__AVR_ATmega103__)
-# define _EEPROM_SUFFIX  _m103
-#elif defined (__AVR_ATmega32__)
-# define _EEPROM_SUFFIX  _m32
-#elif defined (__AVR_ATmega323__)
-# define _EEPROM_SUFFIX  _m323
-#elif defined (__AVR_ATmega324A__)
-# define _EEPROM_SUFFIX  _m324a
-#elif defined (__AVR_ATmega324P__)
-# define _EEPROM_SUFFIX  _m324p
-#elif defined (__AVR_ATmega324PA__)
-# define _EEPROM_SUFFIX  _m324pa
-#elif defined (__AVR_ATmega325__)
-# define _EEPROM_SUFFIX  _m325
-#elif defined (__AVR_ATmega325P__)
-# define _EEPROM_SUFFIX  _m325p
-#elif defined (__AVR_ATmega3250__)
-# define _EEPROM_SUFFIX  _m3250
-#elif defined (__AVR_ATmega3250P__)
-# define _EEPROM_SUFFIX  _m3250p
-#elif defined (__AVR_ATmega328__)
-# define _EEPROM_SUFFIX  _m328
-#elif defined (__AVR_ATmega328P__)
-# define _EEPROM_SUFFIX  _m328p
-#elif defined (__AVR_ATmega329__)
-# define _EEPROM_SUFFIX  _m329
-#elif defined (__AVR_ATmega329P__)
-# define _EEPROM_SUFFIX  _m329p
-#elif defined (__AVR_ATmega329PA__)
-# define _EEPROM_SUFFIX  _m329pa
-#elif defined (__AVR_ATmega3290__)
-# define _EEPROM_SUFFIX  _m3290
-#elif defined (__AVR_ATmega3290P__)
-# define _EEPROM_SUFFIX  _m3290p
-#elif defined (__AVR_ATmega32HVB__)
-# define _EEPROM_SUFFIX  _m32hvb
-#elif defined (__AVR_ATmega64HVE__)
-# define _EEPROM_SUFFIX  _m64hve
-#elif defined (__AVR_ATmega406__)
-# define _EEPROM_SUFFIX  _m406
-#elif defined (__AVR_ATmega16__)
-# define _EEPROM_SUFFIX  _m16
-#elif defined (__AVR_ATmega16A__)
-# define _EEPROM_SUFFIX  _m16a
-#elif defined (__AVR_ATmega161__)
-# define _EEPROM_SUFFIX  _m161
-#elif defined (__AVR_ATmega162__)
-# define _EEPROM_SUFFIX  _m162
-#elif defined (__AVR_ATmega163__)
-# define _EEPROM_SUFFIX  _m163
-#elif defined (__AVR_ATmega164__)
-# define _EEPROM_SUFFIX  _m164
-#elif defined (__AVR_ATmega164P__)
-# define _EEPROM_SUFFIX  _m164p
-#elif defined (__AVR_ATmega165__)
-# define _EEPROM_SUFFIX  _m165
-#elif defined (__AVR_ATmega165A__)
-# define _EEPROM_SUFFIX  _m165a
-#elif defined (__AVR_ATmega165P__)
-# define _EEPROM_SUFFIX  _m165p
-#elif defined (__AVR_ATmega168__)
-# define _EEPROM_SUFFIX  _m168
-#elif defined (__AVR_ATmega168A__)
-# define _EEPROM_SUFFIX  _m168a
-#elif defined (__AVR_ATmega168P__)
-# define _EEPROM_SUFFIX  _m168p
-#elif defined (__AVR_ATmega169__)
-# define _EEPROM_SUFFIX  _m169
-#elif defined (__AVR_ATmega169A__)
-# define _EEPROM_SUFFIX  _m169a
-#elif defined (__AVR_ATmega169P__)
-# define _EEPROM_SUFFIX  _m169p
-#elif defined (__AVR_ATmega169PA__)
-# define _EEPROM_SUFFIX  _m169pa
-#elif defined (__AVR_ATmega8HVA__)
-# define _EEPROM_SUFFIX  _m8hva
-#elif defined (__AVR_ATmega16HVA__)
-# define _EEPROM_SUFFIX  _m16hva
-#elif defined (__AVR_ATmega16HVA2__)
-# define _EEPROM_SUFFIX  _m16hva2
-#elif defined (__AVR_ATmega16HVB__)
-# define _EEPROM_SUFFIX  _m16hvb
-#elif defined (__AVR_ATmega8__)
-# define _EEPROM_SUFFIX  _m8
-#elif defined (__AVR_ATmega48__)
-# define _EEPROM_SUFFIX  _m48
-#elif defined (__AVR_ATmega48A__)
-# define _EEPROM_SUFFIX  _m48a
-#elif defined (__AVR_ATmega48P__)
-# define _EEPROM_SUFFIX  _m48p
-#elif defined (__AVR_ATmega88__)
-# define _EEPROM_SUFFIX  _m88
-#elif defined (__AVR_ATmega88A__)
-# define _EEPROM_SUFFIX  _m88a
-#elif defined (__AVR_ATmega88P__)
-# define _EEPROM_SUFFIX  _m88p
-#elif defined (__AVR_ATmega88PA__)
-# define _EEPROM_SUFFIX  _m88pa
-#elif defined (__AVR_ATmega8515__)
-# define _EEPROM_SUFFIX  _m8515
-#elif defined (__AVR_ATmega8535__)
-# define _EEPROM_SUFFIX  _m8535
-#elif defined (__AVR_AT90S8535__)
-# define _EEPROM_SUFFIX  _8535
-#elif defined (__AVR_AT90C8534__)
-# define _EEPROM_SUFFIX  _8534
-#elif defined (__AVR_AT90S8515__)
-# define _EEPROM_SUFFIX  _8515
-#elif defined (__AVR_AT90S4434__)
-# define _EEPROM_SUFFIX  _4434
-#elif defined (__AVR_AT90S4433__)
-# define _EEPROM_SUFFIX  _4433
-#elif defined (__AVR_AT90S4414__)
-# define _EEPROM_SUFFIX  _4414
-#elif defined (__AVR_ATtiny22__)
-# define _EEPROM_SUFFIX _tn22
-#elif defined (__AVR_ATtiny26__)
-# define _EEPROM_SUFFIX _tn26
-#elif defined (__AVR_AT90S2343__)
-# define _EEPROM_SUFFIX  _2343
-#elif defined (__AVR_AT90S2333__)
-# define _EEPROM_SUFFIX  _2333
-#elif defined (__AVR_AT90S2323__)
-# define _EEPROM_SUFFIX  _2323
-#elif defined (__AVR_AT90S2313__)
-# define _EEPROM_SUFFIX  _2313
-#elif defined (__AVR_ATtiny2313__)
-# define _EEPROM_SUFFIX _tn2313
-#elif defined (__AVR_ATtiny2313A__)
-# define _EEPROM_SUFFIX _tn2313a
-#elif defined (__AVR_ATtiny4313__)
-# define _EEPROM_SUFFIX _tn4313
-#elif defined (__AVR_ATtiny13__)
-# define _EEPROM_SUFFIX _tn13
-#elif defined (__AVR_ATtiny13A__)
-# define _EEPROM_SUFFIX _tn13a
-#elif defined (__AVR_ATtiny25__)
-# define _EEPROM_SUFFIX _tn25
-#elif defined (__AVR_ATtiny45__)
-# define _EEPROM_SUFFIX _tn45
-#elif defined (__AVR_ATtiny85__)
-# define _EEPROM_SUFFIX _tn85
-#elif defined (__AVR_ATtiny24__)
-# define _EEPROM_SUFFIX _tn24
-#elif defined (__AVR_ATtiny24A__)
-# define _EEPROM_SUFFIX _tn24a
-#elif defined (__AVR_ATtiny44__)
-# define _EEPROM_SUFFIX _tn44
-#elif defined (__AVR_ATtiny44A__)
-# define _EEPROM_SUFFIX _tn44a
-#elif defined (__AVR_ATtiny84__)
-# define _EEPROM_SUFFIX _tn84
-#elif defined (__AVR_ATtiny261__)
-# define _EEPROM_SUFFIX _tn261
-#elif defined (__AVR_ATtiny261A__)
-# define _EEPROM_SUFFIX _tn261a
-#elif defined (__AVR_ATtiny461__)
-# define _EEPROM_SUFFIX _tn461
-#elif defined (__AVR_ATtiny461A__)
-# define _EEPROM_SUFFIX _tn461a
-#elif defined (__AVR_ATtiny861__)
-# define _EEPROM_SUFFIX _tn861
-#elif defined (__AVR_ATtiny861A__)
-# define _EEPROM_SUFFIX _tn861a
-#elif defined (__AVR_ATtiny43U__)
-# define _EEPROM_SUFFIX _tn43u
-#elif defined (__AVR_ATtiny48__)
-# define _EEPROM_SUFFIX _tn48
-#elif defined (__AVR_ATtiny88__)
-# define _EEPROM_SUFFIX _tn88
-#elif defined (__AVR_ATtiny87__)
-# define _EEPROM_SUFFIX _tn87
-#elif defined (__AVR_ATtiny167__)
-# define _EEPROM_SUFFIX _tn167
-#elif defined (__AVR_AT90SCR100__)
-# define _EEPROM_SUFFIX _90scr100
-#elif defined (__AVR_ATxmega16A4__)
-# define _EEPROM_SUFFIX   _x16a4
-#elif defined (__AVR_ATxmega16D4__)
-# define _EEPROM_SUFFIX   _x16d4
-#elif defined (__AVR_ATxmega32A4__)
-# define _EEPROM_SUFFIX   _x32a4
-#elif defined (__AVR_ATxmega32D4__)
-# define _EEPROM_SUFFIX   _x32d4
-#elif defined (__AVR_ATxmega64A1__)
-# define _EEPROM_SUFFIX   _x64a1
-#elif defined (__AVR_ATxmega64A3__)
-# define _EEPROM_SUFFIX   _x64a3
-#elif defined (__AVR_ATxmega64D3__)
-# define _EEPROM_SUFFIX   _x64d3
-#elif defined (__AVR_ATxmega128A1__)
-# define _EEPROM_SUFFIX   _x128a1
-#elif defined (__AVR_ATxmega128A3__)
-# define _EEPROM_SUFFIX   _x128a3
-#elif defined (__AVR_ATxmega128D3__)
-# define _EEPROM_SUFFIX   _x128d3
-#elif defined (__AVR_ATxmega192A3__)
-# define _EEPROM_SUFFIX   _x192a3
-#elif defined (__AVR_ATxmega192D3__)
-# define _EEPROM_SUFFIX   _x192d3
-#elif defined (__AVR_ATxmega256A3__)
-# define _EEPROM_SUFFIX   _x256a3
-#elif defined (__AVR_ATxmega256A3B__)
-# define _EEPROM_SUFFIX   _x256a3b
-#elif defined (__AVR_ATxmega256D3__)
-# define _EEPROM_SUFFIX   _x256d3
-#elif defined (__AVR_ATA6289__)
-# define _EEPROM_SUFFIX _a6289
-/* avr1: the following only supported for assembler programs */
-#elif defined (__AVR_ATtiny28__)
-# define _EEPROM_SUFFIX _tn28
-#elif defined (__AVR_AT90S1200__)
-# define _EEPROM_SUFFIX  _1200
-#elif defined (__AVR_ATtiny15__)
-# define _EEPROM_SUFFIX _tn15
-#elif defined (__AVR_ATtiny12__)
-# define _EEPROM_SUFFIX _tn12
-#elif defined (__AVR_ATtiny11__)
-# define _EEPROM_SUFFIX _tn11
-#else
-# define _EEPROM_SUFFIX		_UNKNOWN
-#endif
-
-#define _EEPROM_CONCAT1(s1, s2)     s1 ## s2
-#define _EEPROM_CONCAT2(s1, s2)     _EEPROM_CONCAT1 (s1, s2)
-
-#define eeprom_read_byte      _EEPROM_CONCAT2 (__eerd_byte, _EEPROM_SUFFIX)
-#define eeprom_read_word      _EEPROM_CONCAT2 (__eerd_word, _EEPROM_SUFFIX)
-#define eeprom_read_dword     _EEPROM_CONCAT2 (__eerd_dword, _EEPROM_SUFFIX)
-#define eeprom_read_float     _EEPROM_CONCAT2 (__eerd_float, _EEPROM_SUFFIX)
-#define eeprom_read_block     _EEPROM_CONCAT2 (__eerd_block, _EEPROM_SUFFIX)
-
-#define eeprom_write_byte     _EEPROM_CONCAT2 (__eewr_byte, _EEPROM_SUFFIX)
-#define eeprom_write_word     _EEPROM_CONCAT2 (__eewr_word, _EEPROM_SUFFIX)
-#define eeprom_write_dword    _EEPROM_CONCAT2 (__eewr_dword, _EEPROM_SUFFIX)
-#define eeprom_write_float    _EEPROM_CONCAT2 (__eewr_float, _EEPROM_SUFFIX)
-#define eeprom_write_block    _EEPROM_CONCAT2 (__eewr_block, _EEPROM_SUFFIX)
-
-#define eeprom_update_byte    _EEPROM_CONCAT2 (__eeupd_byte, _EEPROM_SUFFIX)
-#define eeprom_update_word    _EEPROM_CONCAT2 (__eeupd_word, _EEPROM_SUFFIX)
-#define eeprom_update_dword   _EEPROM_CONCAT2 (__eeupd_dword, _EEPROM_SUFFIX)
-#define eeprom_update_float   _EEPROM_CONCAT2 (__eeupd_float, _EEPROM_SUFFIX)
-#define eeprom_update_block   _EEPROM_CONCAT2 (__eeupd_block, _EEPROM_SUFFIX)
-
-#endif	/* !__DOXYGEN__ */
-
-#ifndef	__ASSEMBLER__
-
-#include <stddef.h>	/* size_t */
-#include <stdint.h>
-
-/**
- *  @defgroup avr_eeprom EEPROM handling
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef	__ATTR_PURE__
-# ifdef	 __DOXYGEN__
-#  define __ATTR_PURE__
-# else
-#  define __ATTR_PURE__  __attribute__((__pure__))
-# endif
-#endif
-
-/** \def EEMEM
-    \ingroup avr_eeprom
-    Attribute expression causing a variable to be allocated within the
-    .eeprom section.	*/
-#define EEMEM __attribute__((section(".eeprom")))
-
-/** \def eeprom_is_ready
-    \ingroup avr_eeprom
-    \returns 1 if EEPROM is ready for a new read/write operation, 0 if not.
- */
-#if	defined (__DOXYGEN__)
-# define eeprom_is_ready()
-#elif	defined (__AVR_XMEGA__) && __AVR_XMEGA__
-# define eeprom_is_ready()	bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp)
-#elif	defined (DEECR)
-# define eeprom_is_ready()	bit_is_clear (DEECR, BSY)
-#elif	defined (EEPE)
-# define eeprom_is_ready()	bit_is_clear (EECR, EEPE)
-#else
-# define eeprom_is_ready()	bit_is_clear (EECR, EEWE)
-#endif
-
-
-/** \def eeprom_busy_wait
-    \ingroup avr_eeprom
-    Loops until the eeprom is no longer busy.
-    \returns Nothing.
- */
-#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
-
-
-/** \ingroup avr_eeprom
-    Read one byte from EEPROM address \a __p.
- */
-uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one 16-bit word (little endian) from EEPROM address \a __p.
- */
-uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one 32-bit double word (little endian) from EEPROM address \a __p.
- */
-uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one float value (little endian) from EEPROM address \a __p.
- */
-float eeprom_read_float (const float *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read a block of \a __n bytes from EEPROM address \a __src to SRAM
-    \a __dst.
- */
-void eeprom_read_block (void *__dst, const void *__src, size_t __n);
-
-
-/** \ingroup avr_eeprom
-    Write a byte \a __value to EEPROM address \a __p.
- */
-void eeprom_write_byte (uint8_t *__p, uint8_t __value);
-
-/** \ingroup avr_eeprom
-    Write a word \a __value to EEPROM address \a __p.
- */
-void eeprom_write_word (uint16_t *__p, uint16_t __value);
-
-/** \ingroup avr_eeprom
-    Write a 32-bit double word \a __value to EEPROM address \a __p.
- */
-void eeprom_write_dword (uint32_t *__p, uint32_t __value);
-
-/** \ingroup avr_eeprom
-    Write a float \a __value to EEPROM address \a __p.
- */
-void eeprom_write_float (float *__p, float __value);
-
-/** \ingroup avr_eeprom
-    Write a block of \a __n bytes to EEPROM address \a __dst from \a __src.
-    \note The argument order is mismatch with common functions like strcpy().
- */
-void eeprom_write_block (const void *__src, void *__dst, size_t __n);
-
-
-/** \ingroup avr_eeprom
-    Update a byte \a __value to EEPROM address \a __p.
- */
-void eeprom_update_byte (uint8_t *__p, uint8_t __value);
-
-/** \ingroup avr_eeprom
-    Update a word \a __value to EEPROM address \a __p.
- */
-void eeprom_update_word (uint16_t *__p, uint16_t __value);
-
-/** \ingroup avr_eeprom
-    Update a 32-bit double word \a __value to EEPROM address \a __p.
- */
-void eeprom_update_dword (uint32_t *__p, uint32_t __value);
-
-/** \ingroup avr_eeprom
-    Update a float \a __value to EEPROM address \a __p.
- */
-void eeprom_update_float (float *__p, float __value);
-
-/** \ingroup avr_eeprom
-    Update a block of \a __n bytes to EEPROM address \a __dst from \a __src.
-    \note The argument order is mismatch with common functions like strcpy().
- */
-void eeprom_update_block (const void *__src, void *__dst, size_t __n);
-
-
-/** \name IAR C compatibility defines	*/
-/*@{*/
-
-/** \def _EEPUT
-    \ingroup avr_eeprom
-    Write a byte to EEPROM. Compatibility define for IAR C.	*/
-#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
-
-/** \def __EEPUT
-    \ingroup avr_eeprom
-    Write a byte to EEPROM. Compatibility define for IAR C.	*/
-#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
-
-/** \def _EEGET
-    \ingroup avr_eeprom
-    Read a byte from EEPROM. Compatibility define for IAR C.	*/
-#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-
-/** \def __EEGET
-    \ingroup avr_eeprom
-    Read a byte from EEPROM. Compatibility define for IAR C.	*/
-#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-
-/*@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* !__ASSEMBLER__ */
-#endif	/* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */
-
-/**@}*/
-#endif	/* !_AVR_EEPROM_H_ */
diff --git a/cpukit/score/cpu/avr/avr/fuse.h b/cpukit/score/cpu/avr/avr/fuse.h
deleted file mode 100644
index ba968ba853..0000000000
--- a/cpukit/score/cpu/avr/avr/fuse.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/fuse.h - Fuse API */
-
-#ifndef _AVR_FUSE_H_
-#define _AVR_FUSE_H_ 1
-
-/* This file must be explicitly included by <avr/io.h>. */
-#if !defined(_AVR_IO_H_)
-#error "You must #include <avr/io.h> and not <avr/fuse.h> by itself."
-#endif
-
-
-/** \file */
-/** \defgroup avr_fuse <avr/fuse.h>: Fuse Support
-
-    \par Introduction
-
-    The Fuse API allows a user to specify the fuse settings for the specific
-    AVR device they are compiling for. These fuse settings will be placed
-    in a special section in the ELF output file, after linking.
-
-    Programming tools can take advantage of the fuse information embedded in
-    the ELF file, by extracting this information and determining if the fuses
-    need to be programmed before programming the Flash and EEPROM memories.
-    This also allows a single ELF file to contain all the
-    information needed to program an AVR. 
-
-    To use the Fuse API, include the <avr/io.h> header file, which in turn
-    automatically includes the individual I/O header file and the <avr/fuse.h>
-    file. These other two files provides everything necessary to set the AVR
-    fuses.
-    
-    \par Fuse API
-    
-    Each I/O header file must define the FUSE_MEMORY_SIZE macro which is
-    defined to the number of fuse bytes that exist in the AVR device.
-    
-    A new type, __fuse_t, is defined as a structure. The number of fields in 
-    this structure are determined by the number of fuse bytes in the 
-    FUSE_MEMORY_SIZE macro.
-    
-    If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type
-    unsigned char.
-    
-    If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type
-    unsigned char.
-    
-    If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended,
-    of type unsigned char.
-    
-    If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array
-    of unsigned char with the size of the array being FUSE_MEMORY_SIZE.
-    
-    A convenience macro, FUSEMEM, is defined as a GCC attribute for a 
-    custom-named section of ".fuse".
-    
-    A convenience macro, FUSES, is defined that declares a variable, __fuse, of
-    type __fuse_t with the attribute defined by FUSEMEM. This variable
-    allows the end user to easily set the fuse data.
-
-    \note If a device-specific I/O header file has previously defined FUSEMEM,
-    then FUSEMEM is not redefined. If a device-specific I/O header file has
-    previously defined FUSES, then FUSES is not redefined.
-
-    Each AVR device I/O header file has a set of defined macros which specify the
-    actual fuse bits available on that device. The AVR fuses have inverted
-    values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a
-    programmed (enabled) bit. The defined macros for each individual fuse
-    bit represent this in their definition by a bit-wise inversion of a mask.
-    For example, the FUSE_EESAVE fuse in the ATmega128 is defined as:
-    \code
-    #define FUSE_EESAVE      ~_BV(3)
-    \endcode
-    \note The _BV macro creates a bit mask from a bit number. It is then 
-    inverted to represent logical values for a fuse memory byte.
-    
-    To combine the fuse bits macros together to represent a whole fuse byte,
-    use the bitwise AND operator, like so:
-    \code
-    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN)
-    \endcode
-    
-    Each device I/O header file also defines macros that provide default values
-    for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low
-    Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT
-    is defined for an Extended Fuse byte.
-    
-    If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that
-    provide default values for each fuse byte like so:
-    FUSE0_DEFAULT
-    FUSE1_DEFAULT
-    FUSE2_DEFAULT
-    FUSE3_DEFAULT
-    FUSE4_DEFAULT
-    ....
-    
-    \par API Usage Example
-    
-    Putting all of this together is easy. Using C99's designated initializers:
-    
-    \code
-    #include <avr/io.h>
-
-    FUSES = 
-    {
-        .low = LFUSE_DEFAULT,
-        .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
-        .extended = EFUSE_DEFAULT,
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    Or, using the variable directly instead of the FUSES macro,
-    
-    \code
-    #include <avr/io.h>
-
-    __fuse_t __fuse __attribute__((section (".fuse"))) = 
-    {
-        .low = LFUSE_DEFAULT,
-        .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
-        .extended = EFUSE_DEFAULT,
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    If you are compiling in C++, you cannot use the designated intializers so
-    you must do:
-
-    \code
-    #include <avr/io.h>
-
-    FUSES = 
-    {
-        LFUSE_DEFAULT, // .low
-        (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high
-        EFUSE_DEFAULT, // .extended
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    
-    However there are a number of caveats that you need to be aware of to
-    use this API properly.
-    
-    Be sure to include <avr/io.h> to get all of the definitions for the API.
-    The FUSES macro defines a global variable to store the fuse data. This 
-    variable is assigned to its own linker section. Assign the desired fuse 
-    values immediately in the variable initialization.
-    
-    The .fuse section in the ELF file will get its values from the initial 
-    variable assignment ONLY. This means that you can NOT assign values to 
-    this variable in functions and the new values will not be put into the
-    ELF .fuse section.
-    
-    The global variable is declared in the FUSES macro has two leading 
-    underscores, which means that it is reserved for the "implementation",
-    meaning the library, so it will not conflict with a user-named variable.
-    
-    You must initialize ALL fields in the __fuse_t structure. This is because
-    the fuse bits in all bytes default to a logical 1, meaning unprogrammed. 
-    Normal uninitialized data defaults to all locgial zeros. So it is vital that
-    all fuse bytes are initialized, even with default data. If they are not,
-    then the fuse bits may not programmed to the desired settings.
-    
-    Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
-    your linker command line to have the correct device selected and to have 
-    the correct I/O header file included when you include <avr/io.h>.
-
-    You can print out the contents of the .fuse section in the ELF file by
-    using this command line:
-    \code
-    avr-objdump -s -j .fuse <ELF file>
-    \endcode
-    The section contents shows the address on the left, then the data going from
-    lower address to a higher address, left to right.
-
-*/
-
-#ifndef __ASSEMBLER__
-
-#ifndef FUSEMEM
-#define FUSEMEM  __attribute__((section (".fuse")))
-#endif
-
-#if FUSE_MEMORY_SIZE > 3
-
-typedef struct
-{
-    unsigned char byte[FUSE_MEMORY_SIZE];
-} __fuse_t;
-
-
-#elif FUSE_MEMORY_SIZE == 3
-
-typedef struct
-{
-    unsigned char low;
-    unsigned char high;
-    unsigned char extended;
-} __fuse_t;
-
-#elif FUSE_MEMORY_SIZE == 2
-
-typedef struct
-{
-    unsigned char low;
-    unsigned char high;
-} __fuse_t;
-
-#elif FUSE_MEMORY_SIZE == 1
-
-typedef struct
-{
-    unsigned char byte;
-} __fuse_t;
-
-#endif
-
-#ifndef FUSES
-#define FUSES __fuse_t __fuse FUSEMEM
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* _AVR_FUSE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/interrupt.h b/cpukit/score/cpu/avr/avr/interrupt.h
deleted file mode 100644
index 8dd5e26d09..0000000000
--- a/cpukit/score/cpu/avr/avr/interrupt.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz
-   Copyright (c) 2007, Dean Camera
-
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-#ifndef _AVR_INTERRUPT_H_
-#define _AVR_INTERRUPT_H_
-
-#include <avr/io.h>
-
-#if !defined(__DOXYGEN__) && !defined(__STRINGIFY)
-/* Auxiliary macro for ISR_ALIAS(). */
-#define __STRINGIFY(x) #x
-#endif /* !defined(__DOXYGEN__) */
-
-/** 
-\file 
-\@{ 
-*/
-
-
-/** \name Global manipulation of the interrupt flag
-
-    The global interrupt flag is maintained in the I bit of the status
-    register (SREG). 
-*/
-
-#if defined(__DOXYGEN__)
-/** \def sei()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Enables interrupts by setting the global interrupt mask. This function
-    actually compiles into a single line of assembly, so there is no function
-    call overhead. */
-#define sei()
-#else  /* !DOXYGEN */
-# define sei()  __asm__ __volatile__ ("sei" ::)
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def cli()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Disables all interrupts by clearing the global interrupt mask. This function
-    actually compiles into a single line of assembly, so there is no function
-    call overhead. */
-#define cli()
-#else  /* !DOXYGEN */
-# define cli()  __asm__ __volatile__ ("cli" ::)
-#endif /* DOXYGEN */
-
-
-/** \name Macros for writing interrupt handler functions */
-
-
-#if defined(__DOXYGEN__)
-/** \def ISR(vector [, attributes])
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Introduces an interrupt handler function (interrupt service
-    routine) that runs with global interrupts initially disabled
-    by default with no attributes specified.
-
-    The attributes are optional and alter the behaviour and resultant
-    generated code of the interrupt routine. Multiple attributes may
-    be used for a single function, with a space seperating each
-    attribute.
-
-    Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and
-    ISR_ALIASOF(vect).
-
-    \c vector must be one of the interrupt vector names that are
-    valid for the particular MCU type.
-*/
-#  define ISR(vector, [attributes])
-#else  /* real code */
-
-#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  define __INTR_ATTRS used, externally_visible
-#else /* GCC < 4.1 */
-#  define __INTR_ATTRS used
-#endif
-
-#ifdef __cplusplus
-#  define ISR(vector, ...)            \
-    extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
-    void vector (void)
-#else
-#  define ISR(vector, ...)            \
-    void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
-    void vector (void)
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def SIGNAL(vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Introduces an interrupt handler function that runs with global interrupts
-    initially disabled.
-
-    This is the same as the ISR macro without optional attributes.
-    \deprecated Do not use SIGNAL() in new code. Use ISR() instead.
-*/
-#  define SIGNAL(vector)
-#else  /* real code */
-
-#ifdef __cplusplus
-#  define SIGNAL(vector)					\
-    extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS));	\
-    void vector (void)
-#else
-#  define SIGNAL(vector)					\
-    void vector (void) __attribute__ ((signal, __INTR_ATTRS));		\
-    void vector (void)
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def EMPTY_INTERRUPT(vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Defines an empty interrupt handler function. This will not generate
-    any prolog or epilog code and will only return from the ISR. Do not
-    define a function body as this will define it for you.
-    Example:
-    \code EMPTY_INTERRUPT(ADC_vect);\endcode */
-#  define EMPTY_INTERRUPT(vector)
-#else  /* real code */
-
-#ifdef __cplusplus
-#  define EMPTY_INTERRUPT(vector)                \
-    extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS));    \
-    void vector (void) {  __asm__ __volatile__ ("reti" ::); }
-#else
-#  define EMPTY_INTERRUPT(vector)                \
-    void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS));    \
-    void vector (void) { __asm__ __volatile__ ("reti" ::); }
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def ISR_ALIAS(vector, target_vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Aliases a given vector to another one in the same manner as the
-    ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF
-    attribute macro however, this is compatible for all versions of
-    GCC rather than just GCC version 4.2 onwards.
-
-    \note This macro creates a trampoline function for the aliased
-    macro.  This will result in a two cycle penalty for the aliased
-    vector compared to the ISR the vector is aliased to, due to the
-    JMP/RJMP opcode used.
-
-    \deprecated
-    For new code, the use of ISR(..., ISR_ALIASOF(...))  is
-    recommended.
-
-    Example:
-    \code
-    ISR(INT0_vect)
-    {
-        PORTB = 42;
-    }
-
-    ISR_ALIAS(INT1_vect, INT0_vect);
-    \endcode 
-*/
-#  define ISR_ALIAS(vector, target_vector)
-#else /* real code */
-
-#ifdef __cplusplus
-#  if defined(__AVR_MEGA__) && __AVR_MEGA__
-#    define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("jmp " __STRINGIFY(tgt) ::); }
-#  else /* !__AVR_MEGA */
-#    define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("rjmp " __STRINGIFY(tgt) ::); }
-#  endif  /* __AVR_MEGA__ */
-#else	  /* !__cplusplus */
-#  if defined(__AVR_MEGA__) && __AVR_MEGA__
-#  define ISR_ALIAS(vector, tgt) void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("jmp " __STRINGIFY(tgt) ::); }
-#  else /* !__AVR_MEGA */
-#  define ISR_ALIAS(vector, tgt) void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("rjmp " __STRINGIFY(tgt) ::); }
-#  endif  /* __AVR_MEGA__ */
-#endif	/* __cplusplus */
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def reti()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Returns from an interrupt routine, enabling global interrupts. This should
-    be the last command executed before leaving an ISR defined with the ISR_NAKED
-    attribute.
-
-    This macro actually compiles into a single line of assembly, so there is
-    no function call overhead.
-*/
-#  define reti()
-#else  /* !DOXYGEN */
-#  define reti()  __asm__ __volatile__ ("reti" ::)
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def BADISR_vect
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    This is a vector which is aliased to __vector_default, the vector
-    executed when an ISR fires with no accompanying ISR handler. This
-    may be used along with the ISR() macro to create a catch-all for
-    undefined but used ISRs for debugging purposes.
-*/
-#  define BADISR_vect
-#else  /* !DOXYGEN */
-#  define BADISR_vect __vector_default
-#endif /* DOXYGEN */
-
-/** \name ISR attributes */
-
-#if defined(__DOXYGEN__)
-/** \def ISR_BLOCK
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    Identical to an ISR with no attributes specified. Global
-    interrupts are initially disabled by the AVR hardware when
-    entering the ISR, without the compiler modifying this state.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_BLOCK
-
-/** \def ISR_NOBLOCK
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    ISR runs with global interrupts initially enabled.  The interrupt
-    enable flag is activated by the compiler as early as possible
-    within the ISR to ensure minimal processing delay for nested
-    interrupts.
-
-    This may be used to create nested ISRs, however care should be
-    taken to avoid stack overflows, or to avoid infinitely entering
-    the ISR for those cases where the AVR hardware does not clear the
-    respective interrupt flag before entering the ISR.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_NOBLOCK
-
-/** \def ISR_NAKED
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    ISR is created with no prologue or epilogue code. The user code is
-    responsible for preservation of the machine state including the
-    SREG register, as well as placing a reti() at the end of the
-    interrupt routine.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_NAKED
-
-/** \def ISR_ALIASOF(target_vector)
-    \ingroup avr_interrupts
-
-    \code#include <avr/interrupt.h>\endcode
-
-    The ISR is linked to another ISR, specified by the vect parameter.
-    This is compatible with GCC 4.2 and greater only.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_ALIASOF(target_vector)
-#else  /* !DOXYGEN */
-#  define ISR_BLOCK
-#  define ISR_NOBLOCK    __attribute__((interrupt))
-#  define ISR_NAKED      __attribute__((naked))
-#  define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v))))
-#endif /* DOXYGEN */
-
-/* \@} */
-
-#endif
diff --git a/cpukit/score/cpu/avr/avr/io.h b/cpukit/score/cpu/avr/avr/io.h
deleted file mode 100644
index 22ac57d84f..0000000000
--- a/cpukit/score/cpu/avr/avr/io.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/**
- * @file
- *
- * @brief AVR device-specific IO Definitions
- *
- * This header file includes the apropriate IO definitions for the
- * device that has been specified by the <tt>-mmcu=</tt> compiler
- *  command-line switch.  This is done by diverting to the appropriate
- *  file <tt>&lt;avr/io</tt><em>XXXX</em><tt>.h&gt;</tt> which should
- *  never be included directly.  Some register names common to all
- *  AVR devices are defined directly within <tt>&lt;avr/common.h&gt;</tt>,
- *  which is included in <tt>&lt;avr/io.h&gt;</tt>,
- *  but most of the details come from the respective include file.
- *
- *  Note that this file always includes the following files:
- *  \code
- *  #include <avr/sfr_defs.h>
- *  #include <avr/portpins.h>
- *  #include <avr/common.h>
- *  #include <avr/version.h>
- *  \endcode
- *  See \ref avr_sfr for more details about that header file.
- *
- *  Included are definitions of the IO register set and their
- *  respective bit values as specified in the Atmel documentation.
- *  Note that inconsistencies in naming conventions,
- *  so even identical functions sometimes get different names on
- *  different devices.
- *
- *  Also included are the specific names useable for interrupt
- *  function definitions as documented
- *  \ref avr_signames "here".
- *
- *  Finally, the following macros are defined:
- *
- *  - \b RAMEND
- *  <br>
- *  The last on-chip RAM address.
- *  <br>
- *  - \b XRAMEND
- *  <br>
- *  The last possible RAM location that is addressable. This is equal to
- *  RAMEND for devices that do not allow for external RAM. For devices
- *  that allow external RAM, this will be larger than RAMEND.
- *  <br>
- *  - \b E2END
- *  <br>
- *  The last EEPROM address.
- *  <br>
- *  - \b FLASHEND
- *  <br>
- *  The last byte address in the Flash program space.
- *  <br>
- *  - \b SPM_PAGESIZE
- *  <br>
- *  For devices with bootloader support, the flash pagesize
- *  (in bytes) to be used for the \c SPM instruction.
- *  - \b E2PAGESIZE
- *  <br>
- *  The size of the EEPROM page.
- */
-
-/*
- *  Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
- *  Copyright (c) 2007 Eric B. Weddington
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#define _AVR_IO_H_
-
-/**
- * @defgroup avr_io Input Output
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/sfr_defs.h>
-
-#if defined (__AVR_AT94K__)
-#  include <avr/ioat94k.h>
-#elif defined (__AVR_AT43USB320__)
-#  include <avr/io43u32x.h>
-#elif defined (__AVR_AT43USB355__)
-#  include <avr/io43u35x.h>
-#elif defined (__AVR_AT76C711__)
-#  include <avr/io76c711.h>
-#elif defined (__AVR_AT86RF401__)
-#  include <avr/io86r401.h>
-#elif defined (__AVR_AT90PWM1__)
-#  include <avr/io90pwm1.h>
-#elif defined (__AVR_AT90PWM2__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM2B__)
-#  include <avr/io90pwm2b.h>
-#elif defined (__AVR_AT90PWM3__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM3B__)
-#  include <avr/io90pwm3b.h>
-#elif defined (__AVR_AT90PWM216__)
-#  include <avr/io90pwm216.h>
-#elif defined (__AVR_AT90PWM316__)
-#  include <avr/io90pwm316.h>
-#elif defined (__AVR_AT90PWM81__)
-#  include <avr/io90pwm81.h>
-#elif defined (__AVR_ATmega8U2__)
-#  include <avr/iom8u2.h>
-#elif defined (__AVR_ATmega16M1__)
-#  include <avr/iom16m1.h>
-#elif defined (__AVR_ATmega16U2__)
-#  include <avr/iom16u2.h>
-#elif defined (__AVR_ATmega16U4__)
-#  include <avr/iom16u4.h>
-#elif defined (__AVR_ATmega32C1__)
-#  include <avr/iom32c1.h>
-#elif defined (__AVR_ATmega32M1__)
-#  include <avr/iom32m1.h>
-#elif defined (__AVR_ATmega32U2__)
-#  include <avr/iom32u2.h>
-#elif defined (__AVR_ATmega32U4__)
-#  include <avr/iom32u4.h>
-#elif defined (__AVR_ATmega32U6__)
-#  include <avr/iom32u6.h>
-#elif defined (__AVR_ATmega64C1__)
-#  include <avr/iom64c1.h>
-#elif defined (__AVR_ATmega64M1__)
-#  include <avr/iom64m1.h>
-#elif defined (__AVR_ATmega128__)
-#  include <avr/iom128.h>
-#elif defined (__AVR_ATmega1280__)
-#  include <avr/iom1280.h>
-#elif defined (__AVR_ATmega1281__)
-#  include <avr/iom1281.h>
-#elif defined (__AVR_ATmega1284P__)
-#  include <avr/iom1284p.h>
-#elif defined (__AVR_ATmega128RFA1__)
-#  include <avr/iom128rfa1.h>
-#elif defined (__AVR_ATmega2560__)
-#  include <avr/iom2560.h>
-#elif defined (__AVR_ATmega2561__)
-#  include <avr/iom2561.h>
-#elif defined (__AVR_AT90CAN32__)
-#  include <avr/iocan32.h>
-#elif defined (__AVR_AT90CAN64__)
-#  include <avr/iocan64.h>
-#elif defined (__AVR_AT90CAN128__)
-#  include <avr/iocan128.h>
-#elif defined (__AVR_AT90USB82__)
-#  include <avr/iousb82.h>
-#elif defined (__AVR_AT90USB162__)
-#  include <avr/iousb162.h>
-#elif defined (__AVR_AT90USB646__)
-#  include <avr/iousb646.h>
-#elif defined (__AVR_AT90USB647__)
-#  include <avr/iousb647.h>
-#elif defined (__AVR_AT90USB1286__)
-#  include <avr/iousb1286.h>
-#elif defined (__AVR_AT90USB1287__)
-#  include <avr/iousb1287.h>
-#elif defined (__AVR_ATmega64__)
-#  include <avr/iom64.h>
-#elif defined (__AVR_ATmega640__)
-#  include <avr/iom640.h>
-#elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega644A__)
-#  include <avr/iom644.h>
-#elif defined (__AVR_ATmega644P__)
-#  include <avr/iom644p.h>
-#elif defined (__AVR_ATmega644PA__)
-#  include <avr/iom644pa.h>
-#elif defined (__AVR_ATmega645__) || defined (__AVR_ATmega645A__) || defined (__AVR_ATmega645P__)
-#  include <avr/iom645.h>
-#elif defined (__AVR_ATmega6450__) || defined (__AVR_ATmega6450A__) || defined (__AVR_ATmega6450P__)
-#  include <avr/iom6450.h>
-#elif defined (__AVR_ATmega649__) || defined (__AVR_ATmega649A__)
-#  include <avr/iom649.h>
-#elif defined (__AVR_ATmega6490__) || defined (__AVR_ATmega6490A__) || defined (__AVR_ATmega6490P__)
-#  include <avr/iom6490.h>
-#elif defined (__AVR_ATmega649P__)
-#  include <avr/iom649p.h>
-#elif defined (__AVR_ATmega64HVE__)
-#  include <avr/iom64hve.h>
-#elif defined (__AVR_ATmega103__)
-#  include <avr/iom103.h>
-#elif defined (__AVR_ATmega32__)
-#  include <avr/iom32.h>
-#elif defined (__AVR_ATmega323__)
-#  include <avr/iom323.h>
-#elif defined (__AVR_ATmega324P__) || defined (__AVR_ATmega324A__)
-#  include <avr/iom324.h>
-#elif defined (__AVR_ATmega324PA__)
-#  include <avr/iom324pa.h>
-#elif defined (__AVR_ATmega325__)
-#  include <avr/iom325.h>
-#elif defined (__AVR_ATmega325P__)
-#  include <avr/iom325.h>
-#elif defined (__AVR_ATmega3250__)
-#  include <avr/iom3250.h>
-#elif defined (__AVR_ATmega3250P__)
-#  include <avr/iom3250.h>
-#elif defined (__AVR_ATmega328P__) || defined (__AVR_ATmega328__)
-#  include <avr/iom328p.h>
-#elif defined (__AVR_ATmega329__)
-#  include <avr/iom329.h>
-#elif defined (__AVR_ATmega329P__) || defined (__AVR_ATmega329PA__)
-#  include <avr/iom329.h>
-#elif defined (__AVR_ATmega3290__)
-#  include <avr/iom3290.h>
-#elif defined (__AVR_ATmega3290P__)
-#  include <avr/iom3290.h>
-#elif defined (__AVR_ATmega32HVB__)
-#  include <avr/iom32hvb.h>
-#elif defined (__AVR_ATmega406__)
-#  include <avr/iom406.h>
-#elif defined (__AVR_ATmega16__)
-#  include <avr/iom16.h>
-#elif defined (__AVR_ATmega16A__)
-#  include <avr/iom16a.h>
-#elif defined (__AVR_ATmega161__)
-#  include <avr/iom161.h>
-#elif defined (__AVR_ATmega162__)
-#  include <avr/iom162.h>
-#elif defined (__AVR_ATmega163__)
-#  include <avr/iom163.h>
-#elif defined (__AVR_ATmega164P__) || defined (__AVR_ATmega164A__)
-#  include <avr/iom164.h>
-#elif defined (__AVR_ATmega165__) || defined (__AVR_ATmega165A__)
-#  include <avr/iom165.h>
-#elif defined (__AVR_ATmega165P__)
-#  include <avr/iom165p.h>
-#elif defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
-#  include <avr/iom168.h>
-#elif defined (__AVR_ATmega168P__)
-#  include <avr/iom168p.h>
-#elif defined (__AVR_ATmega169__) || defined (__AVR_ATmega169A__)
-#  include <avr/iom169.h>
-#elif defined (__AVR_ATmega169P__)
-#  include <avr/iom169p.h>
-#elif defined (__AVR_ATmega169PA__)
-#  include <avr/iom169pa.h>
-#elif defined (__AVR_ATmega8HVA__)
-#  include <avr/iom8hva.h>
-#elif defined (__AVR_ATmega16HVA__)
-#  include <avr/iom16hva.h>
-#elif defined (__AVR_ATmega16HVA2__)
-#  include <avr/iom16hva2.h>
-#elif defined (__AVR_ATmega16HVB__)
-#  include <avr/iom16hvb.h>
-#elif defined (__AVR_ATmega8__)
-#  include <avr/iom8.h>
-#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega48A__)
-#  include <avr/iom48.h>
-#elif defined (__AVR_ATmega48P__)
-#  include <avr/iom48p.h>
-#elif defined (__AVR_ATmega88__) || defined (__AVR_ATmega88A__)
-#  include <avr/iom88.h>
-#elif defined (__AVR_ATmega88P__)
-#  include <avr/iom88p.h>
-#elif defined (__AVR_ATmega88PA__)
-#  include <avr/iom88pa.h>
-#elif defined (__AVR_ATmega8515__)
-#  include <avr/iom8515.h>
-#elif defined (__AVR_ATmega8535__)
-#  include <avr/iom8535.h>
-#elif defined (__AVR_AT90S8535__)
-#  include <avr/io8535.h>
-#elif defined (__AVR_AT90C8534__)
-#  include <avr/io8534.h>
-#elif defined (__AVR_AT90S8515__)
-#  include <avr/io8515.h>
-#elif defined (__AVR_AT90S4434__)
-#  include <avr/io4434.h>
-#elif defined (__AVR_AT90S4433__)
-#  include <avr/io4433.h>
-#elif defined (__AVR_AT90S4414__)
-#  include <avr/io4414.h>
-#elif defined (__AVR_ATtiny22__)
-#  include <avr/iotn22.h>
-#elif defined (__AVR_ATtiny26__)
-#  include <avr/iotn26.h>
-#elif defined (__AVR_AT90S2343__)
-#  include <avr/io2343.h>
-#elif defined (__AVR_AT90S2333__)
-#  include <avr/io2333.h>
-#elif defined (__AVR_AT90S2323__)
-#  include <avr/io2323.h>
-#elif defined (__AVR_AT90S2313__)
-#  include <avr/io2313.h>
-#elif defined (__AVR_ATtiny2313__)
-#  include <avr/iotn2313.h>
-#elif defined (__AVR_ATtiny2313A__)
-#  include <avr/iotn2313a.h>
-#elif defined (__AVR_ATtiny13__)
-#  include <avr/iotn13.h>
-#elif defined (__AVR_ATtiny13A__)
-#  include <avr/iotn13a.h>
-#elif defined (__AVR_ATtiny25__)
-#  include <avr/iotn25.h>
-#elif defined (__AVR_ATtiny4313__)
-#  include <avr/iotn4313.h>
-#elif defined (__AVR_ATtiny45__)
-#  include <avr/iotn45.h>
-#elif defined (__AVR_ATtiny85__)
-#  include <avr/iotn85.h>
-#elif defined (__AVR_ATtiny24__)
-#  include <avr/iotn24.h>
-#elif defined (__AVR_ATtiny24A__)
-#  include <avr/iotn24a.h>
-#elif defined (__AVR_ATtiny44__)
-#  include <avr/iotn44.h>
-#elif defined (__AVR_ATtiny44A__)
-#  include <avr/iotn44a.h>
-#elif defined (__AVR_ATtiny84__)
-#  include <avr/iotn84.h>
-#elif defined (__AVR_ATtiny261__)
-#  include <avr/iotn261.h>
-#elif defined (__AVR_ATtiny261A__)
-#  include <avr/iotn261a.h>
-#elif defined (__AVR_ATtiny461__)
-#  include <avr/iotn461.h>
-#elif defined (__AVR_ATtiny461A__)
-#  include <avr/iotn461a.h>
-#elif defined (__AVR_ATtiny861__)
-#  include <avr/iotn861.h>
-#elif defined (__AVR_ATtiny861A__)
-#  include <avr/iotn861a.h>
-#elif defined (__AVR_ATtiny43U__)
-#  include <avr/iotn43u.h>
-#elif defined (__AVR_ATtiny48__)
-#  include <avr/iotn48.h>
-#elif defined (__AVR_ATtiny88__)
-#  include <avr/iotn88.h>
-#elif defined (__AVR_ATtiny87__)
-#  include <avr/iotn87.h>
-#elif defined (__AVR_ATtiny167__)
-#  include <avr/iotn167.h>
-#elif defined (__AVR_AT90SCR100__)
-#  include <avr/io90scr100.h>
-#elif defined (__AVR_ATxmega16A4__)
-#  include <avr/iox16a4.h>
-#elif defined (__AVR_ATxmega16D4__)
-#  include <avr/iox16d4.h>
-#elif defined (__AVR_ATxmega32A4__)
-#  include <avr/iox32a4.h>
-#elif defined (__AVR_ATxmega32D4__)
-#  include <avr/iox32d4.h>
-#elif defined (__AVR_ATxmega64A1__)
-#  include <avr/iox64a1.h>
-#elif defined (__AVR_ATxmega64A3__)
-#  include <avr/iox64a3.h>
-#elif defined (__AVR_ATxmega64D3__)
-#  include <avr/iox64d3.h>
-#elif defined (__AVR_ATxmega128A1__)
-#  include <avr/iox128a1.h>
-#elif defined (__AVR_ATxmega128A3__)
-#  include <avr/iox128a3.h>
-#elif defined (__AVR_ATxmega128D3__)
-#  include <avr/iox128d3.h>
-#elif defined (__AVR_ATxmega192A3__)
-#  include <avr/iox192a3.h>
-#elif defined (__AVR_ATxmega192D3__)
-#  include <avr/iox192d3.h>
-#elif defined (__AVR_ATxmega256A3__)
-#  include <avr/iox256a3.h>
-#elif defined (__AVR_ATxmega256A3B__)
-#  include <avr/iox256a3b.h>
-#elif defined (__AVR_ATxmega256D3__)
-#  include <avr/iox256d3.h>
-#elif defined (__AVR_ATA6289__)
-#  include <avr/ioa6289.h>
-/* avr1: the following only supported for assembler programs */
-#elif defined (__AVR_ATtiny28__)
-#  include <avr/iotn28.h>
-#elif defined (__AVR_AT90S1200__)
-#  include <avr/io1200.h>
-#elif defined (__AVR_ATtiny15__)
-#  include <avr/iotn15.h>
-#elif defined (__AVR_ATtiny12__)
-#  include <avr/iotn12.h>
-#elif defined (__AVR_ATtiny11__)
-#  include <avr/iotn11.h>
-#else
-#  if !defined(__COMPILING_AVR_LIBC__)
-#    warning "device type not defined"
-#  endif
-#endif
-
-#include <avr/portpins.h>
-
-#include <avr/common.h>
-
-#include <avr/version.h>
-
-/* Include fuse.h after individual IO header files. */
-#include <avr/fuse.h>
-
-/* Include lock.h after individual IO header files. */
-#include <avr/lock.h>
-
-/** @} */
-#endif /* _AVR_IO_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io1200.h b/cpukit/score/cpu/avr/avr/io1200.h
deleted file mode 100644
index ae2aa17542..0000000000
--- a/cpukit/score/cpu/avr/avr/io1200.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/**
- * @file avr/io1200.h
- *
- * @brief Definitions for AT90S1200
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO1200_H_
-#define _AVR_IO1200_H_ 1
-
-/**
- *  @defgroup Avr_io1200 AT90S1200 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io1200.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/* I/O registers */
-
-/* 0x00..0x07 reserved */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x0F reserved */
-
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* 0x13..0x15 reserved */
-
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* 0x19..0x1B reserved */
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* 0x1F..0x20 reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22..0x31 reserved */
-
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* 0x3A reserved */
-
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(3)
-#define SIG_COMPARATOR			_VECTOR(3)
-
-#define _VECTORS_SIZE 8
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT0	6
-
-/* TIMSK */
-#define TOIE0	1
-
-/* TIFR */
-#define TOV0	1
-
-/* MCUCR */
-#define SE	5
-#define SM	4
-#define ISC01	1
-#define ISC00	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* WDTCR */
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* EECR */
-#undef EEMWE
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB1 = AIN1
-   PB0 = AIN0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTD */
-#define PD6	6
-#define PD5	5
-#define PD4	4
-#define PD3	3
-#define PD2	2
-#define PD1	1
-#define PD0	0
-
-/* DDRD */
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* ACSR */
-#define ACD	7
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* EEPROM Control Register */
-#define EERIE	3
-#define EEMWE	2
-#define EEWE	1
-#define EERE	0
-
-#undef ZH
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x3F
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_RCEN  (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x01
-
-
-/**@}*/
-#endif  /* _AVR_IO1200_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2313.h b/cpukit/score/cpu/avr/avr/io2313.h
deleted file mode 100644
index 1ca95a6749..0000000000
--- a/cpukit/score/cpu/avr/avr/io2313.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2313.h - definitions for AT90S2313 */
-
-#ifndef _AVR_IO2313_H_
-#define _AVR_IO2313_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2313.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Output Compare Register 1 */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3D SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT1_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP1_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF1_vect		_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(7)
-#define SIG_UART_RECV			_VECTOR(7)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(8)
-#define SIG_UART_DATA			_VECTOR(8)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(9)
-#define SIG_UART_TRANS			_VECTOR(9)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(10)
-#define SIG_COMPARATOR			_VECTOR(10)
-
-#define _VECTORS_SIZE 22
-
-/*
- *  The Register Bit names are represented by their bit number (0-7).
- */     
- 
-/* General Interrupt MaSK register */
-#define    INT1    7
-#define    INT0    6
- 
-/* General Interrupt Flag Register */
-#define    INTF1   7
-#define    INTF0   6
- 
-/* Timer/Counter Interrupt MaSK register */                 
-#define    TOIE1   7
-#define    OCIE1A  6
-#define    TICIE   3 /* old name */ 
-#define    TICIE1  3
-#define    TOIE0   1
- 
-/* Timer/Counter Interrupt Flag register */                   
-#define    TOV1    7
-#define    OCF1A   6
-#define    ICF1    3
-#define    TOV0    1
- 
-/* MCU general Control Register */ 
-#define    SE      5
-#define    SM      4
-#define    ISC11   3
-#define    ISC10   2
-#define    ISC01   1
-#define    ISC00   0
- 
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
- 
-/* Timer/Counter 1 Control Register */
-#define    COM1A1  7
-#define    COM1A0  6
-#define    PWM11   1
-#define    PWM10   0
- 
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1   7
-#define    ICES1   6
-#define    CTC1    3
-#define    CS12    2
-#define    CS11    1
-#define    CS10    0
-                        
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
- 
-/* EEPROM Control Register */
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
- 
-/* Data Register, Port B */  
-#define    PB7     7
-#define    PB6     6
-#define    PB5     5
-#define    PB4     4
-#define    PB3     3
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
- 
-/* Data Direction Register, Port B */
-#define    DDB7    7
-#define    DDB6    6
-#define    DDB5    5
-#define    DDB4    4
-#define    DDB3    3
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
- 
-/* Input Pins, Port B */
-#define    PINB7   7
-#define    PINB6   6
-#define    PINB5   5
-#define    PINB4   4
-#define    PINB3   3
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
- 
-/* Data Register, Port D */
-#define    PD6     6
-#define    PD5     5
-#define    PD4     4
-#define    PD3     3
-#define    PD2     2
-#define    PD1     1
-#define    PD0     0
- 
-/* Data Direction Register, Port D */
-#define    DDD6    6
-#define    DDD5    5
-#define    DDD4    4
-#define    DDD3    3
-#define    DDD2    2
-#define    DDD1    1
-#define    DDD0    0
- 
-/* Input Pins, Port D */
-#define    PIND6   6
-#define    PIND5   5
-#define    PIND4   4
-#define    PIND3   3
-#define    PIND2   2
-#define    PIND1   1
-#define    PIND0   0
- 
-/* UART Status Register */
-#define    RXC     7
-#define    TXC     6
-#define    UDRE    5
-#define    FE      4
-#define    DOR     3
- 
-/* UART Control Register */
-#define    RXCIE   7
-#define    TXCIE   6
-#define    UDRIE   5
-#define    RXEN    4
-#define    TXEN    3
-#define    CHR9    2
-#define    RXB8    1
-#define    TXB8    0
-       
-/* Analog Comparator Control and Status Register */ 
-#define    ACD     7
-#define    ACO     5
-#define    ACI     4
-#define    ACIE    3
-#define    ACIC    2
-#define    ACIS1   1
-#define    ACIS0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-       
-/* Constants */ 
-#define    RAMEND     0xDF
-#define    XRAMEND    RAMEND
-#define    E2END      0x7F
-#define    E2PAGESIZE 0
-#define    FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_FSTRT (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x01
-
-
-#endif  /* _AVR_IO2313_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2323.h b/cpukit/score/cpu/avr/avr/io2323.h
deleted file mode 100644
index 2bfe7174d2..0000000000
--- a/cpukit/score/cpu/avr/avr/io2323.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2323.h - definitions for AT90S2323 */
-
-#ifndef _AVR_IO2323_H_
-#define _AVR_IO2323_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2323.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-#define _VECTORS_SIZE 6
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt MaSK register */
-#define    INT0    6
-#define    INTF0   6
-
-/* General Interrupt Flag Register */
-#define    TOIE0   1
-#define    TOV0    1
-
-/* MCU general Control Register */
-#define    SE      5
-#define    SM      4
-#define    ISC01   1
-#define    ISC00   0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
-
-/*
-   PB2 = SCK/T0
-   PB1 = MISO/INT0
-   PB0 = MOSI
- */
-
-/* Data Register, Port B */
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
-
-/* Data Direction Register, Port B */
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
-
-/* Input Pins, Port B */
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-
-/* Constants */
-#define RAMEND     0xDF
-#define XRAMEND    RAMEND
-#define E2END      0x7F
-#define E2PAGESIZE 0
-#define FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_FSTRT (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x02
-
-
-#endif  /* _AVR_IO2323_H_ */
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x02
-
diff --git a/cpukit/score/cpu/avr/avr/io2333.h b/cpukit/score/cpu/avr/avr/io2333.h
deleted file mode 100644
index 63c7fab337..0000000000
--- a/cpukit/score/cpu/avr/avr/io2333.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2333.h - definitions for AT90S2333 */
-
-#ifndef _AVR_IO2333_H_
-#define _AVR_IO2333_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2333.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* UART Baud Rate Register high */
-#define UBRRH	_SFR_IO8(0x03)
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control/Status Registers */
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(7)
-#define SIG_SPI				_VECTOR(7)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(8)
-#define SIG_UART_RECV			_VECTOR(8)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(9)
-#define SIG_UART_DATA			_VECTOR(9)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(10)
-#define SIG_UART_TRANS			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(12)
-#define SIG_EEPROM_READY		_VECTOR(12)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(13)
-#define SIG_COMPARATOR			_VECTOR(13)
-
-#define _VECTORS_SIZE 28
-/** @} */
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    WDRF        3
-#define    BORF        2
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1       7
-#define    OCIE1       6
-#define    TICIE1      3
-#define    TOIE0       1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1         6
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM11        7
-#define    COM10        6
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* SPI Control Register */
-#define    SPIE       7
-#define    SPE        6
-#define    DORD       5
-#define    MSTR       4
-#define    CPOL       3
-#define    CPHA       2
-#define    SPR1       1
-#define    SPR0       0
-
-/* SPI Status Register */
-#define    SPIF       7
-#define    WCOL       6
-
-/* UART Status Register */
-#define    RXC        7
-#define    TXC        6
-#define    UDRE       5
-#define    FE         4
-#define    DOR        3
-#define    MPCM       0
-
-/* UART Control Register */
-#define    RXCIE      7
-#define    TXCIE      6
-#define    UDRIE      5
-#define    RXEN       4
-#define    TXEN       3
-#define    CHR9       2
-#define    RXB8       1
-#define    TXB8       0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD        7
-#define    AINBG      6
-#define    ACO        5
-#define    ACI        4
-#define    ACIE       3
-#define    ACIC       2
-#define    ACIS1      1
-#define    ACIS0      0
-
-/* ADC MUX */
-#define    ACDBG      6
-#define    MUX2       2
-#define    MUX1       1
-#define    MUX0       0
-
-/* ADC Control and Status Register */
-#define    ADEN       7
-#define    ADSC       6
-#define    ADFR       5
-#define    ADIF       4
-#define    ADIE       3
-#define    ADPS2      2
-#define    ADPS1      1
-#define    ADPS0      0
-
-/* Data Register, Port B */
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* EEPROM Control Register */
-#define    EERIE     3
-#define    EEMWE     2
-#define    EEWE      1
-#define    EERE      0
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define    RAMEND   0xDF    /*Last On-Chip SRAM location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x7F
-#define    FLASHEND 0x7FF
-/** @} */
-
-#endif /* _AVR_IO2333_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2343.h b/cpukit/score/cpu/avr/avr/io2343.h
deleted file mode 100644
index bee4ad4fa7..0000000000
--- a/cpukit/score/cpu/avr/avr/io2343.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
- * @file avr/io2343.h
- *
- * @brief Definitions for AT90S2343
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO2343_H_
-#define _AVR_IO2343_H_ 1
-
-/**
- *  @defgroup Avr_io2343 AT90S2343 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2343.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-#define _VECTORS_SIZE 6
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt MaSK register */
-#define    INT0    6
-#define    INTF0   6
-
-/* General Interrupt Flag Register */
-#define    TOIE0   1
-#define    TOV0    1
-
-/* MCU general Control Register */
-#define    SE      5
-#define    SM      4
-#define    ISC01   1
-#define    ISC00   0
-
-/* MCU Status Register */
-#define PORF    0
-#define EXTRF   1
-
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
-
-/*
-   PB3 = CLOCK
-   PB2 = SCK/T0
-   PB1 = MISO/INT0
-   PB0 = MOSI
- */
-
-/* Data Register, Port B */
-#define    PB4     4
-#define    PB3     3
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
-
-/* Data Direction Register, Port B */
-#define    DDB4    4
-#define    DDB3    3
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
-
-/* Input Pins, Port B */
-#define    PINB4   4
-#define    PINB3   3
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-
-/* Constants */
-#define RAMEND     0xDF
-#define XRAMEND    RAMEND
-#define E2END      0x7F
-#define E2PAGESIZE 0
-#define FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_RCEN (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x03
-
-
-/**@}*/
-#endif /* _AVR_IO2343_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u32x.h b/cpukit/score/cpu/avr/avr/io43u32x.h
deleted file mode 100644
index ed36ff1010..0000000000
--- a/cpukit/score/cpu/avr/avr/io43u32x.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- * @file avr/io43u32x.h
- *
- * @brief Definitions for AT43USB32x
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2003,2005 Keith Gudger
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO43U32X_H_
-#define _AVR_IO43U32X_H_ 1
-
-/**
- *  @defgroup Avr_io43u32x AT43USB32x Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io43u32x.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* Input Pins, Port E */                  // new port for 43324/6
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C..0x1F reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt Mask register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* Interrupt vectors */
-
-#define SIG_INTERRUPT0		_VECTOR(1)
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_TIMER1_CAPT1	_VECTOR(3)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI				_VECTOR(8)
-#define SIG_UART_RECV		_VECTOR(9)
-#define SIG_UART_DATA    	_VECTOR(10)
-#define SIG_UART_TRANS     	_VECTOR(11)
-#define SIG_USB_INT         _VECTOR(12)
-
-#define _VECTORS_SIZE 52
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TICIE1       3
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TOIE1        7
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag Register */
-#define    ICF1         3
-#define    OCF1A        6
-#define    OCF1B        5
-#define    TOV1         7
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port E */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-
-/* Data Direction Register, Port E */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Input Pins, Port E */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Constants */
-#define    RAMEND   0x025F     /*Last On-Chip SRAM Location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x0000
-
-/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory,
-   but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now...  */
-#define    FLASHEND 0x0FFFF
-
-/**@}*/
-#endif /* _AVR_43USB32X_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u35x.h b/cpukit/score/cpu/avr/avr/io43u35x.h
deleted file mode 100644
index 66a06d867a..0000000000
--- a/cpukit/score/cpu/avr/avr/io43u35x.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/* Copyright (c) 2003,2005 Keith Gudger
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io43u35x.h - definitions for AT43USB35x */
-
-#ifndef _AVR_IO43U35X_H_
-#define _AVR_IO43U35X_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io43u35x.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x02)
-#endif
-#define ADCW  	_SFR_IO16(0x02)
-#define ADCL	_SFR_IO8(0x02)
-#define ADCH	_SFR_IO8(0x03)
-
-/* ADC Control and status register */
-#define ADCSR	_SFR_IO8(0x07)
-
-/* ADC Multiplexer select */
-#define ADMUX	_SFR_IO8(0x08)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* Input Pins, Port F */
-#define PINF	_SFR_IO8(0x04)
-
-/* Data Direction Register, Port F */
-#define DDRF    _SFR_IO8(0x05)
-
-/* Data Register, Port F */
-#define PORTF   _SFR_IO8(0x06)
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C..0x1F reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt Mask register */
-#define GIMSK	_SFR_IO8(0x3B)
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-#define SIG_INTERRUPT0		_VECTOR(1)  /* suspend/resume */
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_TIMER1_CAPT1	_VECTOR(3)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI				_VECTOR(8)
-/* 9, 10: reserved */
-#define SIG_ADC         	_VECTOR(11)
-#define SIG_USB_INT         _VECTOR(12)
-
-#define _VECTORS_SIZE 52
-/** @} */
-
-/*
- * The Register Bit names are represented by their bit number (0-7).
- */
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TICIE1       3
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TOIE1        7
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag Register */
-#define    ICF1         3
-#define    OCF1A        6
-#define    OCF1B        5
-#define    TOV1         7
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port F */
-#define    PF3          3
-#define    PF2          2
-#define    PF1          1
-#define    PF0          0
-
-/* Data Direction Register, Port F */
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-
-/* Input Pins, Port F */
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* ADC Multiplexer select */
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0  
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define    RAMEND   0x045F     /*Last On-Chip SRAM Location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x0000
-#define    FLASHEND 0x5FFF
-/** @} */
-
-#endif /* _AVR_43USB355_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4414.h b/cpukit/score/cpu/avr/avr/io4414.h
deleted file mode 100644
index 96c400030d..0000000000
--- a/cpukit/score/cpu/avr/avr/io4414.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90S4414
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io4414.h - definitions for AT90S4414 */
-
-#ifndef _AVR_IO4414_H_
-#define _AVR_IO4414_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4414.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io4414 AT90S4414 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR   _SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3D SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Compare MatchB */
-#define TIMER1_COMPB_vect		_VECTOR(5)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW1			_VECTOR(6)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(7)
-#define SIG_OVERFLOW0			_VECTOR(7)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(8)
-#define SIG_SPI				_VECTOR(8)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(9)
-#define SIG_UART_RECV			_VECTOR(9)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(10)
-#define SIG_UART_DATA			_VECTOR(10)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(11)
-#define SIG_UART_TRANS			_VECTOR(11)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-#define _VECTORS_SIZE 26
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* General Interrupt MaSK register */
-#define    INT1         7
-#define    INT0         6
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1        7
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TICIE1       3
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1A        6
-#define    OCF1B        5
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants        */
-#define RAMEND       0x15F    /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0xFF
-#define E2PAGESIZE   0
-#define FLASHEND     0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN (unsigned char)~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT (unsigned char)~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x01
-
-/** @} */
-
-#endif /* _AVR_IO4414_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4433.h b/cpukit/score/cpu/avr/avr/io4433.h
deleted file mode 100644
index 62cbb00cd3..0000000000
--- a/cpukit/score/cpu/avr/avr/io4433.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/**
- * @file avr/io4433.h
- *
- * @brief Definitions for AT90S4433
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO4433_H_
-#define _AVR_IO4433_H_ 1
-
-/**
- *  @defgroup Avr_io4433 AT90S4433 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4433.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* UART Baud Rate Register high */
-#define UBRRH	_SFR_IO8(0x03)
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control/Status Registers */
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(7)
-#define SIG_SPI				_VECTOR(7)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(8)
-#define SIG_UART_RECV			_VECTOR(8)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(9)
-#define SIG_UART_DATA			_VECTOR(9)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(10)
-#define SIG_UART_TRANS			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(12)
-#define SIG_EEPROM_READY		_VECTOR(12)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(13)
-#define SIG_COMPARATOR			_VECTOR(13)
-
-#define _VECTORS_SIZE 28
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    WDRF        3
-#define    BORF        2
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1       7
-#define    OCIE1       6
-#define    TICIE1      3
-#define    TOIE0       1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1         6
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM11        7
-#define    COM10        6
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* SPI Control Register */
-#define    SPIE       7
-#define    SPE        6
-#define    DORD       5
-#define    MSTR       4
-#define    CPOL       3
-#define    CPHA       2
-#define    SPR1       1
-#define    SPR0       0
-
-/* SPI Status Register */
-#define    SPIF       7
-#define    WCOL       6
-
-/* UART Status Register */
-#define    RXC        7
-#define    TXC        6
-#define    UDRE       5
-#define    FE         4
-#define    DOR        3
-#define    MPCM       0
-
-/* UART Control Register */
-#define    RXCIE      7
-#define    TXCIE      6
-#define    UDRIE      5
-#define    RXEN       4
-#define    TXEN       3
-#define    CHR9       2
-#define    RXB8       1
-#define    TXB8       0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD        7
-#define    AINBG      6
-#define    ACO        5
-#define    ACI        4
-#define    ACIE       3
-#define    ACIC       2
-#define    ACIS1      1
-#define    ACIS0      0
-
-/* ADC MUX */
-#define    ACDBG      6
-#define    MUX2       2
-#define    MUX1       1
-#define    MUX0       0
-
-/* ADC Control and Status Register */
-#define    ADEN       7
-#define    ADSC       6
-#define    ADFR       5
-#define    ADIF       4
-#define    ADIE       3
-#define    ADPS2      2
-#define    ADPS1      1
-#define    ADPS0      0
-
-/* Data Register, Port B */
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* EEPROM Control Register */
-#define    EERIE     3
-#define    EEMWE     2
-#define    EEWE      1
-#define    EERE      0
-
-/* Constants */
-#define RAMEND     0xDF    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0xFF
-#define E2PAGESIZE 0
-#define FLASHEND   0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)
-#define FUSE_BODEN (unsigned char)~_BV(3)
-#define FUSE_BODLEVEL (unsigned char)~_BV(4)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IO4433_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4434.h b/cpukit/score/cpu/avr/avr/io4434.h
deleted file mode 100644
index 72bc72680d..0000000000
--- a/cpukit/score/cpu/avr/avr/io4434.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/**
- * @file avr/io4434.h
- *
- * @brief Definitions for AT90S4434
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO4434_H_
-#define _AVR_IO4434_H_ 1
-
-/**
- *  @defgroup Avr_io4434 AT90S4434 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4434.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR  	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Asynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control Register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2       7
-#define    TOIE2       6
-#define    TICIE1      5
-#define    OCIE1A      4
-#define    OCIE1B      3
-#define    TOIE1       2
-#define    TOIE0       0
-
-/* Timer/Counter Interrupt Flag register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SE           6
-#define    SM1          5
-#define    SM0          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control Register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Asynchronous mode Status Register */
-#define    AS2          3
-#define    TCN2UB       2
-#define    OCR2UB       1
-#define    TCR2UB       0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7      7
-#define    PA6      6
-#define    PA5      5
-#define    PA4      4
-#define    PA3      3
-#define    PA2      2
-#define    PA1      1
-#define    PA0      0
-
-/* Data Direction Register, Port A */
-#define    DDA7     7
-#define    DDA6     6
-#define    DDA5     5
-#define    DDA4     4
-#define    DDA3     3
-#define    DDA2     2
-#define    DDA1     1
-#define    DDA0     0
-
-/* Input Pins, Port A */
-#define    PINA7    7
-#define    PINA6    6
-#define    PINA5    5
-#define    PINA4    4
-#define    PINA3    3
-#define    PINA2    2
-#define    PINA1    1
-#define    PINA0    0
-
-/* Data Register, Port B */
-#define    PB7      7
-#define    PB6      6
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB7     7
-#define    DDB6     6
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB7    7
-#define    PINB6    6
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC7      7
-#define    PC6      6
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC7     7
-#define    DDC6     6
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC7    7
-#define    PINC6    6
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* SPI Control Register */
-#define    SPIE     7
-#define    SPE     6
-#define    DORD     5
-#define    MSTR     4
-#define    CPOL     3
-#define    CPHA     2
-#define    SPR1     1
-#define    SPR0     0
-
-/* SPI Status Register */
-#define    SPIF     7
-#define    WCOL     6
-
-/* UART Status Register */
-#define    RXC      7
-#define    TXC      6
-#define    UDRE     5
-#define    FE       4
-#define    DOR      3
-
-/* UART Control Register */
-#define    RXCIE    7
-#define    TXCIE    6
-#define    UDRIE    5
-#define    RXEN     4
-#define    TXEN     3
-#define    CHR9     2
-#define    RXB8     1
-#define    TXB8     0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD      7
-#define    ACO      5
-#define    ACI      4
-#define    ACIE     3
-#define    ACIC     2
-#define    ACIS1    1
-#define    ACIS0    0
-
-/* ADC MUX */
-#define    MUX2     2
-#define    MUX1     1
-#define    MUX0     0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0
-
-/* EEPROM Control Register */
-#define    EERIE    3
-#define    EEMWE    2
-#define    EEWE     1
-#define    EERE     0
-
-/* Constants */
-#define RAMEND     0x15F    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0xFF
-#define E2PAGESIZE 0
-#define FLASHEND   0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN ~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT ~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IO4434_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io76c711.h b/cpukit/score/cpu/avr/avr/io76c711.h
deleted file mode 100644
index e0c68e2267..0000000000
--- a/cpukit/score/cpu/avr/avr/io76c711.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT76C711
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io76c711.h - definitions for AT76C711 */
-
-#ifndef _AVR_IO76C711_H_
-#define _AVR_IO76C711_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io76c711.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io76c711 AT76C711 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* 0x00-0x0C reserved */
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Peripheral Enable Register */
-#define PERIPHEN _SFR_IO8(0x13)
-
-/* Clock Control Register */
-#define CLK_CNTR _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* Port A */
-#define PINA	_SFR_IO8(0x19)
-#define DDRA	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C-0x1F reserved */
-
-#define IRDAMOD	_SFR_IO8(0x20)
-
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22-0x25 reserved */
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* 0x30 reserved */
-
-/* Timer 0 */
-#define PRELD	_SFR_IO8(0x31)
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUSR	_SFR_IO8(0x34)
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TIFR	_SFR_IO8(0x36)
-#define TIMSK	_SFR_IO8(0x37)
-
-/* 0x38 reserved */
-
-#define EIMSK	_SFR_IO8(0x39)
-
-/* 0x3A-0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_SUSPEND_RESUME	_VECTOR(1)
-#define SIG_INTERRUPT0		_VECTOR(2)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI			_VECTOR(8)
-#define SIG_TDMAC		_VECTOR(9)
-#define SIG_UART0		_VECTOR(10)
-#define SIG_RDMAC		_VECTOR(11)
-#define SIG_USB_HW		_VECTOR(12)
-#define SIG_UART1		_VECTOR(13)
-#define SIG_INTERRUPT1		_VECTOR(14)
-
-#define _VECTORS_SIZE 60
-
-/* Bit numbers */
-
-/* EIMSK */
-/* bits 7-4 reserved */
-#define POL1	3
-#define POL0	2
-#define INT1	1
-#define INT0	0
-
-/* TIMSK */
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B	5
-/* bit 4 reserved */
-#define TICIE1	3
-/* bit 2 reserved */
-#define TOIE0	1
-/* bit 0 reserved */
-
-/* TIFR */
-#define TOV1	7
-#define OCF1A	6
-#define OCF1B	5
-/* bit 4 reserved */
-#define ICF1	3
-/* bit 2 reserved */
-#define TOV0	1
-/* bit 0 reserved */
-
-/* MCUCR */
-/* bits 7-6 reserved */
-#define SE	5
-#define SM1	4
-#define SM0	3
-/* bits 2-0 reserved */
-
-/* MCUSR */
-/* bits 7-2 reserved */
-#define EXTRF	1
-#define PORF	0
-
-/* TCCR0 */
-/* bits 7-6 reserved */
-#define COM01	5
-#define COM00	4
-#define CTC0	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-/* bits 3-0 reserved */
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bits 5-4 reserved */
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* IRDAMOD */
-/* bits 7-3 reserved */
-#define POL	2
-#define MODE	1
-#define EN	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB2 = ICP
-   PB1 = T1
-   PB0 = T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTC */
-/* bits 7-4 reserved */
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/*
-   PD7 = INT1 / OC1B
-   PD6 = INT0 / OC1A
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* CLK_CNTR */
-/* bits 7-5 reserved */
-#define UOSC	4
-#define UCK	3
-#define IRCK	2
-/* bits 1-0 reserved */
-
-/* PERIPHEN */
-/* bits 7-3 reserved */
-#define IRDA	2
-#define UART	1
-#define USB	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-/* bits 5-0 reserved */
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */
-
-/* UART */
-#define UART0_BASE 0x2020
-#define UART1_BASE 0x2030
-/* offsets from the base address */
-#define US_RHR		0x00
-#define US_THR		0x00
-#define US_IER		0x01
-#define US_FCR		0x02
-#define US_PMR		0x03
-#define US_MR		0x04
-#define US_CSR		0x05
-#define US_CR		0x06
-#define US_BL		0x07
-#define US_BM		0x08
-#define US_RTO		0x09
-#define US_TTG		0x0A
-
-/* DMA */
-#define DMA_BASE 0x2000
-/* offsets from the base address */
-#define TXTADL		0x01
-#define TXPLL		0x03
-#define TXPLM		0x04
-#define TXTPLL		0x05
-#define TXTPLM		0x06
-#define RXTADL		0x07
-#define RXTADMEN	0x08
-#define RSPLL		0x09
-#define RXPLM		0x0A
-#define RXTPLL		0x0B
-#define RXTPLM		0x0C
-#define INTCST		0x0D
-/* XXX DPORG register mentioned on page 20, but undocumented */
-
-/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */
-#define PROGRAM_MEMORY_CONTROL_BIT 0x2040
-
-/* USB */
-#define USB_BASE 0x1000
-/* offsets from the base address */
-#define FRM_NUM_H	0x0FD
-#define FRM_NUM_L	0x0FC
-#define GLB_STATE	0x0FB
-#define SPRSR		0x0FA
-#define SPRSIE		0x0F9
-#define UISR		0x0F7
-#define UIAR		0x0F5
-#define FADDR		0x0F2
-#define ENDPPGPG	0x0F1
-#define ECR0		0x0EF
-#define ECR1		0x0EE
-#define ECR2		0x0ED
-#define ECR3		0x0EC
-#define ECR4		0x0EB
-#define ECR5		0x0EA
-#define ECR6		0x0E9
-#define ECR7		0x0E8
-#define CSR0		0x0DF
-#define CSR1		0x0DE
-#define CSR2		0x0DD
-#define CSR3		0x0DC
-#define CSR4		0x0DB
-#define CSR5		0x0DA
-#define CSR6		0x0D9
-#define CSR7		0x0D8
-#define FDR0		0x0CF
-#define FDR1		0x0CE
-#define FDR2		0x0CD
-#define FDR3		0x0CC
-#define FDR4		0x0CB
-#define FDR5		0x0CA
-#define FDR6		0x0C9
-#define FDR7		0x0C8
-#define FBYTE_CNT0_L	0x0BF
-#define FBYTE_CNT1_L	0x0BE
-#define FBYTE_CNT2_L	0x0BD
-#define FBYTE_CNT3_L	0x0BC
-#define FBYTE_CNT4_L	0x0BB
-#define FBYTE_CNT5_L	0x0BA
-#define FBYTE_CNT6_L	0x0B9
-#define FBYTE_CNT7_L	0x0B8
-#define FBYTE_CNT0_H	0x0AF
-#define FBYTE_CNT1_H	0x0AE
-#define FBYTE_CNT2_H	0x0AD
-#define FBYTE_CNT3_H	0x0AC
-#define FBYTE_CNT4_H	0x0AB
-#define FBYTE_CNT5_H	0x0AA
-#define FBYTE_CNT6_H	0x0A9
-#define FBYTE_CNT7_H	0x0A8
-#define SLP_MD_EN	0x100
-#define IRQ_EN		0x101
-#define IRQ_STAT	0x102
-#define SUSP_WUP	0x103
-#define PA_EN		0x104
-#define USB_DMA_ADL	0x105
-#define USB_DMA_ADH	0x106
-#define USB_DMA_PLR	0x107
-#define USB_DMA_EAD	0x108
-#define USB_DMA_PLT	0x109
-#define USB_DMA_EN	0x10A
-
-/* Last memory addresses */
-#define RAMEND		0x07FF
-#define XRAMEND		RAMEND
-#define E2END		0
-#define FLASHEND	0x3FFF
-
-/*
-   AT76C711 data space memory map (ranges not listed are reserved):
-   0x0000 - 0x001F - AVR registers
-   0x0020 - 0x005F - AVR I/O space
-   0x0060 - 0x07FF - AVR data SRAM
-   0x1000 - 0x1FFF - USB (not all locations used)
-   0x2000 - 0x201F - DMA controller
-   0x2020 - 0x202F - UART0
-   0x2030 - 0x203F - UART1 (IRDA)
-   0x2040          - the mysterious Program Memory Control bit (???)
-   0x3000 - 0x37FF - DPRAM
-   0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
-                     AVR devices did that as well (no need to use LPM!)
- */
-
-/** @} */
-
-#endif /* _AVR_IO76C711_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8515.h b/cpukit/score/cpu/avr/avr/io8515.h
deleted file mode 100644
index 305224d201..0000000000
--- a/cpukit/score/cpu/avr/avr/io8515.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io8515.h - definitions for AT90S8515 */
-
-#ifndef _AVR_IO8515_H_
-#define _AVR_IO8515_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8515.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR   _SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Compare MatchB */
-#define TIMER1_COMPB_vect		_VECTOR(5)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW1			_VECTOR(6)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(7)
-#define SIG_OVERFLOW0			_VECTOR(7)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(8)
-#define SIG_SPI				_VECTOR(8)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(9)
-#define SIG_UART_RECV			_VECTOR(9)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(10)
-#define SIG_UART_DATA			_VECTOR(10)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(11)
-#define SIG_UART_TRANS			_VECTOR(11)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-#define _VECTORS_SIZE 26
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* General Interrupt MaSK register */
-#define    INT1         7
-#define    INT0         6
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1        7
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TICIE1       3
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1A        6
-#define    OCF1B        5
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants        */
-#define RAMEND       0x25F    /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x1FF
-#define E2PAGESIZE   0
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN ~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT ~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x01
-
-
-#endif /* _AVR_IO8515_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8534.h b/cpukit/score/cpu/avr/avr/io8534.h
deleted file mode 100644
index c873a71430..0000000000
--- a/cpukit/score/cpu/avr/avr/io8534.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90C8534
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io8534.h - definitions for AT90C8534 */
-
-#ifndef _AVR_IO8534_
-#define _AVR_IO8534_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8534.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io8534 AT90C8534 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* 0x00..0x03 reserved */
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC Multiplexer Select Register */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* 0x08..0x0F reserved */
-
-/* General Interrupt Pin Register */
-#define GIPR	_SFR_IO8(0x10)
-
-/* 0x11..0x19 reserved */
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* 0x20..0x2B reserved */
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register */
-#define TCCR1	_SFR_IO8(0x2E)
-
-/* 0x2F..0x31 reserved */
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_INTERRUPT0		_VECTOR(1)
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_OVERFLOW1		_VECTOR(3)
-#define SIG_OVERFLOW0		_VECTOR(4)
-#define SIG_ADC			_VECTOR(5)
-#define SIG_EEPROM_READY	_VECTOR(6)
-
-#define _VECTORS_SIZE 14
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-
-/* GIPR */
-#define IPIN1	3
-#define IPIN0	2
-
-/* TIMSK */
-#define TOIE1	2
-#define TOIE0	0
-
-/* TIFR */
-#define TOV1	2
-#define TOV0	0
-
-/* MCUCR */
-#define SE	6
-#define SM	5
-#define ISC1	2
-#define ISC0	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR1 */
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Last memory addresses */
-#define RAMEND		0x15F
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define FLASHEND	0x1FFF
-
-/** @} */
-
-#endif /* _AVR_IO8534_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8535.h b/cpukit/score/cpu/avr/avr/io8535.h
deleted file mode 100644
index cf31f00c32..0000000000
--- a/cpukit/score/cpu/avr/avr/io8535.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/**
- * @file avr/io8535.h
- *
- * @brief Definitions for AT90S8535
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO8535_H_
-#define _AVR_IO8535_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8535.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_io8535 AT90S8535 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR  	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Asynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control Register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2       7
-#define    TOIE2       6
-#define    TICIE1      5
-#define    OCIE1A      4
-#define    OCIE1B      3
-#define    TOIE1       2
-#define    TOIE0       0
-
-/* Timer/Counter Interrupt Flag register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SE           6
-#define    SM1          5
-#define    SM0          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control Register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Asynchronous mode Status Register */
-#define    AS2          3
-#define    TCN2UB       2
-#define    OCR2UB       1
-#define    TCR2UB       0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7      7
-#define    PA6      6
-#define    PA5      5
-#define    PA4      4
-#define    PA3      3
-#define    PA2      2
-#define    PA1      1
-#define    PA0      0
-
-/* Data Direction Register, Port A */
-#define    DDA7     7
-#define    DDA6     6
-#define    DDA5     5
-#define    DDA4     4
-#define    DDA3     3
-#define    DDA2     2
-#define    DDA1     1
-#define    DDA0     0
-
-/* Input Pins, Port A */
-#define    PINA7    7
-#define    PINA6    6
-#define    PINA5    5
-#define    PINA4    4
-#define    PINA3    3
-#define    PINA2    2
-#define    PINA1    1
-#define    PINA0    0
-
-/* Data Register, Port B */
-#define    PB7      7
-#define    PB6      6
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB7     7
-#define    DDB6     6
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB7    7
-#define    PINB6    6
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC7      7
-#define    PC6      6
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC7     7
-#define    DDC6     6
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC7    7
-#define    PINC6    6
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* SPI Control Register */
-#define    SPIE     7
-#define    SPE     6
-#define    DORD     5
-#define    MSTR     4
-#define    CPOL     3
-#define    CPHA     2
-#define    SPR1     1
-#define    SPR0     0
-
-/* SPI Status Register */
-#define    SPIF     7
-#define    WCOL     6
-
-/* UART Status Register */
-#define    RXC      7
-#define    TXC      6
-#define    UDRE     5
-#define    FE       4
-#define    DOR      3
-
-/* UART Control Register */
-#define    RXCIE    7
-#define    TXCIE    6
-#define    UDRIE    5
-#define    RXEN     4
-#define    TXEN     3
-#define    CHR9     2
-#define    RXB8     1
-#define    TXB8     0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD      7
-#define    ACO      5
-#define    ACI      4
-#define    ACIE     3
-#define    ACIC     2
-#define    ACIS1    1
-#define    ACIS0    0
-
-/* ADC MUX */
-#define    MUX2     2
-#define    MUX1     1
-#define    MUX0     0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0
-
-/* EEPROM Control Register */
-#define    EERIE    3
-#define    EEMWE    2
-#define    EEWE     1
-#define    EERE     0
-
-/* Constants */
-#define RAMEND     0x25F    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0x1FF
-#define E2PAGESIZE 0
-#define FLASHEND   0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN (unsigned char)~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT (unsigned char)~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x03
-
-/** @} */
-#endif /* _AVR_IO8535_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io86r401.h b/cpukit/score/cpu/avr/avr/io86r401.h
deleted file mode 100644
index 56f2d568f3..0000000000
--- a/cpukit/score/cpu/avr/avr/io86r401.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/**
- * @file avr/io86r401.h
- *
- * @brief Definitions for AT86RF401
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Colin O'Flynn
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO86RF401_H_
-#define _AVR_IO86RF401_H_ 1
-
-/**
- *  @defgroup Avr_io86r401 AT86RF401 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io86r401.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#include <avr/sfr_defs.h>
-
-/* Status REGister */
-#define SREG    _SFR_IO8(0x3F)
-
-/* Stack Pointer */
-#define SP      _SFR_IO16(0x3D)
-#define SPH     _SFR_IO8(0x3E)
-#define SPL     _SFR_IO8(0x3D)
-
-/*Battery low configeration register */
-#define BL_CONFIG       _SFR_IO8(0x35)
-
-/*Button detect register*/
-#define B_DET           _SFR_IO8(0x34)
-
-/*AVR Configeration register*/
-#define AVR_CONFIG      _SFR_IO8(0x33)
-
-/* I/O registers */
-
-/*Data in register */
-#define IO_DATIN        _SFR_IO8(0x32)
-
-/*Data out register */
-#define IO_DATOUT       _SFR_IO8(0x31)
-
-/*IO Enable register */
-#define IO_ENAB         _SFR_IO8(0x30)
-
-/* Watchdog Timer Control Register */
-#define WDTCR           _SFR_IO8(0x22)
-
-/* Bit Timer Control Register */
-#define BTCR            _SFR_IO8(0x21)
-
-#define BTCNT           _SFR_IO8(0x20)
-
-/*
-NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
-you may want to remove the leading D.
-*/
-/* EEPROM Control Register */
-
-/* EEPROM Address Register */
-#define DEEAR           _SFR_IO8(0x1E)
-#define DEEARL          _SFR_IO8(0x1E)
-
-/* EEPROM Data Register */
-#define DEEDR           _SFR_IO8(0x1D)
-/* EEPROM Control Register */
-#define DEECR           _SFR_IO8(0x1C)
-
-/* Lock Detector Configuration Register 2 */
-#define LOCKDET2        _SFR_IO8(0x17)
-
-/* VCO Tuning Register*/
-#define VCOTUNE         _SFR_IO8(0x16)
-
-/* Power Attenuation Control Register */
-#define PWR_ATTEN       _SFR_IO8(0x14)
-
-/* Transmitter Control Register */
-#define TX_CNTL         _SFR_IO8(0x12)
-
-/* Lock Detector Configuration Register 1 */
-#define LOCKDET1        _SFR_IO8(0x10)
-
-
-/* Interrupt vectors */
-
-/* Transmission Done, Bit Timer Flag 2 Interrupt */
-#define TXDONE_vect			_VECTOR(1)
-#define SIG_TXDONE			_VECTOR(1)
-
-/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */
-#define TXEMPTY_vect			_VECTOR(2)
-#define SIG_TXBE			_VECTOR(2)
-
-#define _VECTORS_SIZE 12
-
-/*
- *  The Register Bit names are represented by their bit number (0-7).
- */
-
-/* Lock Detector Configuration Register 1 - LOCKDET1 */
-#define UPOK    4
-#define ENKO    3
-#define BOD     2
-#define CS1     1
-#define CS0     0
-
-/* Transmit Control Register - TX_CNTL */
-#define TXE     5
-#define TXK     4
-#define LOC     2
-
-/* Power Attenuation Control Register - PWR_ATTEN */
-#define PCC2        5
-#define PCC1        4
-#define PCC0        3
-#define PCF2        2
-#define PCF1        1
-#define PCF0        0
-
-/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/
-#define VCOVDET1        7
-#define VCOVDET0        6
-#define VCOTUNE4        4
-#define VCOTUNE3        3
-#define VCOTUNE2        2
-#define VCOTUNE1        1
-#define VCOTUNE0        0
-
-/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/
-#define EUD         7
-#define LAT         6
-#define ULC2        5
-#define ULC1        4
-#define ULC0        3
-#define LC2         2
-#define LC1         1
-#define LC0         0
-
-/* Data EEPROM Control Register - DEECR */
-#define BSY         3
-#define EEU         2
-#define EEL         1
-#define EER         0
-
-/* Data EEPROM Data Register - DEEDR */
-#define ED7         7
-#define ED6         6
-#define ED5         5
-#define ED4         4
-#define ED3         3
-#define ED2         2
-#define ED1         1
-#define ED0         0
-
-/* Data EEPROM Address Register - DEEAR */
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define BA2     2  /* B is not a typo! */
-#define BA1     1
-#define BA0     0
-
-/* Bit Timer Count Register - BTCNT */
-#define C7      7
-#define C6      6
-#define C5      5
-#define C4      4
-#define C3      3
-#define C2      2
-#define C1      1
-#define C0      0
-
-/* Bit Timer Control Register - BTCR */
-#define C9      7
-#define C8      6
-#define M1      5
-#define M0      4
-#define IE      3
-#define F2      2
-#define DATA    1
-#define F0      0
-
-/* Watchdog Timer Control Register - WDTCR */
-#define WDTOE       4
-#define WDE         3
-#define WDP2        2
-#define WDP1        1
-#define WDP0        0
-
-/* I/O Enable Register - IO_ENAB */
-#define BOHYST      6
-#define IOE5        5
-#define IOE4        4
-#define IOE3        3
-#define IOE2        2
-#define IOE1        1
-#define IOE0        0
-
-/* Note: No PORTB or whatever, this is the equivalent. */
-/* I/O Data Out Register - IO_DATOUT */
-#define IOO5     5
-#define IOO4     4
-#define IOO3     3
-#define IOO2     2
-#define IOO1     1
-#define IOO0     0
-
-/* Note: No PINB or whatever, this is the equivalent. */
-/* I/O Data In Register - IO_DATIN */
-#define IOI5     5
-#define IOI4     4
-#define IOI3     3
-#define IOI2     2
-#define IOI1     1
-#define IOI0     0
-
-/* AVR Configuration Register - AVR_CONFIG */
-#define ACS1    6
-#define ACS0    5
-#define TM      4
-#define BD      3
-#define BLI     2
-#define SLEEP   1
-#define BBM     0
-
-/* Button Detect Register - B_DET */
-#define BD5     5
-#define BD4     4
-#define BD3     3
-#define BD2     2
-#define BD1     1
-#define BD0     0
-
-/* Battery Low Configuration Register - BL_CONFIG */
-#define BL      7
-#define BLV     6
-#define BL5     5
-#define BL4     4
-#define BL3     3
-#define BL2     2
-#define BL1     1
-#define BL0     0
-
-/* Pointer definition   */
-#define XL      r26
-#define XH      r27
-#define YL      r28
-#define YH      r29
-#define ZL      r30
-#define ZH      r31
-
-/* Constants */
-#define RAMEND      0xDF
-#define XRAMEND     RAMEND
-#define E2END       0x7F
-#define E2PAGESIZE  0
-#define FLASHEND    0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 0
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x81
-
-/**@}*/
-#endif  /* _AVR_IO86RF401_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm1.h b/cpukit/score/cpu/avr/avr/io90pwm1.h
deleted file mode 100644
index 6c3aad03a5..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm1.h
+++ /dev/null
@@ -1,1137 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2005, Andrey Pashchenko
-   Copyright (c) 2007, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iopwm1.h - definitions for AT90PWM1 device */
-
-#ifndef _AVR_IOPWM1_H_
-#define _AVR_IOPWM1_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iopwm1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm1 AT90PWM1 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Reserved [0x00..0x02] */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Reserved [0x06..0x08] */
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-/* PINE */
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-/* DDRE */
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-/* PORTE */
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-/* Reserved [0x0F..0x14] */
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-/* TIFR0 */
-#define OCF0B   2   /* Output Compare Flag 0B */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define TOV0    0   /* Overflow Flag */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-/* TIFR1 */
-#define ICF1    5   /* Input Capture Flag 1 */
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define TOV1    0   /* Overflow Flag */
-
-/* Reserved [0x17..0x18] */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-/* GPIOR1 */
-#define GPIOR17 7
-#define GPIOR16 6
-#define GPIOR15 5
-#define GPIOR14 4
-#define GPIOR13 3
-#define GPIOR12 2
-#define GPIOR11 1
-#define GPIOR10 0
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-/* GPIOR2 */
-#define GPIOR27 7
-#define GPIOR26 6
-#define GPIOR25 5
-#define GPIOR24 4
-#define GPIOR23 3
-#define GPIOR22 2
-#define GPIOR21 1
-#define GPIOR20 0
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-/* GPIOR3 */
-#define GPIOR37 7
-#define GPIOR36 6
-#define GPIOR35 5
-#define GPIOR34 4
-#define GPIOR33 3
-#define GPIOR32 2
-#define GPIOR31 1
-#define GPIOR30 0
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-/* EIFR */
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-/* EIMSK */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT0    0   /* External Interrupt Request 0 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-/* GPIOR0 */
-#define GPIOR07 7
-#define GPIOR06 6
-#define GPIOR05 5
-#define GPIOR04 4
-#define GPIOR03 3
-#define GPIOR02 2
-#define GPIOR01 1
-#define GPIOR00 0
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-/* EECR */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EERE    0   /* EEPROM Read Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-/* EEDR */
-#define EEDR7   7
-#define EEDR6   6
-#define EEDR5   5
-#define EEDR4   4
-#define EEDR3   3
-#define EEDR2   2
-#define EEDR1   1
-#define EEDR0   0
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-/* EEARH */
-#define EEAR11  3
-#define EEAR10  2
-#define EEAR9   1
-#define EEAR8   0
-/* EEARL */
-#define EEAR7   7
-#define EEAR6   6
-#define EEAR5   5
-#define EEAR4   4
-#define EEAR3   3
-#define EEAR2   2
-#define EEAR1   1
-#define EEAR0   0
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-/* GTCCR */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define PSRSYNC 0
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-/* TCCR0A */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define WGM01   1   /* Waveform Generation Mode */
-#define WGM00   0   /* Waveform Generation Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-/* TCCR0B */
-#define FOC0A   7   /* Force Output Compare A */
-#define FOC0B   6   /* Force Output Compare B */
-#define WGM02   3   /* Waveform Generation Mode */
-#define CS02    2   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS00    0   /* Clock Select */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-/* TCNT0 */
-#define TCNT07  7
-#define TCNT06  6
-#define TCNT05  5
-#define TCNT04  4
-#define TCNT03  3
-#define TCNT02  2
-#define TCNT01  1
-#define TCNT00  0
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-/* OCR0A */
-#define OCR0A7  7
-#define OCR0A6  6
-#define OCR0A5  5
-#define OCR0A4  4
-#define OCR0A3  3
-#define OCR0A2  2
-#define OCR0A1  1
-#define OCR0A0  0
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-/* OCR0B */
-#define OCR0B7  7
-#define OCR0B6  6
-#define OCR0B5  5
-#define OCR0B4  4
-#define OCR0B3  3
-#define OCR0B2  2
-#define OCR0B1  1
-#define OCR0B0  0
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-/* PLLCSR */
-#define PLLF    2
-#define PLLE    1   /* PLL Enable */
-#define PLOCK   0   /* PLL Lock Detector */
-
-/* Reserved [0x2A..0x2B] */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-/* SPCR */
-#define SPIE    7   /* SPI Interrupt Enable */
-#define SPE     6   /* SPI Enable */
-#define DORD    5   /* Data Order */
-#define MSTR    4   /* Master/Slave Select */
-#define CPOL    3   /* Clock polarity */
-#define CPHA    2   /* Clock Phase */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-/* SPSR */
-#define SPIF    7   /* SPI Interrupt Flag */
-#define WCOL    6   /* Write Collision Flag */
-#define SPI2X   0   /* Double SPI Speed Bit */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-/* SPDR */
-#define SPD7    7
-#define SPD6    6
-#define SPD5    5
-#define SPD4    4
-#define SPD3    3
-#define SPD2    2
-#define SPD1    1
-#define SPD0    0
-
-/* Reserved [0x2F] */
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-/* ACSR */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-
-/* Monitor Data Register */
-#define MONDR   _SFR_IO8(0x31)
-
-/* Monitor Stop Mode Control Register */
-#define MSMCR   _SFR_IO8(0x32)
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-/* SMCR */
-#define SM2     3   /* Sleep Mode Select bit2 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SE      0   /* Sleep Enable */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-/* MCUSR */
-#define WDRF    3   /* Watchdog Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define EXTRF   1   /* External Reset Flag */
-#define PORF    0   /* Power-on reset flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-/* MCUCR */
-#define SPIPS   7   /* SPI Pin Select */
-#define PUD     4   /* Pull-up disable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define IVCE    0   /* Interrupt Vector Change Enable */
-
-/* Reserved [0x36] */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-/* SPMCSR */
-#define SPMIE   7   /* SPM Interrupt Enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define PGWRT   2   /* Page Write */
-#define PGERS   1   /* Page Erase */
-#define SPMEN   0   /* Store Program Memory Enable */
-
-/* Reserved [0x38..0x3C] */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-/* WDTCSR */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDE     3   /* Watchdog Enable */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-/* CLKPR */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-
-/* Reserved [0x62..0x63] */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-/* PRR */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRADC   0   /* Power Reduction ADC */
-
-/* Reserved [0x65] */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-/* OSCCAL */
-#define CAL6    6
-#define CAL5    5
-#define CAL4    4
-#define CAL3    3
-#define CAL2    2
-#define CAL1    1
-#define CAL0    0
-
-/* Reserved [0x67..0x68] */
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-/* EICRA */
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Reserved [0x6A..0x6D] */
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-/* TIMSK0 */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE0   0   /* Overflow Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-/* TIMSK1 */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE1   0   /* Overflow Interrupt Enable */
-
-/* Reserved [0x70..0x75] */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0EN  7
-#define AMP0IS  6
-#define AMP0G1  5
-#define AMP0G0  4
-#define AMP0TS1 1
-#define AMP0TS0 0
-
-/* Reserved [0x77] */
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-/* ADCSRA */
-#define ADEN    7   /* ADC Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-/* ADCSRB */
-#define ADTS3   3   /* ADC Auto Trigger Source 2 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-/* ADMUX */
-#define REFS1   7   /* Reference Selection bit1 */
-#define REFS0   6   /* Reference Selection bit0 */
-#define ADLAR   5   /* Left Adjust Result */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-
-/* Reserved [0x7D] */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-/* DIDR0 */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC0D   0   /* ADC0 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-/* DIDR1 */
-#define ACMP0D  5
-#define AMP0PD  4
-#define AMP0ND  3
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC8D   0   /* ADC8 Digital input Disable */
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-/* TCCR1A */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define WGM11   1   /* Waveform Generation Mode */
-#define WGM10   0   /* Waveform Generation Mode */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-/* TCCR1B */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define WGM13   4   /* Waveform Generation Mode */
-#define WGM12   3   /* Waveform Generation Mode */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-/* TCCR1C */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-#define FOC1B   6   /* Force Output Compare for Channel B */
-
-/* Reserved [0x83] */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-/* TCNT1H */
-#define TCNT115 7
-#define TCNT114 6
-#define TCNT113 5
-#define TCNT112 4
-#define TCNT111 3
-#define TCNT110 2
-#define TCNT19  1
-#define TCNT18  0
-/* TCNT1L */
-#define TCNT17  7
-#define TCNT16  6
-#define TCNT15  5
-#define TCNT14  4
-#define TCNT13  3
-#define TCNT12  2
-#define TCNT11  1
-#define TCNT10  0
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-/* ICR1H */
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-/* ICR1L */
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-/* OCR1AH */
-#define OCR1A15 7
-#define OCR1A14 6
-#define OCR1A13 5
-#define OCR1A12 4
-#define OCR1A11 3
-#define OCR1A10 2
-#define OCR1A9  1
-#define OCR1A8  0
-/* OCR1AL */
-#define OCR1A7  7
-#define OCR1A6  6
-#define OCR1A5  5
-#define OCR1A4  4
-#define OCR1A3  3
-#define OCR1A2  2
-#define OCR1A1  1
-#define OCR1A0  0
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-/* OCR1BH */
-#define OCR1B15 7
-#define OCR1B14 6
-#define OCR1B13 5
-#define OCR1B12 4
-#define OCR1B11 3
-#define OCR1B10 2
-#define OCR1B9  1
-#define OCR1B8  0
-/* OCR1BL */
-#define OCR1B7  7
-#define OCR1B6  6
-#define OCR1B5  5
-#define OCR1B4  4
-#define OCR1B3  3
-#define OCR1B2  2
-#define OCR1B1  1
-#define OCR1B0  0
-
-/* Reserved [0x8C..0x9F] */
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-/* PIFR0 */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-/* PIM0 */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-
-/* Reserved [0xA2..0xA3] */
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-/* PIFR2 */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-/* PIM2 */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-
-/* Reserved [0xA6..0xAC] */
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-/* AC0CON */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-
-/* Reserved [0xB0..0xAE] */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-/* AC2CON */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-
-/* Reserved [0xB0..0xCF] */
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-/* PSOC0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-
-/* Reserved [0xD1] */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-/* PCNF0 */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-/* PCTL0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PRUN0   0   /* PSC 0 Run */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-/* PFRC0A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-/* PFRC0B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-
-#define PICR0L  _SFR_MEM8(0xDE)
-
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* Reserved [0xE0..0xEF] */
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-/* PSOC2 */
-#define POS23   7   /* PSCOUT23 Selection */
-#define POS22   6   /* PSCOUT22 Selection */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-/* POM2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-/* PCNF2 */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-/* PCTL2 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PRUN2   0   /* PSC 2 Run */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-/* PFRC2A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-/* PFRC2B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-
-#define PICR2L  _SFR_MEM8(0xFE)
-
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-
-/* Interrupt vectors */
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect			_VECTOR(1)
-#define SIG_PSC2_CAPTURE		_VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect			_VECTOR(2)
-#define SIG_PSC2_END_CYCLE		_VECTOR(2)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect			_VECTOR(5)
-#define SIG_PSC0_CAPTURE		_VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect			_VECTOR(6)
-#define SIG_PSC0_END_CYCLE		_VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect		_VECTOR(7)
-#define SIG_COMPARATOR0			_VECTOR(7)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect		_VECTOR(9)
-#define SIG_COMPARATOR2			_VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(10)
-#define SIG_INTERRUPT0			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1_A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1_B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0_A		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(18)
-#define SIG_ADC				_VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(19)
-#define SIG_INTERRUPT1			_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(24)
-#define SIG_INTERRUPT2			_VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(25)
-#define SIG_WDT				_VECTOR(25)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0_B		_VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(28)
-#define SIG_INTERRUPT3			_VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(31)
-#define SIG_SPM_READY			_VECTOR(31)
-
-#define _VECTORS_SIZE   64
-
-/* Constants */
-#define SPM_PAGESIZE    64
-
-#define RAMEND      0x02FF
-#define XRAMEND     RAMEND
-#define E2END       0x01FF
-#define FLASHEND    0x0FFF
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
-#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_PSCRV       (unsigned char)~_BV(4)
-#define FUSE_PSC0RB      (unsigned char)~_BV(5)
-#define FUSE_PSC2RB      (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-/** @} */
-
-#endif /* _AVR_IOPWM1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm216.h b/cpukit/score/cpu/avr/avr/io90pwm216.h
deleted file mode 100644
index c6befa4081..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm216.h
+++ /dev/null
@@ -1,1197 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM216
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm216.h - definitions for AT90PWM216 */
-
-#ifndef _AVR_IO90PWM216_H_
-#define _AVR_IO90PWM216_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm216.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm216 AT90PWM216 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-#define PINE0   0
-#define PINE1   1
-#define PINE2   2
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE0    0
-#define DDE1    1
-#define DDE2    2
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-#define PE0     0
-#define PE1     1
-#define PE2     2
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0   /* Overflow Flag */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define OCF0B   2   /* Output Compare Flag 0B */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0   /* Overflow Flag */
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define ICF1    5   /* Input Capture Flag 1 */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-#define INTF2   2
-#define INTF3   3
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0   /* External Interrupt Request 0 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0   /* EEPROM Read Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEAR0   0
-#define EEAR1   1
-#define EEAR2   2
-#define EEAR3   3
-#define EEAR4   4
-#define EEAR5   5
-#define EEAR6   6
-#define EEAR7   7
-#define EEARH   _SFR_IO8(0x22)
-#define EEAR8   0
-#define EEAR9   1
-#define EEAR10  2
-#define EEAR11  3
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0   /* Waveform Generation Mode */
-#define WGM01   1   /* Waveform Generation Mode */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS02    2   /* Clock Select */
-#define WGM02   3   /* Waveform Generation Mode */
-#define FOC0B   6   /* Force Output Compare B */
-#define FOC0A   7   /* Force Output Compare A */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-#define OCR0A0  0
-#define OCR0A1  1
-#define OCR0A2  2
-#define OCR0A3  3
-#define OCR0A4  4
-#define OCR0A5  5
-#define OCR0A6  6
-#define OCR0A7  7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-#define OCR0B0  0
-#define OCR0B1  1
-#define OCR0B2  2
-#define OCR0B3  3
-#define OCR0B4  4
-#define OCR0B5  5
-#define OCR0B6  6
-#define OCR0B7  7
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0   /* PLL Lock Detector */
-#define PLLE    1   /* PLL Enable */
-#define PLLF    2   /* PLL Factor */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define CPHA    2   /* Clock Phase */
-#define CPOL    3   /* Clock polarity */
-#define MSTR    4   /* Master/Slave Select */
-#define DORD    5   /* Data Order */
-#define SPE     6   /* SPI Enable */
-#define SPIE    7   /* SPI Interrupt Enable */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0   /* Double SPI Speed Bit */
-#define WCOL    6   /* Write Collision Flag */
-#define SPIF    7   /* SPI Interrupt Flag */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-#define SPD0    0
-#define SPD1    1
-#define SPD2    2
-#define SPD3    3
-#define SPD4    4
-#define SPD5    5
-#define SPD6    6
-#define SPD7    7
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0   /* Sleep Enable */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM2     3   /* Sleep Mode Select bit2 */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0   /* Power-on reset flag */
-#define EXTRF   1   /* External Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define WDRF    3   /* Watchdog Reset Flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0   /* Interrupt Vector Change Enable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define PUD     4   /* Pull-up disable */
-#define SPIPS   7   /* SPI Pin Select */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0   /* Store Program Memory Enable */
-#define PGERS   1   /* Page Erase */
-#define PGWRT   2   /* Page Write */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define SPMIE   7   /* SPM Interrupt Enable */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDE     3   /* Watchdog Enable */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0   /* Power Reduction ADC */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define ISC20   4
-#define ISC21   5
-#define ISC30   6
-#define ISC31   7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0   /* Overflow Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0   /* Overflow Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0  4
-#define AMP0G1  5
-#define AMP0IS  6
-#define AMP0EN  7
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0  4
-#define AMP1G1  5
-#define AMP1IS  6
-#define AMP1EN  7
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADEN    7   /* ADC Enable */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADHSM   7   /* ADC High Speed Mode */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define ADLAR   5   /* Left Adjust Result */
-#define REFS0   6   /* Reference Selection bit0 */
-#define REFS1   7   /* Reference Selection bit1 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0   /* ADC0 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   0   /* ADC8 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define AMP0ND  3
-#define AMP0PD  4
-#define ACMP0D  5
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0   /* Waveform Generation Mode */
-#define WGM11   1   /* Waveform Generation Mode */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define WGM12   3   /* Waveform Generation Mode */
-#define WGM13   4   /* Waveform Generation Mode */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6   /* Force Output Compare for Channel B */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT10  0
-#define TCNT11  1
-#define TCNT12  2
-#define TCNT13  3
-#define TCNT14  4
-#define TCNT15  5
-#define TCNT16  6
-#define TCNT17  7
-#define TCNT1H  _SFR_MEM8(0x85)
-#define TCNT18  0
-#define TCNT19  1
-#define TCNT110 2
-#define TCNT111 3
-#define TCNT112 4
-#define TCNT113 5
-#define TCNT114 6
-#define TCNT115 7
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-#define ICR1H   _SFR_MEM8(0x87)
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1A0  0
-#define OCR1A1  1
-#define OCR1A2  2
-#define OCR1A3  3
-#define OCR1A4  4
-#define OCR1A5  5
-#define OCR1A6  6
-#define OCR1A7  7
-#define OCR1AH  _SFR_MEM8(0x89)
-#define OCR1A8  0
-#define OCR1A9  1
-#define OCR1A10 2
-#define OCR1A11 3
-#define OCR1A12 4
-#define OCR1A13 5
-#define OCR1A14 6
-#define OCR1A15 7
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1B0  0
-#define OCR1B1  1
-#define OCR1B2  2
-#define OCR1B3  3
-#define OCR1B4  4
-#define OCR1B5  5
-#define OCR1B6  6
-#define OCR1B7  7
-#define OCR1BH  _SFR_MEM8(0x8B)
-#define OCR1B8  0
-#define OCR1B9  1
-#define OCR1B10 2
-#define OCR1B11 3
-#define OCR1B12 4
-#define OCR1B13 5
-#define OCR1B14 6
-#define OCR1B15 7
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define POAC0B  7   /* PSC0 Output B Activity */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define POAC2B  7   /* PSC2 Output B Activity */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-#define DAEN    0   /* Digital to Analog Enable bit */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0   /* Multi-processor Communication Mode */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define UPE     2   /* USART Parity Error */
-#define DOR     3   /* Data OverRun */
-#define FE      4   /* Frame Error */
-#define UDRE    5   /* USART Data Register Empty */
-#define TXC     6   /* USART Transmit Complete */
-#define RXC     7   /* USART Receive Complete */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-#define TXB8    0   /* Transmit Data Bit 8 */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define UCSZ2   2   /* Character Size */
-#define TXEN    3   /* Transmitter Enable */
-#define RXEN    4   /* Receiver Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0   /* Clock Polarity */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCSZ1   2   /* Character Size bit1 */
-#define USBS    3   /* Stop Bit Select */
-#define UPM0    4   /* Parity Mode bit0 */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UMSEL   6   /* USART Mode Select */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-#define BODR    0   /* Bit Order */
-#define EMCH    1   /* Manchester mode */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EUSART  4   /* EUSART Enable Bit */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-#define STP0    0   /* Stop bits values bit0 */
-#define STP1    1   /* Stop bits values bit1 */
-#define F1617   2
-#define FEM     3   /* Frame Error Manchester */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-#define PRUN0   0   /* PSC 0 Run */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-#define PICR0L  _SFR_MEM8(0xDE)
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-#define PICR1L  _SFR_MEM8(0xEE)
-#define PICR1H  _SFR_MEM8(0xEF)
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define POS22   6   /* PSCOUT22 Selection */
-#define POS23   7   /* PSCOUT23 Selection */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-#define PRUN2   0   /* PSC 2 Run */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-#define PICR2L  _SFR_MEM8(0xFE)
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-
-
-/* Interrupt Vectors */
-/* Interrupt 0 is the reset vector. */
-
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect     _VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect       _VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect     _VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect       _VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect     _VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect       _VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect _VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect _VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect _VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect          _VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect   _VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect  _VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect  _VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect    _VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect _VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect    _VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect           _VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect          _VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect       _VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect      _VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect    _VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect      _VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect          _VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect           _VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect      _VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect  _VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect          _VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect     _VECTOR(31)
-
-#define _VECTORS_SIZE   (4 * 32)
-
-/* Constants */
-
-#define RAMEND         0x4FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x3FFF
-#define SPM_PAGESIZE   128
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV    (unsigned char)~_BV(4)
-#define FUSE_PSC0RB   (unsigned char)~_BV(5)
-#define FUSE_PSC1RB   (unsigned char)~_BV(6)
-#define FUSE_PSC2RB   (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x83
-
-/** @} */
-
-#endif /* _AVR_IO90PWM216_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm2b.h b/cpukit/score/cpu/avr/avr/io90pwm2b.h
deleted file mode 100644
index 22d0c1c379..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm2b.h
+++ /dev/null
@@ -1,1404 +0,0 @@
-/**
- * @file avr/io90pwm2b.h
- *
- * @brief Definitions for AT90PWM2B
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2007 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm2b.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IO90PWM2B_H_
-#define _AVR_IO90PWM2B_H_ 1
-
-/**
- * @defgroup Avr_io90pwm2b AT90PWM2B Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define GPIOR3 _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0_0 0    /* Deprecated */
-#define OCR0_1 1    /* Deprecated */
-#define OCR0_2 2    /* Deprecated */
-#define OCR0_3 3    /* Deprecated */
-#define OCR0_4 4    /* Deprecated */
-#define OCR0_5 5    /* Deprecated */
-#define OCR0_6 6    /* Deprecated */
-#define OCR0_7 7    /* Deprecated */
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define ACCKDIV 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC1 6
-#define PRPSC2 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADASCR 4
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define PIFR0 _SFR_MEM8(0xA0)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define PSEI0 5
-#define POAC0A 6
-#define POAC0B 7
-
-#define PIM0 _SFR_MEM8(0xA1)
-#define PEOPE0 0
-#define PEVE0A 3
-#define PEVE0B 4
-#define PSEIE0 5
-
-#define PIFR1 _SFR_MEM8(0xA2)
-#define PEOP1 0
-#define PRN10 1
-#define PRN11 2
-#define PEV1A 3
-#define PEV1B 4
-#define PSEI1 5
-#define POAC1A 6
-#define POAC1B 7
-
-#define PIM1 _SFR_MEM8(0xA3)
-#define PEOPE1 0
-#define PEVE1A 3
-#define PEVE1B 4
-#define PSEIE1 5
-
-#define PIFR2 _SFR_MEM8(0xA4)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PIM2 _SFR_MEM8(0xA5)
-#define PEOPE2 0
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define DACON _SFR_MEM8(0xAA)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0xAB)
-
-#define DACL _SFR_MEM8(0xAB)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0xAC)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0xAD)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0xAE)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0xAF)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define UCSRA _SFR_MEM8(0xC0)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UCSRB _SFR_MEM8(0xC1)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRC _SFR_MEM8(0xC2)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL0 6
-
-#define UBRR _SFR_MEM16(0xC4)
-
-#define UBRRL _SFR_MEM8(0xC4)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRRH _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR _SFR_MEM8(0xC6)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define EUCSRA _SFR_MEM8(0xC8)
-#define URxS0 0
-#define URxS1 1
-#define URxS2 2
-#define URxS3 3
-#define UTxS0 4
-#define UTxS1 5
-#define UTxS2 6
-#define UTxS3 7
-
-#define EUCSRB _SFR_MEM8(0xC9)
-#define BODR 0
-#define EMCH 1
-#define EUSBS 3
-#define EUSART 4
-
-#define EUCSRC _SFR_MEM8(0xCA)
-#define STP0 0
-#define STP1 1
-#define F1617 2
-#define FEM 3
-
-#define MUBRR _SFR_MEM16(0xCC)
-
-#define MUBRRL _SFR_MEM8(0xCC)
-#define MUBRR0 0
-#define MUBRR1 1
-#define MUBRR2 2
-#define MUBRR3 3
-#define MUBRR4 4
-#define MUBRR5 5
-#define MUBRR6 6
-#define MUBRR7 7
-
-#define MUBRRH _SFR_MEM8(0xCD)
-#define MUBRR8 0
-#define MUBRR9 1
-#define MUBRR10 2
-#define MUBRR11 3
-#define MUBRR12 4
-#define MUBRR13 5
-#define MUBRR14 6
-#define MUBRR15 7
-
-#define EUDR _SFR_MEM8(0xCE)
-#define EUDR0 0
-#define EUDR1 1
-#define EUDR2 2
-#define EUDR3 3
-#define EUDR4 4
-#define EUDR5 5
-#define EUDR6 6
-#define EUDR7 7
-
-#define PSOC0 _SFR_MEM8(0xD0)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-
-#define OCR0SA _SFR_MEM16(0xD2)
-
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0xD3)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define OCR0RA _SFR_MEM16(0xD4)
-
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_MEM8(0xD5)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#define OCR0SB _SFR_MEM16(0xD6)
-
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_MEM8(0xD7)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_MEM16(0xD8)
-
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_MEM8(0xD9)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define PCNF0 _SFR_MEM8(0xDA)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_MEM8(0xDB)
-#define PRUN0 0
-#define PCCYC0 1
-#define PARUN0 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM0 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PFRC0A _SFR_MEM8(0xDC)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0xDD)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define PICR0 _SFR_MEM16(0xDE)
-
-#define PICR0L _SFR_MEM8(0xDE)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0xDF)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC1 _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-#define OCR1SA _SFR_MEM16(0xE2)
-
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SA_0 0
-#define OCR1SA_1 1
-#define OCR1SA_2 2
-#define OCR1SA_3 3
-#define OCR1SA_4 4
-#define OCR1SA_5 5
-#define OCR1SA_6 6
-#define OCR1SA_7 7
-
-#define OCR1SAH _SFR_MEM8(0xE3)
-#define OCR1SA_8 0
-#define OCR1SA_9 1
-#define OCR1SA_10 2
-#define OCR1SA_11 3
-
-#define OCR1RA _SFR_MEM16(0xE4)
-
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RA_0 0
-#define OCR1RA_1 1
-#define OCR1RA_2 2
-#define OCR1RA_3 3
-#define OCR1RA_4 4
-#define OCR1RA_5 5
-#define OCR1RA_6 6
-#define OCR1RA_7 7
-
-#define OCR1RAH _SFR_MEM8(0xE5)
-#define OCR1RA_8 0
-#define OCR1RA_9 1
-#define OCR1RA_10 2
-#define OCR1RA_11 3
-
-#define OCR1SB _SFR_MEM16(0xE6)
-
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SB_0 0
-#define OCR1SB_1 1
-#define OCR1SB_2 2
-#define OCR1SB_3 3
-#define OCR1SB_4 4
-#define OCR1SB_5 5
-#define OCR1SB_6 6
-#define OCR1SB_7 7
-
-#define OCR1SBH _SFR_MEM8(0xE7)
-#define OCR1SB_8 0
-#define OCR1SB_9 1
-#define OCR1SB_10 2
-#define OCR1SB_11 3
-
-#define OCR1RB _SFR_MEM16(0xE8)
-
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RB_0 0
-#define OCR1RB_1 1
-#define OCR1RB_2 2
-#define OCR1RB_3 3
-#define OCR1RB_4 4
-#define OCR1RB_5 5
-#define OCR1RB_6 6
-#define OCR1RB_7 7
-
-#define OCR1RBH _SFR_MEM8(0xE9)
-#define OCR1RB_8 0
-#define OCR1RB_9 1
-#define OCR1RB_10 2
-#define OCR1RB_11 3
-#define OCR1RB_12 4
-#define OCR1RB_13 5
-#define OCR1RB_14 6
-#define OCR1RB_15 7
-
-#define PCNF1 _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1 2
-#define PMODE10 3
-#define PMODE11 4
-#define PLOCK1 5
-#define PALOCK1 6
-#define PFIFTY1 7
-
-#define PCTL1 _SFR_MEM8(0xEB)
-#define PRUN1 0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1 5
-#define PPRE10 6
-#define PPRE11 7
-
-#define PFRC1A _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A 7
-
-#define PFRC1B _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B 7
-
-#define PICR1 _SFR_MEM16(0xEE)
-
-#define PICR1L _SFR_MEM8(0xEE)
-#define PICR1_0 0
-#define PICR1_1 1
-#define PICR1_2 2
-#define PICR1_3 3
-#define PICR1_4 4
-#define PICR1_5 5
-#define PICR1_6 6
-#define PICR1_7 7
-
-#define PICR1H _SFR_MEM8(0xEF)
-#define PICR1_8 0
-#define PICR1_9 1
-#define PICR1_10 2
-#define PICR1_11 3
-#define PCST1 7
-
-#define PSOC2 _SFR_MEM8(0xF0)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0xF1)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define OCR2SA _SFR_MEM16(0xF2)
-
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0xF3)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define OCR2RA _SFR_MEM16(0xF4)
-
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_MEM8(0xF5)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define OCR2SB _SFR_MEM16(0xF6)
-
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_MEM8(0xF7)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_MEM16(0xF8)
-
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_MEM8(0xF9)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define PCNF2 _SFR_MEM8(0xFA)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_MEM8(0xFB)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define PFRC2A _SFR_MEM8(0xFC)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0xFD)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR2 _SFR_MEM16(0xFE)
-
-#define PICR2L _SFR_MEM8(0xFE)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0xFF)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-#define PSC2_CAPT_vect      _VECTOR(1)   /* PSC2 Capture Event */
-#define PSC2_EC_vect        _VECTOR(2)   /* PSC2 End Cycle */
-#define PSC1_CAPT_vect      _VECTOR(3)   /* PSC1 Capture Event */
-#define PSC1_EC_vect        _VECTOR(4)   /* PSC1 End Cycle */
-#define PSC0_CAPT_vect      _VECTOR(5)   /* PSC0 Capture Event */
-#define PSC0_EC_vect        _VECTOR(6)   /* PSC0 End Cycle */
-#define ANALOG_COMP_0_vect  _VECTOR(7)   /* Analog Comparator 0 */
-#define ANALOG_COMP_1_vect  _VECTOR(8)   /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect  _VECTOR(9)   /* Analog Comparator 2 */
-#define INT0_vect           _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect    _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect   _VECTOR(13)  /* Timer/Counter Compare Match B */
-/* Vector 14, Reserved */
-#define TIMER1_OVF_vect     _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_OVF_vect     _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define ADC_vect            _VECTOR(18)  /* ADC Conversion Complete */
-#define INT1_vect           _VECTOR(19)  /* External Interrupt Request 1 */
-#define SPI_STC_vect        _VECTOR(20)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect       _VECTOR(21)  /* USART, Rx Complete */
-#define USART_UDRE_vect     _VECTOR(22)  /* USART Data Register Empty */
-#define USART_TX_vect       _VECTOR(23)  /* USART, Tx Complete */
-#define INT2_vect           _VECTOR(24)  /* External Interrupt Request 2 */
-#define WDT_vect            _VECTOR(25)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect       _VECTOR(26)  /* EEPROM Ready */
-#define TIMER0_COMPB_vect   _VECTOR(27)  /* Timer Counter 0 Compare Match B */
-#define INT3_vect           _VECTOR(28)  /* External Interrupt Request 3 */
-/* Vector 29, Reserved */
-/* Vector 30, Reserved */
-#define SPM_READY_vect      _VECTOR(31)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE 64
-
-
-
-/* Memory Sizes */
-#define RAMEND         0x2FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x1FFF
-#define SPM_PAGESIZE   32
-
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6) /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV   (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC1RB  (unsigned char)~_BV(6)  /* PSC1 Reset Behaviour */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x83
-
-
-/** @} */
-#endif /* _AVR_IO90PWM2B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm316.h b/cpukit/score/cpu/avr/avr/io90pwm316.h
deleted file mode 100644
index fbc1256922..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm316.h
+++ /dev/null
@@ -1,1223 +0,0 @@
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm316.h - definitions for AT90PWM316 */
-
-#ifndef _AVR_IO90PWM316_H_
-#define _AVR_IO90PWM316_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm316.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-#define PINE0   0
-#define PINE1   1
-#define PINE2   2
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE0    0
-#define DDE1    1
-#define DDE2    2
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-#define PE0     0
-#define PE1     1
-#define PE2     2
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0   /* Overflow Flag */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define OCF0B   2   /* Output Compare Flag 0B */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0   /* Overflow Flag */
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define ICF1    5   /* Input Capture Flag 1 */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-#define INTF2   2
-#define INTF3   3
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0   /* External Interrupt Request 0 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0   /* EEPROM Read Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEAR0   0
-#define EEAR1   1
-#define EEAR2   2
-#define EEAR3   3
-#define EEAR4   4
-#define EEAR5   5
-#define EEAR6   6
-#define EEAR7   7
-#define EEARH   _SFR_IO8(0x22)
-#define EEAR8   0
-#define EEAR9   1
-#define EEAR10  2
-#define EEAR11  3
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0   /* Waveform Generation Mode */
-#define WGM01   1   /* Waveform Generation Mode */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS02    2   /* Clock Select */
-#define WGM02   3   /* Waveform Generation Mode */
-#define FOC0B   6   /* Force Output Compare B */
-#define FOC0A   7   /* Force Output Compare A */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-#define OCR0A0  0
-#define OCR0A1  1
-#define OCR0A2  2
-#define OCR0A3  3
-#define OCR0A4  4
-#define OCR0A5  5
-#define OCR0A6  6
-#define OCR0A7  7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-#define OCR0B0  0
-#define OCR0B1  1
-#define OCR0B2  2
-#define OCR0B3  3
-#define OCR0B4  4
-#define OCR0B5  5
-#define OCR0B6  6
-#define OCR0B7  7
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0   /* PLL Lock Detector */
-#define PLLE    1   /* PLL Enable */
-#define PLLF    2   /* PLL Factor */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define CPHA    2   /* Clock Phase */
-#define CPOL    3   /* Clock polarity */
-#define MSTR    4   /* Master/Slave Select */
-#define DORD    5   /* Data Order */
-#define SPE     6   /* SPI Enable */
-#define SPIE    7   /* SPI Interrupt Enable */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0   /* Double SPI Speed Bit */
-#define WCOL    6   /* Write Collision Flag */
-#define SPIF    7   /* SPI Interrupt Flag */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-#define SPD0    0
-#define SPD1    1
-#define SPD2    2
-#define SPD3    3
-#define SPD4    4
-#define SPD5    5
-#define SPD6    6
-#define SPD7    7
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0   /* Sleep Enable */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM2     3   /* Sleep Mode Select bit2 */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0   /* Power-on reset flag */
-#define EXTRF   1   /* External Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define WDRF    3   /* Watchdog Reset Flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0   /* Interrupt Vector Change Enable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define PUD     4   /* Pull-up disable */
-#define SPIPS   7   /* SPI Pin Select */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0   /* Store Program Memory Enable */
-#define PGERS   1   /* Page Erase */
-#define PGWRT   2   /* Page Write */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define SPMIE   7   /* SPM Interrupt Enable */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDE     3   /* Watchdog Enable */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0   /* Power Reduction ADC */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define ISC20   4
-#define ISC21   5
-#define ISC30   6
-#define ISC31   7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0   /* Overflow Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0   /* Overflow Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0  4
-#define AMP0G1  5
-#define AMP0IS  6
-#define AMP0EN  7
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0  4
-#define AMP1G1  5
-#define AMP1IS  6
-#define AMP1EN  7
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADEN    7   /* ADC Enable */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADHSM   7   /* ADC High Speed Mode */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define ADLAR   5   /* Left Adjust Result */
-#define REFS0   6   /* Reference Selection bit0 */
-#define REFS1   7   /* Reference Selection bit1 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0   /* ADC0 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   0   /* ADC8 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define AMP0ND  3
-#define AMP0PD  4
-#define ACMP0D  5
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0   /* Waveform Generation Mode */
-#define WGM11   1   /* Waveform Generation Mode */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define WGM12   3   /* Waveform Generation Mode */
-#define WGM13   4   /* Waveform Generation Mode */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6   /* Force Output Compare for Channel B */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT10  0
-#define TCNT11  1
-#define TCNT12  2
-#define TCNT13  3
-#define TCNT14  4
-#define TCNT15  5
-#define TCNT16  6
-#define TCNT17  7
-#define TCNT1H  _SFR_MEM8(0x85)
-#define TCNT18  0
-#define TCNT19  1
-#define TCNT110 2
-#define TCNT111 3
-#define TCNT112 4
-#define TCNT113 5
-#define TCNT114 6
-#define TCNT115 7
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-#define ICR1H   _SFR_MEM8(0x87)
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1A0  0
-#define OCR1A1  1
-#define OCR1A2  2
-#define OCR1A3  3
-#define OCR1A4  4
-#define OCR1A5  5
-#define OCR1A6  6
-#define OCR1A7  7
-#define OCR1AH  _SFR_MEM8(0x89)
-#define OCR1A8  0
-#define OCR1A9  1
-#define OCR1A10 2
-#define OCR1A11 3
-#define OCR1A12 4
-#define OCR1A13 5
-#define OCR1A14 6
-#define OCR1A15 7
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1B0  0
-#define OCR1B1  1
-#define OCR1B2  2
-#define OCR1B3  3
-#define OCR1B4  4
-#define OCR1B5  5
-#define OCR1B6  6
-#define OCR1B7  7
-#define OCR1BH  _SFR_MEM8(0x8B)
-#define OCR1B8  0
-#define OCR1B9  1
-#define OCR1B10 2
-#define OCR1B11 3
-#define OCR1B12 4
-#define OCR1B13 5
-#define OCR1B14 6
-#define OCR1B15 7
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define POAC0B  7   /* PSC0 Output B Activity */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-#define PEOP1   0
-#define PRN10   1
-#define PRN11   2
-#define PEV1A   3
-#define PEV1B   4
-#define PSEI1   5
-#define POAC1A  6
-#define POAC1B  7
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define POAC2B  7   /* PSC2 Output B Activity */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-#define DAEN    0   /* Digital to Analog Enable bit */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0   /* Multi-processor Communication Mode */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define UPE     2   /* USART Parity Error */
-#define DOR     3   /* Data OverRun */
-#define FE      4   /* Frame Error */
-#define UDRE    5   /* USART Data Register Empty */
-#define TXC     6   /* USART Transmit Complete */
-#define RXC     7   /* USART Receive Complete */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-#define TXB8    0   /* Transmit Data Bit 8 */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define UCSZ2   2   /* Character Size */
-#define TXEN    3   /* Transmitter Enable */
-#define RXEN    4   /* Receiver Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0   /* Clock Polarity */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCSZ1   2   /* Character Size bit1 */
-#define USBS    3   /* Stop Bit Select */
-#define UPM0    4   /* Parity Mode bit0 */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UMSEL   6   /* USART Mode Select */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-#define BODR    0   /* Bit Order */
-#define EMCH    1   /* Manchester mode */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EUSART  4   /* EUSART Enable Bit */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-#define STP0    0   /* Stop bits values bit0 */
-#define STP1    1   /* Stop bits values bit1 */
-#define F1617   2
-#define FEM     3   /* Frame Error Manchester */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-#define PRUN0   0   /* PSC 0 Run */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-#define PICR0L  _SFR_MEM8(0xDE)
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1     2
-#define PMODE10  3
-#define PMODE11  4
-#define PLOCK1   5
-#define PALOCK1  6
-#define PFIFTY1  7
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-#define PRUN1  0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1  5
-#define PPRE10 6
-#define PPRE11 7
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A  7
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B  7
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-#define PICR1L  _SFR_MEM8(0xEE)
-#define PICR1H  _SFR_MEM8(0xEF)
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define POS22   6   /* PSCOUT22 Selection */
-#define POS23   7   /* PSCOUT23 Selection */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-#define PRUN2   0   /* PSC 2 Run */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-#define PICR2L  _SFR_MEM8(0xFE)
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-
-
-/* Interrupt Vectors */
-/* Interrupt 0 is the reset vector. */
-
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect     _VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect       _VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect     _VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect       _VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect     _VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect       _VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect _VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect _VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect _VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect          _VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect   _VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect  _VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect  _VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect    _VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect _VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect    _VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect           _VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect          _VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect       _VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect      _VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect    _VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect      _VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect          _VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect           _VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect      _VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect  _VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect          _VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect     _VECTOR(31)
-
-#define _VECTORS_SIZE   (4 * 32)
-
-/* Constants */
-
-#define RAMEND         0x4FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x3FFF
-#define SPM_PAGESIZE   128
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV    (unsigned char)~_BV(4)
-#define FUSE_PSC0RB   (unsigned char)~_BV(5)
-#define FUSE_PSC1RB   (unsigned char)~_BV(6)
-#define FUSE_PSC2RB   (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x83
-
-
-#endif /* _AVR_IO90PWM316_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm3b.h b/cpukit/score/cpu/avr/avr/io90pwm3b.h
deleted file mode 100644
index 5b1a7537cb..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm3b.h
+++ /dev/null
@@ -1,1408 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM3B
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/io90pwm3b.h - definitions for AT90PWM3B */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm3b.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IO90PWM3B_H_
-#define _AVR_IO90PWM3B_H_ 1
-
-/**
- * @defgroup AvrDef_io90pwm3b AT90PWM3B Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-      
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define GPIOR3 _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0_0 0    /* Deprecated */
-#define OCR0_1 1    /* Deprecated */
-#define OCR0_2 2    /* Deprecated */
-#define OCR0_3 3    /* Deprecated */
-#define OCR0_4 4    /* Deprecated */
-#define OCR0_5 5    /* Deprecated */
-#define OCR0_6 6    /* Deprecated */
-#define OCR0_7 7    /* Deprecated */
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define ACCKDIV 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC1 6
-#define PRPSC2 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADASCR 4
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define PIFR0 _SFR_MEM8(0xA0)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define PSEI0 5
-#define POAC0A 6
-#define POAC0B 7
-
-#define PIM0 _SFR_MEM8(0xA1)
-#define PEOPE0 0
-#define PEVE0A 3
-#define PEVE0B 4
-#define PSEIE0 5
-
-#define PIFR1 _SFR_MEM8(0xA2)
-#define PEOP1 0
-#define PRN10 1
-#define PRN11 2
-#define PEV1A 3
-#define PEV1B 4
-#define PSEI1 5
-#define POAC1A 6
-#define POAC1B 7
-
-#define PIM1 _SFR_MEM8(0xA3)
-#define PEOPE1 0
-#define PEVE1A 3
-#define PEVE1B 4
-#define PSEIE1 5
-
-#define PIFR2 _SFR_MEM8(0xA4)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PIM2 _SFR_MEM8(0xA5)
-#define PEOPE2 0
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define DACON _SFR_MEM8(0xAA)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0xAB)
-
-#define DACL _SFR_MEM8(0xAB)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0xAC)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0xAD)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0xAE)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0xAF)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define UCSRA _SFR_MEM8(0xC0)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UCSRB _SFR_MEM8(0xC1)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRC _SFR_MEM8(0xC2)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL0 6
-
-#define UBRR _SFR_MEM16(0xC4)
-
-#define UBRRL _SFR_MEM8(0xC4)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRRH _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR _SFR_MEM8(0xC6)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define EUCSRA _SFR_MEM8(0xC8)
-#define URxS0 0
-#define URxS1 1
-#define URxS2 2
-#define URxS3 3
-#define UTxS0 4
-#define UTxS1 5
-#define UTxS2 6
-#define UTxS3 7
-
-#define EUCSRB _SFR_MEM8(0xC9)
-#define BODR 0
-#define EMCH 1
-#define EUSBS 3
-#define EUSART 4
-
-#define EUCSRC _SFR_MEM8(0xCA)
-#define STP0 0
-#define STP1 1
-#define F1617 2
-#define FEM 3 
-
-#define MUBRR _SFR_MEM16(0xCC)
-
-#define MUBRRL _SFR_MEM8(0xCC)
-#define MUBRR0 0
-#define MUBRR1 1
-#define MUBRR2 2
-#define MUBRR3 3
-#define MUBRR4 4
-#define MUBRR5 5
-#define MUBRR6 6
-#define MUBRR7 7
-
-#define MUBRRH _SFR_MEM8(0xCD)
-#define MUBRR8 0
-#define MUBRR9 1
-#define MUBRR10 2
-#define MUBRR11 3
-#define MUBRR12 4
-#define MUBRR13 5
-#define MUBRR14 6
-#define MUBRR15 7
-
-#define EUDR _SFR_MEM8(0xCE)
-#define EUDR0 0
-#define EUDR1 1
-#define EUDR2 2
-#define EUDR3 3
-#define EUDR4 4
-#define EUDR5 5
-#define EUDR6 6
-#define EUDR7 7
-
-#define PSOC0 _SFR_MEM8(0xD0)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-
-#define OCR0SA _SFR_MEM16(0xD2)
-
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0xD3)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define OCR0RA _SFR_MEM16(0xD4)
-
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_MEM8(0xD5)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#define OCR0SB _SFR_MEM16(0xD6)
-
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_MEM8(0xD7)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_MEM16(0xD8)
-
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_MEM8(0xD9)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define PCNF0 _SFR_MEM8(0xDA)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_MEM8(0xDB)
-#define PRUN0 0
-#define PCCYC0 1
-#define PARUN0 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM0 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PFRC0A _SFR_MEM8(0xDC)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0xDD)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define PICR0 _SFR_MEM16(0xDE)
-
-#define PICR0L _SFR_MEM8(0xDE)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0xDF)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC1 _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-#define OCR1SA _SFR_MEM16(0xE2)
-
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SA_0 0
-#define OCR1SA_1 1
-#define OCR1SA_2 2
-#define OCR1SA_3 3
-#define OCR1SA_4 4
-#define OCR1SA_5 5
-#define OCR1SA_6 6
-#define OCR1SA_7 7
-
-#define OCR1SAH _SFR_MEM8(0xE3)
-#define OCR1SA_8 0
-#define OCR1SA_9 1
-#define OCR1SA_10 2
-#define OCR1SA_11 3
-
-#define OCR1RA _SFR_MEM16(0xE4)
-
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RA_0 0
-#define OCR1RA_1 1
-#define OCR1RA_2 2
-#define OCR1RA_3 3
-#define OCR1RA_4 4
-#define OCR1RA_5 5
-#define OCR1RA_6 6
-#define OCR1RA_7 7
-
-#define OCR1RAH _SFR_MEM8(0xE5)
-#define OCR1RA_8 0
-#define OCR1RA_9 1
-#define OCR1RA_10 2
-#define OCR1RA_11 3
-
-#define OCR1SB _SFR_MEM16(0xE6)
-
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SB_0 0
-#define OCR1SB_1 1
-#define OCR1SB_2 2
-#define OCR1SB_3 3
-#define OCR1SB_4 4
-#define OCR1SB_5 5
-#define OCR1SB_6 6
-#define OCR1SB_7 7
-
-#define OCR1SBH _SFR_MEM8(0xE7)
-#define OCR1SB_8 0
-#define OCR1SB_9 1
-#define OCR1SB_10 2
-#define OCR1SB_11 3
-
-#define OCR1RB _SFR_MEM16(0xE8)
-
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RB_0 0
-#define OCR1RB_1 1
-#define OCR1RB_2 2
-#define OCR1RB_3 3
-#define OCR1RB_4 4
-#define OCR1RB_5 5
-#define OCR1RB_6 6
-#define OCR1RB_7 7
-
-#define OCR1RBH _SFR_MEM8(0xE9)
-#define OCR1RB_8 0
-#define OCR1RB_9 1
-#define OCR1RB_10 2
-#define OCR1RB_11 3
-#define OCR1RB_12 4
-#define OCR1RB_13 5
-#define OCR1RB_14 6
-#define OCR1RB_15 7
-
-#define PCNF1 _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1 2
-#define PMODE10 3
-#define PMODE11 4
-#define PLOCK1 5
-#define PALOCK1 6
-#define PFIFTY1 7
-
-#define PCTL1 _SFR_MEM8(0xEB)
-#define PRUN1 0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1 5
-#define PPRE10 6
-#define PPRE11 7
-
-#define PFRC1A _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A 7
-
-#define PFRC1B _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B 7
-
-#define PICR1 _SFR_MEM16(0xEE)
-
-#define PICR1L _SFR_MEM8(0xEE)
-#define PICR1_0 0
-#define PICR1_1 1
-#define PICR1_2 2
-#define PICR1_3 3
-#define PICR1_4 4
-#define PICR1_5 5
-#define PICR1_6 6
-#define PICR1_7 7
-
-#define PICR1H _SFR_MEM8(0xEF)
-#define PICR1_8 0
-#define PICR1_9 1
-#define PICR1_10 2
-#define PICR1_11 3
-#define PCST1 7
-
-#define PSOC2 _SFR_MEM8(0xF0)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0xF1)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define OCR2SA _SFR_MEM16(0xF2)
-
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0xF3)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define OCR2RA _SFR_MEM16(0xF4)
-
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_MEM8(0xF5)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define OCR2SB _SFR_MEM16(0xF6)
-
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_MEM8(0xF7)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_MEM16(0xF8)
-
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_MEM8(0xF9)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define PCNF2 _SFR_MEM8(0xFA)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_MEM8(0xFB)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define PFRC2A _SFR_MEM8(0xFC)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0xFD)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR2 _SFR_MEM16(0xFE)
-
-#define PICR2L _SFR_MEM8(0xFE)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0xFF)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-#define PSC2_CAPT_vect      _VECTOR(1)   /* PSC2 Capture Event */
-#define PSC2_EC_vect        _VECTOR(2)   /* PSC2 End Cycle */
-#define PSC1_CAPT_vect      _VECTOR(3)   /* PSC1 Capture Event */
-#define PSC1_EC_vect        _VECTOR(4)   /* PSC1 End Cycle */
-#define PSC0_CAPT_vect      _VECTOR(5)   /* PSC0 Capture Event */
-#define PSC0_EC_vect        _VECTOR(6)   /* PSC0 End Cycle */
-#define ANALOG_COMP_0_vect  _VECTOR(7)   /* Analog Comparator 0 */
-#define ANALOG_COMP_1_vect  _VECTOR(8)   /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect  _VECTOR(9)   /* Analog Comparator 2 */
-#define INT0_vect           _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect    _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect   _VECTOR(13)  /* Timer/Counter Compare Match B */
-/* Vector 14, Reserved */
-#define TIMER1_OVF_vect     _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_OVF_vect     _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define ADC_vect            _VECTOR(18)  /* ADC Conversion Complete */
-#define INT1_vect           _VECTOR(19)  /* External Interrupt Request 1 */
-#define SPI_STC_vect        _VECTOR(20)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect       _VECTOR(21)  /* USART, Rx Complete */
-#define USART_UDRE_vect     _VECTOR(22)  /* USART Data Register Empty */
-#define USART_TX_vect       _VECTOR(23)  /* USART, Tx Complete */
-#define INT2_vect           _VECTOR(24)  /* External Interrupt Request 2 */
-#define WDT_vect            _VECTOR(25)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect       _VECTOR(26)  /* EEPROM Ready */
-#define TIMER0_COMPB_vect   _VECTOR(27)  /* Timer Counter 0 Compare Match B */
-#define INT3_vect           _VECTOR(28)  /* External Interrupt Request 3 */
-/* Vector 29, Reserved */
-/* Vector 30, Reserved */
-#define SPM_READY_vect      _VECTOR(31)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE 64
-
-
-
-/* Memory Sizes */
-#define RAMEND         0x2FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x1FFF
-#define SPM_PAGESIZE   32
-
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV   (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC1RB  (unsigned char)~_BV(6)  /* PSC1 Reset Behaviour */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x83
-
-/** @} */
-
-#endif /* _AVR_IO90PWM3B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm81.h b/cpukit/score/cpu/avr/avr/io90pwm81.h
deleted file mode 100644
index b2faea85f6..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwm81.h
+++ /dev/null
@@ -1,1040 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM81
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm81.h - definitions for AT90PWM81 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm81.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm81 AT90PWM81 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_AT90PWM81_H_
-#define _AVR_AT90PWM81_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define ACSR _SFR_IO8(0x00)
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define TIMSK1 _SFR_IO8(0x01)
-#define TOIE1 0
-#define ICIE1 5
-
-#define TIFR1 _SFR_IO8(0x02)
-#define TOV1 0
-#define ICF1 5
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_IO8(0x07)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADSSEN 4
-#define ADNCDIS 6
-#define ADHSM 7
-
-#define ADMUX _SFR_IO8(0x08)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define PIM0 _SFR_IO8(0x0F)
-#define PEOPE0 0
-#define PEOEPE0 1
-#define PEVE0A 3
-#define PEVE0B 4
-
-#define PIFR0 _SFR_IO8(0x10)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define POAC0A 6
-#define POAC0B 7
-
-#define PCNF0 _SFR_IO8(0x11)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_IO8(0x12)
-#define PRUN0 0
-#define PCCYC0 1
-#define PBFM00 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM01 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PIM2 _SFR_IO8(0x13)
-#define PEOPE2 0
-#define PEOEPE2 1
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define PIFR2 _SFR_IO8(0x14)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PCNF2 _SFR_IO8(0x15)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_IO8(0x16)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define SPCR _SFR_IO8(0x17)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x18)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define GPIOR0 _SFR_IO8(0x19)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x1A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-#define EEPAGE 6
-#define NVMBSY 7
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define EIFR _SFR_IO8(0x20)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x21)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define OCR0SB _SFR_IO16(0x22)
-
-#define OCR0SBL _SFR_IO8(0x22)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_IO8(0x23)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_IO16(0x24)
-
-#define OCR0RBL _SFR_IO8(0x24)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_IO8(0x25)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define OCR2SB _SFR_IO16(0x26)
-
-#define OCR2SBL _SFR_IO8(0x26)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_IO8(0x27)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_IO16(0x28)
-
-#define OCR2RBL _SFR_IO8(0x28)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_IO8(0x29)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define OCR0RA _SFR_IO16(0x2A)
-
-#define OCR0RAL _SFR_IO8(0x2A)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_IO8(0x2B)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x2C)
-#endif
-#define ADCW _SFR_IO16(0x2C)
-
-#define ADCL _SFR_IO8(0x2C)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x2D)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define OCR2RA _SFR_IO16(0x2E)
-
-#define OCR2RAL _SFR_IO8(0x2E)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_IO8(0x2F)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define DWDR _SFR_IO8(0x31)
-
-#define MSMCR _SFR_IO8(0x32)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define CKRC81 2
-#define RSTDIS 3
-#define PUD 4
-
-#define SPDR _SFR_IO8(0x36)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define DAC _SFR_IO16(0x38)
-
-#define DACL _SFR_IO8(0x38)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_IO8(0x39)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define TCNT1 _SFR_IO16(0x3A)
-
-#define TCNT1L _SFR_IO8(0x3A)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x3B)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR0SA _SFR_MEM16(0x60)
-
-#define OCR0SAL _SFR_MEM8(0x60)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0x61)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define PFRC0A _SFR_MEM8(0x62)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0x63)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define OCR2SA _SFR_MEM16(0x64)
-
-#define OCR2SAL _SFR_MEM8(0x64)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0x65)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define PFRC2A _SFR_MEM8(0x66)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0x67)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR0 _SFR_MEM16(0x68)
-
-#define PICR0L _SFR_MEM8(0x68)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0x69)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC0 _SFR_MEM8(0x6A)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-#define PISEL0B1 6
-#define PISEL0A1 7
-
-#define PICR2 _SFR_MEM16(0x6C)
-
-#define PICR2L _SFR_MEM8(0x6C)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0x6D)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-#define PSOC2 _SFR_MEM8(0x6E)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0x6F)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define PCNFE2 _SFR_MEM8(0x70)
-#define PISEL2B1 0
-#define PISEL2A1 1
-#define PELEV2B1 2
-#define PELEV2A1 3
-#define PBFM21 4
-#define PASDLK20 5
-#define PASDLK21 6
-#define PASDLK22 7
-
-#define PASDLY2 _SFR_MEM8(0x71)
-#define PASDLY2_0 0
-#define PASDLY2_1 1
-#define PASDLY2_2 2
-#define PASDLY2_3 3
-#define PASDLY2_4 4
-#define PASDLY2_5 5
-#define PASDLY2_6 6
-#define PASDLY2_7 7
-
-#define DACON _SFR_MEM8(0x76)
-#define DAEN 0
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DIDR0 _SFR_MEM8(0x77)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC7D 6
-#define ADC8D 7
-
-#define DIDR1 _SFR_MEM8(0x78)
-#define ADC9D 0
-#define ADC10D 1
-#define AMP0PD 2
-#define ACMP1MD 3
-
-#define AMP0CSR _SFR_MEM8(0x79)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0GS 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AC1ECON _SFR_MEM8(0x7A)
-#define AC1H0 0
-#define AC1H1 1
-#define AC1H2 2
-#define AC1ICE 3
-#define AC1OE 4
-#define AC1OI 5
-
-#define AC2ECON _SFR_MEM8(0x7B)
-#define AC2H0 0
-#define AC2H1 1
-#define AC2H2 2
-#define AC2OE 4
-#define AC2OI 5
-
-#define AC3ECON _SFR_MEM8(0x7C)
-#define AC3H0 0
-#define AC3H1 1
-#define AC3H2 2
-#define AC3OE 4
-#define AC3OI 5
-
-#define AC1CON _SFR_MEM8(0x7D)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x7E)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x7F)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3OEA 3
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define BGCRR _SFR_MEM8(0x80)
-#define BGCR0 0
-#define BGCR1 1
-#define BGCR2 2
-#define BGCR3 3
-
-#define BGCCR _SFR_MEM8(0x81)
-#define BGCC0 0
-#define BGCC1 1
-#define BGCC2 2
-#define BGCC3 3
-
-#define WDTCSR _SFR_MEM8(0x82)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x83)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define CLKCSR _SFR_MEM8(0x84)
-#define CLKC0 0
-#define CLKC1 1
-#define CLKC2 2
-#define CLKC3 3
-#define CLKRDY 4
-#define CLKCCE 7
-
-#define CLKSELR _SFR_MEM8(0x85)
-#define CKSEL0 0
-#define CKSEL1 1
-#define CKSEL2 2
-#define CKSEL3 3
-#define CSUT0 4
-#define CSUT1 5
-#define COUT 6
-
-#define PRR _SFR_MEM8(0x86)
-#define PRADC 0
-#define PRSPI 2
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC2 7
-
-#define PLLCSR _SFR_MEM8(0x87)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF0 2
-#define PLLF1 3
-#define PLLF2 4
-#define PLLF3 5
-
-#define OSCCAL _SFR_MEM8(0x88)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define EICRA _SFR_MEM8(0x89)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define TCCR1B _SFR_MEM8(0x8A)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define ICR1 _SFR_MEM16(0x8C)
-
-#define ICR1L _SFR_MEM8(0x8C)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x8D)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define PSC2_CAPT_vect_num  1
-#define PSC2_CAPT_vect      _VECTOR(1)  /* PSC2 Capture Event */
-#define PSC2_EC_vect_num  2
-#define PSC2_EC_vect      _VECTOR(2)  /* PSC2 End Cycle */
-#define PSC2_EEC_vect_num  3
-#define PSC2_EEC_vect      _VECTOR(3)  /* PSC2 End Of Enhanced Cycle */
-#define PSC0_CAPT_vect_num  4
-#define PSC0_CAPT_vect      _VECTOR(4)  /* PSC0 Capture Event */
-#define PSC0_EC_vect_num  5
-#define PSC0_EC_vect      _VECTOR(5)  /* PSC0 End Cycle */
-#define PSC0_EEC_vect_num  6
-#define PSC0_EEC_vect      _VECTOR(6)  /* PSC0 End Of Enhanced Cycle */
-#define ANALOG_COMP_1_vect_num  7
-#define ANALOG_COMP_1_vect      _VECTOR(7)  /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect_num  8
-#define ANALOG_COMP_2_vect      _VECTOR(8)  /* Analog Comparator 2 */
-#define ANALOG_COMP_3_vect_num  9
-#define ANALOG_COMP_3_vect      _VECTOR(9)  /* Analog Comparator 3 */
-#define INT0_vect_num  10
-#define INT0_vect      _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_OVF_vect_num  12
-#define TIMER1_OVF_vect      _VECTOR(12)  /* Timer/Counter1 Overflow */
-#define ADC_vect_num  13
-#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
-#define INT1_vect_num  14
-#define INT1_vect      _VECTOR(14)  /* External Interrupt Request 1 */
-#define SPI_STC_vect_num  15
-#define SPI_STC_vect      _VECTOR(15)  /* SPI Serial Transfer Complet */
-#define INT2_vect_num  16
-#define INT2_vect      _VECTOR(16)  /* External Interrupt Request 2 */
-#define WDT_vect_num  17
-#define WDT_vect      _VECTOR(17)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect_num  18
-#define EE_READY_vect      _VECTOR(18)  /* EEPROM Ready */
-#define SPM_READY_vect_num  19
-#define SPM_READY_vect      _VECTOR(19)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (20 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (256)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_PSCINRB  (unsigned char)~_BV(3)  /* PSC2 & PSC0 Input Reset Behavior */
-#define FUSE_PSCRV  (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC2RBA  (unsigned char)~_BV(6)  /* PSC2 Rest Behavior for out OUT22 & 23 */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x88
-
-/** @} */
-
-#endif /* _AVR_AT90PWM81_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/io90pwmx.h b/cpukit/score/cpu/avr/avr/io90pwmx.h
deleted file mode 100644
index b66b65c541..0000000000
--- a/cpukit/score/cpu/avr/avr/io90pwmx.h
+++ /dev/null
@@ -1,1387 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM2(B) and AT90PWM3(B)
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2005, Andrey Pashchenko
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */
-
-#ifndef _AVR_IO90PWMX_H_
-#define _AVR_IO90PWMX_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwmX.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup io90pwmx AT90PWM2(B) and AT90PWM3(B) Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-/* PINC */
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-/* DDRC */
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-/* PORTC */
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-/* PINE */
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-/* DDRE */
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-/* PORTE */
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-/* TIFR0 */
-#define OCF0B   2   /* Output Compare Flag 0B */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define TOV0    0   /* Overflow Flag */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-/* TIFR1 */
-#define ICF1    5   /* Input Capture Flag 1 */
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define TOV1    0   /* Overflow Flag */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-/* GPIOR1 */
-#define GPIOR17 7
-#define GPIOR16 6
-#define GPIOR15 5
-#define GPIOR14 4
-#define GPIOR13 3
-#define GPIOR12 2
-#define GPIOR11 1
-#define GPIOR10 0
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-/* GPIOR2 */
-#define GPIOR27 7
-#define GPIOR26 6
-#define GPIOR25 5
-#define GPIOR24 4
-#define GPIOR23 3
-#define GPIOR22 2
-#define GPIOR21 1
-#define GPIOR20 0
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-/* GPIOR3 */
-#define GPIOR37 7
-#define GPIOR36 6
-#define GPIOR35 5
-#define GPIOR34 4
-#define GPIOR33 3
-#define GPIOR32 2
-#define GPIOR31 1
-#define GPIOR30 0
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-/* EIFR */
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-/* EIMSK */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT0    0   /* External Interrupt Request 0 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-/* GPIOR0 */
-#define GPIOR07 7
-#define GPIOR06 6
-#define GPIOR05 5
-#define GPIOR04 4
-#define GPIOR03 3
-#define GPIOR02 2
-#define GPIOR01 1
-#define GPIOR00 0
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-/* EECR */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EERE    0   /* EEPROM Read Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-/* EEDR */
-#define EEDR7   7
-#define EEDR6   6
-#define EEDR5   5
-#define EEDR4   4
-#define EEDR3   3
-#define EEDR2   2
-#define EEDR1   1
-#define EEDR0   0
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-/* EEARH */
-#define EEAR11  3
-#define EEAR10  2
-#define EEAR9   1
-#define EEAR8   0
-/* EEARL */
-#define EEAR7   7
-#define EEAR6   6
-#define EEAR5   5
-#define EEAR4   4
-#define EEAR3   3
-#define EEAR2   2
-#define EEAR1   1
-#define EEAR0   0
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-/* GTCCR */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-/* TCCR0A */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define WGM01   1   /* Waveform Generation Mode */
-#define WGM00   0   /* Waveform Generation Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-/* TCCR0B */
-#define FOC0A   7   /* Force Output Compare A */
-#define FOC0B   6   /* Force Output Compare B */
-#define WGM02   3   /* Waveform Generation Mode */
-#define CS02    2   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS00    0   /* Clock Select */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-/* TCNT0 */
-#define TCNT07  7
-#define TCNT06  6
-#define TCNT05  5
-#define TCNT04  4
-#define TCNT03  3
-#define TCNT02  2
-#define TCNT01  1
-#define TCNT00  0
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-/* OCR0A */
-#define OCR0A7  7
-#define OCR0A6  6
-#define OCR0A5  5
-#define OCR0A4  4
-#define OCR0A3  3
-#define OCR0A2  2
-#define OCR0A1  1
-#define OCR0A0  0
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-/* OCR0B */
-#define OCR0B7  7
-#define OCR0B6  6
-#define OCR0B5  5
-#define OCR0B4  4
-#define OCR0B3  3
-#define OCR0B2  2
-#define OCR0B1  1
-#define OCR0B0  0
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-/* PLLCSR */
-#define PCKE    2   /* PCK Enable */
-/* Bit 2 has been renamed in later versions of the datasheet. */
-#define PLLF    2   /* PLL Factor */
-#define PLLE    1   /* PLL Enable */
-#define PLOCK   0   /* PLL Lock Detector */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-/* SPCR */
-#define SPIE    7   /* SPI Interrupt Enable */
-#define SPE     6   /* SPI Enable */
-#define DORD    5   /* Data Order */
-#define MSTR    4   /* Master/Slave Select */
-#define CPOL    3   /* Clock polarity */
-#define CPHA    2   /* Clock Phase */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-/* SPSR */
-#define SPIF    7   /* SPI Interrupt Flag */
-#define WCOL    6   /* Write Collision Flag */
-#define SPI2X   0   /* Double SPI Speed Bit */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-/* SPDR */
-#define SPD7    7
-#define SPD6    6
-#define SPD5    5
-#define SPD4    4
-#define SPD3    3
-#define SPD2    2
-#define SPD1    1
-#define SPD0    0
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-/* ACSR */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-
-/* Monitor Data Register */
-#define MONDR   _SFR_IO8(0x31)
-
-/* Monitor Stop Mode Control Register */
-#define MSMCR   _SFR_IO8(0x32)
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-/* SMCR */
-#define SM2     3   /* Sleep Mode Select bit2 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SE      0   /* Sleep Enable */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-/* MCUSR */
-#define WDRF    3   /* Watchdog Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define EXTRF   1   /* External Reset Flag */
-#define PORF    0   /* Power-on reset flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-/* MCUCR */
-#define SPIPS   7   /* SPI Pin Select */
-#define PUD     4   /* Pull-up disable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define IVCE    0   /* Interrupt Vector Change Enable */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-/* SPMCSR */
-#define SPMIE   7   /* SPM Interrupt Enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define PGWRT   2   /* Page Write */
-#define PGERS   1   /* Page Erase */
-#define SPMEN   0   /* Store Program Memory Enable */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-/* WDTCSR */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDE     3   /* Watchdog Enable */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-/* CLKPR */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-/* PRR */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRADC   0   /* Power Reduction ADC */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-/* OSCCAL */
-#define CAL6    6
-#define CAL5    5
-#define CAL4    4
-#define CAL3    3
-#define CAL2    2
-#define CAL1    1
-#define CAL0    0
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-/* EICRA */
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-/* TIMSK0 */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE0   0   /* Overflow Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-/* TIMSK1 */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE1   0   /* Overflow Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0EN  7
-#define AMP0IS  6
-#define AMP0G1  5
-#define AMP0G0  4
-#define AMP0TS1 1
-#define AMP0TS0 0
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1EN  7
-#define AMP1IS  6
-#define AMP1G1  5
-#define AMP1G0  4
-#define AMP1TS1 1
-#define AMP1TS0 0
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-/* ADCSRA */
-#define ADEN    7   /* ADC Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-/* ADCSRB */
-#define ADHSM   7   /* ADC High Speed Mode */
-#define ADASCR  4
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-/* ADMUX */
-#define REFS1   7   /* Reference Selection bit1 */
-#define REFS0   6   /* Reference Selection bit0 */
-#define ADLAR   5   /* Left Adjust Result */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-/* DIDR0 */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC0D   0   /* ADC0 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-/* DIDR1 */
-#define ACMP0D  5
-#define AMP0PD  4
-#define AMP0ND  3
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC8D   0   /* ADC8 Digital input Disable */
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-/* TCCR1A */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define WGM11   1   /* Waveform Generation Mode */
-#define WGM10   0   /* Waveform Generation Mode */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-/* TCCR1B */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define WGM13   4   /* Waveform Generation Mode */
-#define WGM12   3   /* Waveform Generation Mode */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-/* TCCR1C */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-#define FOC1B   6   /* Force Output Compare for Channel B */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-/* TCNT1H */
-#define TCNT115 7
-#define TCNT114 6
-#define TCNT113 5
-#define TCNT112 4
-#define TCNT111 3
-#define TCNT110 2
-#define TCNT19  1
-#define TCNT18  0
-/* TCNT1L */
-#define TCNT17  7
-#define TCNT16  6
-#define TCNT15  5
-#define TCNT14  4
-#define TCNT13  3
-#define TCNT12  2
-#define TCNT11  1
-#define TCNT10  0
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-/* ICR1H */
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-/* ICR1L */
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-/* OCR1AH */
-#define OCR1A15 7
-#define OCR1A14 6
-#define OCR1A13 5
-#define OCR1A12 4
-#define OCR1A11 3
-#define OCR1A10 2
-#define OCR1A9  1
-#define OCR1A8  0
-/* OCR1AL */
-#define OCR1A7  7
-#define OCR1A6  6
-#define OCR1A5  5
-#define OCR1A4  4
-#define OCR1A3  3
-#define OCR1A2  2
-#define OCR1A1  1
-#define OCR1A0  0
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-/* OCR1BH */
-#define OCR1B15 7
-#define OCR1B14 6
-#define OCR1B13 5
-#define OCR1B12 4
-#define OCR1B11 3
-#define OCR1B10 2
-#define OCR1B9  1
-#define OCR1B8  0
-/* OCR1BL */
-#define OCR1B7  7
-#define OCR1B6  6
-#define OCR1B5  5
-#define OCR1B4  4
-#define OCR1B3  3
-#define OCR1B2  2
-#define OCR1B1  1
-#define OCR1B0  0
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-/* PIFR0 */
-#define POAC0B  7   /* PSC0 Output B Activity */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-/* PIM0 */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-/* PIFR1 */
-#define POAC1B  7   /* PSC1 Output B Activity */
-#define POAC1A  6   /* PSC1 Output A Activity */
-#define PSEI1   5   /* PSC1 Synchro Error Interrupt */
-#define PEV1B   4   /* PSC1 External Event B Interrupt */
-#define PEV1A   3   /* PSC1 External Event A Interrupt */
-#define PRN11   2   /* PSC1 Ramp Number bit1 */
-#define PRN10   1   /* PSC1 Ramp Number bit0 */
-#define PEOP1   0   /* End Of PSC1 Interrupt */
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-/* PIM1 */
-#define PSEIE1  5   /* PSC1 Synchro Error Interrupt Enable */
-#define PEVE1B  4   /* PSC1 External Event B Interrupt Enable */
-#define PEVE1A  3   /* PSC1 External Event A Interrupt Enable */
-#define PEOPE1  0   /* PSC1 End Of Cycle Interrupt Enable */
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-/* PIFR2 */
-#define POAC2B  7   /* PSC2 Output B Activity */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-/* PIM2 */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-/* DACON */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DAEN    0   /* Digital to Analog Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-/* AC0CON */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-/* AC1CON */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-/* AC2CON */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-/* UCSRA */
-#define RXC     7   /* USART Receive Complete */
-#define TXC     6   /* USART Transmit Complete */
-#define UDRE    5   /* USART Data Register Empty */
-#define FE      4   /* Frame Error */
-#define DOR     3   /* Data OverRun */
-#define UPE     2   /* USART Parity Error */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define MPCM    0   /* Multi-processor Communication Mode */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-/* UCSRB */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define RXEN    4   /* Receiver Enable */
-#define TXEN    3   /* Transmitter Enable */
-#define UCSZ2   2   /* Character Size */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define TXB8    0   /* Transmit Data Bit 8 */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-/* UCSRC */
-#define UMSEL   6   /* USART Mode Select */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UPM0    4   /* Parity Mode bit0 */
-#define USBS    3   /* Stop Bit Select */
-#define UCSZ1   2   /* Character Size bit1 */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCPOL   0   /* Clock Polarity */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-/* EUCSRA */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-/* EUCSRB */
-#define EUSART  4   /* EUSART Enable Bit */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EMCH    1   /* Manchester mode */
-#define BODR    0   /* Bit Order */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-/* EUCSRC */
-#define FEM     3   /* Frame Error Manchester */
-#define F1617   2
-#define STP1    1   /* Stop bits values bit1 */
-#define STP0    0   /* Stop bits values bit0 */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-/* PSOC0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-/* PCNF0 */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-/* PCTL0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PRUN0   0   /* PSC 0 Run */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-/* PFRC0A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-/* PFRC0B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-
-#define PICR0L  _SFR_MEM8(0xDE)
-
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-/* PSOC1 */
-#define PSYNC11 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC10 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN1B  2   /* PSC 1 OUT Part B Output Enable */
-#define POEN1A  0   /* PSC 1 OUT Part A Output Enable */
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-/* PCNF1 */
-#define PFIFTY1  7  /* PSC 1 Fifty */
-#define PALOCK1  6  /* PSC 1 Autolock */
-#define PLOCK1   5  /* PSC 1 Lock */
-#define PMODE11  4  /* PSC 1 Mode bit1 */
-#define PMODE10  3  /* PSC 1 Mode bit0 */
-#define POP1     2  /* PSC 1 Output Polarity */
-#define PCLKSEL1 1  /* PSC 1 Input Clock Select */
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-/* PCTL1 */
-#define PPRE11  7   /* PSC 1 Prescaler Select bit1 */
-#define PPRE10  6   /* PSC 1 Prescaler Select bit0 */
-#define PBFM1   5   /* Balance Flank Width Modulation */
-#define PAOC1B  4   /* PSC 1 Asynchronous Output Control B */
-#define PAOC1A  3   /* PSC 1 Asynchronous Output Control A */
-#define PARUN1  2   /* PSC 1 Autorun */
-#define PCCYC1  1   /* PSC 1 Complete Cycle */
-#define PRUN1   0   /* PSC 1 Run */
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-/* PFRC1A */
-#define PCAE1A  7   /* PSC 1 Capture Enable Input Part A */
-#define PISEL1A 6   /* PSC 1 Input Select for Part A */
-#define PELEV1A 5   /* PSC 1 Edge Level Selector of Input Part A */
-#define PFLTE1A 4   /* PSC 1 Filter Enable on Input Part A */
-#define PRFM1A3 3   /* PSC 1 Fault Mode bit3 */
-#define PRFM1A2 2   /* PSC 1 Fault Mode bit2 */
-#define PRFM1A1 1   /* PSC 1 Fault Mode bit1 */
-#define PRFM1A0 0   /* PSC 1 Fault Mode bit0 */
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-/* PFRC1B */
-#define PCAE1B  7   /* PSC 1 Capture Enable Input Part B */
-#define PISEL1B 6   /* PSC 1 Input Select for Part B */
-#define PELEV1B 5   /* PSC 1 Edge Level Selector of Input Part B */
-#define PFLTE1B 4   /* PSC 1 Filter Enable on Input Part B */
-#define PRFM1B3 3   /* PSC 1 Fault Mode bit3 */
-#define PRFM1B2 2   /* PSC 1 Fault Mode bit2 */
-#define PRFM1B1 1   /* PSC 1 Fault Mode bit1 */
-#define PRFM1B0 0   /* PSC 1 Fault Mode bit0 */
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-
-#define PICR1L  _SFR_MEM8(0xEE)
-
-#define PICR1H  _SFR_MEM8(0xEF)
-#define PCST1   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-/* PSOC2 */
-#define POS23   7   /* PSCOUT23 Selection */
-#define POS22   6   /* PSCOUT22 Selection */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-/* POM2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-/* PCNF2 */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-/* PCTL2 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PRUN2   0   /* PSC 2 Run */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-/* PFRC2A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-/* PFRC2B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-
-#define PICR2L  _SFR_MEM8(0xFE)
-
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-
-/* Interrupt vectors */
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect			_VECTOR(1)
-#define SIG_PSC2_CAPTURE		_VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect			_VECTOR(2)
-#define SIG_PSC2_END_CYCLE		_VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect			_VECTOR(3)
-#define SIG_PSC1_CAPTURE		_VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect			_VECTOR(4)
-#define SIG_PSC1_END_CYCLE		_VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect			_VECTOR(5)
-#define SIG_PSC0_CAPTURE		_VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect			_VECTOR(6)
-#define SIG_PSC0_END_CYCLE		_VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect		_VECTOR(7)
-#define SIG_COMPARATOR0			_VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect		_VECTOR(8)
-#define SIG_COMPARATOR1			_VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect		_VECTOR(9)
-#define SIG_COMPARATOR2			_VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(10)
-#define SIG_INTERRUPT0			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1_A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1_B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0_A		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(18)
-#define SIG_ADC				_VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(19)
-#define SIG_INTERRUPT1			_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(21)
-#define SIG_USART_RECV			_VECTOR(21)
-#define SIG_UART_RECV			_VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(22)
-#define SIG_USART_DATA			_VECTOR(22)
-#define SIG_UART_DATA			_VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect			_VECTOR(23)
-#define SIG_USART_TRANS			_VECTOR(23)
-#define SIG_UART_TRANS			_VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(24)
-#define SIG_INTERRUPT2			_VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(25)
-#define SIG_WDT				_VECTOR(25)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0_B		_VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(28)
-#define SIG_INTERRUPT3			_VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(31)
-#define SIG_SPM_READY			_VECTOR(31)
-
-#define _VECTORS_SIZE   64
-
-/* Constants */
-#define SPM_PAGESIZE    64
-
-#define RAMEND      0x02FF
-#define XRAMEND     RAMEND
-#define E2END       0x01FF
-#define E2PAGESIZE  4
-#define FLASHEND    0x0FFF
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
-#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_PSCRV       (unsigned char)~_BV(4)
-#define FUSE_PSC0RB      (unsigned char)~_BV(5)
-#define FUSE_PSC1RB      (unsigned char)~_BV(6)
-#define FUSE_PSC2RB      (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-/** @} */
-
-#endif /* _AVR_IO90PWMX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90scr100.h b/cpukit/score/cpu/avr/avr/io90scr100.h
deleted file mode 100644
index cb9f59247a..0000000000
--- a/cpukit/score/cpu/avr/avr/io90scr100.h
+++ /dev/null
@@ -1,1708 +0,0 @@
-/**
- * @file avr/io90scr100.h
- *
- * @brief Definitions for AT90SCR100
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90scr100.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_AT90SCR100_H_
-#define _AVR_AT90SCR100_H_ 1
-
-/**
- *  @defgroup Avr_io90scr100 AT90SCR100 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-#define PINE3 3
-#define PINE4 4
-#define PINE5 5
-#define PINE6 6
-#define PINE7 7
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-#define DDE3 3
-#define DDE4 4
-#define DDE5 5
-#define DDE6 6
-#define DDE7 7
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-#define PORTE3 3
-#define PORTE4 4
-#define PORTE5 5
-#define PORTE6 6
-#define PORTE7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define EIRR _SFR_IO8(0x1A)
-#define INTD2 2
-#define INTD3 3
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PLLCR _SFR_MEM8(0x62)
-#define ON 0
-#define LOCK 1
-#define PLLMUX 7
-
-#define SMONCR _SFR_MEM8(0x63)
-#define SMONEN 0
-#define SMONIE 1
-#define SMONIF 4
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSBH 0
-#define PRUSB 1
-#define PRHSSPI 2
-#define PRSCI 3
-#define PRAES 4
-#define PRKB 5
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define PCMSK3 _SFR_MEM8(0x73)
-
-#define LEDCR _SFR_MEM8(0x75)
-#define LED00 0
-#define LED01 1
-#define LED10 2
-#define LED11 3
-#define LED20 4
-#define LED21 5
-#define lED30 6
-#define LED31 7
-
-#define AESCR _SFR_MEM8(0x78)
-#define AESGO 0
-#define ENCRYPT 1
-#define KS 3
-#define KEYGN 4
-#define AUTOKEY 5
-#define AESIF 6
-#define AESIE 7
-
-#define AESACR _SFR_MEM8(0x79)
-#define KD 0
-#define AUTOINC 1
-#define MANINC 2
-#define XOR 3
-
-#define AESADDR _SFR_MEM8(0x7A)
-#define ADDR0 0
-#define ADDR1 1
-#define ADDR2 2
-#define ADDR3 3
-#define ADDR4 4
-#define ADDR5 5
-#define ADDR6 6
-#define ADDR7 7
-
-#define AESDR _SFR_MEM8(0x7B)
-#define DATA0 0
-#define DATA1 1
-#define DATA2 2
-#define DATA3 3
-#define DATA4 4
-#define DATA5 5
-#define DATA6 6
-#define DATA7 7
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define KBLSR _SFR_MEM8(0x8D)
-#define KBLS0 0
-#define KBLS1 1
-#define KBLS2 2
-#define KBLS3 3
-#define KBLS4 4
-#define KBLS5 5
-#define KBLS6 6
-#define KBLS7 7
-
-#define KBER _SFR_MEM8(0x8E)
-#define KBE0 0
-#define KBE1 1
-#define KBE2 2
-#define KBE3 3
-#define KBE4 4
-#define KBE5 5
-#define KBE6 6
-#define KBE7 7
-
-#define KBFR _SFR_MEM8(0x8F)
-#define KBF0 0
-#define KBF1 1
-#define KBF2 2
-#define KBF3 3
-#define KBF4 4
-#define KBF5 5
-#define KBF6 6
-#define KBF7 7
-
-#define RDWDR _SFR_MEM8(0x90)
-#define RDD0 0
-#define RDD1 1
-#define RDD2 2
-#define RDD3 3
-#define RDD4 4
-#define RDD5 5
-#define RDD6 6
-#define RDD7 7
-
-#define LFSR0 _SFR_MEM8(0x91)
-#define LFSD0 0
-#define LFSD1 1
-#define LFSD2 2
-#define LFSD3 3
-#define LFSD4 4
-#define LFSD5 5
-#define LFSD6 6
-#define LFSD7 7
-
-#define LFSR1 _SFR_MEM8(0x92)
-#define LFSD8 0
-#define LFSD9 1
-#define LFSD10 2
-#define LFSD11 3
-#define LFSD12 4
-#define LFSD13 5
-#define LFSD14 6
-#define LFSD15 7
-
-#define LFSR2 _SFR_MEM8(0x93)
-#define LFSD16 0
-#define LFSD17 1
-#define LFSD18 2
-#define LFSD19 3
-#define LFSD20 4
-#define LFSD21 5
-#define LFSD22 6
-#define LFSD23 7
-
-#define LFSR3 _SFR_MEM8(0x94)
-#define LFSD24 0
-#define LFSD25 1
-#define LFSD26 2
-#define LFSD27 3
-#define LFSD28 4
-#define LFSD29 5
-#define LFSD30 6
-#define LFSD31 7
-
-#define RNGCR _SFR_MEM8(0x95)
-#define ROSCE 0
-
-#define UHSR _SFR_MEM8(0x99)
-#define SPEED 3
-
-#define UPINT _SFR_MEM8(0x9A)
-#define PINT0 0
-#define PINT1 1
-#define PINT2 2
-#define PINT3 3
-
-#define UPBCX _SFR_MEM16(0x9B)
-
-#define UPBCXL _SFR_MEM8(0x9B)
-#define PBYTCT0 0
-#define PBYTCT1 1
-#define PBYTCT2 2
-#define PBYTCT3 3
-#define PBYTCT4 4
-#define PBYTCT5 5
-#define PBYTCT6 6
-#define PBYTCT7 7
-
-#define UPBCXH _SFR_MEM8(0x9C)
-#define PBYTCT8 0
-#define PBYTCT9 1
-#define PBYTCT10 2
-
-#define UPERRX _SFR_MEM8(0x9D)
-#define DATATGL 0
-#define DATAPID 1
-#define PID 2
-#define PTIMEOUT 3
-#define CRC16 4
-#define COUNTER0 5
-#define COUNTER1 6
-
-#define UHCR _SFR_MEM8(0x9E)
-#define SOFEN 0
-#define RESET 1
-#define RESUME 2
-#define FRZCLK 4
-#define PAD0 5
-#define PAD1 6
-#define UHEN 7
-
-#define UHINT _SFR_MEM8(0x9F)
-#define DCONNI 0
-#define DDISCI 1
-#define RSTI 2
-#define RSMEDI 3
-#define RXRSMI 4
-#define HSOFI 5
-#define HWUPI 6
-
-#define UHIEN _SFR_MEM8(0xA0)
-#define DCONNE 0
-#define DDISCE 1
-#define RSTE 2
-#define RSMEDE 3
-#define RXRSME 4
-#define HSOFE 5
-#define HWUPE 6
-
-#define UHADDR _SFR_MEM8(0xA1)
-#define HADDR0 0
-#define HADDR1 1
-#define HADDR2 2
-#define HADDR3 3
-#define HADDR4 4
-#define HADDR5 5
-#define HADDR6 6
-
-#define UHFNUM _SFR_MEM16(0xA2)
-
-#define UHFNUML _SFR_MEM8(0xA2)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UHFNUMH _SFR_MEM8(0xA3)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UHFLEN _SFR_MEM8(0xA4)
-#define FLEN0 0
-#define FLEN1 1
-#define FLEN2 2
-#define FLEN3 3
-#define FLEN4 4
-#define FLEN5 5
-#define FLEN6 6
-#define FLEN7 7
-
-#define UPINRQX _SFR_MEM8(0xA5)
-#define INRQ0 0
-#define INRQ1 1
-#define INRQ2 2
-#define INRQ3 3
-#define INRQ4 4
-#define INRQ5 5
-#define INRQ6 6
-#define INRQ7 7
-
-#define UPINTX _SFR_MEM8(0xA6)
-#define RXINI 0
-#define RXSTALLI 1
-#define TXOUTI 2
-#define TXSTPI 3
-#define PERRI 4
-#define RWAL 5
-#define NAKEDI 6
-#define FIFOCON 7
-
-#define UPNUM _SFR_MEM8(0xA7)
-#define PNUM0 0
-#define PNUM1 1
-
-#define UPRST _SFR_MEM8(0xA8)
-#define P0RST 0
-#define P1RST 1
-#define P2RST 2
-#define P3RST 3
-
-#define UPCRX _SFR_MEM8(0xA9)
-#define PEN 0
-#define RSTDT 3
-#define INMODE 5
-#define PFREEZE 6
-
-#define UPCFG0X _SFR_MEM8(0xAA)
-#define PEPNUM0 0
-#define PEPNUM1 1
-#define PEPNUM2 2
-#define PEPNUM3 3
-#define PTOKEN0 4
-#define PTOKEN1 5
-#define PTYPE0 6
-#define PTYPE1 7
-
-#define UPCFG1X _SFR_MEM8(0xAB)
-#define ALLOC 1
-#define PBK0 2
-#define PBK1 3
-#define PSIZE0 4
-#define PSIZE1 5
-#define PSIZE2 6
-
-#define UPSTAX _SFR_MEM8(0xAC)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UPCFG2X _SFR_MEM8(0xAD)
-#define INTFRQ0 0
-#define INTFRQ1 1
-#define INTFRQ2 2
-#define INTFRQ3 3
-#define INTFRQ4 4
-#define INTFRQ5 5
-#define INTFRQ6 6
-#define INTFRQ7 7
-
-#define UPIENX _SFR_MEM8(0xAE)
-#define RXINE 0
-#define RXSTALLE 1
-#define TXOUTE 2
-#define TXSTPE 3
-#define PERRE 4
-#define NAKEDE 6
-#define FLERRE 7
-
-#define UPDATX _SFR_MEM8(0xAF)
-#define PDAT0 0
-#define PDAT1 1
-#define PDAT2 2
-#define PDAT3 3
-#define PDAT4 4
-#define PDAT5 5
-#define PDAT6 6
-#define PDAT7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A0 0
-#define OCR2A1 1
-#define OCR2A2 2
-#define OCR2A3 3
-#define OCR2A4 4
-#define OCR2A5 5
-#define OCR2A6 6
-#define OCR2A7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B0 0
-#define OCR2B1 1
-#define OCR2B2 2
-#define OCR2B3 3
-#define OCR2B4 4
-#define OCR2B5 5
-#define OCR2B6 6
-#define OCR2B7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR00 0
-#define UBRR01 1
-#define UBRR02 2
-#define UBRR03 3
-#define UBRR04 4
-#define UBRR05 5
-#define UBRR06 6
-#define UBRR07 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR08 0
-#define UBRR09 1
-#define UBRR010 2
-#define UBRR011 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR00 0
-#define UDR01 1
-#define UDR02 2
-#define UDR03 3
-#define UDR04 4
-#define UDR05 5
-#define UDR06 6
-#define UDR07 7
-
-#define USBENUM _SFR_MEM8(0xCA)
-#define USBENUM0 0
-#define USBENUM1 1
-#define USBENUM2 2
-
-#define USBCSEX _SFR_MEM8(0xCB)
-#define TXC 0
-#define RCVD 1
-#define RXSETUP 2
-#define STSENT 3
-#define TXPB 4
-#define FSTALL 5
-#define IERR 6
-
-#define USBDBCEX _SFR_MEM8(0xCC)
-#define BCT0 0
-#define BCT1 1
-#define BCT2 2
-#define BCT3 3
-#define BCT4 4
-#define BCT5 5
-#define BCT6 6
-#define BCT7 7
-
-#define USBFCEX _SFR_MEM8(0xCD)
-#define EPTYP0 0
-#define EPTYP1 1
-#define EPDIR 2
-#define EPE 7
-
-#define HSSPITO _SFR_MEM16(0xD1)
-
-#define HSSPITOL _SFR_MEM8(0xD1)
-#define HSSPITOD0 0
-#define HSSPITOD1 1
-#define HSSPITOD2 2
-#define HSSPITOD3 3
-#define HSSPITOD4 4
-#define HSSPITOD5 5
-#define HSSPITOD6 6
-#define HSSPITOD7 7
-
-#define HSSPITOH _SFR_MEM8(0xD2)
-#define HSSPITOD8 0
-#define HSSPITOD9 1
-#define HSSPITOD10 2
-#define HSSPITOD11 3
-#define HSSPITOD12 4
-#define HSSPITOD13 5
-#define HSSPITOD14 6
-#define HSSPITOD15 7
-
-#define HSSPICNT _SFR_MEM8(0xD3)
-#define HSSPICNTD0 0
-#define HSSPICNTD1 1
-#define HSSPICNTD2 2
-#define HSSPICNTD3 3
-#define HSSPICNTD4 4
-
-#define HSSPIIER _SFR_MEM8(0xD4)
-#define NSSIE 4
-#define RCVOFIE 5
-#define BTDIE 6
-#define TIMEOUTIE 7
-
-#define HSSPIGTR _SFR_MEM8(0xD5)
-#define HSSPIGTD0 0
-#define HSSPIGTD1 1
-#define HSSPIGTD2 2
-#define HSSPIGTD3 3
-#define HSSPIGTD4 4
-#define HSSPIGTD5 5
-#define HSSPIGTD6 6
-#define HSSPIGTD7 7
-
-#define HSSPIRDR _SFR_MEM8(0xD6)
-#define HSSPIRDD0 0
-#define HSSPIRDD1 1
-#define HSSPIRDD2 2
-#define HSSPIRDD3 3
-#define HSSPIRDD4 4
-#define HSSPIRDD5 5
-#define HSSPIRDD6 6
-#define HSSPIRDD7 7
-
-#define HSSPITDR _SFR_MEM8(0xD7)
-#define HSSPITDD0 0
-#define HSSPITDD1 1
-#define HSSPITDD2 2
-#define HSSPITDD3 3
-#define HSSPITDD4 4
-#define HSSPITDD5 5
-#define HSSPITDD6 6
-#define HSSPITDD7 7
-
-#define HSSPISR _SFR_MEM8(0xD8)
-#define SPICKRDY 0
-#define TXBUFE 1
-#define RXBUFF 2
-#define NSS 3
-#define DPRAMRDY 4
-
-#define HSSPICFG _SFR_MEM8(0xD9)
-#define HSSPIEN 0
-#define HSMSTR 1
-#define HSCPOL 2
-#define HSCPHA 3
-#define DPRAM 4
-#define SPICKDIV0 5
-#define SPICKDIV1 6
-#define SPICKDIV2 7
-
-#define HSSPIIR _SFR_MEM8(0xDA)
-#define NSSFE 3
-#define NSSRE 4
-#define RCVOF 5
-#define BTD 6
-#define TIMEOUT 7
-
-#define HSSPICR _SFR_MEM8(0xDB)
-#define CS 0
-#define RETTO 1
-#define STTTO 2
-
-#define HSSPIDMACS _SFR_MEM8(0xDC)
-#define HSSPIDMAR 0
-#define HSSPIDMADIR 1
-#define HSSPIDMAERR 2
-
-#define HSSPIDMAD _SFR_MEM16(0xDD)
-
-#define HSSPIDMADL _SFR_MEM8(0xDD)
-#define HSSPIDMAD0 0
-#define HSSPIDMAD1 1
-#define HSSPIDMAD2 2
-#define HSSPIDMAD3 3
-#define HSSPIDMAD4 4
-#define HSSPIDMAD5 5
-#define HSSPIDMAD6 6
-#define HSSPIDMAD7 7
-
-#define HSSPIDMADH _SFR_MEM8(0xDE)
-#define HSSPIDMAD8 0
-#define HSSPIDMAD9 1
-#define HSSPIDMAD10 2
-#define HSSPIDMAD11 3
-#define HSSPIDMAD12 4
-#define HSSPIDMAD13 5
-
-#define HSSPIDMAB _SFR_MEM8(0xDF)
-#define HSSPIDMAB0 0
-#define HSSPIDMAB1 1
-#define HSSPIDMAB2 2
-#define HSSPIDMAB3 3
-#define HSSPIDMAB4 4
-
-#define USBCR _SFR_MEM8(0xE0)
-#define USBE 1
-#define UPUC 5
-#define URMWU 7
-
-#define USBPI _SFR_MEM8(0xE1)
-#define SUSI 0
-#define RESI 1
-#define RMWUI 2
-#define SOFI 3
-#define FEURI 4
-
-#define USBPIM _SFR_MEM8(0xE2)
-#define SUSIM 0
-#define RESIM 1
-#define RMWUIM 2
-#define SOFIM 3
-
-#define USBEI _SFR_MEM8(0xE3)
-#define EP0I 0
-#define EP1I 1
-#define EP2I 2
-#define EP3I 3
-#define EP4I 4
-#define EP5I 5
-#define EP6I 6
-#define EP7I 7
-
-#define USBEIM _SFR_MEM8(0xE4)
-#define EP0IM 0
-#define EP1IM 1
-#define EP2IM 2
-#define EP3IM 3
-#define EP4IM 4
-#define EP5IM 5
-#define EP6IM 6
-#define EP7IM 7
-
-#define USBRSTE _SFR_MEM8(0xE5)
-#define RSTE0 0
-#define RSTE1 1
-#define RSTE2 2
-#define RSTE3 3
-#define RSTE4 4
-#define RSTE5 5
-#define RSTE6 6
-#define RST7 7
-
-#define USBGS _SFR_MEM8(0xE6)
-#define FAF 0
-#define FCF 1
-#define RMWUE 2
-#define RSMON 3
-
-#define USBFA _SFR_MEM8(0xE7)
-#define FADD0 0
-#define FADD1 1
-#define FADD2 2
-#define FADD3 3
-#define FADD4 4
-#define FADD5 5
-#define FADD6 6
-
-#define USBFN _SFR_MEM16(0xE8)
-
-#define USBFNL _SFR_MEM8(0xE8)
-#define FN0 0
-#define FN1 1
-#define FN2 2
-#define FN3 3
-#define FN4 4
-#define FN5 5
-#define FN6 6
-#define FN7 7
-
-#define USBFNH _SFR_MEM8(0xE9)
-#define FN8 0
-#define FN9 1
-#define FN10 2
-#define FNERR 3
-#define FNEND 4
-
-#define USBDMACS _SFR_MEM8(0xEA)
-#define USBDMAR 0
-#define USBDMADIR 1
-#define USBDMAERR 2
-#define EPS0 4
-#define EPS1 5
-#define EPS2 6
-
-#define USBDMAD _SFR_MEM16(0xEB)
-
-#define USBDMADL _SFR_MEM8(0xEB)
-#define USBDMAD0 0
-#define USBDMAD1 1
-#define USBDMAD2 2
-#define USBDMAD3 3
-#define USBDMAD4 4
-#define USBDMAD5 5
-#define USBDMAD6 6
-#define USBDMAD7 7
-
-#define USBDMADH _SFR_MEM8(0xEC)
-#define USBDMAD8 0
-#define USBDMAD9 1
-#define USBDMAD10 2
-#define USBDMAD11 3
-#define USBDMAD12 4
-#define USBDMAD13 5
-
-#define USBDMAB _SFR_MEM8(0xED)
-#define USBDMAB0 0
-#define USBDMAB1 1
-#define USBDMAB2 2
-#define USBDMAB3 3
-#define USBDMAB4 4
-#define USBDMAB5 5
-#define USBDMAB6 6
-
-#define DCCR _SFR_MEM8(0xEF)
-#define DCBUSY 5
-#define DCRDY 6
-#define DCON 7
-
-#define SCICLK _SFR_MEM8(0xF0)
-#define SCICLK0 0
-#define SCICLK1 1
-#define SCICLK2 2
-#define SCICLK3 3
-#define SCICLK4 4
-#define SCICLK5 5
-
-#define SCWT0 _SFR_MEM8(0xF1)
-#define WT0 0
-#define WT1 1
-#define WT2 2
-#define WT3 3
-#define WT4 4
-#define WT5 5
-#define WT6 6
-#define WT7 7
-
-#define SCWT1 _SFR_MEM8(0xF2)
-#define WT8 0
-#define WT9 1
-#define WT10 2
-#define WT11 3
-#define WT12 4
-#define WT13 5
-#define WT14 6
-#define WT15 7
-
-#define SCWT2 _SFR_MEM8(0xF3)
-#define WT16 0
-#define WT17 1
-#define WT18 2
-#define WT19 3
-#define WT20 4
-#define WT21 5
-#define WT22 6
-#define WT23 7
-
-#define SCWT3 _SFR_MEM8(0xF4)
-#define WT24 0
-#define WT25 1
-#define WT26 2
-#define WT27 3
-#define WT28 4
-#define WT29 5
-#define WT30 6
-#define WT31 7
-
-#define SCGT _SFR_MEM16(0xF5)
-
-#define SCGTL _SFR_MEM8(0xF5)
-#define GT0 0
-#define GT1 1
-#define GT2 2
-#define GT3 3
-#define GT4 4
-#define GT5 5
-#define GT6 6
-#define GT7 7
-
-#define SCGTH _SFR_MEM8(0xF6)
-#define GT8 0
-
-#define SCETU _SFR_MEM16(0xF7)
-
-#define SCETUL _SFR_MEM8(0xF7)
-#define ETU0 0
-#define ETU1 1
-#define ETU2 2
-#define ETU3 3
-#define ETU4 4
-#define ETU5 5
-#define ETU6 6
-#define ETU7 7
-
-#define SCETUH _SFR_MEM8(0xF8)
-#define ETU8 0
-#define ETU9 1
-#define ETU10 2
-#define COMP 7
-
-#define SCIBUF _SFR_MEM8(0xF9)
-#define SCIBUFD0 0
-#define SCIBUFD1 1
-#define SCIBUFD2 2
-#define SCIBUFD3 3
-#define SCIBUFD4 4
-#define SCIBUFD5 5
-#define SCIBUFD6 6
-#define SCIBUFD7 7
-
-#define SCSR _SFR_MEM8(0xFA)
-#define CPRESRES 3
-#define CREPSEL 4
-#define BGTEN 6
-
-#define SCIER _SFR_MEM8(0xFB)
-#define ESCPI 0
-#define ESCRI 1
-#define ESCTI 2
-#define ESCWTI 3
-#define EVCARDER 4
-#define CARDINE 6
-#define ESCTBI 7
-
-#define SCIIR _SFR_MEM8(0xFC)
-#define SCPI 0
-#define SCRI 1
-#define SCTI 2
-#define SCWTI 3
-#define VCARDERR 4
-#define SCTBI 7
-
-#define SCISR _SFR_MEM8(0xFD)
-#define SCPE 0
-#define SCRC 1
-#define SCTC 2
-#define SCWTO 3
-#define VCARDOK 4
-#define CARDIN 6
-#define SCTBE 7
-
-#define SCCON _SFR_MEM8(0xFE)
-#define CARDVCC 0
-#define CARDRST 1
-#define CARDCLK 2
-#define CARDIO 3
-#define CARDC4 4
-#define CARDC8 5
-#define CLK 7
-
-#define SCICR _SFR_MEM8(0xFF)
-#define CONV 0
-#define CREP 1
-#define WTEN 2
-#define UART 3
-#define VCARD0 4
-#define VCARD1 5
-#define CARDDET 6
-#define SCIRESET 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define PCINT0_vect_num  5
-#define PCINT0_vect      _VECTOR(5)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  6
-#define PCINT1_vect      _VECTOR(6)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  7
-#define PCINT2_vect      _VECTOR(7)  /* Pin Change Interrupt Request 2 */
-#define WDT_vect_num  8
-#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  9
-#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  10
-#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect_num  11
-#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  12
-#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  13
-#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  14
-#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  15
-#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  16
-#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  17
-#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  18
-#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  19
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  20
-#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  21
-#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  22
-#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
-#define SUPPLY_MON_vect_num  23
-#define SUPPLY_MON_vect      _VECTOR(23)  /* Supply Monitor Interruption */
-#define RFU_vect_num  24
-#define RFU_vect      _VECTOR(24)  /* Reserved for Future Use */
-#define EE_READY_vect_num  25
-#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect_num  26
-#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect_num  27
-#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
-#define KEYBOARD_vect_num  28
-#define KEYBOARD_vect      _VECTOR(28)  /* Keyboard Input Changed */
-#define AES_Operation_vect_num  29
-#define AES_Operation_vect      _VECTOR(29)  /* AES Block Operation Ended */
-#define HSSPI_vect_num  30
-#define HSSPI_vect      _VECTOR(30)  /* High-Speed SPI Interruption */
-#define USB_Endpoint_vect_num  31
-#define USB_Endpoint_vect      _VECTOR(31)  /* USB Endpoint Related Interruption */
-#define USB_Protocol_vect_num  32
-#define USB_Protocol_vect      _VECTOR(32)  /* USB Protocol Related Interruption */
-#define SCIB_vect_num  33
-#define SCIB_vect      _VECTOR(33)  /* Smart Card Reader Interface */
-#define USBHost_Control_vect_num  34
-#define USBHost_Control_vect      _VECTOR(34)  /* USB Host Controller Interrupt */
-#define USBHost_Pipe_vect_num  35
-#define USBHost_Pipe_vect      _VECTOR(35)  /* USB Host Pipe Interrupt */
-#define CPRES_vect_num  36
-#define CPRES_vect      _VECTOR(36)  /* Card Presence Detection */
-#define PCINT3_vect_num  37
-#define PCINT3_vect      _VECTOR(37)  /* Pin Change Interrupt Request 3 */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Clock Selection */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Clock Selection */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define LFUSE_DEFAULT (FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODENABLE  (unsigned char)~_BV(0)  /* Brown-out Detector Enable Signal */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0xC1
-
-
-/**@}*/
-#endif /* _AVR_AT90SCR100_H_ */
diff --git a/cpukit/score/cpu/avr/avr/ioa6289.h b/cpukit/score/cpu/avr/avr/ioa6289.h
deleted file mode 100644
index d51e3a965a..0000000000
--- a/cpukit/score/cpu/avr/avr/ioa6289.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/**
- * @file avr/ioa6289.h
- *
- * @brief Definitions for ATA6289
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2008 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6289.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATA6289_H_
-#define _AVR_ATA6289_H_ 1
-
-/**
- * @defgroup Avr_ioa6289 ATA6289 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-
-#define DDRC _SFR_IO8(0x07)
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define CMCR _SFR_IO8(0x0F)
-#define CMM0 0
-#define CMM1 1
-#define SRCD 2
-#define CMONEN 3
-#define CCS 4
-#define ECINS 5
-#define CMCCE 7
-
-#define CMSR _SFR_IO8(0x10)
-#define ECF 0
-
-#define T2CRA _SFR_IO8(0x11)
-#define T2OTM 0
-#define T2CTM 1
-#define T2CR 2
-#define T2CRM 3
-#define T2CPRM 4
-#define T2ICS 5
-#define T2TS 6
-#define T2E 7
-
-#define T2CRB _SFR_IO8(0x12)
-#define T2SCE 0
-
-#define T3CRA _SFR_IO8(0x14)
-#define T3AC 0
-#define T3SCE 1
-#define T3CR 2
-#define T3TS 6
-#define T3E 7
-
-#define VMCSR _SFR_IO8(0x16)
-#define VMEN 0
-#define VMLS0 1
-#define VMLS1 2
-#define VMLS2 3
-#define VMIM 4
-#define VMF 5
-#define BODPD 6
-#define BODLS 7
-
-#define PCIFR _SFR_IO8(0x17)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define LFFR _SFR_IO8(0x18)
-#define LFWPF 0
-#define LFBF 1
-#define LFEDF 2
-#define LFRF 3
-
-#define SSFR _SFR_IO8(0x19)
-#define MSENF 0
-#define MSENO 1
-
-#define T10IFR _SFR_IO8(0x1A)
-#define T0F 0
-#define T1F 1
-
-#define T2IFR _SFR_IO8(0x1B)
-#define T2OFF 0
-#define T2COF 1
-#define T2ICF 2
-#define T2RXF 3
-#define T2TXF 4
-#define T2TCF 5
-
-#define T3IFR _SFR_IO8(0x1C)
-#define T3OFF 0
-#define T3COAF 1
-#define T3COBF 2
-#define T3ICF 3
-
-#define EIFR _SFR_IO8(0x1D)
-#define INTF0 0
-#define INTF1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define PCICR _SFR_IO8(0x23)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EIMSK _SFR_IO8(0x24)
-#define INT0 0
-#define INT1 1
-
-#define SVCR _SFR_IO8(0x27)
-#define SVCS0 0
-#define SVCS1 1
-#define SVCS2 2
-#define SVCS3 3
-#define SVCS4 4
-
-#define SCR _SFR_IO8(0x28)
-#define SMS 0
-#define SEN0 1
-#define SEN1 2
-#define SMEN 3
-
-#define SCCR _SFR_IO8(0x29)
-#define SRCC0 0
-#define SRCC1 1
-#define SCCS0 2
-#define SCCS1 3
-#define SCCS2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define T2MDR _SFR_IO8(0x2F)
-#define T2MDR0 0
-#define T2MDR1 1
-#define T2MDR2 2
-#define T2MDR3 3
-#define T2MDR4 4
-#define T2MDR5 5
-#define T2MDR6 6
-#define T2MDR7 7
-
-#define LFRR _SFR_IO8(0x30)
-#define LFRR0 0
-#define LFRR1 1
-#define LFRR2 2
-#define LFRR3 3
-#define LFRR4 4
-#define LFRR5 5
-#define LFRR6 6
-
-#define LFCDR _SFR_IO8(0x32)
-#define LFDO 0
-#define LFRST 6
-#define LFSCE 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define TSRF 5
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-
-#define LFRB _SFR_IO8(0x36)
-#define LFRB0 0
-#define LFRB1 1
-#define LFRB2 2
-#define LFRB3 3
-#define LFRB4 4
-#define LFRB5 5
-#define LFRB6 6
-#define LFRB7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define T1CR _SFR_IO8(0x38)
-#define T1PS0 0
-#define T1PS1 1
-#define T1PS2 2
-#define T1CS0 3
-#define T1CS1 4
-#define T1CS2 5
-#define T1IE 7
-
-#define T0CR _SFR_IO8(0x39)
-#define T0PAS0 0
-#define T0PAS1 1
-#define T0PAS2 2
-#define T0IE 3
-#define T0PR 4
-#define T0PBS0 5
-#define T0PBS1 6
-#define T0PBS2 7
-
-#define CMIMR _SFR_IO8(0x3B)
-#define ECIE 0
-
-#define CLKPR _SFR_IO8(0x3C)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLTPS0 3
-#define CLTPS1 4
-#define CLTPS2 5
-#define CLPCE 7
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDPS0 0
-#define WDPS1 1
-#define WDPS2 2
-#define WDE 3
-#define WDCE 4
-
-#define SIMSK _SFR_MEM8(0x61)
-#define MSIE 0
-
-#define TSCR _SFR_MEM8(0x64)
-#define TSSD 0
-
-#define SRCCAL _SFR_MEM8(0x65)
-#define SCAL0 0
-#define SCAL1 1
-#define SCAL2 2
-#define SCAL3 3
-#define SCAL4 4
-#define SCAL5 5
-#define SCAL6 6
-#define SCAL7 7
-
-#define FRCCAL _SFR_MEM8(0x66)
-#define FCAL0 0
-#define FCAL1 1
-#define FCAL2 2
-#define FCAL3 3
-#define FCAL4 4
-#define FCAL5 5
-#define FCAL6 6
-#define FCAL7 7
-
-#define MSVCAL _SFR_MEM8(0x67)
-#define VRCAL0 0
-#define VRCAL1 1
-#define VRCAL2 2
-#define VRCAL3 3
-#define VRCAL4 4
-#define VRCAL5 5
-#define VRCAL6 6
-#define VRCAL7 7
-
-#define BGCAL _SFR_MEM8(0x68)
-#define BGCAL0 0
-#define BGCAL1 1
-#define BGCAL2 2
-#define BGCAL3 3
-#define BGCAL4 4
-#define BGCAL5 5
-#define BGCAL6 6
-#define BGCAL7 7
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define T2ICR _SFR_MEM16(0x6E)
-
-#define T2ICRL _SFR_MEM8(0x6E)
-#define T2ICRL0 0
-#define T2ICRL1 1
-#define T2ICRL2 2
-#define T2ICRL3 3
-#define T2ICRL4 4
-#define T2ICRL5 5
-#define T2ICRL6 6
-#define T2ICRL7 7
-
-#define T2ICRH _SFR_MEM8(0x6F)
-#define T2ICRH0 0
-#define T2ICRH1 1
-#define T2ICRH2 2
-#define T2ICRH3 3
-#define T2ICRH4 4
-#define T2ICRH5 5
-#define T2ICRH6 6
-#define T2ICRH7 7
-
-#define T2COR _SFR_MEM16(0x70)
-
-#define T2CORL _SFR_MEM8(0x70)
-#define T2CORL0 0
-#define T2CORL1 1
-#define T2CORL2 2
-#define T2CORL3 3
-#define T2CORL4 4
-#define T2CORL5 5
-#define T2CORL6 6
-#define T2CORL7 7
-
-#define T2CORH _SFR_MEM8(0x71)
-#define T2CORH0 0
-#define T2CORH1 1
-#define T2CORH2 2
-#define T2CORH3 3
-#define T2CORH4 4
-#define T2CORH5 5
-#define T2CORH6 6
-#define T2CORH7 7
-
-#define T2MRA _SFR_MEM8(0x72)
-#define T2CS0 0
-#define T2CS1 1
-#define T2CS2 2
-#define T2CE0 3
-#define T2CE1 4
-#define T2CNC 5
-#define T2TP0 6
-#define T2TP1 7
-
-#define T2MRB _SFR_MEM8(0x73)
-#define T2M0 0
-#define T2M1 1
-#define T2M2 2
-#define T2M3 3
-#define T2TOP 4
-#define T2CPOL 6
-#define T2SSIE 7
-
-#define T2IMR _SFR_MEM8(0x74)
-#define T2OIM 0
-#define T2CIM 1
-#define T2CPIM 2
-#define T2RXIM 3
-#define T2TXIM 4
-#define T2TCIM 5
-
-#define T3ICR _SFR_MEM16(0x76)
-
-#define T3ICRL _SFR_MEM8(0x76)
-#define T3ICRL0 0
-#define T3ICRL1 1
-#define T3ICRL2 2
-#define T3ICRL3 3
-#define T3ICRL4 4
-#define T3ICRL5 5
-#define T3ICRL6 6
-#define T3ICRL7 7
-
-#define T3ICRH _SFR_MEM8(0x77)
-#define T3ICRH0 0
-#define T3ICRH1 1
-#define T3ICRH2 2
-#define T3ICRH3 3
-#define T3ICRH4 4
-#define T3ICRH5 5
-#define T3ICRH6 6
-#define T3ICRH7 7
-
-#define T3CORA _SFR_MEM16(0x78)
-
-#define T3CORAL _SFR_MEM8(0x78)
-#define T3CORAL0 0
-#define T3CORAL1 1
-#define T3CORAL2 2
-#define T3CORAL3 3
-#define T3CORAL4 4
-#define T3CORAL5 5
-#define T3CORAL6 6
-#define T3CORAL7 7
-
-#define T3CORAH _SFR_MEM8(0x79)
-#define T3CORAH0 0
-#define T3CORAH1 1
-#define T3CORAH2 2
-#define T3CORAH3 3
-#define T3CORAH4 4
-#define T3CORAH5 5
-#define T3CORAH6 6
-#define T3CORAH7 7
-
-#define T3CORB _SFR_MEM16(0x7A)
-
-#define T3CORBL _SFR_MEM8(0x7A)
-#define T3CORBL0 0
-#define T3CORBL1 1
-#define T3CORBL2 2
-#define T3CORBL3 3
-#define T3CORBL4 4
-#define T3CORBL5 5
-#define T3CORBL6 6
-#define T3CORBL7 7
-
-#define T3CORBH _SFR_MEM8(0x7B)
-#define T3CORBH0 0
-#define T3CORBH1 1
-#define T3CORBH2 2
-#define T3CORBH3 3
-#define T3CORBH4 4
-#define T3CORBH5 5
-#define T3CORBH6 6
-#define T3CORBH7 7
-
-#define T3MRA _SFR_MEM8(0x7C)
-#define T3CS0 0
-#define T3CS1 1
-#define T3CS2 2
-#define T3CE0 3
-#define T3CE1 4
-#define T3CNC 5
-#define T3ICS0 6
-#define T3ICS1 7
-
-#define T3MRB _SFR_MEM8(0x7D)
-#define T3M0 0
-#define T3M1 1
-#define T3M2 2
-#define T3TOP 4
-
-#define T3CRB _SFR_MEM8(0x7E)
-#define T3CTMA 0
-#define T3SAMA 1
-#define T3CRMA 2
-#define T3CTMB 3
-#define T3SAMB 4
-#define T3CRMB 5
-#define T3CPRM 6
-
-#define T3IMR _SFR_MEM8(0x7F)
-#define T3OIM 0
-#define T3CAIM 1
-#define T3CBIM 2
-#define T3CPIM 3
-
-#define LFIMR _SFR_MEM8(0x81)
-#define LFWIM 0
-#define LFBIM 1
-#define LFEIM 2
-
-#define LFRCR _SFR_MEM8(0x82)
-#define LFEN 0
-#define LFBM 1
-#define LFWM0 2
-#define LFWM1 3
-#define LFRSS 4
-#define LFCS0 5
-#define LFCS1 6
-#define LFCS2 7
-
-#define LFHCR _SFR_MEM8(0x83)
-#define LFHCR0 0
-#define LFHCR1 1
-#define LFHCR2 2
-#define LFHCR3 3
-#define LFHCR4 4
-#define LFHCR5 5
-#define LFHCR6 6
-
-#define LFIDC _SFR_MEM16(0x84)
-
-#define LFIDCL _SFR_MEM8(0x84)
-#define LFIDCL_0 0
-#define LFIDCL_1 1
-#define LFIDCL_2 2
-#define LFIDCL_3 3
-#define LFIDCL_4 4
-#define LFIDCL_5 5
-#define LFIDCL_6 6
-#define LFIDCL_7 7
-
-#define LFIDCH _SFR_MEM8(0x85)
-#define LFIDCH_8 0
-#define LFIDCH_9 1
-#define LFIDCH_10 2
-#define LFIDCH_11 3
-#define LFIDCH_12 4
-#define LFIDCH_13 5
-#define LFIDCH_14 6
-#define LFIDCH_15 7
-
-#define LFCAL _SFR_MEM16(0x86)
-
-#define LFCALL _SFR_MEM8(0x86)
-#define LFCAL_00 0
-#define LFCAL_01 1
-#define LFCAL_02 2
-#define LFCAL_03 3
-#define LFCAL_04 4
-#define LFCAL_05 5
-#define LFCAL_06 6
-#define LFCAL_07 7
-
-#define LFCALH _SFR_MEM8(0x87)
-#define LFCAL_08 0
-#define LFCAL_09 1
-#define LFCAL_10 2
-#define LFCAL_11 3
-#define LFCAL_12 4
-#define LFCAL_13 5
-#define LFCAL_14 6
-#define LFCAL_15 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define PCINT0_vect_num  3
-#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  4
-#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  5
-#define PCINT2_vect      _VECTOR(5)  /* Pin Change Interrupt Request 2 */
-#define INTVM_vect_num  6
-#define INTVM_vect      _VECTOR(6)  /* Voltage Monitor Interrupt */
-#define SENINT_vect_num  7
-#define SENINT_vect      _VECTOR(7)  /* Sensor Interface Interrupt */
-#define INTT0_vect_num  8
-#define INTT0_vect      _VECTOR(8)  /* Timer0 Interval Interrupt */
-#define LFWP_vect_num  9
-#define LFWP_vect      _VECTOR(9)  /* LF-Receiver Wake-up Interrupt */
-#define T3CAP_vect_num  10
-#define T3CAP_vect      _VECTOR(10)  /* Timer/Counter3 Capture Event */
-#define T3COMA_vect_num  11
-#define T3COMA_vect      _VECTOR(11)  /* Timer/Counter3 Compare Match A */
-#define T3COMB_vect_num  12
-#define T3COMB_vect      _VECTOR(12)  /* Timer/Counter3 Compare Match B */
-#define T3OVF_vect_num  13
-#define T3OVF_vect      _VECTOR(13)  /* Timer/Counter3 Overflow */
-#define T2CAP_vect_num  14
-#define T2CAP_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
-#define T2COM_vect_num  15
-#define T2COM_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match */
-#define T2OVF_vect_num  16
-#define T2OVF_vect      _VECTOR(16)  /* Timer/Counter2 Overflow */
-#define SPISTC_vect_num  17
-#define SPISTC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define LFRXB_vect_num  18
-#define LFRXB_vect      _VECTOR(18)  /* LF Receive Buffer Interrupt */
-#define INTT1_vect_num  19
-#define INTT1_vect      _VECTOR(19)  /* Timer1 Interval Interrupt */
-#define T2RXB_vect_num  20
-#define T2RXB_vect      _VECTOR(20)  /* Timer2 SSI Receive Buffer Interrupt */
-#define T2TXB_vect_num  21
-#define T2TXB_vect      _VECTOR(21)  /* Timer2 SSI Transmit Buffer Interrupt */
-#define T2TXC_vect_num  22
-#define T2TXC_vect      _VECTOR(22)  /* Timer2 SSI Transmit Complete Interrupt */
-#define LFREOB_vect_num  23
-#define LFREOB_vect      _VECTOR(23)  /* LF-Receiver End of Burst Interrupt */
-#define EXCM_vect_num  24
-#define EXCM_vect      _VECTOR(24)  /* External Input Clock break down Interrupt */
-#define EEREADY_vect_num  25
-#define EEREADY_vect      _VECTOR(25)  /* EEPROM Ready Interrupt */
-#define SPM_RDY_vect_num  26
-#define SPM_RDY_vect      _VECTOR(26)  /* Store Program Memory Ready */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (27 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      RAMEND
-#define E2END        (320 - 1)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (8192 - 1)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_TSRDI ~_BV(0)  /* Disable Temperature shutdown Reset  */
-#define FUSE_BODEN ~_BV(1)  /* Enable Brown-out detection */
-#define FUSE_FRCFS ~_BV(2)  /* Fast RC-Oscillator Frequency select */
-#define FUSE_WDRCON ~_BV(3)  /* Enable Watchdog RC-Oscillator */
-#define FUSE_SUT0 ~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1 ~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT ~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 ~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST ~_BV(0)  /* Select reset vector */
-#define FUSE_BOOTSZ0 ~_BV(1)  /* Boot size select */
-#define FUSE_BOOTSZ1 ~_BV(2)  /* Boot size select */
-#define FUSE_EESAVE ~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON ~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN ~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN ~_BV(6)  /* debugWIRE Enable */
-#define FUSE_EELOCK ~_BV(7)  /* Upper EEPROM Locked (disabled) */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x82
-
-
-/** @} */
-#endif /* _AVR_ATA6289_H_ */
diff --git a/cpukit/score/cpu/avr/avr/ioat94k.h b/cpukit/score/cpu/avr/avr/ioat94k.h
deleted file mode 100644
index dc0cab6890..0000000000
--- a/cpukit/score/cpu/avr/avr/ioat94k.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/**
- * @file avr/ioat94k.h
- *
- * @brief Definitions for AT94K Series FPSLIC(tm)
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOAT94K_H_
-#define _AVR_IOAT94K_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioat94k.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- *  @defgroup Avr_ioat94k AT94K Series FPSLIC(tm) Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* I/O registers */
-
-/* UART1 Baud Rate Register */
-#define UBRR1	_SFR_IO8(0x00)
-
-/* UART1 Control and Status Registers */
-#define UCSR1B	_SFR_IO8(0x01)
-#define UCSR1A	_SFR_IO8(0x02)
-
-/* UART1 I/O Data Register */
-#define UDR1	_SFR_IO8(0x03)
-
-/* 0x04 reserved */
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x05)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x06)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x07)
-
-/* On Chip Debug Register (reserved) */
-#define OCDR    _SFR_IO8(0x08)
-
-/* UART0 Baud Rate Register */
-#define UBRR0	_SFR_IO8(0x09)
-
-/* UART0 Control and Status Registers */
-#define UCSR0B	_SFR_IO8(0x0A)
-#define UCSR0A	_SFR_IO8(0x0B)
-
-/* UART0 I/O Data Register */
-#define UDR0	_SFR_IO8(0x0C)
-
-/* 0x0D..0x0F reserved */
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* FPGA I/O Select Control Register */
-#define FISCR	_SFR_IO8(0x13)
-
-/* FPGA I/O Select Registers A, B, C, D */
-#define FISUA	_SFR_IO8(0x14)
-#define FISUB	_SFR_IO8(0x15)
-#define FISUC	_SFR_IO8(0x16)
-#define FISUD	_SFR_IO8(0x17)
-
-/* FPGA Cache Logic(R) registers (top secret, under NDA) */
-#define FPGAX	_SFR_IO8(0x18)
-#define FPGAY	_SFR_IO8(0x19)
-#define FPGAZ	_SFR_IO8(0x1A)
-#define FPGAD	_SFR_IO8(0x1B)
-
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-
-/* 2-wire Serial Bit Rate Register */
-#define TWBR	_SFR_IO8(0x1C)
-
-/* 2-wire Serial Status Register */
-#define TWSR	_SFR_IO8(0x1D)
-
-/* 2-wire Serial (Slave) Address Register */
-#define TWAR	_SFR_IO8(0x1E)
-
-/* 2-wire Serial Data Register */
-#define TWDR	_SFR_IO8(0x1F)
-
-/* UART Baud Register High */
-#define UBRRH	_SFR_IO8(0x20)
-#define UBRRHI	UBRRH           /* New name in datasheet (1138F-FPSLI-06/02) */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x22)
-
-/* Timer/Counter2 (8-bit) */
-#define TCNT2	_SFR_IO8(0x23)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Asynchronous mode StatuS Register */
-#define ASSR	_SFR_IO8(0x26)
-
-/* Timer/Counter2 Control Register */
-#define TCCR2	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare RegisterB */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare RegisterA */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR	_SFR_IO8(0x30)
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-/* MCU Control/Status Register */
-#define MCUR	_SFR_IO8(0x35)
-
-/* 2-wire Serial Control Register */
-#define TWCR	_SFR_IO8(0x36)
-
-/* 0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* Software Control Register */
-#define SFTCR	_SFR_IO8(0x3A)
-
-/* External Interrupt Mask/Flag Register */
-#define EIMF	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_FPGA_INTERRUPT0     _VECTOR(1)   /* FPGA_INT0  */
-#define SIG_INTERRUPT0          _VECTOR(2)   /* EXT_INT0   */
-#define SIG_FPGA_INTERRUPT1     _VECTOR(3)   /* FPGA_INT1  */
-#define SIG_INTERRUPT1          _VECTOR(4)   /* EXT_INT1   */
-#define SIG_FPGA_INTERRUPT2     _VECTOR(5)   /* FPGA_INT2  */
-#define SIG_INTERRUPT2          _VECTOR(6)   /* EXT_INT2   */
-#define SIG_FPGA_INTERRUPT3     _VECTOR(7)   /* FPGA_INT3  */
-#define SIG_INTERRUPT3          _VECTOR(8)   /* EXT_INT3   */
-#define SIG_OUTPUT_COMPARE2     _VECTOR(9)   /* TIM2_COMP  */
-#define SIG_OVERFLOW2           _VECTOR(10)  /* TIM2_OVF   */
-#define SIG_INPUT_CAPTURE1      _VECTOR(11)  /* TIM1_CAPT  */
-#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)  /* TIM1_COMPA */
-#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)  /* TIM1_COMPB */
-#define SIG_OVERFLOW1           _VECTOR(14)  /* TIM1_OVF   */
-#define SIG_OUTPUT_COMPARE0     _VECTOR(15)  /* TIM0_COMP  */
-#define SIG_OVERFLOW0           _VECTOR(16)  /* TIM0_OVF   */
-#define SIG_FPGA_INTERRUPT4     _VECTOR(17)  /* FPGA_INT4  */
-#define SIG_FPGA_INTERRUPT5     _VECTOR(18)  /* FPGA_INT5  */
-#define SIG_FPGA_INTERRUPT6     _VECTOR(19)  /* FPGA_INT6  */
-#define SIG_FPGA_INTERRUPT7     _VECTOR(20)  /* FPGA_INT7  */
-#define SIG_UART0_RECV          _VECTOR(21)  /* UART0_RXC  */
-#define SIG_UART0_DATA          _VECTOR(22)  /* UART0_DRE  */
-#define SIG_UART0_TRANS         _VECTOR(23)  /* UART0_TXC  */
-#define SIG_FPGA_INTERRUPT8     _VECTOR(24)  /* FPGA_INT8  */
-#define SIG_FPGA_INTERRUPT9     _VECTOR(25)  /* FPGA_INT9  */
-#define SIG_FPGA_INTERRUPT10    _VECTOR(26)  /* FPGA_INT10 */
-#define SIG_FPGA_INTERRUPT11    _VECTOR(27)  /* FPGA_INT11 */
-#define SIG_UART1_RECV          _VECTOR(28)  /* UART1_RXC  */
-#define SIG_UART1_DATA          _VECTOR(29)  /* UART1_DRE  */
-#define SIG_UART1_TRANS         _VECTOR(30)  /* UART1_TXC  */
-#define SIG_FPGA_INTERRUPT12    _VECTOR(31)  /* FPGA_INT12 */
-#define SIG_FPGA_INTERRUPT13    _VECTOR(32)  /* FPGA_INT13 */
-#define SIG_FPGA_INTERRUPT14    _VECTOR(33)  /* FPGA_INT14 */
-#define SIG_FPGA_INTERRUPT15    _VECTOR(34)  /* FPGA_INT15 */
-#define SIG_2WIRE_SERIAL        _VECTOR(35)  /* TWS_INT    */
-
-#define _VECTORS_SIZE 144
-
-/* Bit numbers (SFRs alphabetically sorted) */
-
-/* ASSR */
-#define AS2           3
-#define TCN2UB        2
-#define OCR2UB        1
-#define TCR2UB        0
-
-/* DDRD */
-#define DDD7          7
-#define DDD6          6
-#define DDD5          5
-#define DDD4          4
-#define DDD3          3
-#define DDD2          2
-#define DDD1          1
-#define DDD0          0
-
-/* DDRE */
-#define DDE7          7
-#define DDE6          6
-#define DDE5          5
-#define DDE4          4
-#define DDE3          3
-#define DDE2          2
-#define DDE1          1
-#define DDE0          0
-
-/* EIMF */
-#define INTF3         7
-#define INTF2         6
-#define INTF1         5
-#define INTF0         4
-#define INT3          3
-#define INT2          2
-#define INT1          1
-#define INT0          0
-
-/* FISCR */
-#define FIADR         7
-#define XFIS1         1
-#define XFIS0         0
-
-/* FISUA */
-#define FIF3          7
-#define FIF2          6
-#define FIF1          5
-#define FIF0          4
-#define FINT3         3
-#define FINT2         2
-#define FINT1         1
-#define FINT0         0
-
-/* FISUB */
-#define FIF7          7
-#define FIF6          6
-#define FIF5          5
-#define FIF4          4
-#define FINT7         3
-#define FINT6         2
-#define FINT5         1
-#define FINT4         0
-
-/* FISUC */
-#define FIF11         7
-#define FIF10         6
-#define FIF9          5
-#define FIF8          4
-#define FINT11        3
-#define FINT10        2
-#define FINT9         1
-#define FINT8         0
-
-/* FISUD */
-#define FIF15         7
-#define FIF14         6
-#define FIF13         5
-#define FIF12         4
-#define FINT15        3
-#define FINT14        2
-#define FINT13        1
-#define FINT12        0
-
-/* MCUR */
-#define JTRF          7
-#define JTD           6
-#define SE            5
-#define SM1           4
-#define SM0           3
-#define PORF          2
-#define WDRF          1
-#define EXTRF         0
-
-/* OCDR (reserved) */
-#define IDRD          7
-
-/* PIND */
-#define PIND7         7
-#define PIND6         6
-#define PIND5         5
-#define PIND4         4
-#define PIND3         3
-#define PIND2         2
-#define PIND1         1
-#define PIND0         0
-
-/* PINE */
-#define PINE7         7
-#define PINE6         6
-#define PINE5         5
-#define PINE4         4
-#define PINE3         3
-#define PINE2         2
-#define PINE1         1
-#define PINE0         0
-
-/* PORTD */
-#define PD7        7
-#define PD6        6
-#define PD5        5
-#define PD4        4
-#define PD3        3
-#define PD2        2
-#define PD1        1
-#define PD0        0
-
-/* PORTE */
-/*
-   PE7 = IC1  / INT3 (alternate)
-   PE6 = OC1A / INT2 (alternate)
-   PE5 = OC1B / INT1 (alternate)
-   PE4 = ET11 / INT0 (alternate)
-   PE3 = OC2  / RX1  (alternate)
-   PE2 =      / TX1  (alternate)
-   PE1 = OC0  / RX0  (alternate)
-   PE0 = ET0  / TX0  (alternate)
- */
-#define PE7        7
-#define PE6        6
-#define PE5        5
-#define PE4        4
-#define PE3        3
-#define PE2        2
-#define PE1        1
-#define PE0        0
-
-/* SFIOR */
-#define PSR2          1
-#define PSR10         0
-
-/* SFTCR */
-#define FMXOR         3
-#define WDTS          2
-#define DBG           1
-#define SRST          0
-
-/* TCCR0 */
-#define FOC0          7
-#define PWM0          6
-#define COM01         5
-#define COM00         4
-#define CTC0          3
-#define CS02          2
-#define CS01          1
-#define CS00          0
-
-/* TCCR1A */
-#define COM1A1        7
-#define COM1A0        6
-#define COM1B1        5
-#define COM1B0        4
-#define FOC1A         3
-#define FOC1B         2
-#define PWM11         1
-#define PWM10         0
-
-/* TCCR1B */
-#define ICNC1         7
-#define ICES1         6
-#define ICPE          5
-#define CTC1          3
-#define CS12          2
-#define CS11          1
-#define CS10          0
-
-/* TCCR2 */
-#define FOC2          7
-#define PWM2          6
-#define COM21         5
-#define COM20         4
-#define CTC2          3
-#define CS22          2
-#define CS21          1
-#define CS20          0
-
-/* TIFR */
-#define TOV1          7
-#define OCF1A         6
-#define OCF1B         5
-#define TOV2          4
-#define ICF1          3
-#define OCF2          2
-#define TOV0          1
-#define OCF0          0
-
-/* TIMSK */
-#define TOIE1         7
-#define OCIE1A        6
-#define OCIE1B        5
-#define TOIE2         4
-#define TICIE1        3
-#define OCIE2         2
-#define TOIE0         1
-#define OCIE0         0
-
-/* TWAR */
-/* #define TWA           1 */ /* TWA is bits 7:1 */
-#define TWGCE         0
-
-/* TWCR */
-#define TWINT         7
-#define TWEA          6
-#define TWSTA         5
-#define TWSTO         4
-#define TWWC          3
-#define TWEN          2
-#define TWIE          0
-
-/* TWSR */
-#define TWS7          7
-#define TWS6          6
-#define TWS5          5
-#define TWS4          4
-#define TWS3          3
-
-/* UBRRHI
-   Bits 11..8 of UART1 are bits 7..4 of UBRRHI.
-   Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */
-/* #define UBRRHI1       4 */
-/* #define UBRRHI0       0 */
-
-/* UCSR0A */
-#define RXC0          7
-#define TXC0          6
-#define UDRE0         5
-#define FE0           4
-#define OR0           3
-#define U2X0          1
-#define MPCM0         0
-
-/* UCSR0B */
-#define RXCIE0        7
-#define TXCIE0        6
-#define UDRIE0        5
-#define RXEN0         4
-#define TXEN0         3
-#define CHR90         2
-#define RXB80         1
-#define TXB80         0
-
-/* UCSR1A */
-#define RXC1          7
-#define TXC1          6
-#define UDRE1         5
-#define FE1           4
-#define OR1           3
-#define U2X1          1
-#define MPCM1         0
-
-/* UCSR1B */
-#define RXCIE1        7
-#define TXCIE1        6
-#define UDRIE1        5
-#define RXEN1         4
-#define TXEN1         3
-#define CHR91         2
-#define RXB81         1
-#define TXB81         0
-
-/* WDTCR */
-#define WDTOE         4
-#define WDE           3
-#define WDP2          2
-#define WDP1          1
-#define WDP0          0
-
-/*
-   Last memory addresses - depending on configuration, it is possible
-   to have 20K-32K of program memory and 4K-16K of data memory
-   (all in the same 36K total of SRAM, loaded from external EEPROM).
- */
-
-#ifndef RAMEND
-#define RAMEND 0x0FFF
-#endif
-
-#ifndef XRAMEND
-#define XRAMEND RAMEND
-#endif
-
-#define E2END 0
-
-#ifndef FLASHEND
-#define FLASHEND 0x7FFF
-#endif
-
-/**@}*/
-#endif /* _AVR_IOAT94K_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan128.h b/cpukit/score/cpu/avr/avr/iocan128.h
deleted file mode 100644
index d7996f0c8b..0000000000
--- a/cpukit/score/cpu/avr/avr/iocan128.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright (c) 2004,2005, Colin O'Flynn <coflynn@newae.com>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iocan128.h - definitions for CAN128 */
-
-#ifndef _AVR_IOCAN128_H_
-#define _AVR_IOCAN128_H_ 1
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x0FFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x81
-
-
-#endif  /* _AVR_IOCAN128_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan32.h b/cpukit/score/cpu/avr/avr/iocan32.h
deleted file mode 100644
index 512b45d7b5..0000000000
--- a/cpukit/score/cpu/avr/avr/iocan32.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * @file iocan32.h
- *
- * @brief Definitions for CAN32
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOCAN32_H_
-#define _AVR_IOCAN32_H_ 1
-
-/**
- * @defgroup AvrDef_CAN32 CAN32 Defintions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x08FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x03FF
-#define E2PAGESIZE   8
-#define FLASHEND     0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x81
-
-
-/** @} */
-#endif  /* _AVR_IOCAN32_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan64.h b/cpukit/score/cpu/avr/avr/iocan64.h
deleted file mode 100644
index d7525c0939..0000000000
--- a/cpukit/score/cpu/avr/avr/iocan64.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iocan64.h - definitions for CAN64 */
-
-#ifndef _AVR_IOCAN64_H_
-#define _AVR_IOCAN64_H_ 1
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x07FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x81
-
-
-#endif  /* _AVR_IOCAN64_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocanxx.h b/cpukit/score/cpu/avr/avr/iocanxx.h
deleted file mode 100644
index a593539cb1..0000000000
--- a/cpukit/score/cpu/avr/avr/iocanxx.h
+++ /dev/null
@@ -1,1990 +0,0 @@
-/**
- * @file iocanxx.h
- *
- * @brief Definitions for AT90CAN32, AT90CAN64 and AT90CAN128
- *
- * This file should only be included from <avr/io.h>, never directly.
- *
- * This file is based largely on:
- * - iom128.h by Peter Jansen (bit defines)
- * - iom169.h by Juergen Schilling <juergen.schilling@honeywell.com>
- *   (register addresses)
- * - AT90CAN128 Datasheet (bit defines and register addresses)
- * - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need
- *   to change)
- */
-
-/*
- *   Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOCANXX_H_
-#define _AVR_IOCANXX_H_ 1
-
-/**
- *  @defgroup Avr_iocanxx AT90CAN32, AT90CAN64, AT90CAN128 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iocanxx.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers and bit definitions. */
-
-/* RegDef:  Port A */
-#define PINA   _SFR_IO8(0x00)
-#define DDRA   _SFR_IO8(0x01)
-#define PORTA  _SFR_IO8(0x02)
-
-/* RegDef:  Port B */
-#define PINB   _SFR_IO8(0x03)
-#define DDRB   _SFR_IO8(0x04)
-#define PORTB  _SFR_IO8(0x05)
-
-/* RegDef:  Port C */
-#define PINC   _SFR_IO8(0x06)
-#define DDRC   _SFR_IO8(0x07)
-#define PORTC  _SFR_IO8(0x08)
-
-/* RegDef:  Port D */
-#define PIND   _SFR_IO8(0x09)
-#define DDRD   _SFR_IO8(0x0A)
-#define PORTD  _SFR_IO8(0x0B)
-
-/* RegDef:  Port E */
-#define PINE   _SFR_IO8(0x0C)
-#define DDRE   _SFR_IO8(0x0D)
-#define PORTE  _SFR_IO8(0x0E)
-
-/* RegDef:  Port F */
-#define PINF   _SFR_IO8(0x0F)
-#define DDRF   _SFR_IO8(0x10)
-#define PORTF  _SFR_IO8(0x11)
-
-/* RegDef:  Port G */
-#define PING   _SFR_IO8(0x12)
-#define DDRG   _SFR_IO8(0x13)
-#define PORTG  _SFR_IO8(0x14)
-
-/* RegDef:  Timer/Counter 0 interrupt Flag Register */
-#define TIFR0  _SFR_IO8(0x15)
-
-/* RegDef:  Timer/Counter 1 interrupt Flag Register */
-#define TIFR1  _SFR_IO8(0x16)
-
-/* RegDef:  Timer/Counter 2 interrupt Flag Register */
-#define TIFR2  _SFR_IO8(0x17)
-
-/* RegDef:  Timer/Counter 3 interrupt Flag Register */
-#define TIFR3  _SFR_IO8(0x18)
-
-/* RegDef:  External Interrupt Flag Register */
-#define EIFR   _SFR_IO8(0x1C)
-
-/* RegDef:  External Interrupt Mask Register */
-#define EIMSK  _SFR_IO8(0x1D)
-
-/* RegDef:  General Purpose I/O Register 0 */
-#define GPIOR0 _SFR_IO8(0x1E)
-
-/* RegDef:  EEPROM Control Register */
-#define EECR   _SFR_IO8(0x1F)
-
-/* RegDef:  EEPROM Data Register */
-#define EEDR   _SFR_IO8(0x20)
-
-/* RegDef:  EEPROM Address Register */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* RegDef:  General Timer/Counter Control Register */
-#define GTCCR  _SFR_IO8(0x23)
-
-/* RegDef:  Timer/Counter Control Register A */
-#define TCCR0A _SFR_IO8(0x24)
-
-/* RegDef:  Timer/Counter Register */
-#define TCNT0  _SFR_IO8(0x26)
-
-/* RegDef:  Output Compare Register A */
-#define OCR0A  _SFR_IO8(0x27)
-
-/* RegDef:  General Purpose I/O Register 1 */
-#define GPIOR1 _SFR_IO8(0x2A)
-
-/* RegDef:  General Purpose I/O Register 2 */
-#define GPIOR2 _SFR_IO8(0x2B)
-
-/* RegDef:  SPI Control Register */
-#define SPCR   _SFR_IO8(0x2C)
-
-/* RegDef:  SPI Status Register */
-#define SPSR   _SFR_IO8(0x2D)
-
-/* RegDef:  SPI Data Register */
-#define SPDR   _SFR_IO8(0x2E)
-
-/* RegDef:  Analog Comperator Control and Status Register */
-#define ACSR   _SFR_IO8(0x30)
-
-/* RegDef:  On-chip Debug Register */
-#define OCDR   _SFR_IO8(0x31)
-
-/* RegDef:  Sleep Mode Control Register */
-#define SMCR   _SFR_IO8(0x33)
-
-/* RegDef:  MCU Status Register */
-#define MCUSR  _SFR_IO8(0x34)
-
-/* RegDef:  MCU Control Rgeister */
-#define MCUCR  _SFR_IO8(0x35)
-
-/* RegDef:  Store Program Memory Control and Status Register */
-#define SPMCSR _SFR_IO8(0x37)
-
-/* RegDef:  RAMPZ register. */
-#define RAMPZ  _SFR_IO8(0x3B)
-
-/* RegDef:  Watchdog Timer Control Register */
-#define WDTCR  _SFR_MEM8(0x60)
-
-/* RegDef:  Clock Prescale Register */
-#define CLKPR  _SFR_MEM8(0x61)
-
-/* RegDef:  Oscillator Calibration Register */
-#define OSCCAL _SFR_MEM8(0x66)
-
-/* RegDef:  External Interrupt Control Register A */
-#define EICRA  _SFR_MEM8(0x69)
-
-/* RegDef:  External Interrupt Control Register B */
-#define EICRB  _SFR_MEM8(0x6A)
-
-/* RegDef:  Timer/Counter 0 Interrupt Mask Register */
-#define TIMSK0 _SFR_MEM8(0x6E)
-
-/* RegDef:  Timer/Counter 1 Interrupt Mask Register */
-#define TIMSK1 _SFR_MEM8(0x6F)
-
-/* RegDef:  Timer/Counter 2 Interrupt Mask Register */
-#define TIMSK2 _SFR_MEM8(0x70)
-
-/* RegDef:  Timer/Counter 3 Interrupt Mask Register */
-#define TIMSK3 _SFR_MEM8(0x71)
-
-/* RegDef:  External Memory Control Register A */
-#define XMCRA _SFR_MEM8(0x74)
-
-/* RegDef:  External Memory Control Register A */
-#define XMCRB _SFR_MEM8(0x75)
-
-/* RegDef:  ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC    _SFR_MEM16(0x78)
-#endif
-#define ADCW   _SFR_MEM16(0x78)
-#define ADCL   _SFR_MEM8(0x78)
-#define ADCH   _SFR_MEM8(0x79)
-
-/* RegDef:  ADC Control and Status Register A */
-#define ADCSRA _SFR_MEM8(0x7A)
-
-/* RegDef:  ADC Control and Status Register B */
-#define ADCSRB _SFR_MEM8(0x7B)
-
-/* RegDef:  ADC Multiplex Selection Register */
-#define ADMUX  _SFR_MEM8(0x7C)
-
-/* RegDef:  Digital Input Disable Register 0 */
-#define DIDR0  _SFR_MEM8(0x7E)
-
-/* RegDef:  Digital Input Disable Register 1 */
-#define DIDR1  _SFR_MEM8(0x7F)
-
-/* RegDef:  Timer/Counter1 Control Register A */
-#define TCCR1A _SFR_MEM8(0x80)
-
-/* RegDef:  Timer/Counter1 Control Register B */
-#define TCCR1B _SFR_MEM8(0x81)
-
-/* RegDef:  Timer/Counter1 Control Register C */
-#define TCCR1C _SFR_MEM8(0x82)
-
-/* RegDef:  Timer/Counter1 Register */
-#define TCNT1  _SFR_MEM16(0x84)
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1H _SFR_MEM8(0x85)
-
-/* RegDef:  Timer/Counter1 Input Capture Register */
-#define ICR1   _SFR_MEM16(0x86)
-#define ICR1L  _SFR_MEM8(0x86)
-#define ICR1H  _SFR_MEM8(0x87)
-
-/* RegDef:  Timer/Counter1 Output Compare Register A */
-#define OCR1A  _SFR_MEM16(0x88)
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AH _SFR_MEM8(0x89)
-
-/* RegDef:  Timer/Counter1 Output Compare Register B */
-#define OCR1B  _SFR_MEM16(0x8A)
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BH _SFR_MEM8(0x8B)
-
-/* RegDef:  Timer/Counter1 Output Compare Register C */
-#define OCR1C  _SFR_MEM16(0x8C)
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CH _SFR_MEM8(0x8D)
-
-/* RegDef:  Timer/Counter3 Control Register A */
-#define TCCR3A _SFR_MEM8(0x90)
-
-/* RegDef:  Timer/Counter3 Control Register B */
-#define TCCR3B _SFR_MEM8(0x91)
-
-/* RegDef:  Timer/Counter3 Control Register C */
-#define TCCR3C _SFR_MEM8(0x92)
-
-/* RegDef:  Timer/Counter3 Register */
-#define TCNT3  _SFR_MEM16(0x94)
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3H _SFR_MEM8(0x95)
-
-/* RegDef:  Timer/Counter3 Input Capture Register */
-#define ICR3   _SFR_MEM16(0x96)
-#define ICR3L  _SFR_MEM8(0x96)
-#define ICR3H  _SFR_MEM8(0x97)
-
-/* RegDef:  Timer/Counter3 Output Compare Register A */
-#define OCR3A  _SFR_MEM16(0x98)
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AH _SFR_MEM8(0x99)
-
-/* RegDef:  Timer/Counter3 Output Compare Register B */
-#define OCR3B  _SFR_MEM16(0x9A)
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3BH _SFR_MEM8(0x9B)
-
-/* RegDef:  Timer/Counter3 Output Compare Register C */
-#define OCR3C  _SFR_MEM16(0x9C)
-#define OCR3CL _SFR_MEM8(0x9C)
-#define OCR3CH _SFR_MEM8(0x9D)
-
-/* RegDef:  Timer/Counter2 Control Register A */
-#define TCCR2A _SFR_MEM8(0xB0)
-
-/* RegDef:  Timer/Counter2 Register */
-#define TCNT2  _SFR_MEM8(0xB2)
-
-/* RegDef:  Timer/Counter2 Output Compare Register */
-#define OCR2A  _SFR_MEM8(0xB3)
-
-/* RegDef:  Asynchronous Status Register */
-#define ASSR   _SFR_MEM8(0xB6)
-
-/* RegDef:  TWI Bit Rate Register */
-#define TWBR   _SFR_MEM8(0xB8)
-
-/* RegDef:  TWI Status Register */
-#define TWSR   _SFR_MEM8(0xB9)
-
-/* RegDef:  TWI (Slave) Address Register */
-#define TWAR   _SFR_MEM8(0xBA)
-
-/* RegDef:  TWI Data Register */
-#define TWDR   _SFR_MEM8(0xBB)
-
-/* RegDef:  TWI Control Register */
-#define TWCR   _SFR_MEM8(0xBC)
-
-/* RegDef:  USART0 Control and Status Register A */
-#define UCSR0A _SFR_MEM8(0xC0)
-
-/* RegDef:  USART0 Control and Status Register B */
-#define UCSR0B _SFR_MEM8(0xC1)
-
-/* RegDef:  USART0 Control and Status Register C */
-#define UCSR0C _SFR_MEM8(0xC2)
-
-/* RegDef:  USART0 Baud Rate Register */
-#define UBRR0  _SFR_MEM16(0xC4)
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0H _SFR_MEM8(0xC5)
-
-/* RegDef:  USART0 I/O Data Register */
-#define UDR0   _SFR_MEM8(0xC6)
-
-/* RegDef:  USART1 Control and Status Register A */
-#define UCSR1A _SFR_MEM8(0xC8)
-
-/* RegDef:  USART1 Control and Status Register B */
-#define UCSR1B _SFR_MEM8(0xC9)
-
-/* RegDef:  USART1 Control and Status Register C */
-#define UCSR1C _SFR_MEM8(0xCA)
-
-/* RegDef:  USART1 Baud Rate Register */
-#define UBRR1  _SFR_MEM16(0xCC)
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1H _SFR_MEM8(0xCD)
-
-/* RegDef:  USART1 I/O Data Register */
-#define UDR1   _SFR_MEM8(0xCE)
-
-/* RegDef:  CAN General Control Register*/
-#define CANGCON _SFR_MEM8(0xD8)
-
-/* RegDef:  CAN General Status Register*/
-#define CANGSTA _SFR_MEM8(0xD9)
-
-/* RegDef:  CAN General Interrupt Register*/
-#define CANGIT _SFR_MEM8(0xDA)
-
-/* RegDef:  CAN General Interrupt Enable Register*/
-#define CANGIE _SFR_MEM8(0xDB)
-
-/* RegDef:  CAN Enable MOb Register*/
-#define CANEN2 _SFR_MEM8(0xDC)
-
-/* RegDef:  CAN Enable MOb Register*/
-#define CANEN1 _SFR_MEM8(0xDD)
-
-/* RegDef:  CAN Enable Interrupt MOb Register*/
-#define CANIE2 _SFR_MEM8(0xDE)
-
-/* RegDef:  CAN Enable Interrupt MOb Register*/
-#define CANIE1 _SFR_MEM8(0xDF)
-
-/* RegDef:  CAN Status Interrupt MOb Register*/
-/*
- * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
- * register.
- */
-#define CANSIT  _SFR_MEM16(0xE0)
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-/* RegDef:  CAN Bit Timing Register 1*/
-#define CANBT1 _SFR_MEM8(0xE2)
-
-/* RegDef:  CAN Bit Timing Register 2*/
-#define CANBT2 _SFR_MEM8(0xE3)
-
-/* RegDef:  CAN Bit Timing Register 3*/
-#define CANBT3 _SFR_MEM8(0xE4)
-
-/* RegDef:  CAN Timer Control Register*/
-#define CANTCON _SFR_MEM8(0xE5)
-
-/* RegDef:  CAN Timer Register*/
-#define CANTIM _SFR_MEM16(0xE6)
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIMH _SFR_MEM8(0xE7)
-
-/* RegDef:  CAN TTC Timer Register*/
-#define CANTTC _SFR_MEM16(0xE8)
-#define CANTTCL _SFR_MEM8(0xE8)
-#define CANTTCH _SFR_MEM8(0xE9)
-
-/* RegDef:  CAN Transmitt Error Counter Register*/
-#define CANTEC _SFR_MEM8(0xEA)
-
-/* RegDef:  CAN Receive Error Counter Register*/
-#define CANREC _SFR_MEM8(0xEB)
-
-/* RegDef:  CAN Highest Priority MOb Register*/
-#define CANHPMOB _SFR_MEM8(0xEC)
-
-/* RegDef:  CAN Page MOb Register*/
-#define CANPAGE _SFR_MEM8(0xED)
-
-/* RegDef:  CAN MOb Status Register*/
-#define CANSTMOB _SFR_MEM8(0xEE)
-
-/* RegDef:  CAN MOb Control and DLC Register*/
-#define CANCDMOB _SFR_MEM8(0xEF)
-
-/* RegDef:  CAN Identifier Tag Registers*/
-#define CANIDT  _SFR_MEM32(0xF0)
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define CANIDT1 _SFR_MEM8(0xF3)
-
-/* RegDef:  CAN Identifier Mask Registers */
-#define CANIDM  _SFR_MEM32(0xF4)
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define CANIDM1 _SFR_MEM8(0xF7)
-
-/* RegDef:  CAN TTC Timer Register*/
-#define CANSTM _SFR_MEM16(0xF8)
-#define CANSTML _SFR_MEM8(0xF8)
-#define CANSTMH _SFR_MEM8(0xF9)
-
-/* RegDef:  CAN Message Register*/
-#define CANMSG _SFR_MEM8(0xFA)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* CAN Transfer Complete or Error */
-#define CANIT_vect			_VECTOR(18)
-#define SIG_CAN_INTERRUPT1		_VECTOR(18)
-
-/* CAN Timer Overrun */
-#define OVRIT_vect			_VECTOR(19)
-#define SIG_CAN_OVERFLOW1		_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(21)
-#define SIG_UART0_RECV			_VECTOR(21)
-#define SIG_USART0_RECV			_VECTOR(21)
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect		_VECTOR(22)
-#define SIG_UART0_DATA			_VECTOR(22)
-#define SIG_USART0_DATA			_VECTOR(22)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(23)
-#define SIG_UART0_TRANS			_VECTOR(23)
-#define SIG_USART0_TRANS		_VECTOR(23)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(24)
-#define SIG_COMPARATOR			_VECTOR(24)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(25)
-#define SIG_ADC				_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(27)
-#define SIG_INPUT_CAPTURE3		_VECTOR(27)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(28)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(28)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(29)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(29)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(30)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(30)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(31)
-#define SIG_OVERFLOW3			_VECTOR(31)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(32)
-#define SIG_UART1_RECV			_VECTOR(32)
-#define SIG_USART1_RECV			_VECTOR(32)
-
-/* USART1, Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(33)
-#define SIG_UART1_DATA			_VECTOR(33)
-#define SIG_USART1_DATA			_VECTOR(33)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(34)
-#define SIG_UART1_TRANS			_VECTOR(34)
-#define SIG_USART1_TRANS		_VECTOR(34)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(35)
-#define SIG_2WIRE_SERIAL		_VECTOR(35)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(36)
-#define SIG_SPM_READY			_VECTOR(36)
-
-#define _VECTORS_SIZE 148
-
-/* The Register Bit names are represented by their bit number (0-7). */
-
-/* Register Bits [ASSR]  */
-/* Asynchronous Status Register */
-#define    EXCLK      4
-#define    AS2        3
-#define    TCN2UB     2
-#define    OCR2UB     1
-#define    TCR2UB     0
-/* End Register Bits */
-
-/* Register Bits [TWCR] */
-/* 2-wire Control Register - TWCR */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-/* End Register Bits */
-
-/* Register Bits [TWAR]  */
-/* 2-wire Address Register - TWAR */
-#define    TWA6         7
-#define    TWA5         6
-#define    TWA4         5
-#define    TWA3         4
-#define    TWA2         3
-#define    TWA1         2
-#define    TWA0         1
-#define    TWGCE        0
-/* End Register Bits */
-
-/* Register Bits [TWSR]  */
-/* 2-wire Status Register - TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-/* End Register Bits */
-
-/* Register Bits [XMCRB]  */
-/* External Memory Control Register B - XMCRB */
-#define    XMBK         7
-#define    XMM2         2
-#define    XMM1         1
-#define    XMM0         0
-/* End Register Bits */
-
-/* Register Bits [XMCRA]  */
-/* External Memory Control Register A - XMCRA */
-#define    SRE         7
-#define    SRL2        6
-#define    SRL1        5
-#define    SRL0        4
-#define    SRW11       3
-#define    SRW10       2
-#define    SRW01       1
-#define    SRW00       0
-/* End Register Bits */
-
-/* Register Bits [RAMPZ]  */
-/* RAM Page Z select register - RAMPZ */
-#define     RAMPZ0      0
-/* End Register Bits */
-
-/* Register Bits [EICRA]  */
-/* External Interrupt Control Register A - EICRA */
-#define    ISC31        7
-#define    ISC30        6
-#define    ISC21        5
-#define    ISC20        4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-/* End Register Bits */
-
-/* Register Bits [EICRB]  */
-/* External Interrupt Control Register B - EICRB */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-/* End Register Bits */
-
-/* Register Bits [SPMCSR]  */
-/* Store Program Memory Control Register - SPMCSR, SPMCR */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-/* End Register Bits */
-
-/* Register Bits [EIMSK]  */
-/* External Interrupt MaSK register - EIMSK */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-/* End Register Bits */
-
-/* Register Bits [EIFR]  */
-/* External Interrupt Flag Register - EIFR */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-#define    INTF3        3
-#define    INTF2        2
-#define    INTF1        1
-#define    INTF0        0
-/* End Register Bits */
-
-/* Register Bits [TCCR2]  */
-/* Timer/Counter 2 Control Register - TCCR2 */
-#define    FOC2A        7
-#define    WGM20        6
-#define    COM2A1       5
-#define    COM2A0       4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-/* End Register Bits */
-
-/* Register Bits [TCCR1A]  */
-/* Timer/Counter 1 Control and Status Register A - TCCR1A */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    COM1C1       3
-#define    COM1C0       2
-#define    WGM11        1
-#define    WGM10        0
-/* End Register Bits */
-
-/* Register Bits [TCCR3A]  */
-/* Timer/Counter 3 Control and Status Register A - TCCR3A */
-#define    COM3A1       7
-#define    COM3A0       6
-#define    COM3B1       5
-#define    COM3B0       4
-#define    COM3C1       3
-#define    COM3C0       2
-#define    WGM31        1
-#define    WGM30        0
-/* End Register Bits */
-
-/* Register Bits [TCCR1B]  */
-/* Timer/Counter 1 Control and Status Register B - TCCR1B */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-/* End Register Bits */
-
-/* Register Bits [TCCR3B]  */
-/* Timer/Counter 3 Control and Status Register B - TCCR3B */
-#define    ICNC3        7
-#define    ICES3        6
-#define    WGM33        4
-#define    WGM32        3
-#define    CS32         2
-#define    CS31         1
-#define    CS30         0
-/* End Register Bits */
-
-/* Register Bits [TCCR3C]  */
-/* Timer/Counter 3 Control Register C - TCCR3C */
-#define    FOC3A        7
-#define    FOC3B        6
-#define    FOC3C        5
-/* End Register Bits */
-
-/* Register Bits [TCCR1C]  */
-/* Timer/Counter 1 Control Register C - TCCR1C */
-#define    FOC1A        7
-#define    FOC1B        6
-#define    FOC1C        5
-/* End Register Bits */
-
-/* Register Bits [OCDR]  */
-/* On-chip Debug Register - OCDR */
-#define    IDRD         7
-#define    OCDR7        7
-#define    OCDR6        6
-#define    OCDR5        5
-#define    OCDR4        4
-#define    OCDR3        3
-#define    OCDR2        2
-#define    OCDR1        1
-#define    OCDR0        0
-/* End Register Bits */
-
-/* Register Bits [WDTCR]  */
-/* Watchdog Timer Control Register - WDTCR */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-/* End Register Bits */
-
-/* Register Bits [SPSR]  */
-/* SPI Status Register - SPSR */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-/* End Register Bits */
-
-/* Register Bits [SPCR]  */
-/* SPI Control Register - SPCR */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-/* End Register Bits */
-
-/* Register Bits [UCSR1C]  */
-/* USART1 Register C - UCSR1C */
-#define    UMSEL1       6
-#define    UPM11        5
-#define    UPM10        4
-#define    USBS1        3
-#define    UCSZ11       2
-#define    UCSZ10       1
-#define    UCPOL1       0
-/* End Register Bits */
-
-/* Register Bits [UCSR0C]  */
-/* USART0 Register C - UCSR0C */
-#define    UMSEL0       6
-#define    UPM01        5
-#define    UPM00        4
-#define    USBS0        3
-#define    UCSZ01       2
-#define    UCSZ00       1
-#define    UCPOL0       0
-/* End Register Bits */
-
-/* Register Bits [UCSR1A]  */
-/* USART1 Status Register A - UCSR1A */
-#define    RXC1         7
-#define    TXC1         6
-#define    UDRE1        5
-#define    FE1          4
-#define    DOR1         3
-#define    UPE1         2
-#define    U2X1         1
-#define    MPCM1        0
-/* End Register Bits */
-
-/* Register Bits [UCSR0A]  */
-/* USART0 Status Register A - UCSR0A */
-#define    RXC0         7
-#define    TXC0         6
-#define    UDRE0        5
-#define    FE0          4
-#define    DOR0         3
-#define    UPE0         2
-#define    U2X0         1
-#define    MPCM0        0
-/* End Register Bits */
-
-/* Register Bits [UCSR1B]  */
-/* USART1 Control Register B - UCSR1B */
-#define    RXCIE1       7
-#define    TXCIE1       6
-#define    UDRIE1       5
-#define    RXEN1        4
-#define    TXEN1        3
-#define    UCSZ12       2
-#define    RXB81        1
-#define    TXB81        0
-/* End Register Bits */
-
-/* Register Bits [UCSR0B]  */
-/* USART0 Control Register B - UCSR0B */
-#define    RXCIE0       7
-#define    TXCIE0       6
-#define    UDRIE0       5
-#define    RXEN0        4
-#define    TXEN0        3
-#define    UCSZ02       2
-#define    RXB80        1
-#define    TXB80        0
-/* End Register Bits */
-
-/* Register Bits [ACSR]  */
-/* Analog Comparator Control and Status Register - ACSR */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-/* End Register Bits */
-
-/* Register Bits [ADCSRA]  */
-/* ADC Control and status register - ADCSRA */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADATE        5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-/* End Register Bits */
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-/* Register Bits [ADCSRB]  */
-/* ADC Control and status register - ADCSRB */
-#define    ACME         6
-#define    ADTS2        2
-#define    ADTS1        1
-#define    ADTS0        0
-/* End Register Bits */
-
-/* Register Bits [ADMUX]  */
-/* ADC Multiplexer select - ADMUX */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-/* End Register Bits */
-
-/* Register Bits [DIDR0]  */
-/* Digital Input Disable Register 0 */
-#define    ADC7D        7
-#define    ADC6D        6
-#define    ADC5D        5
-#define    ADC4D        4
-#define    ADC3D        3
-#define    ADC2D        2
-#define    ADC1D        1
-#define    ADC0D        0
-/* End Register Bits */
-
-/* Register Bits [DIDR1]  */
-/* Digital Input Disable Register 1 */
-#define    AIN1D        1
-#define    AIN0D        0
-/* End Register Bits */
-
-/* Register Bits [PORTA]  */
-/* Port A Data Register - PORTA */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-/* End Register Bits */
-
-/* Register Bits [DDRA]  */
-/* Port A Data Direction Register - DDRA */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-/* End Register Bits */
-
-/* Register Bits [PINA]  */
-/* Port A Input Pins - PINA */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-/* End Register Bits */
-
-/* Register Bits [PORTB]  */
-/* Port B Data Register - PORTB */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-/* End Register Bits */
-
-/* Register Bits [DDRB]  */
-/* Port B Data Direction Register - DDRB */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-/* End Register Bits */
-
-/* Register Bits [PINB]  */
-/* Port B Input Pins - PINB */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-/* End Register Bits */
-
-/* Register Bits [PORTC]  */
-/* Port C Data Register - PORTC */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-/* End Register Bits */
-
-/* Register Bits [DDRC]  */
-/* Port C Data Direction Register - DDRC */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-/* End Register Bits */
-
-/* Register Bits [PINC]  */
-/* Port C Input Pins - PINC */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-/* End Register Bits */
-
-/* Register Bits [PORTD]  */
-/* Port D Data Register - PORTD */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-/* End Register Bits */
-
-/* Register Bits [DDRD]  */
-/* Port D Data Direction Register - DDRD */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-/* End Register Bits */
-
-/* Register Bits [PIND]  */
-/* Port D Input Pins - PIND */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-/* End Register Bits */
-
-/* Register Bits [PORTE]  */
-/* Port E Data Register - PORTE */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-/* End Register Bits */
-
-/* Register Bits [DDRE]  */
-/* Port E Data Direction Register - DDRE */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-/* End Register Bits */
-
-/* Register Bits [PINE]  */
-/* Port E Input Pins - PINE */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-/* End Register Bits */
-
-/* Register Bits [PORTF]  */
-/* Port F Data Register - PORTF */
-#define    PF7          7
-#define    PF6          6
-#define    PF5          5
-#define    PF4          4
-#define    PF3          3
-#define    PF2          2
-#define    PF1          1
-#define    PF0          0
-/* End Register Bits */
-
-/* Register Bits [DDRF]  */
-/* Port F Data Direction Register - DDRF */
-#define    DDF7         7
-#define    DDF6         6
-#define    DDF5         5
-#define    DDF4         4
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-#define    DDF0         0
-/* End Register Bits */
-
-/* Register Bits [PINF]  */
-/* Port F Input Pins - PINF */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-/* End Register Bits */
-
-/* Register Bits [PORTG]  */
-/* Port G Data Register - PORTG */
-#define    PG4          4
-#define    PG3          3
-#define    PG2          2
-#define    PG1          1
-#define    PG0          0
-/* End Register Bits */
-
-/* Register Bits [DDRG]  */
-/* Port G Data Direction Register - DDRG */
-#define    DDG4         4
-#define    DDG3         3
-#define    DDG2         2
-#define    DDG1         1
-#define    DDG0         0
-/* End Register Bits */
-
-/* Register Bits [PING]  */
-/* Port G Input Pins - PING */
-#define    PING4        4
-#define    PING3        3
-#define    PING2        2
-#define    PING1        1
-#define    PING0        0
-/* End Register Bits */
-
-
-/* Register Bits [TIFR0]  */
-/* Timer/Counter 0 interrupt Flag Register */
-#define    OCF0A        1
-#define    TOV0         0
-/* End Register Bits */
-
-/* Register Bits [TIFR1]  */
-/* Timer/Counter 1 interrupt Flag Register */
-#define    ICF1       5
-#define    OCF1C      3
-#define    OCF1B      2
-#define    OCF1A      1
-#define    TOV1       0
-/* End Register Bits */
-
-/* Register Bits [TIFR2]  */
-/* Timer/Counter 2 interrupt Flag Register */
-#define    OCF2A      1
-#define    TOV2       0
-/* End Register Bits */
-
-/* Register Bits [TIFR3]  */
-/* Timer/Counter 3 interrupt Flag Register */
-#define    ICF3       5
-#define    OCF3C      3
-#define    OCF3B      2
-#define    OCF3A      1
-#define    TOV3       0
-/* End Register Bits */
-
-/* Register Bits [GPIOR0]  */
-/* General Purpose I/O Register 0 */
-#define    GPIOR07     7
-#define    GPIOR06     6
-#define    GPIOR05     5
-#define    GPIOR04     4
-#define    GPIOR03     3
-#define    GPIOR02     2
-#define    GPIOR01     1
-#define    GPIOR00     0
-/* End Register Bits */
-
-/* Register Bits [GPIOR1]  */
-/* General Purpose I/O Register 1 */
-#define    GPIOR17     7
-#define    GPIOR16     6
-#define    GPIOR15     5
-#define    GPIOR14     4
-#define    GPIOR13     3
-#define    GPIOR12     2
-#define    GPIOR11     1
-#define    GPIOR10     0
-/* End Register Bits */
-
-/* Register Bits [GPIOR2]  */
-/* General Purpose I/O Register 2 */
-#define    GPIOR27     7
-#define    GPIOR26     6
-#define    GPIOR25     5
-#define    GPIOR24     4
-#define    GPIOR23     3
-#define    GPIOR22     2
-#define    GPIOR21     1
-#define    GPIOR20     0
-/* End Register Bits */
-
-/* Register Bits [EECR]  */
-/* EEPROM Control Register */
-#define    EERIE       3
-#define    EEMWE       2
-#define    EEWE        1
-#define    EERE        0
-/* End Register Bits */
-
-/* Register Bits [EEDR]  */
-/* EEPROM Data Register */
-#define    EEDR7     7
-#define    EEDR6     6
-#define    EEDR5     5
-#define    EEDR4     4
-#define    EEDR3     3
-#define    EEDR2     2
-#define    EEDR1     1
-#define    EEDR0     0
-/* End Register Bits */
-
-/* Register Bits [EEARL]  */
-/* EEPROM Address Register */
-#define    EEAR7     7
-#define    EEAR6     6
-#define    EEAR5     5
-#define    EEAR4     4
-#define    EEAR3     3
-#define    EEAR2     2
-#define    EEAR1     1
-#define    EEAR0     0
-/* End Register Bits */
-
-/* Register Bits [EEARH]  */
-/* EEPROM Address Register */
-#define    EEAR11    3
-#define    EEAR10    2
-#define    EEAR9     1
-#define    EEAR8     0
-/* End Register Bits */
-
-/* Register Bits [GTCCR]  */
-/* General Timer/Counter Control Register  */
-#define    TSM      7
-#define    PSR2     1
-#define    PSR310   0
-/* End Register Bits */
-
-/* Register Bits [TCCR0A]  */
-/* Timer/Counter Control Register A */
-/* ALSO COVERED IN GENERIC SECTION */
-#define    FOC0A    7
-#define    WGM00    6
-#define    COM0A1   5
-#define    COM0A0   4
-#define    WGM01    3
-#define    CS02     2
-#define    CS01     1
-#define    CS00     0
-/* End Register Bits */
-
-/* Register Bits [OCR0A]  */
-/* Output Compare Register A */
-#define    OCR0A7     7
-#define    OCR0A6     6
-#define    OCR0A5     5
-#define    OCR0A4     4
-#define    OCR0A3     3
-#define    OCR0A2     2
-#define    OCR0A1     1
-#define    OCR0A0     0
-/* End Register Bits */
-
-
-/* Register Bits [SPIDR]  */
-/* SPI Data Register */
-#define    SPD7     7
-#define    SPD6     6
-#define    SPD5     5
-#define    SPD4     4
-#define    SPD3     3
-#define    SPD2     2
-#define    SPD1     1
-#define    SPD0     0
-/* End Register Bits */
-
-/* Register Bits [SMCR]  */
-/* Sleep Mode Control Register */
-#define    SM2     3
-#define    SM1     2
-#define    SM0     1
-#define    SE      0
-/* End Register Bits */
-
-/* Register Bits [MCUSR]  */
-/* MCU Status Register */
-#define    JTRF    4
-#define    WDRF    3
-#define    BORF    2
-#define    EXTRF   1
-#define    PORF    0
-/* End Register Bits */
-
-/* Register Bits [MCUCR]  */
-/* MCU Control Register */
-#define    JTD     7
-#define    PUD     4
-#define    IVSEL   1
-#define    IVCE    0
-/* End Register Bits */
-
-/* Register Bits [CLKPR]  */
-/* Clock Prescale Register */
-#define    CLKPCE     7
-#define    CLKPS3     3
-#define    CLKPS2     2
-#define    CLKPS1     1
-#define    CLKPS0     0
-/* End Register Bits */
-
-/* Register Bits [OSCCAL]  */
-/* Oscillator Calibration Register */
-#define    CAL6     6
-#define    CAL5     5
-#define    CAL4     4
-#define    CAL3     3
-#define    CAL2     2
-#define    CAL1     1
-#define    CAL0     0
-/* End Register Bits */
-
-/* Register Bits [TIMSK0]  */
-/* Timer/Counter 0 interrupt mask Register */
-#define    OCIE0A      1
-#define    TOIE0       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK1]  */
-/* Timer/Counter 1 interrupt mask Register */
-#define    ICIE1       5
-#define    OCIE1C      3
-#define    OCIE1B      2
-#define    OCIE1A      1
-#define    TOIE1       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK2]  */
-/* Timer/Counter 2 interrupt mask Register */
-#define    OCIE2A      1
-#define    TOIE2       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK3]  */
-/* Timer/Counter 3 interrupt mask Register */
-#define    ICIE3       5
-#define    OCIE3C      3
-#define    OCIE3B      2
-#define    OCIE3A      1
-#define    TOIE3       0
-/* End Register Bits */
-
-//Begin CAN specific parts
-
-/* Register Bits [CANGCON]  */
-/* CAN General Control Register */
-#define    ABRQ       7
-#define    OVRQ       6
-#define    TTC        5
-#define    SYNTTC     4
-#define    LISTEN     3
-#define    TEST       2
-#define    ENASTB     1
-#define    SWRES      0
-/* End Register Bits */
-
-/* Register Bits [CANGSTA]  */
-/* CAN General Status Register */
-#define    OVFG       6
-#define    OVRG       6
-#define    TXBSY      4
-#define    RXBSY      3
-#define    ENFG       2
-#define    BOFF       1
-#define    ERRP       0
-/* End Register Bits */
-
-/* Register Bits [CANGIT]  */
-/* CAN General Interrupt Register */
-#define    CANIT      7
-#define    BOFFIT     6
-#define    OVRTIM     5
-#define    BXOK       4
-#define    SERG       3
-#define    CERG       2
-#define    FERG       1
-#define    AERG       0
-/* End Register Bits */
-
-/* Register Bits [CANGIE]  */
-/* CAN General Interrupt Enable */
-#define    ENIT        7
-#define    ENBOFF      6
-#define    ENRX        5
-#define    ENTX        4
-#define    ENERR       3
-#define    ENBX        2
-#define    ENERG       1
-#define    ENOVRT      0
-/* End Register Bits */
-
-/* Register Bits [CANEN2]  */
-/* CAN Enable MOb Register */
-#define    ENMOB7      7
-#define    ENMOB6      6
-#define    ENMOB5      5
-#define    ENMOB4      4
-#define    ENMOB3      3
-#define    ENMOB2      2
-#define    ENMOB1      1
-#define    ENMOB0      0
-/* End Register Bits */
-
-/* Register Bits [CANEN1]  */
-/* CAN Enable MOb Register */
-#define    ENMOB14      6
-#define    ENMOB13      5
-#define    ENMOB12      4
-#define    ENMOB11      3
-#define    ENMOB10      2
-#define    ENMOB9       1
-#define    ENMOB8       0
-/* End Register Bits */
-
-/* Register Bits [CANIE2]  */
-/* CAN Interrupt Enable MOb Register */
-#define    IEMOB7      7
-#define    IEMOB6      6
-#define    IEMOB5      5
-#define    IEMOB4      4
-#define    IEMOB3      3
-#define    IEMOB2      2
-#define    IEMOB1      1
-#define    IEMOB0      0
-/* End Register Bits */
-
-/* Register Bits [CANIE1]  */
-/* CAN Interrupt Enable MOb Register */
-#define    IEMOB14      6
-#define    IEMOB13      5
-#define    IEMOB12      4
-#define    IEMOB11      3
-#define    IEMOB10      2
-#define    IEMOB9       1
-#define    IEMOB8       0
-/* End Register Bits */
-
-/* Register Bits [CANSIT2]  */
-/* CAN Status Interrupt MOb Register */
-#define    SIT7      7
-#define    SIT6      6
-#define    SIT5      5
-#define    SIT4      4
-#define    SIT3      3
-#define    SIT2      2
-#define    SIT1      1
-#define    SIT0      0
-/* End Register Bits */
-
-/* Register Bits [CANSIT1]  */
-/* CAN Status Interrupt MOb Register */
-#define    SIT14      6
-#define    SIT13      5
-#define    SIT12      4
-#define    SIT11      3
-#define    SIT10      2
-#define    SIT9       1
-#define    SIT8       0
-/* End Register Bits */
-
-/* Register Bits [CANBT1]  */
-/* Bit Timing Register 1 */
-#define    BRP5       6
-#define    BRP4       5
-#define    BRP3       4
-#define    BRP2       3
-#define    BRP1       2
-#define    BRP0       1
-/* End Register Bits */
-
-/* Register Bits [CANBT2]  */
-/* Bit Timing Register 2 */
-#define    SJW1       6
-#define    SJW0       5
-#define    PRS2       3
-#define    PRS1       2
-#define    PRS0       1
-/* End Register Bits */
-
-/* Register Bits [CANBT3]  */
-/* Bit Timing Register 3 */
-#define    PHS22      6
-#define    PHS21      5
-#define    PHS20      4
-#define    PHS12      3
-#define    PHS11      2
-#define    PHS10      1
-#define    SMP        0
-/* End Register Bits */
-
-/* Register Bits [CANTCON]  */
-/* CAN Timer Control Register */
-#define    TPRSC7      7
-#define    TPRSC6      6
-#define    TPRSC5      5
-#define    TPRSC4      4
-#define    TPRSC3      3
-#define    TPRSC2      2
-#define    TPRSC1      1
-#define    TPRSC0      0
-/* End Register Bits */
-
-/* Register Bits [CANTIML]  */
-/* CAN Timer Register Low */
-#define    CANTIM7      7
-#define    CANTIM6      6
-#define    CANTIM5      5
-#define    CANTIM4      4
-#define    CANTIM3      3
-#define    CANTIM2      2
-#define    CANTIM1      1
-#define    CANTIM0      0
-/* End Register Bits */
-
-/* Register Bits [CANTIMH]  */
-/* CAN Timer Register High */
-#define    CANTIM15     7
-#define    CANTIM14     6
-#define    CANTIM13     5
-#define    CANTIM12     4
-#define    CANTIM11     3
-#define    CANTIM10     2
-#define    CANTIM9      1
-#define    CANTIM8      0
-/* End Register Bits */
-
-/* Register Bits [CANTTCL]  */
-/* CAN TTC Timer Register Low */
-#define    TIMTTC7      7
-#define    TIMTTC6      6
-#define    TIMTTC5      5
-#define    TIMTTC4      4
-#define    TIMTTC3      3
-#define    TIMTTC2      2
-#define    TIMTTC1      1
-#define    TIMTTC0      0
-/* End Register Bits */
-
-/* Register Bits [CANTTCH]  */
-/* CAN TTC Timer Register High */
-#define    TIMTTC15     7
-#define    TIMTTC14     6
-#define    TIMTTC13     5
-#define    TIMTTC12     4
-#define    TIMTTC11     3
-#define    TIMTTC10     2
-#define    TIMTTC9      1
-#define    TIMTTC8      0
-/* End Register Bits */
-
-/* Register Bits [CANTEC]  */
-/* CAN Transmitt Error Counter */
-#define    TEC7      7
-#define    TEC6      6
-#define    TEC5      5
-#define    TEC4      4
-#define    TEC3      3
-#define    TEC2      2
-#define    TEC1      1
-#define    TEC0      0
-/* End Register Bits */
-
-/* Register Bits [CANREC]  */
-/* CAN Receive Error Counter */
-#define    REC7      7
-#define    REC6      6
-#define    REC5      5
-#define    REC4      4
-#define    REC3      3
-#define    REC2      2
-#define    REC1      1
-#define    REC0      0
-/* End Register Bits */
-
-/* Register Bits [CANHPMOB]  */
-/* Highest Priority MOb */
-#define    HPMOB3     7
-#define    HPMOB2     6
-#define    HPMOB1     5
-#define    HPMOB0     4
-#define    CGP3       3
-#define    CGP2       2
-#define    CGP1       1
-#define    CGP0       0
-/* End Register Bits */
-
-/* Register Bits [CANPAGE]  */
-/* CAN Page MOb Register */
-#define    MOBNB3     7
-#define    MOBNB2     6
-#define    MOBNB1     5
-#define    MOBNB0     4
-#define    AINC       3
-#define    INDX2      2
-#define    INDX1      1
-#define    INDX0      0
-/* End Register Bits */
-
-/* Register Bits [CANSTMOB]  */
-/* CAN MOb Status Register */
-#define    DLCW       7
-#define    TXOK       6
-#define    RXOK       5
-#define    BERR       4
-#define    SERR       3
-#define    CERR       2
-#define    FERR       1
-#define    AERR       0
-/* End Register Bits */
-
-/* Register Bits [CANCDMOB]  */
-/* CAN MOb Control and DLC Register */
-#define    CONMOB1    7
-#define    CONMOB0    6
-#define    RPLV       5
-#define    IDE        4
-#define    DLC3       3
-#define    DLC2       2
-#define    DLC1       1
-#define    DLC0       0
-/* End Register Bits */
-
-/* Register Bits [CANIDT4]  */
-/* CAN Identifier Tag Register 4 */
-#define    IDT4       7
-#define    IDT3       6
-#define    IDT2       5
-#define    IDT1       4
-#define    IDT0       3
-#define    RTRTAG     2
-#define    RB1TAG     1
-#define    RB0TAG     0
-/* End Register Bits */
-
-/* Register Bits [CANIDT3]  */
-/* CAN Identifier Tag Register 3 */
-#define    IDT12      7
-#define    IDT11      6
-#define    IDT10      5
-#define    IDT9       4
-#define    IDT8       3
-#define    IDT7       2
-#define    IDT6       1
-#define    IDT5       0
-/* End Register Bits */
-
-/* Register Bits [CANIDT2]  */
-/* CAN Identifier Tag Register 2 */
-#define    IDT20      7
-#define    IDT19      6
-#define    IDT18      5
-#define    IDT17      4
-#define    IDT16      3
-#define    IDT15      2
-#define    IDT14      1
-#define    IDT13      0
-/* End Register Bits */
-
-/* Register Bits [CANIDT1]  */
-/* CAN Identifier Tag Register 1 */
-#define    IDT28      7
-#define    IDT27      6
-#define    IDT26      5
-#define    IDT25      4
-#define    IDT24      3
-#define    IDT23      2
-#define    IDT22      1
-#define    IDT21      0
-/* End Register Bits */
-
-/* Register Bits [CANIDM4]  */
-/* CAN Identifier Mask Register 4 */
-#define    IDMSK4       7
-#define    IDMSK3       6
-#define    IDMSK2       5
-#define    IDMSK1       4
-#define    IDMSK0       3
-#define    RTRMSK       2
-#define    IDEMSK       0
-/* End Register Bits */
-
-/* Register Bits [CANIDM3]  */
-/* CAN Identifier Mask Register 3 */
-#define    IDMSK12      7
-#define    IDMSK11      6
-#define    IDMSK10      5
-#define    IDMSK9       4
-#define    IDMSK8       3
-#define    IDMSK7       2
-#define    IDMSK6       1
-#define    IDMSK5       0
-/* End Register Bits */
-
-/* Register Bits [CANIDM2]  */
-/* CAN Identifier Mask Register 2 */
-#define    IDMSK20      7
-#define    IDMSK19      6
-#define    IDMSK18      5
-#define    IDMSK17      4
-#define    IDMSK16      3
-#define    IDMSK15      2
-#define    IDMSK14      1
-#define    IDMSK13      0
-/* End Register Bits */
-
-/* Register Bits [CANIDM1]  */
-/* CAN Identifier Mask Register 1 */
-#define    IDMSK28      7
-#define    IDMSK27      6
-#define    IDMSK26      5
-#define    IDMSK25      4
-#define    IDMSK24      3
-#define    IDMSK23      2
-#define    IDMSK22      1
-#define    IDMSK21      0
-/* End Register Bits */
-
-/* Register Bits [CANSTML]  */
-/* CAN Timer Register of some sort, low*/
-#define    TIMSTM7       7
-#define    TIMSTM6       6
-#define    TIMSTM5       5
-#define    TIMSTM4       4
-#define    TIMSTM3       3
-#define    TIMSTM2       2
-#define    TIMSTM1       1
-#define    TIMSTM0       0
-/* End Register Bits */
-
-/* Register Bits [CANSTMH]  */
-/* CAN Timer Register of some sort, high */
-#define    TIMSTM15       7
-#define    TIMSTM14       6
-#define    TIMSTM13       5
-#define    TIMSTM12       4
-#define    TIMSTM11       3
-#define    TIMSTM10       2
-#define    TIMSTM9        1
-#define    TIMSTM8        0
-/* End Register Bits */
-
-/* Register Bits [CANMSG]  */
-/* CAN Message Register */
-#define    MSG7           7
-#define    MSG6           6
-#define    MSG5           5
-#define    MSG4           4
-#define    MSG3           3
-#define    MSG2           2
-#define    MSG1           1
-#define    MSG0           0
-/* End Register Bits */
-
-/* Begin Verbatim */
-
-/* Timer/Counter Control Register (generic) */
-#define    FOC          7
-#define    WGM0         6
-#define    COM1         5
-#define    COM0         4
-#define    WGM1         3
-#define    CS2          2
-#define    CS1          1
-#define    CS0          0
-
-/* Timer/Counter Control Register A (generic) */
-#define    COMA1        7
-#define    COMA0        6
-#define    COMB1        5
-#define    COMB0        4
-#define    COMC1        3
-#define    COMC0        2
-#define    WGMA1        1
-#define    WGMA0        0
-
-/* Timer/Counter Control and Status Register B (generic) */
-#define    ICNC         7
-#define    ICES         6
-#define    WGMB3        4
-#define    WGMB2        3
-#define    CSB2         2
-#define    CSB1         1
-#define    CSB0         0
-
-/* Timer/Counter Control Register C (generic) */
-#define    FOCA         7
-#define    FOCB         6
-#define    FOCC         5
-
-/* Port Data Register (generic) */
-#define    PORT7        7
-#define    PORT6        6
-#define    PORT5        5
-#define    PORT4        4
-#define    PORT3        3
-#define    PORT2        2
-#define    PORT1        1
-#define    PORT0        0
-
-/* Port Data Direction Register (generic) */
-#define    DD7          7
-#define    DD6          6
-#define    DD5          5
-#define    DD4          4
-#define    DD3          3
-#define    DD2          2
-#define    DD1          1
-#define    DD0          0
-
-/* Port Input Pins (generic) */
-#define    PIN7         7
-#define    PIN6         6
-#define    PIN5         5
-#define    PIN4         4
-#define    PIN3         3
-#define    PIN2         2
-#define    PIN1         1
-#define    PIN0         0
-
-/* USART Status Register A (generic) */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    UPE          2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART Control Register B (generic) */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ         2
-#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
-#define    RXB8         1
-#define    TXB8         0
-
-/* USART Register C (generic) */
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* End Verbatim */
-
-/**@}*/
-#endif  /* _AVR_IOCANXX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom103.h b/cpukit/score/cpu/avr/avr/iom103.h
deleted file mode 100644
index 6ca791b100..0000000000
--- a/cpukit/score/cpu/avr/avr/iom103.h
+++ /dev/null
@@ -1,687 +0,0 @@
-/**
- * @file avr/iom103.h
- *
- * @brief Definitions for ATmega103
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM103_H_
-#define _AVR_IOM103_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom103.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_iom103 ATmega103 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Input Pins, Port F */
-#define PINF	_SFR_IO8(0x00)
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and status register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC Multiplexer select */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define ASSR	_SFR_IO8(0x30)
-
-/* Output Compare Register 0 */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x36)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x37)
-
-/* Èxternal Interrupt Flag Register */
-#define EIFR	_SFR_IO8(0x38)
-
-/* External Interrupt MaSK register */
-#define EIMSK	_SFR_IO8(0x39)
-
-/* External Interrupt Control Register */
-#define EICR	_SFR_IO8(0x3A)
-
-/* RAM Page Z select register */
-#define RAMPZ	_SFR_IO8(0x3B)
-
-/* XDIV Divide control register */
-#define XDIV	_SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(14)
-#define SIG_OVERFLOW1			_VECTOR(14)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(15)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(18)
-#define SIG_UART_RECV			_VECTOR(18)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(19)
-#define SIG_UART_DATA			_VECTOR(19)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(20)
-#define SIG_UART_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-#define _VECTORS_SIZE 96
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* XDIV Divide control register*/
-#define    XDIVEN       7
-#define    XDIV6        6
-#define    XDIV5        5
-#define    XDIV4        4
-#define    XDIV3        3
-#define    XDIV2        2
-#define    XDIV1        1
-#define    XDIV0        0
-
-/* RAM Page Z select register */
-#define     RAMPZ0      0
-
-/* External Interrupt Control Register */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-
-/* External Interrupt MaSK register */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-
-/* Èxternal Interrupt Flag Register */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag Register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM1          4
-#define    SM0          3
-
-/* MCU Status Register */
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter 0 Control Register */
-#define    PWM0         6
-#define    COM01        5
-#define    COM00        4
-#define    CTC0         3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define    AS0          3
-#define    TCN0UB       2
-#define    OCR0UB       1
-#define    TCR0UB       0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port E */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-
-/* Data Direction Register, Port E */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Input Pins, Port E */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* Input Pins, Port F */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Control and status register */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADFR         5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* ADC Multiplexer select */
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define RAMEND     0x0FFF     /*Last On-Chip SRAM Location*/
-#define XRAMEND    0xFFFF
-#define E2END      0x0FFF
-#define E2PAGESIZE 0
-#define FLASHEND   0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0 (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1 (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_BODEN (unsigned char)~_BV(6)  /* Brown out detector enable */
-#define FUSE_BODLEVEL (unsigned char)~_BV(7)  /* Brown out detector trigger level */
-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x01
-
-/** @} */
-#endif /* _AVR_IOM103_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom128.h b/cpukit/score/cpu/avr/avr/iom128.h
deleted file mode 100644
index 7eeb3f57e6..0000000000
--- a/cpukit/score/cpu/avr/avr/iom128.h
+++ /dev/null
@@ -1,1215 +0,0 @@
-/**
- * @file avr/iom128.h
- *
- * @brief Definitions for ATmega128
- *
- * This file should only be included from <avr/io.h>, never directly.
- *
- *  As of 2002-08-27:
- *  - This should be up to date with data sheet 2467E-AVR-05/02
- */
-
-/*
- *  Copyright (c) 2002, Peter Jansen
- *  Copyright (c) 2007, Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM128_H_
-#define _AVR_IOM128_H_ 1
-
-/**
- *  @defgroup Avr_iom128 ATmega128 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom128.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Input Pins, Port F */
-#define PINF      _SFR_IO8(0x00)
-
-/* Input Pins, Port E */
-#define PINE      _SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE      _SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE     _SFR_IO8(0x03)
-
-/* ADC Data Register */
-#define ADCW      _SFR_IO16(0x04) /* for backwards compatibility */
-#ifndef __ASSEMBLER__
-#define ADC       _SFR_IO16(0x04)
-#endif
-#define ADCL      _SFR_IO8(0x04)
-#define ADCH      _SFR_IO8(0x05)
-
-/* ADC Control and status register */
-#define ADCSR     _SFR_IO8(0x06)
-#define ADCSRA    _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* ADC Multiplexer select */
-#define ADMUX     _SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR      _SFR_IO8(0x08)
-
-/* USART0 Baud Rate Register Low */
-#define UBRR0L    _SFR_IO8(0x09)
-
-/* USART0 Control and Status Register B */
-#define UCSR0B    _SFR_IO8(0x0A)
-
-/* USART0 Control and Status Register A */
-#define UCSR0A    _SFR_IO8(0x0B)
-
-/* USART0 I/O Data Register */
-#define UDR0      _SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR      _SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR      _SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR      _SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND      _SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD      _SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD     _SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC      _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC      _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC     _SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB      _SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB      _SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB     _SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA      _SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA      _SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA     _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR      _SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR      _SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR      _SFR_IO16(0x1E)
-#define EEARL     _SFR_IO8(0x1E)
-#define EEARH     _SFR_IO8(0x1F)
-
-/* Special Function I/O Register */
-#define SFIOR     _SFR_IO8(0x20)
-
-/* Watchdog Timer Control Register */
-#define WDTCR     _SFR_IO8(0x21)
-
-/* On-chip Debug Register */
-#define OCDR      _SFR_IO8(0x22)
-
-/* Timer2 Output Compare Register */
-#define OCR2      _SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2     _SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control register */
-#define TCCR2     _SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1      _SFR_IO16(0x26)
-#define ICR1L     _SFR_IO8(0x26)
-#define ICR1H     _SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B     _SFR_IO16(0x28)
-#define OCR1BL    _SFR_IO8(0x28)
-#define OCR1BH    _SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A     _SFR_IO16(0x2A)
-#define OCR1AL    _SFR_IO8(0x2A)
-#define OCR1AH    _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1     _SFR_IO16(0x2C)
-#define TCNT1L    _SFR_IO8(0x2C)
-#define TCNT1H    _SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B    _SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A    _SFR_IO8(0x2F)
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define ASSR      _SFR_IO8(0x30)
-
-/* Output Compare Register 0 */
-#define OCR0      _SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0     _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0     _SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR     _SFR_IO8(0x34)
-#define MCUCSR    _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* MCU general Control Register */
-#define MCUCR     _SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR      _SFR_IO8(0x36)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK     _SFR_IO8(0x37)
-
-/* External Interrupt Flag Register */
-#define EIFR      _SFR_IO8(0x38)
-
-/* External Interrupt MaSK register */
-#define EIMSK     _SFR_IO8(0x39)
-
-/* External Interrupt Control Register B */
-#define EICRB     _SFR_IO8(0x3A)
-
-/* RAM Page Z select register */
-#define RAMPZ     _SFR_IO8(0x3B)
-
-/* XDIV Divide control register */
-#define XDIV      _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Extended I/O registers */
-
-/* Data Direction Register, Port F */
-#define DDRF      _SFR_MEM8(0x61)
-
-/* Data Register, Port F */
-#define PORTF     _SFR_MEM8(0x62)
-
-/* Input Pins, Port G */
-#define PING      _SFR_MEM8(0x63)
-
-/* Data Direction Register, Port G */
-#define DDRG      _SFR_MEM8(0x64)
-
-/* Data Register, Port G */
-#define PORTG     _SFR_MEM8(0x65)
-
-/* Store Program Memory Control and Status Register */
-#define SPMCR     _SFR_MEM8(0x68)
-#define SPMCSR    _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* External Interrupt Control Register A */
-#define EICRA     _SFR_MEM8(0x6A)
-
-/* External Memory Control Register B */
-#define XMCRB     _SFR_MEM8(0x6C)
-
-/* External Memory Control Register A */
-#define XMCRA     _SFR_MEM8(0x6D)
-
-/* Oscillator Calibration Register */
-#define OSCCAL    _SFR_MEM8(0x6F)
-
-/* 2-wire Serial Interface Bit Rate Register */
-#define TWBR      _SFR_MEM8(0x70)
-
-/* 2-wire Serial Interface Status Register */
-#define TWSR      _SFR_MEM8(0x71)
-
-/* 2-wire Serial Interface Address Register */
-#define TWAR      _SFR_MEM8(0x72)
-
-/* 2-wire Serial Interface Data Register */
-#define TWDR      _SFR_MEM8(0x73)
-
-/* 2-wire Serial Interface Control Register */
-#define TWCR      _SFR_MEM8(0x74)
-
-/* Time Counter 1 Output Compare Register C */
-#define OCR1C     _SFR_MEM16(0x78)
-#define OCR1CL    _SFR_MEM8(0x78)
-#define OCR1CH    _SFR_MEM8(0x79)
-
-/* Timer/Counter 1 Control Register C */
-#define TCCR1C    _SFR_MEM8(0x7A)
-
-/* Extended Timer Interrupt Flag Register */
-#define ETIFR     _SFR_MEM8(0x7C)
-
-/* Extended Timer Interrupt Mask Register */
-#define ETIMSK    _SFR_MEM8(0x7D)
-
-/* Timer/Counter 3 Input Capture Register */
-#define ICR3      _SFR_MEM16(0x80)
-#define ICR3L     _SFR_MEM8(0x80)
-#define ICR3H     _SFR_MEM8(0x81)
-
-/* Timer/Counter 3 Output Compare Register C */
-#define OCR3C     _SFR_MEM16(0x82)
-#define OCR3CL    _SFR_MEM8(0x82)
-#define OCR3CH    _SFR_MEM8(0x83)
-
-/* Timer/Counter 3 Output Compare Register B */
-#define OCR3B     _SFR_MEM16(0x84)
-#define OCR3BL    _SFR_MEM8(0x84)
-#define OCR3BH    _SFR_MEM8(0x85)
-
-/* Timer/Counter 3 Output Compare Register A */
-#define OCR3A     _SFR_MEM16(0x86)
-#define OCR3AL    _SFR_MEM8(0x86)
-#define OCR3AH    _SFR_MEM8(0x87)
-
-/* Timer/Counter 3 Counter Register */
-#define TCNT3     _SFR_MEM16(0x88)
-#define TCNT3L    _SFR_MEM8(0x88)
-#define TCNT3H    _SFR_MEM8(0x89)
-
-/* Timer/Counter 3 Control Register B */
-#define TCCR3B    _SFR_MEM8(0x8A)
-
-/* Timer/Counter 3 Control Register A */
-#define TCCR3A    _SFR_MEM8(0x8B)
-
-/* Timer/Counter 3 Control Register C */
-#define TCCR3C    _SFR_MEM8(0x8C)
-
-/* USART0 Baud Rate Register High */
-#define UBRR0H    _SFR_MEM8(0x90)
-
-/* USART0 Control and Status Register C */
-#define UCSR0C    _SFR_MEM8(0x95)
-
-/* USART1 Baud Rate Register High */
-#define UBRR1H    _SFR_MEM8(0x98)
-
-/* USART1 Baud Rate Register Low*/
-#define UBRR1L    _SFR_MEM8(0x99)
-
-/* USART1 Control and Status Register B */
-#define UCSR1B    _SFR_MEM8(0x9A)
-
-/* USART1 Control and Status Register A */
-#define UCSR1A    _SFR_MEM8(0x9B)
-
-/* USART1 I/O Data Register */
-#define UDR1      _SFR_MEM8(0x9C)
-
-/* USART1 Control and Status Register C */
-#define UCSR1C    _SFR_MEM8(0x9D)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(14)
-#define SIG_OVERFLOW1			_VECTOR(14)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(15)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(18)
-#define SIG_USART0_RECV			_VECTOR(18)
-#define SIG_UART0_RECV			_VECTOR(18)
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect		_VECTOR(19)
-#define SIG_USART0_DATA			_VECTOR(19)
-#define SIG_UART0_DATA			_VECTOR(19)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(20)
-#define SIG_USART0_TRANS		_VECTOR(20)
-#define SIG_UART0_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(24)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(24)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(25)
-#define SIG_INPUT_CAPTURE3		_VECTOR(25)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(26)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(26)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(27)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(28)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(28)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(29)
-#define SIG_OVERFLOW3			_VECTOR(29)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(30)
-#define SIG_USART1_RECV			_VECTOR(30)
-#define SIG_UART1_RECV			_VECTOR(30)
-
-/* USART1, Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(31)
-#define SIG_USART1_DATA			_VECTOR(31)
-#define SIG_UART1_DATA			_VECTOR(31)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(32)
-#define SIG_USART1_TRANS		_VECTOR(32)
-#define SIG_UART1_TRANS			_VECTOR(32)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(33)
-#define SIG_2WIRE_SERIAL		_VECTOR(33)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(34)
-#define SIG_SPM_READY			_VECTOR(34)
-
-#define _VECTORS_SIZE 140
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* 2-wire Control Register - TWCR */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-
-/* 2-wire Address Register - TWAR */
-#define    TWA6         7
-#define    TWA5         6
-#define    TWA4         5
-#define    TWA3         4
-#define    TWA2         3
-#define    TWA1         2
-#define    TWA0         1
-#define    TWGCE        0
-
-/* 2-wire Status Register - TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-
-/* External Memory Control Register A - XMCRA */
-#define    SRL2         6
-#define    SRL1         5
-#define    SRL0         4
-#define    SRW01        3
-#define    SRW00        2
-#define    SRW11        1
-
-/* External Memory Control Register B - XMCRA */
-#define    XMBK         7
-#define    XMM2         2
-#define    XMM1         1
-#define    XMM0         0
-
-/* XDIV Divide control register - XDIV */
-#define    XDIVEN       7
-#define    XDIV6        6
-#define    XDIV5        5
-#define    XDIV4        4
-#define    XDIV3        3
-#define    XDIV2        2
-#define    XDIV1        1
-#define    XDIV0        0
-
-/* RAM Page Z select register - RAMPZ */
-#define     RAMPZ0      0
-
-/* External Interrupt Control Register A - EICRA */
-#define    ISC31        7
-#define    ISC30        6
-#define    ISC21        5
-#define    ISC20        4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* External Interrupt Control Register B - EICRB */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-
-/* Store Program Memory Control Register - SPMCSR, SPMCR */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-
-/* External Interrupt MaSK register - EIMSK */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-
-/* External Interrupt Flag Register - EIFR */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-#define    INTF3        3
-#define    INTF2        2
-#define    INTF1        1
-#define    INTF0        0
-
-/* Timer/Counter Interrupt MaSK register - TIMSK */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag Register - TIFR */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* Extended Timer Interrupt MaSK register - ETIMSK */
-#define    TICIE3       5
-#define    OCIE3A       4
-#define    OCIE3B       3
-#define    TOIE3        2
-#define    OCIE3C       1
-#define    OCIE1C       0
-
-/* Extended Timer Interrupt Flag Register - ETIFR */
-#define    ICF3         5
-#define    OCF3A        4
-#define    OCF3B        3
-#define    TOV3         2
-#define    OCF3C        1
-#define    OCF1C        0
-
-/* MCU general Control Register - MCUCR */
-#define    SRE          7
-#define    SRW          6
-#define    SRW10        6       /* new name in datasheet (2467E-AVR-05/02) */
-#define    SE           5
-#define    SM1          4
-#define    SM0          3
-#define    SM2          2
-#define    IVSEL        1
-#define    IVCE         0
-
-/* MCU Status Register - MCUSR, MCUCSR */
-#define    JTD          7
-#define    JTRF         4
-#define    WDRF         3
-#define    BORF         2
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter Control Register (generic) */
-#define    FOC          7
-#define    WGM0         6
-#define    COM1         5
-#define    COM0         4
-#define    WGM1         3
-#define    CS2          2
-#define    CS1          1
-#define    CS0          0
-
-/* Timer/Counter 0 Control Register - TCCR0 */
-#define    FOC0         7
-#define    WGM00        6
-#define    COM01        5
-#define    COM00        4
-#define    WGM01        3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 2 Control Register - TCCR2 */
-#define    FOC2         7
-#define    WGM20        6
-#define    COM21        5
-#define    COM20        4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */
-#define    AS0          3
-#define    TCN0UB       2
-#define    OCR0UB       1
-#define    TCR0UB       0
-
-/* Timer/Counter Control Register A (generic) */
-#define    COMA1        7
-#define    COMA0        6
-#define    COMB1        5
-#define    COMB0        4
-#define    COMC1        3
-#define    COMC0        2
-#define    WGMA1        1
-#define    WGMA0        0
-
-/* Timer/Counter 1 Control and Status Register A - TCCR1A */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    COM1C1       3
-#define    COM1C0       2
-#define    WGM11        1
-#define    WGM10        0
-
-/* Timer/Counter 3 Control and Status Register A - TCCR3A */
-#define    COM3A1       7
-#define    COM3A0       6
-#define    COM3B1       5
-#define    COM3B0       4
-#define    COM3C1       3
-#define    COM3C0       2
-#define    WGM31        1
-#define    WGM30        0
-
-/* Timer/Counter Control and Status Register B (generic) */
-#define    ICNC         7
-#define    ICES         6
-#define    WGMB3        4
-#define    WGMB2        3
-#define    CSB2         2
-#define    CSB1         1
-#define    CSB0         0
-
-/* Timer/Counter 1 Control and Status Register B - TCCR1B */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 3 Control and Status Register B - TCCR3B */
-#define    ICNC3        7
-#define    ICES3        6
-#define    WGM33        4
-#define    WGM32        3
-#define    CS32         2
-#define    CS31         1
-#define    CS30         0
-
-/* Timer/Counter Control Register C (generic) */
-#define    FOCA         7
-#define    FOCB         6
-#define    FOCC         5
-
-/* Timer/Counter 3 Control Register C - TCCR3C */
-#define    FOC3A        7
-#define    FOC3B        6
-#define    FOC3C        5
-
-/* Timer/Counter 1 Control Register C - TCCR1C */
-#define    FOC1A        7
-#define    FOC1B        6
-#define    FOC1C        5
-
-/* On-chip Debug Register - OCDR */
-#define    IDRD         7
-#define    OCDR7        7
-#define    OCDR6        6
-#define    OCDR5        5
-#define    OCDR4        4
-#define    OCDR3        3
-#define    OCDR2        2
-#define    OCDR1        1
-#define    OCDR0        0
-
-/* Watchdog Timer Control Register - WDTCR */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-/* Special Function I/O Register - SFIOR */
-#define    TSM          7
-#define    ACME         3
-#define    PUD          2
-#define    PSR0         1
-#define    PSR321       0
-
-/* SPI Status Register - SPSR */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-
-/* SPI Control Register - SPCR */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* USART Register C (generic) */
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* USART1 Register C - UCSR1C */
-#define    UMSEL1       6
-#define    UPM11        5
-#define    UPM10        4
-#define    USBS1        3
-#define    UCSZ11       2
-#define    UCSZ10       1
-#define    UCPOL1       0
-
-/* USART0 Register C - UCSR0C */
-#define    UMSEL0       6
-#define    UPM01        5
-#define    UPM00        4
-#define    USBS0        3
-#define    UCSZ01       2
-#define    UCSZ00       1
-#define    UCPOL0       0
-
-/* USART Status Register A (generic) */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    UPE          2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART1 Status Register A - UCSR1A */
-#define    RXC1         7
-#define    TXC1         6
-#define    UDRE1        5
-#define    FE1          4
-#define    DOR1         3
-#define    UPE1         2
-#define    U2X1         1
-#define    MPCM1        0
-
-/* USART0 Status Register A - UCSR0A */
-#define    RXC0         7
-#define    TXC0         6
-#define    UDRE0        5
-#define    FE0          4
-#define    DOR0         3
-#define    UPE0         2
-#define    U2X0         1
-#define    MPCM0        0
-
-/* USART Control Register B (generic) */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ         2
-#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
-#define    RXB8         1
-#define    TXB8         0
-
-/* USART1 Control Register B - UCSR1B */
-#define    RXCIE1       7
-#define    TXCIE1       6
-#define    UDRIE1       5
-#define    RXEN1        4
-#define    TXEN1        3
-#define    UCSZ12       2
-#define    RXB81        1
-#define    TXB81        0
-
-/* USART0 Control Register B - UCSR0B */
-#define    RXCIE0       7
-#define    TXCIE0       6
-#define    UDRIE0       5
-#define    RXEN0        4
-#define    TXEN0        3
-#define    UCSZ02       2
-#define    RXB80        1
-#define    TXB80        0
-
-/* Analog Comparator Control and Status Register - ACSR */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Control and status register - ADCSRA */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADFR         5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* ADC Multiplexer select - ADMUX */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* Port A Data Register - PORTA */
-#define    PA7       7
-#define    PA6       6
-#define    PA5       5
-#define    PA4       4
-#define    PA3       3
-#define    PA2       2
-#define    PA1       1
-#define    PA0       0
-
-/* Port A Data Direction Register - DDRA */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Port A Input Pins - PINA */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Port B Data Register - PORTB */
-#define    PB7       7
-#define    PB6       6
-#define    PB5       5
-#define    PB4       4
-#define    PB3       3
-#define    PB2       2
-#define    PB1       1
-#define    PB0       0
-
-/* Port B Data Direction Register - DDRB */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Port B Input Pins - PINB */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Port C Data Register - PORTC */
-#define    PC7       7
-#define    PC6       6
-#define    PC5       5
-#define    PC4       4
-#define    PC3       3
-#define    PC2       2
-#define    PC1       1
-#define    PC0       0
-
-/* Port C Data Direction Register - DDRC */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Port C Input Pins - PINC */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Port D Data Register - PORTD */
-#define    PD7       7
-#define    PD6       6
-#define    PD5       5
-#define    PD4       4
-#define    PD3       3
-#define    PD2       2
-#define    PD1       1
-#define    PD0       0
-
-/* Port D Data Direction Register - DDRD */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Port D Input Pins - PIND */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Port E Data Register - PORTE */
-#define    PE7       7
-#define    PE6       6
-#define    PE5       5
-#define    PE4       4
-#define    PE3       3
-#define    PE2       2
-#define    PE1       1
-#define    PE0       0
-
-/* Port E Data Direction Register - DDRE */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Port E Input Pins - PINE */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* Port F Data Register - PORTF */
-#define    PF7       7
-#define    PF6       6
-#define    PF5       5
-#define    PF4       4
-#define    PF3       3
-#define    PF2       2
-#define    PF1       1
-#define    PF0       0
-
-/* Port F Data Direction Register - DDRF */
-#define    DDF7         7
-#define    DDF6         6
-#define    DDF5         5
-#define    DDF4         4
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-#define    DDF0         0
-
-/* Port F Input Pins - PINF */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* Port G Data Register - PORTG */
-#define    PG4       4
-#define    PG3       3
-#define    PG2       2
-#define    PG1       1
-#define    PG0       0
-
-/* Port G Data Direction Register - DDRG */
-#define    DDG4         4
-#define    DDG3         3
-#define    DDG2         2
-#define    DDG1         1
-#define    DDG0         0
-
-/* Port G Input Pins - PING */
-#define    PING4        4
-#define    PING3        3
-#define    PING2        2
-#define    PING1        1
-#define    PING0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND     0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND    0xFFFF
-#define E2END      0x0FFF
-#define E2PAGESIZE 8
-#define FLASHEND   0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_WDTON       (unsigned char)~_BV(0)
-#define FUSE_M103C       (unsigned char)~_BV(1)
-#define EFUSE_DEFAULT (FUSE_M103C)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x02
-
-
-/**@}*/
-#endif /* _AVR_IOM128_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1280.h b/cpukit/score/cpu/avr/avr/iom1280.h
deleted file mode 100644
index a6aff362b8..0000000000
--- a/cpukit/score/cpu/avr/avr/iom1280.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega1280
- */
-
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom1280.h - definitions for ATmega1280 */
-
-#ifndef _AVR_IOM1280_H_
-#define _AVR_IOM1280_H_ 1
-
-#include <avr/iomxx0_1.h>
-
-/**
- * @defgroup AvrDef_iom1280 ATmega1280 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x03
-
-/** @} */
-
-#endif /* _AVR_IOM1280_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1281.h b/cpukit/score/cpu/avr/avr/iom1281.h
deleted file mode 100644
index 8b764c675e..0000000000
--- a/cpukit/score/cpu/avr/avr/iom1281.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file avr/iom1281.h
- *
- * @brief Definitions for ATmega1281
- */
-
-/*
- *  Copyright (c) 2005 Anatoly Sokolov
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_IOM1281_H_
-#define _AVR_IOM1281_H_ 1
-
-/**
- *  @defgroup Avr_iom1281 ATmega1281 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomxx0_1.h>
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x04
-
-/**@}*/
-#endif /* _AVR_IOM1281_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1284p.h b/cpukit/score/cpu/avr/avr/iom1284p.h
deleted file mode 100644
index 3076de21c6..0000000000
--- a/cpukit/score/cpu/avr/avr/iom1284p.h
+++ /dev/null
@@ -1,1141 +0,0 @@
-/**
- * @file avr/iom1284p.h
- *
- * @brief Definitions for ATmega1284P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom1284p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM1284P_H_
-#define _AVR_IOM1284P_H_ 1
-
-/**
- *  @defgroup Avr_iom1284p ATmega1284P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define ICF3 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRUSART1 4
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRTIM3 0
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define ICIE3 5
-
-#define PCMSK3 _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-
-#define INT0_vect         _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect         _VECTOR(3)  /* External Interrupt Request 2 */
-#define PCINT0_vect       _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect       _VECTOR(6)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect       _VECTOR(7)  /* Pin Change Interrupt Request 3 */
-#define WDT_vect          _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect   _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect    _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect  _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect    _VECTOR(22)  /* USART0, Tx Complete */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define ADC_vect          _VECTOR(24)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect          _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(27)  /* Store Program Memory Read */
-#define USART1_RX_vect    _VECTOR(28)  /* USART1 RX complete */
-#define USART1_UDRE_vect  _VECTOR(29)  /* USART1 Data Register Empty */
-#define USART1_TX_vect    _VECTOR(30)  /* USART1 TX complete */
-#define TIMER3_CAPT_vect  _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_OVF_vect   _VECTOR(34)  /* Timer/Counter3 Overflow */
-
-#define _VECTORS_SIZE (35 * 4)
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x40FF    /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0xFFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x05
-
-/**@}*/
-#endif  /* _AVR_IOM1284P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom128rfa1.h b/cpukit/score/cpu/avr/avr/iom128rfa1.h
deleted file mode 100644
index 480ae200f8..0000000000
--- a/cpukit/score/cpu/avr/avr/iom128rfa1.h
+++ /dev/null
@@ -1,5372 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */
-
-#ifndef _AVR_IOM128RFA1_H_
-#define _AVR_IOM128RFA1_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom128rfa1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#include <avr/sfr_defs.h>
-
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flag 2 */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior0 : 8;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/*  */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior1 : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior2 : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz : 2;	/* Extended Z-Pointer Value */
-        unsigned int : 6;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-#define RAMPZ1                          1
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAM 3 */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
-
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
-
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart : 3;	/* Reserved */
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRUSART2                        1
-#define PRUSART3                        2
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
-
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enable 2 */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 2;	/* Pin Change Enable Mask */
-        unsigned int pcint1 : 6;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint1 : 4;	/* Pin Change Enable Mask */
-        unsigned int pcint2 : 4;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
-
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
-#ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int : 7;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register of SRAM 3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define P_ON                            0
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Reserved */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 5;
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int pa_lt : 2;	/* Power Amplifier Lead Time */
-        unsigned int pa_buf_lt : 2;	/* Power Amplifier Buffer Lead Time */
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-/* symbolic names */
-
-#define PA_LT_2US                       0
-#define PA_LT_4US                       1
-#define PA_LT_6US                       2
-#define PA_LT_8US                       3
-#define PA_BUF_LT_0US                   0
-#define PA_BUF_LT_2US                   1
-#define PA_BUF_LT_4US                   2
-#define PA_BUF_LT_6US                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-#define PA_LT0                          4
-#define PA_LT1                          5
-#define PA_BUF_LT0                      6
-#define PA_BUF_LT1                      7
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          84
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 3;
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_PDT_DIS                      7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_ATmega128RFA1                 131
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           2
-#define REV_B                           3
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_0 : 8;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_1 : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_0 : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_1 : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_0 : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_1 : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_0 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_1 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_2 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_3 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_4 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_5 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_6 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_7 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_0 : 8;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_RX_LENGTH */
-
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
-
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
-
-  /* TRXFBST */
-
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
-
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
-
-  /* TRXFBEND */
-
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  288
-
-/* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
-
-/* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
-
-/* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
-
-/* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
-
-/* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
-
-/* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
-
-/* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
-
-/* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
-
-/* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
-
-/* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
-
-/* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
-
-/* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
-
-/* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
-
-/* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
-
-/* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
-
-/* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
-
-/* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
-
-/* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
-
-/* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
-
-/* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
-
-/* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
-
-/* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
-
-/* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* USART2, Rx Complete */
-#define USART2_RX_vect                  _VECTOR(51)
-#define USART2_RX_vect_num              51
-
-/* USART2 Data register Empty */
-#define USART2_UDRE_vect                _VECTOR(52)
-#define USART2_UDRE_vect_num            52
-
-/* USART2, Tx Complete */
-#define USART2_TX_vect                  _VECTOR(53)
-#define USART2_TX_vect_num              53
-
-/* USART3, Rx Complete */
-#define USART3_RX_vect                  _VECTOR(54)
-#define USART3_RX_vect_num              54
-
-/* USART3 Data register Empty */
-#define USART3_UDRE_vect                _VECTOR(55)
-#define USART3_UDRE_vect_num            55
-
-/* USART3, Tx Complete */
-#define USART3_TX_vect                  _VECTOR(56)
-#define USART3_TX_vect_num              56
-
-/* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
-
-/* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
-
-/* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
-
-/* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
-
-/* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
-
-/* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
-
-/* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
-
-/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
-
-/* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
-
-/* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
-
-/* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
-
-/* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
-
-/* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
-
-/* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
-
-/* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
-
-
-/* memory parameters */
-
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x4000)
-#define RAMEND                          (0x41FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0xFFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x1ffff)
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-
-/* Lock Bits */
-
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0xA7
-#define SIGNATURE_2 0x01
-
-#endif /* _AVR_IOM128RFA1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16.h b/cpukit/score/cpu/avr/avr/iom16.h
deleted file mode 100644
index 6d6e9e3e2c..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * @file avr/iom16.h
- *
- * @brief Definitions for ATmega16
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004 Eric B. Weddington
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM16_H_
-#define _AVR_IOM16_H_ 1
-
-/**
- *  @defgroup Avr_iom16 ATmega16 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define TWBR    _SFR_IO8(0x00)
-
-#define TWSR    _SFR_IO8(0x01)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_IO8(0x02)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_IO8(0x03)
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSRA  _SFR_IO8(0x06)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADMUX   _SFR_IO8(0x07)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-#define ACSR    _SFR_IO8(0x08)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define UBRRL   _SFR_IO8(0x09)
-
-#define UCSRB   _SFR_IO8(0x0A)
-#define TXB8    0
-#define RXB8    1
-#define UCSZ2   2
-#define TXEN    3
-#define RXEN    4
-#define UDRIE   5
-#define TXCIE   6
-#define RXCIE   7
-
-#define UCSRA   _SFR_IO8(0x0B)
-#define MPCM    0
-#define U2X     1
-#define PE      2
-#define DOR     3
-#define FE      4
-#define UDRE    5
-#define TXC     6
-#define RXC     7
-
-#define UDR     _SFR_IO8(0x0C)
-
-#define SPCR    _SFR_IO8(0x0D)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x0E)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x0F)
-
-#define PIND    _SFR_IO8(0x10)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-#define DDRD    _SFR_IO8(0x11)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-#define PORTD   _SFR_IO8(0x12)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-#define PINC    _SFR_IO8(0x13)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-#define DDRC    _SFR_IO8(0x14)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-#define PORTC   _SFR_IO8(0x15)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA0   0
-#define PINA1   1
-#define PINA2   2
-#define PINA3   3
-#define PINA4   4
-#define PINA5   5
-#define PINA6   6
-#define PINA7   7
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PA0     0
-#define PA1     1
-#define PA2     2
-#define PA3     3
-#define PA4     4
-#define PA5     5
-#define PA6     6
-#define PA7     7
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UCSRC   _SFR_IO8(0x20)
-#define UCPOL   0
-#define UCSZ0   1
-#define UCSZ1   2
-#define USBS    3
-#define UPM0    4
-#define UPM1    5
-#define UMSEL   6
-#define URSEL   7
-
-#define UBRRH   _SFR_IO8(0x20)
-#define URSEL   7
-
-#define WDTCR   _SFR_IO8(0x21)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDTOE   4
-
-#define ASSR    _SFR_IO8(0x22)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-
-#define OCR2    _SFR_IO8(0x23)
-
-#define TCNT2   _SFR_IO8(0x24)
-
-#define TCCR2   _SFR_IO8(0x25)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM20   4
-#define COM21   5
-#define WGM20   6
-#define FOC2    7
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_IO16(0x26)
-
-#define ICR1L   _SFR_IO8(0x26)
-#define ICR1H   _SFR_IO8(0x27)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_IO16(0x28)
-
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_IO16(0x2A)
-
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_IO16(0x2C)
-
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-#define TCCR1B  _SFR_IO8(0x2E)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1A  _SFR_IO8(0x2F)
-#define WGM10   0
-#define WGM11   1
-#define FOC1B   2
-#define FOC1A   3
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-#define SFIOR   _SFR_IO8(0x30)
-#define PSR10   0
-#define PSR2    1
-#define PUD     2
-#define ACME    3
-#define ADTS0   5
-#define ADTS1   6
-#define ADTS2   7
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define OCDR    _SFR_IO8(0x31)
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0   _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM00   4
-#define COM01   5
-#define WGM00   6
-#define FOC0    7
-
-#define MCUCSR  _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-#define ISC2    6
-#define JTD     7
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define SM0     4
-#define SM1     5
-#define SE      6
-#define SM2     7
-
-#define TWCR    _SFR_IO8(0x36)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define SPMCR   _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-#define TIFR    _SFR_IO8(0x38)
-#define TOV0    0
-#define OCF0    1
-#define TOV1    2
-#define OCF1B   3
-#define OCF1A   4
-#define ICF1    5
-#define TOV2    6
-#define OCF2    7
-
-#define TIMSK   _SFR_IO8(0x39)
-#define TOIE0   0
-#define OCIE0   1
-#define TOIE1   2
-#define OCIE1B  3
-#define OCIE1A  4
-#define TICIE1  5
-#define TOIE2   6
-#define OCIE2   7
-
-#define GIFR    _SFR_IO8(0x3A)
-#define INTF2   5
-#define INTF0   6
-#define INTF1   7
-
-#define GICR    _SFR_IO8(0x3B)
-#define IVCE    0
-#define IVSEL   1
-#define INT2    5
-#define INT0    6
-#define INT1    7
-
-#define OCR0    _SFR_IO8(0x3C)
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector. */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* USART, Rx Complete */
-#define USART_RXC_vect			_VECTOR(11)
-#define SIG_USART_RECV			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(12)
-#define SIG_USART_DATA			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* USART, Tx Complete */
-#define USART_TXC_vect			_VECTOR(13)
-#define SIG_USART_TRANS			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(18)
-#define SIG_INTERRUPT2			_VECTOR(18)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(19)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(19)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(20)
-#define SIG_SPM_READY			_VECTOR(20)
-
-#define _VECTORS_SIZE 84
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x45F
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IOM16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom161.h b/cpukit/score/cpu/avr/avr/iom161.h
deleted file mode 100644
index af7bebeec1..0000000000
--- a/cpukit/score/cpu/avr/avr/iom161.h
+++ /dev/null
@@ -1,685 +0,0 @@
-/**
- * @file avr/iom161.h
- *
- * @brief Definitions for ATmega161
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2002, Marek Michalkiewicz
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM161_H_
-#define _AVR_IOM161_H_ 1
-
-/**
- *  @defgroup Avr_iom161 ATmega161 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom161.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* UART1 Baud Rate Register */
-#define UBRR1	_SFR_IO8(0x00)
-
-/* UART1 Control and Status Registers */
-#define UCSR1B	_SFR_IO8(0x01)
-#define UCSR1A	_SFR_IO8(0x02)
-
-/* UART1 I/O Data Register */
-#define UDR1	_SFR_IO8(0x03)
-
-/* 0x04 reserved */
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x05)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x06)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART0 Baud Rate Register */
-#define UBRR0	_SFR_IO8(0x09)
-
-/* UART0 Control and Status Registers */
-#define UCSR0B	_SFR_IO8(0x0A)
-#define UCSR0A	_SFR_IO8(0x0B)
-
-/* UART0 I/O Data Register */
-#define UDR0	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* UART Baud Register HIgh */
-#define UBRRH	_SFR_IO8(0x20)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x22)
-
-/* Timer/Counter2 (8-bit) */
-#define TCNT2	_SFR_IO8(0x23)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* ASynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x26)
-
-/* Timer/Counter2 Control Register */
-#define TCCR2	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare RegisterB */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare RegisterA */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR	_SFR_IO8(0x30)
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Extended MCU general Control Register */
-#define EMCUCR	_SFR_IO8(0x36)
-
-/* Store Program Memory Control Register */
-#define SPMCR	_SFR_IO8(0x37)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* UART0, Rx Complete */
-#define UART0_RX_vect			_VECTOR(13)
-#define SIG_UART0_RECV			_VECTOR(13)
-
-/* UART1, Rx Complete */
-#define UART1_RX_vect			_VECTOR(14)
-#define SIG_UART1_RECV			_VECTOR(14)
-
-/* UART0 Data Register Empty */
-#define UART0_UDRE_vect			_VECTOR(15)
-#define SIG_UART0_DATA			_VECTOR(15)
-
-/* UART1 Data Register Empty */
-#define UART1_UDRE_vect			_VECTOR(16)
-#define SIG_UART1_DATA			_VECTOR(16)
-
-/* UART0, Tx Complete */
-#define UART0_TX_vect			_VECTOR(17)
-#define SIG_UART0_TRANS			_VECTOR(17)
-
-/* UART1, Tx Complete */
-#define UART1_TX_vect			_VECTOR(18)
-#define SIG_UART1_TRANS			_VECTOR(18)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(19)
-#define SIG_EEPROM_READY		_VECTOR(19)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(20)
-#define SIG_COMPARATOR			_VECTOR(20)
-
-#define _VECTORS_SIZE 84
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-#define INT2	5
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-#define INTF2	5
-
-/* TIMSK */
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B	5
-#define TOIE2	4
-#define TICIE1	3
-#define OCIE2	2
-#define TOIE0	1
-#define OCIE0	0
-
-/* TIFR */
-#define TOV1	7
-#define	OCF1A	6
-#define	OCF1B	5
-#define TOV2	4
-#define ICF1	3
-#define OCF2	2
-#define TOV0	1
-#define OCF0	0
-
-/* MCUCR */
-#define SRE	7
-#define SRW10	6
-#define SE	5
-#define SM1	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* EMCUCR */
-#define SM0	7
-#define SRL2	6
-#define SRL1	5
-#define SRL0	4
-#define SRW01	3
-#define SRW00	2
-#define SRW11	1
-#define ISC2	0
-
-/* SPMCR */
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* SFIOR */
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-#define FOC0	7
-#define PWM0	6
-#define COM01	5
-#define COM00	4
-#define CTC0	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define PWM2	6
-#define COM21	5
-#define COM20	4
-#define CTC2	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define PWM11	1
-#define PWM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = TXD1 / AIN1
-   PB2 = RXD1 / AIN0
-   PB1 = OC2 / T1
-   PB0 = OC0 / T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = RD#
-   PD6 = WR#
-   PD5 = TOSC2 / OC1A
-   PD4 = TOSC1
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD0
-   PD0 = RXD0
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/*
-   PE2 = ALE
-   PE1 = OC1B
-   PE0 = ICP / INT2
- */
-
-/* PORTE */
-#define PE2	2
-#define PE1	1
-#define PE0	0
-
-/* DDRE */
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-/* PINE */
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSR0A, UCSR1A */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-#define U2X	1
-#define MPCM	0
-
-/* UCSR0B, UCSR1B */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define CHR9	2
-#define RXB8	1
-#define TXB8	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x45F
-#define XRAMEND		0xFFFF
-#define E2END		0x1FF
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_SUT         (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BOOTRST     (unsigned char)~_BV(6)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x01
-
-
-/**@}*/
-#endif /* _AVR_IOM161_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom162.h b/cpukit/score/cpu/avr/avr/iom162.h
deleted file mode 100644
index d10a59aff7..0000000000
--- a/cpukit/score/cpu/avr/avr/iom162.h
+++ /dev/null
@@ -1,964 +0,0 @@
-/**
- * @file iom162.h
- *
- * @brief Definitions for ATmega162
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM162_H_
-#define _AVR_IOM162_H_ 1
-
-/**
- *  @defgroup Avr_iom162 ATmega162 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom162.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Memory mapped I/O registers */
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A	_SFR_MEM8(0x8B)
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B	_SFR_MEM8(0x8A)
-
-/* Timer/Counter3 - Counter Register */
-#define TCNT3H	_SFR_MEM8(0x89)
-#define TCNT3L	_SFR_MEM8(0x88)
-#define TCNT3	_SFR_MEM16(0x88)
-
-/* Timer/Counter3 - Output Compare Register A */
-#define OCR3AH	_SFR_MEM8(0x87)
-#define OCR3AL	_SFR_MEM8(0x86)
-#define OCR3A	_SFR_MEM16(0x86)
-
-/* Timer/Counter3 - Output Compare Register B */
-#define OCR3BH	_SFR_MEM8(0x85)
-#define OCR3BL	_SFR_MEM8(0x84)
-#define OCR3B	_SFR_MEM16(0x84)
-
-/* Timer/Counter3 - Input Capture Register */
-#define ICR3H	_SFR_MEM8(0x81)
-#define ICR3L	_SFR_MEM8(0x80)
-#define ICR3	_SFR_MEM16(0x80)
-
-/* Extended Timer/Counter Interrupt Mask */
-#define ETIMSK	_SFR_MEM8(0x7D)
-
-/* Extended Timer/Counter Interrupt Flag Register */
-#define ETIFR	_SFR_MEM8(0x7C)
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1	_SFR_MEM8(0x6C)
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0	_SFR_MEM8(0x6B)
-
-/* Clock PRescale */
-#define CLKPR	_SFR_MEM8(0x61)
-
-
-/* Standard I/O registers */
-
-/* 0x3F SREG */
-/* 0x3D..0x3E SP */
-#define	UBRR1H  _SFR_IO8(0x3C)  /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */
-#define UCSR1C  _SFR_IO8(0x3C)  /* USART 1 Control and Status Register, Shared with UBRR1H */
-#define GICR    _SFR_IO8(0x3B)	/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)	/* General Interrupt Flag Register */
-#define TIMSK	_SFR_IO8(0x39)	/* Timer Interrupt Mask */
-#define TIFR	_SFR_IO8(0x38)	/* Timer Interrupt Flag Register */
-#define SPMCR	_SFR_IO8(0x37)	/* Store Program Memory Control Register */
-#define EMCUCR	_SFR_IO8(0x36)	/* Extended MCU Control Register */
-#define MCUCR	_SFR_IO8(0x35)	/* MCU Control Register */
-#define MCUCSR	_SFR_IO8(0x34)	/* MCU Control and Status Register */
-#define TCCR0	_SFR_IO8(0x33)	/* Timer/Counter 0 Control Register */
-#define TCNT0	_SFR_IO8(0x32)	/* TImer/Counter 0 */
-#define OCR0	_SFR_IO8(0x31)	/* Output Compare Register 0 */
-#define SFIOR	_SFR_IO8(0x30)	/* Special Function I/O Register */
-#define TCCR1A	_SFR_IO8(0x2F)	/* Timer/Counter 1 Control Register A */
-#define TCCR1B	_SFR_IO8(0x2E)	/* Timer/Counter 1 Control Register A */
-#define TCNT1H	_SFR_IO8(0x2D)	/* Timer/Counter 1 High Byte */
-#define TCNT1L	_SFR_IO8(0x2C)	/* Timer/Counter 1 Low Byte */
-#define TCNT1	_SFR_IO16(0x2C)	/* Timer/Counter 1 */
-#define OCR1AH	_SFR_IO8(0x2B)	/* Timer/Counter 1 Output Compare Register A High Byte */
-#define OCR1AL	_SFR_IO8(0x2A)  /* Timer/Counter 1 Output Compare Register A Low Byte */
-#define OCR1A	_SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */
-#define OCR1BH	_SFR_IO8(0x29)	/* Timer/Counter 1 Output Compare Register B High Byte */
-#define OCR1BL	_SFR_IO8(0x28)	/* Timer/Counter 1 Output Compare Register B Low Byte */
-#define OCR1B	_SFR_IO16(0x28)	/* Timer/Counter 1 Output Compare Register B */
-#define TCCR2	_SFR_IO8(0x27)	/* Timer/Counter 2 Control Register */
-#define ASSR	_SFR_IO8(0x26)	/* Asynchronous Status Register */
-#define ICR1H	_SFR_IO8(0x25)	/* Input Capture Register 1 High Byte */
-#define ICR1L	_SFR_IO8(0x24)	/* Input Capture Register 1 Low Byte */
-#define ICR1	_SFR_IO16(0x24)	/* Input Capture Register 1 */
-#define TCNT2	_SFR_IO8(0x23)	/* Timer/Counter 2 */
-#define OCR2	_SFR_IO8(0x22)	/* Timer/Counter 2 Output Compare Register */
-#define WDTCR	_SFR_IO8(0x21)	/* Watchdow Timer Control Register */
-#define UBRR0H	_SFR_IO8(0x20)	/* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */
-#define UCSR0C	_SFR_IO8(0x20)	/* USART 0 Control and Status Register C, Shared with UBRR0H */
-#define EEARH	_SFR_IO8(0x1F)  /* EEPROM Address Register High Byte */
-#define EEARL	_SFR_IO8(0x1E)  /* EEPROM Address Register Low Byte */
-#define EEAR	_SFR_IO16(0x1E) /* EEPROM Address Register */
-#define EEDR	_SFR_IO8(0x1D)  /* EEPROM Data Register */
-#define EECR	_SFR_IO8(0x1C)  /* EEPROM Control Register */
-#define PORTA	_SFR_IO8(0x1B)	/* Port A */
-#define DDRA	_SFR_IO8(0x1A)	/* Port A Data Direction Register */
-#define PINA	_SFR_IO8(0x19)	/* Port A Pin Register */
-#define PORTB	_SFR_IO8(0x18)	/* Port B */
-#define DDRB	_SFR_IO8(0x17)	/* Port B Data Direction Register */
-#define PINB	_SFR_IO8(0x16)	/* Port B Pin Register */
-#define PORTC	_SFR_IO8(0x15)	/* Port C */
-#define DDRC	_SFR_IO8(0x14)	/* Port C Data Direction Register */
-#define PINC	_SFR_IO8(0x13)	/* Port C Pin Register */
-#define PORTD	_SFR_IO8(0x12)	/* Port D */
-#define DDRD	_SFR_IO8(0x11)	/* Port D Data Direction Register */
-#define PIND	_SFR_IO8(0x10)	/* Port D Pin Register */
-#define SPDR	_SFR_IO8(0x0F)  /* SPI Data Register */
-#define SPSR	_SFR_IO8(0x0E)	/* SPI Status Register */
-#define SPCR	_SFR_IO8(0x0D)	/* SPI Control Register */
-#define UDR0	_SFR_IO8(0x0C)	/* USART 0 Data Register */
-#define UCSR0A	_SFR_IO8(0x0B)	/* USART 0 Control and Status Register A */
-#define UCSR0B	_SFR_IO8(0x0A)	/* USART 0 Control and Status Register B */
-#define UBRR0L	_SFR_IO8(0x09)	/* USART 0 Baud-Rate Register Low Byte */
-#define ACSR	_SFR_IO8(0x08)	/* Analog Comparator Status Register */
-#define PORTE	_SFR_IO8(0x07)	/* Port E */
-#define DDRE	_SFR_IO8(0x06)	/* Port E Data Direction Register */
-#define PINE	_SFR_IO8(0x05)	/* Port E Pin Register */
-#define OSCCAL	_SFR_IO8(0x04) 	/* Oscillator Calibration, Shared with OCDR */
-#define OCDR	_SFR_IO8(0x04) 	/* On-Chip Debug Register, Shared with OSCCAL */
-#define UDR1	_SFR_IO8(0x03)	/* USART 1 Data Register */
-#define UCSR1A	_SFR_IO8(0x02)	/* USART 1 Control and Status Register A */
-#define UCSR1B	_SFR_IO8(0x01)	/* USART 1 Control and Status Register B */
-#define	UBRR1L  _SFR_IO8(0x00)  /* USART 0 Baud Rate Register High Byte */
-
-
-/* Interrupt vectors (byte addresses) */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(4)
-#define SIG_PIN_CHANGE0			_VECTOR(4)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(5)
-#define SIG_PIN_CHANGE1			_VECTOR(5)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE3		_VECTOR(6)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(7)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(8)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW3			_VECTOR(9)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(10)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW2			_VECTOR(11)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(12)
-#define SIG_INPUT_CAPTURE1		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(13)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(18)
-#define SIG_SPI				_VECTOR(18)
-
-/* USART0, Rx Complete */
-#define USART0_RXC_vect			_VECTOR(19)
-#define SIG_USART0_RECV			_VECTOR(19)
-
-/* USART1, Rx Complete */
-#define USART1_RXC_vect			_VECTOR(20)
-#define SIG_USART1_RECV			_VECTOR(20)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(21)
-#define SIG_USART0_DATA			_VECTOR(21)
-
-/* USART1, Data register Empty */
-#define USART1_UDRE_vect		_VECTOR(22)
-#define SIG_USART1_DATA			_VECTOR(22)
-
-/* USART0, Tx Complete */
-#define USART0_TXC_vect			_VECTOR(23)
-#define SIG_USART0_TRANS		_VECTOR(23)
-
-/* USART1, Tx Complete */
-#define USART1_TXC_vect			_VECTOR(24)
-#define SIG_USART1_TRANS		_VECTOR(24)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(25)
-#define SIG_EEPROM_READY		_VECTOR(25)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(26)
-#define SIG_COMPARATOR			_VECTOR(26)
-
-/* Store Program Memory Read */
-#define SPM_RDY_vect			_VECTOR(27)
-#define SIG_SPM_READY			_VECTOR(27)
-
-#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */
-
-
-
-
-
-/* TCCR3B bit definitions, memory mapped I/O */
-
-#define ICNC3	7
-#define ICES3	6
-#define WGM33	4
-#define WGM32	3
-#define CS32	2
-#define CS31	1
-#define CS30	0
-
-
-
-/* TCCR3A bit definitions, memory mapped I/O */
-
-#define COM3A1	7
-#define COM3A0	6
-#define COM3B1	5
-#define COM3B0	4
-#define FOC3A	3
-#define FOC3B	2
-#define WGM31	1
-#define WGM30	0
-
-
-
-/* ETIMSK bit definitions, memory mapped I/O */
-
-#define TICIE3		5
-#define OCIE3A		4
-#define OCIE3B		3
-#define TOIE3		2
-
-
-
-/* ETIFR bit definitions, memory mapped I/O */
-
-#define ICF3		5
-#define OCF3A		4
-#define OCF3B		3
-#define TOV3		2
-
-
-
-/* PCMSK1 bit definitions, memory mapped I/O */
-#define PCINT15	7
-#define PCINT14	6
-#define PCINT13	5
-#define PCINT12	4
-#define PCINT11	3
-#define PCINT10	2
-#define PCINT9	1
-#define PCINT8	0
-
-
-
-/* PCMSK0 bit definitions, memory mapped I/O */
-
-#define PCINT7	7
-#define PCINT6	6
-#define PCINT5	5
-#define PCINT4	4
-#define PCINT3	3
-#define PCINT2	2
-#define PCINT1	1
-#define PCINT0	0
-
-
-
-/* CLKPR bit definitions, memory mapped I/O */
-
-#define CLKPCE	7
-#define CLKPS3	3
-#define CLKPS2	2
-#define CLKPS1	1
-#define CLKPS0	0
-
-
-
-/* SPH bit definitions */
-
-#define SP15	15
-#define SP14	14
-#define SP13	13
-#define SP12	12
-#define SP11	11
-#define SP10	10
-#define SP9	9
-#define SP8	8
-
-
-
-/* SPL bit definitions */
-
-#define SP7	7
-#define SP6	6
-#define SP5	5
-#define SP4	4
-#define SP3	3
-#define SP2	2
-#define SP1	1
-#define SP0	0
-
-
-
-/* UBRR1H bit definitions */
-
-#define URSEL1	7
-#define UBRR111	3
-#define UBRR110	2
-#define UBRR19	1
-#define UBRR18	0
-
-
-
-/* UCSR1C bit definitions */
-
-#define URSEL1	7
-#define UMSEL1	6
-#define UPM11	5
-#define UPM10	4
-#define USBS1	3
-#define UCSZ11	2
-#define UCSZ10	1
-#define UCPOL1	0
-
-
-
-/* GICR bit definitions */
-
-#define INT1	7
-#define INT0	6
-#define INT2	5
-#define PCIE1	4
-#define PCIE0	3
-#define IVSEL	1
-#define IVCE	0
-
-
-
-/* GIFR bit definitions */
-
-#define INTF1	7
-#define INTF0	6
-#define INTF2	5
-#define PCIF1	4
-#define PCIF0	3
-
-
-
-/* TIMSK bit definitions */
-
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B  5
-#define OCIE2	4
-#define TICIE1	3
-#define TOIE2	2
-#define TOIE0	1
-#define OCIE0	0
-
-
-
-/* TIFR bit definitions */
-
-#define TOV1	7
-#define OCF1A	6
-#define OCF1B	5
-#define OCF2	4
-#define ICF1	3
-#define TOV2	2
-#define TOV0	1
-#define OCF0	0
-
-
-
-/* SPMCR bit definitions */
-
-#define SPMIE	7
-#define RWWSB	6
-#define RWWSRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-
-
-/* EMCUCR bit definitions */
-
-#define SM0	7
-#define SRL2	6
-#define SRL1	5
-#define SRL0	4
-#define SRW01	3
-#define SRW00	2
-#define SRW11	1
-#define ISC2	0
-
-
-
-/* MCUCR bit definitions */
-
-#define SRE	7
-#define SRW10	6
-#define SE	5
-#define SM1	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-
-
-/* MCUCSR bit definitions */
-
-#define JTD	7
-#define SM2	5
-#define JTRF	4
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-
-
-/* TCCR0 bit definitions */
-
-#define FOC0	7
-#define WGM00	6
-#define COM01	5
-#define COM00	4
-#define WGM01	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-
-
-/* SFIOR bit definitions */
-
-#define TSM	7
-#define XMBK	6
-#define XMM2	5
-#define XMM1	4
-#define XMM0	3
-#define PUD	2
-#define PSR2	1
-#define PSR310	0
-
-
-
-/* TCCR1A bit definitions */
-
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define FOC1A   3
-#define FOC1B   2
-#define WGM11   1
-#define WGM10   0
-
-
-
-
-/* TCCR1B bit definitions */
-
-#define ICNC1	7		/* Input Capture Noise Canceler */
-#define ICES1	6		/* Input Capture Edge Select */
-#define WGM13	4		/* Waveform Generation Mode 3 */
-#define WGM12	3		/* Waveform Generation Mode 2 */
-#define CS12	2		/* Clock Select 2 */
-#define CS11	1		/* Clock Select 1 */
-#define CS10	0		/* Clock Select 0 */
-
-
-
-/* TCCR2 bit definitions */
-
-#define FOC2	7
-#define WGM20	6
-#define COM21	5
-#define COM20	4
-#define WGM21	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-
-
-/* ASSR bit definitions */
-
-#define AS2	3
-#define TCN2UB  2
-#define TCON2UB	2   /* Kept for backwards compatibility. */
-#define OCR2UB	1
-#define TCR2UB	0
-
-
-
-/* WDTCR bit definitions */
-
-#define WDCE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-
-
-/* UBRR0H bif definitions */
-
-#define URSEL0	7
-#define UBRR011	3
-#define UBRR010	2
-#define UBRR09	1
-#define UBRR08	0
-
-
-
-/* UCSR0C bit definitions */
-
-#define URSEL0	7
-#define UMSEL0	6
-#define UPM01	5
-#define UPM00	4
-#define USBS0	3
-#define UCSZ01	2
-#define UCSZ00	1
-#define UCPOL0	0
-
-
-
-/* EEARH bit definitions */
-
-#define EEAR8	0
-
-
-
-/* EECR bit definitions */
-
-#define EERIE	3
-#define EEMWE	2
-#define EEWE	1
-#define EERE	0
-
-
-
-/* PORTA bit definitions */
-
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-
-
-/* DDRA bit definitions */
-
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-
-
-/* PINA bit definitions */
-
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-
-/* PORTB bit definitions */
-
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-
-
-/* DDRB bit definitions */
-
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-
-
-/* PINB bit definitions */
-
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-
-
-/* PORTC bit definitions */
-
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-
-
-/* DDRC bit definitions */
-
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-
-
-/* PINC bit definitions */
-
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-
-
-/* PORTD bit definitions */
-
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-
-
-/* DDRD bit definitions */
-
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-
-
-/* PIND bit definitions */
-
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-
-
-/* SPSR bit definitions */
-
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-
-
-/* SPCR bit definitions */
-
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-
-
-/* UCSR0A bit definitions */
-
-#define RXC0	7
-#define TXC0	6
-#define UDRE0	5
-#define FE0	4
-#define DOR0	3
-#define UPE0	2
-#define U2X0	1
-#define MPCM0	0
-
-
-
-/* UCSR0B bit definitions */
-
-#define RXCIE0	7
-#define TXCIE0	6
-#define UDRIE0	5
-#define RXEN0	4
-#define	TXEN0	3
-#define UCSZ02 	2
-#define RXB80	1
-#define TXB80	0
-
-
-
-/* ACSR bit definitions */
-
-#define ACD	7
-#define ACBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-
-
-/* PORTE bit definitions */
-
-#define PE2	2
-#define PE1	1
-#define PE0	0
-
-
-
-/* DDRE bit definitions */
-
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-
-
-/* PINE bit definitions */
-
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-
-
-/* UCSR1A bit definitions */
-
-#define RXC1	7
-#define TXC1	6
-#define UDRE1	5
-#define FE1	4
-#define DOR1	3
-#define UPE1    2
-#define U2X1	1
-#define MPCM1	0
-
-
-
-/* UCSR1B bit definitions */
-
-#define RXCIE1	7
-#define TXCIE1	6
-#define UDRIE1	5
-#define RXEN1	4
-#define TXEN1	3
-#define UCSZ12	2
-#define RXB81	1
-#define TXB81	0
-
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x4FF
-#define XRAMEND		0xFFFF
-#define E2END		0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define FUSE_M161C       (unsigned char)~_BV(4)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x04
-
-
-/**@}*/
-#endif  /* _AVR_IOM162_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom163.h b/cpukit/score/cpu/avr/avr/iom163.h
deleted file mode 100644
index 2dabcd8d40..0000000000
--- a/cpukit/score/cpu/avr/avr/iom163.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/**
- * @file avr/iom163.h
- *
- * @brief Definitions for ATmega163
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2007 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM163_H_
-#define _AVR_IOM163_H_ 1
-
-/**
- *  @defgroup Avr_iom163 ATmega163 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom163.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-#define TWBR	_SFR_IO8(0x00)
-#define TWSR	_SFR_IO8(0x01)
-#define TWAR	_SFR_IO8(0x02)
-#define TWDR	_SFR_IO8(0x03)
-
-/* ADC */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-#define ADCSR	_SFR_IO8(0x06)
-#define ADMUX	_SFR_IO8(0x07)
-
-/* analog comparator */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART */
-#define UBRR	_SFR_IO8(0x09)
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Port C */
-#define PINC	_SFR_IO8(0x13)
-#define DDRC	_SFR_IO8(0x14)
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* Port A */
-#define PINA	_SFR_IO8(0x19)
-#define DDRA	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UBRRHI	_SFR_IO8(0x20)
-
-#define WDTCR	_SFR_IO8(0x21)
-
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer 2 */
-#define OCR2	_SFR_IO8(0x23)
-#define TCNT2	_SFR_IO8(0x24)
-#define TCCR2	_SFR_IO8(0x25)
-
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-#define SFIOR	_SFR_IO8(0x30)
-
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer 0 */
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUSR	_SFR_IO8(0x34)
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TWCR	_SFR_IO8(0x36)
-
-#define SPMCR	_SFR_IO8(0x37)
-
-#define TIFR	_SFR_IO8(0x38)
-#define TIMSK	_SFR_IO8(0x39)
-
-#define GIFR	_SFR_IO8(0x3A)
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* 2-Wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-#define _VECTORS_SIZE 72
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-/* bit 5 reserved, undefined */
-/* bits 4-0 reserved */
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-/* bits 5-0 reserved */
-
-/* TIMSK */
-#define OCIE2	7
-#define TOIE2	6
-#define TICIE1	5
-#define OCIE1A	4
-#define OCIE1B	3
-#define TOIE1	2
-/* bit 1 reserved */
-#define TOIE0	0
-
-/* TIFR */
-#define OCF2	7
-#define TOV2	6
-#define ICF1	5
-#define OCF1A	4
-#define OCF1B	3
-#define TOV1	2
-/* bit 1 reserved, undefined */
-#define TOV0	0
-
-/* SPMCR */
-/* bit 7 reserved */
-#define ASB	6
-/* bit 5 reserved */
-#define ASRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* TWCR */
-#define TWINT	7
-#define TWEA	6
-#define TWSTA	5
-#define TWSTO	4
-#define TWWC	3
-#define TWEN	2
-/* bit 1 reserved */
-#define TWIE	0
-
-/* TWAR */
-#define TWGCE	0
-
-/* TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-/* bits 2-0 reserved */
-
-/* MCUCR */
-/* bit 7 reserved */
-#define SE	6
-#define SM1	5
-#define SM0	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* MCUSR */
-/* bits 7-4 reserved */
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-/* SFIOR */
-/* bits 7-4 reserved */
-#define ACME	3
-#define PUD	2
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-/* bits 7-3 reserved */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define PWM2	6
-#define COM21	5
-#define COM20	4
-#define CTC2	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-/* bits 7-4 reserved */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define PWM11	1
-#define PWM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bits 5-4 reserved */
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* PA7-PA0 = ADC7-ADC0 */
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = AIN1
-   PB2 = AIN0
-   PB1 = T1
-   PB0 = T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/*
-   PC7 = TOSC2
-   PC6 = TOSC1
-   PC1 = SDA
-   PC0 = SCL
- */
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = OC2
-   PD6 = ICP
-   PD5 = OC1A
-   PD4 = OC1B
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-/* bits 5-1 reserved */
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSRA */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-/* bit 2 reserved */
-#define U2X	1
-#define MPCM	0
-
-/* UCSRB */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define CHR9	2
-#define RXB8	1
-#define TXB8	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* ADCSR */
-#define ADEN	7
-#define ADSC	6
-#define ADFR	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-/* ADMUX */
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-#define MUX4	4
-#define MUX3	3
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x45F
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define HFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x02
-
-
-/**@}*/
-#endif /* _AVR_IOM163_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom164.h b/cpukit/score/cpu/avr/avr/iom164.h
deleted file mode 100644
index 160663da88..0000000000
--- a/cpukit/score/cpu/avr/avr/iom164.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega164
- */
-
-/* Copyright (c) 2005, 2006 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom164.h - definitions for ATmega164 */
-
-
-#ifndef _AVR_IOM164_H_
-#define _AVR_IOM164_H_ 1
-
-#include <avr/iomxx4.h>
-
-/**
- * @defgroup AvrDef_iom164 ATmega164 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x04FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature (ATmega164P) */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0A 
-
-/** @} */
-
-#endif /* _AVR_IOM164_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom165.h b/cpukit/score/cpu/avr/avr/iom165.h
deleted file mode 100644
index 72cbc39fec..0000000000
--- a/cpukit/score/cpu/avr/avr/iom165.h
+++ /dev/null
@@ -1,836 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega165
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom165.h - definitions for ATmega165 */
-
-#ifndef _AVR_IOM165_H_
-#define _AVR_IOM165_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom165.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom165 ATmega165 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   6
-#define PCIF1   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   6
-#define PCIE1   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-/* Combine PCMSK0 and PCMSK1 */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0
-#define U2X     1
-#define UPE     2
-#define DOR     3
-#define FE      4
-#define UDRE    5
-#define TXC     6
-#define RXC     7
-
-#define UCSRB   _SFR_MEM8(0XC1)
-#define TXB8    0
-#define RXB8    1
-#define UCSZ2   2
-#define TXEN    3
-#define RXEN    4
-#define UDRIE   5
-#define TXCIE   6
-#define RXCIE   7
-
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0
-#define UCSZ0   1
-#define UCSZ1   2
-#define USBS    3
-#define UPM0    4
-#define UPM1    5
-#define UMSEL   6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRRL and UBRRH */
-#define UBRR    _SFR_MEM16(0xC4)
-
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-#define UDR     _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define USART_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-#define _VECTORS_SIZE 88
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x4FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x07
-
-/** @} */
-
-#endif /* _AVR_IOM165_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom165p.h b/cpukit/score/cpu/avr/avr/iom165p.h
deleted file mode 100644
index 90daff565f..0000000000
--- a/cpukit/score/cpu/avr/avr/iom165p.h
+++ /dev/null
@@ -1,821 +0,0 @@
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   Copyright (c) 2006 Anatoly Sokolov <aesok@post.ru>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom165p.h - definitions for ATmega165P */
-
-#ifndef _AVR_IOM165P_H_
-#define _AVR_IOM165P_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom165p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   6
-#define PCIF1   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   6
-#define PCIE1   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-/* Combine PCMSK0 and PCMSK1 */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRRL and UBRRH */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define USART_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-#define _VECTORS_SIZE 88
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x4FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x07
-
-
-#endif /* _AVR_IOM165P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168.h b/cpukit/score/cpu/avr/avr/iom168.h
deleted file mode 100644
index 7f1dee2345..0000000000
--- a/cpukit/score/cpu/avr/avr/iom168.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for iom168
- */
-
-/*
- *  Copyright (c) 2004, Theodore A. Roth
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM168_H_
-#define _AVR_IOM168_H_ 1
-
-/**
- *  @defgroup Avr_iom168 iom168 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomx8.h>
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND      0x4FF
-#define XRAMEND     RAMEND
-#define E2END       0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND    0x3FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x06
-
-/**@}*/
-#endif /* _AVR_IOM168_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168p.h b/cpukit/score/cpu/avr/avr/iom168p.h
deleted file mode 100644
index 987d489434..0000000000
--- a/cpukit/score/cpu/avr/avr/iom168p.h
+++ /dev/null
@@ -1,885 +0,0 @@
-/**
- * @file avr/iom168p.h
- *
- * @brief Definitions for ATmega168P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom168p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM168P_H_
-#define _AVR_IOM168P_H_ 1
-
-/**
- *  @defgroup Avr_iom168p ATmega168P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define EEPROM_REG_LOCATIONS 1F2021
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCPHA0 1
-#define UCSZ01 2
-#define UDORD0 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect         _VECTOR(1)   /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)   /* External Interrupt Request 1 */
-#define PCINT0_vect       _VECTOR(3)   /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(4)   /* Pin Change Interrupt Request 0 */
-#define PCINT2_vect       _VECTOR(5)   /* Pin Change Interrupt Request 1 */
-#define WDT_vect          _VECTOR(6)   /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(7)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(8)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(16)  /* Timer/Couner0 Overflow */
-#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect     _VECTOR(18)  /* USART Rx Complete */
-#define USART_UDRE_vect   _VECTOR(19)  /* USART, Data Register Empty */
-#define USART_TX_vect     _VECTOR(20)  /* USART Tx Complete */
-#define ADC_vect          _VECTOR(21)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(22)  /* EEPROM Ready */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define TWI_vect          _VECTOR(24)  /* Two-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(25)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE (26 * 4)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND       0x4FF     /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x3FFF
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0B
-
-/**@}*/
-#endif  /* _AVR_IOM168P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169.h b/cpukit/score/cpu/avr/avr/iom169.h
deleted file mode 100644
index 64910dd115..0000000000
--- a/cpukit/score/cpu/avr/avr/iom169.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega169
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, 2003, 2004, 2005 
-   Juergen Schilling <juergen.schilling@honeywell.com>
-   Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iom169.h - definitions for ATmega169 */
-
-/* This should be up to date with data sheet version 2514J-AVR-12/03. */
-
-#ifndef _AVR_IOM169_H_
-#define _AVR_IOM169_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom169.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom169 ATmega169 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port A */
-#define PINA   _SFR_IO8(0x00)
-#define DDRA   _SFR_IO8(0x01)
-#define PORTA  _SFR_IO8(0x02)
-
-/* Port B */
-#define PINB   _SFR_IO8(0x03)
-#define DDRB   _SFR_IO8(0x04)
-#define PORTB  _SFR_IO8(0x05)
-
-/* Port C */
-#define PINC   _SFR_IO8(0x06)
-#define DDRC   _SFR_IO8(0x07)
-#define PORTC  _SFR_IO8(0x08)
-
-/* Port D */
-#define PIND   _SFR_IO8(0x09)
-#define DDRD   _SFR_IO8(0x0A)
-#define PORTD  _SFR_IO8(0x0B)
-
-/* Port E */
-#define PINE   _SFR_IO8(0x0C)
-#define DDRE   _SFR_IO8(0x0D)
-#define PORTE  _SFR_IO8(0x0E)
-
-/* Port F */
-#define PINF   _SFR_IO8(0x0F)
-#define DDRF   _SFR_IO8(0x10)
-#define PORTF  _SFR_IO8(0x11)
-
-/* Port G */
-#define PING   _SFR_IO8(0x12)
-#define DDRG   _SFR_IO8(0x13)
-#define PORTG  _SFR_IO8(0x14)
-
-/* Timer/Counter 0 interrupt Flag Register */
-#define TIFR0  _SFR_IO8(0x15)
-
-/* Timer/Counter 1 interrupt Flag Register */
-#define TIFR1  _SFR_IO8(0x16)
-
-/* Timer/Counter 2 interrupt Flag Register */
-#define TIFR2  _SFR_IO8(0x17)
-
-/* External Interrupt Flag Register */
-#define EIFR   _SFR_IO8(0x1C)
-
-/* External Interrupt Mask Register */
-#define EIMSK  _SFR_IO8(0x1D)
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0 _SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR  _SFR_IO8(0x23)
-
-/* Timer/Counter Control Register A */
-#define TCCR0A _SFR_IO8(0x24)
-
-/* Timer/Counter Register */
-#define TCNT0  _SFR_IO8(0x26)
-
-/* Output Compare Register A */
-#define OCR0A  _SFR_IO8(0x27)
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1 _SFR_IO8(0x2A)
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2 _SFR_IO8(0x2B)
-
-/* SPI Control Register */
-#define SPCR   _SFR_IO8(0x2C)
-
-/* SPI Status Register */
-#define SPSR   _SFR_IO8(0x2D)
-
-/* SPI Data Register */
-#define SPDR   _SFR_IO8(0x2E)
-
-/* Analog Comperator Control and Status Register */
-#define ACSR   _SFR_IO8(0x30)
-
-/* On-chip Debug Register */
-#define OCDR   _SFR_IO8(0x31)
-
-/* Sleep Mode Control Register */
-#define SMCR   _SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR  _SFR_IO8(0x34)
-
-/* MCU Control Rgeister */
-#define MCUCR  _SFR_IO8(0x35)
-
-/* Store Program Memory Control and Status Register */
-#define SPMCSR _SFR_IO8(0x37)
-
-/* Watchdog Timer Control Register */
-#define WDTCR  _SFR_MEM8(0x60)
-
-/* Clock Prescale Register */
-#define CLKPR  _SFR_MEM8(0x61)
-
-#define PRR    _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Oscillator Calibration Register */
-#define OSCCAL _SFR_MEM8(0x66)
-
-/* External Interrupt Control Register A */
-#define EICRA  _SFR_MEM8(0x69)
-
-/* Pin Change Mask Register */
-#define PCMSK  _SFR_MEM16(0x6B)
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCMSK1 _SFR_MEM8(0x6C)
-
-/* Timer/Counter 0 Interrupt Mask Register */
-#define TIMSK0 _SFR_MEM8(0x6E)
-
-/* Timer/Counter 1 Interrupt Mask Register */
-#define TIMSK1 _SFR_MEM8(0x6F)
-
-/* Timer/Counter 2 Interrupt Mask Register */
-#define TIMSK2 _SFR_MEM8(0x70)
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC    _SFR_MEM16(0x78)
-#endif
-#define ADCW   _SFR_MEM16(0x78)
-#define ADCL   _SFR_MEM8(0x78)
-#define ADCH   _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA _SFR_MEM8(0x7A)
-
-/* ADC Control and Status Register B */
-#define ADCSRB _SFR_MEM8(0x7B)
-
-/* ADC Multiplex Selection Register */
-#define ADMUX  _SFR_MEM8(0x7C)
-
-/* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet
-   (2514D-AVR-01/03), but seem to be correct in the discussions of the
-   registers. */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0  _SFR_MEM8(0x7E)
-
-/* Digital Input Disable Register 1 */
-#define DIDR1  _SFR_MEM8(0x7F)
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A _SFR_MEM8(0x80)
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B _SFR_MEM8(0x81)
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C _SFR_MEM8(0x82)
-
-/* Timer/Counter1 Register */
-#define TCNT1  _SFR_MEM16(0x84)
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1H _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1   _SFR_MEM16(0x86)
-#define ICR1L  _SFR_MEM8(0x86)
-#define ICR1H  _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A  _SFR_MEM16(0x88)
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AH _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Registare B */
-#define OCR1B  _SFR_MEM16(0x8A)
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BH _SFR_MEM8(0x8B)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A _SFR_MEM8(0xB0)
-
-/* Timer/Counter2 Register */
-#define TCNT2  _SFR_MEM8(0xB2)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2A  _SFR_MEM8(0xB3)
-
-/* Asynchronous Status Register */
-#define ASSR   _SFR_MEM8(0xB6)
-
-/* USI Control Register */
-#define USICR  _SFR_MEM8(0xB8)
-
-/* USI Status Register */
-#define USISR  _SFR_MEM8(0xB9)
-
-/* USI Data Register */
-#define USIDR  _SFR_MEM8(0xBA)
-
-/* USART0 Control and Status Register A */
-#define UCSRA  _SFR_MEM8(0xC0)
-
-/* USART0 Control and Status Register B */
-#define UCSRB  _SFR_MEM8(0xC1)
-
-/* USART0 Control and Status Register C */
-#define UCSRC  _SFR_MEM8(0xC2)
-
-/* USART0 Baud Rate Register */
-#define UBRR   _SFR_MEM16(0xC4)
-#define UBRRL  _SFR_MEM8(0xC4)
-#define UBRRH  _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR    _SFR_MEM8(0xC6)
-
-/* LCD Control and Status Register A */
-#define LCDCRA _SFR_MEM8(0xE4)
-
-/* LCD Control and Status Register B */
-#define LCDCRB _SFR_MEM8(0xE5)
-
-/* LCD Frame Rate Register */
-#define LCDFRR _SFR_MEM8(0xE6)
-
-/* LCD Contrast Control Register */
-#define LCDCCR _SFR_MEM8(0xE7)
-
-/* LCD Memory mapping */
-#define LCDDR0 _SFR_MEM8(0xEC)
-#define LCDDR1 _SFR_MEM8(0xED)
-#define LCDDR2 _SFR_MEM8(0xEE)
-#define LCDDR3 _SFR_MEM8(0xEF)
-#define LCDDR5 _SFR_MEM8(0xF1)
-#define LCDDR6 _SFR_MEM8(0xF2)
-#define LCDDR7 _SFR_MEM8(0xF3)
-#define LCDDR8 _SFR_MEM8(0xF4)
-#define LCDDR10 _SFR_MEM8(0xF6)
-#define LCDDR11 _SFR_MEM8(0xF7)
-#define LCDDR12 _SFR_MEM8(0xF8)
-#define LCDDR13 _SFR_MEM8(0xF9)
-#define LCDDR15 _SFR_MEM8(0xFB)
-#define LCDDR16 _SFR_MEM8(0xFC)
-#define LCDDR17 _SFR_MEM8(0xFD)
-#define LCDDR18 _SFR_MEM8(0xFE)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_USART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_USART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_USART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-#define _VECTORS_SIZE 92
-
-/* Bit numbers */
-
-/*
-   PA7 = SEG3
-   PA6 = SEG2
-   PA5 = SEG1
-   PA4 = SEG0
-   PA3 = COM3
-   PA2 = COM2
-   PA1 = COM1
-   PA0 = COM0
-*/
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = OC2A / PCINT15
-   PB6 = OC1B / PCINT14
-   PB5 = OC1A / PCINT13
-   PB4 = OC0A / PCINT12
-   PB3 = MISO / PCINT11
-   PB2 = MOSI / PCINT10
-   PB1 = SCK / PCINT9
-   PB0 = SS# / PCINT8
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/*
-   PC7 = SEG5
-   PC6 = SEG6
-   PC5 = SEG7
-   PC4 = SEG8
-   PC3 = SEG9
-   PC2 = SEG10
-   PC1 = SEG11
-   PC0 = SEG12
-*/
-
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = SEG15
-   PD6 = SEG16
-   PD5 = SEG17
-   PD4 = SEG18
-   PD3 = SEG19
-   PD2 = SEG20
-   PD1 = INT0 / SEG21
-   PD0 = ICP / SEG22
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/*
-   PE7 = CLK0 / PCINT7
-   PE6 = DO / PCINT6
-   PE5 = DI / SDA / PCINT5
-   PE4 = USCK / SCL / PCINT4
-   PE3 = AIN1 / PCINT3
-   PE2 = XCK / AIN0 / PCINT2
-   PE1 = TXD / PCINT1
-   PE0 = RXD / PCINT0
- */
-
-/* PORTE */
-#define PE7 7
-#define PE6 6
-#define PE5 5
-#define PE4 4
-#define PE3 3
-#define PE2 2
-#define PE1 1
-#define PE0 0
-
-/* DDRE */
-#define DDE7	7
-#define DDE6	6
-#define DDE5	5
-#define DDE4	4
-#define DDE3	3
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-/* PINE */
-#define PINE7	7
-#define PINE6	6
-#define PINE5	5
-#define PINE4	4
-#define PINE3	3
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-/*
-   PF7 = ADC7 / TDI
-   PF6 = ADC6 / TDO
-   PF5 = ADC5 / TMS
-   PF4 = ADC4 / TCK
-   PF3 = ADC3
-   PF2 = ADC2
-   PF1 = ADC1
-   PF0 = ADC0
- */
-
-/* PORTF */
-#define PF7 7
-#define PF6 6
-#define PF5 5
-#define PF4 4
-#define PF3 3
-#define PF2 2
-#define PF1 1
-#define PF0 0
-
-/* DDRF */
-#define DDF7	7
-#define DDF6	6
-#define DDF5	5
-#define DDF4	4
-#define DDF3	3
-#define DDF2	2
-#define DDF1	1
-#define DDF0	0
-
-/* PINF */
-#define PINF7	7
-#define PINF6	6
-#define PINF5	5
-#define PINF4	4
-#define PINF3	3
-#define PINF2	2
-#define PINF1	1
-#define PINF0	0
-
-/*
-   PG5 = RESET#
-   PG4 = T0 / SEG23
-   PG3 = T1 / SEG24
-   PG2 = SEG4
-   PG1 = SEG13
-   PG0 = SEG14
- */
-
-/* PORTG */
-#define PG4 4
-#define PG3 3
-#define PG2 2
-#define PG1 1
-#define PG0 0
-
-/* DDRG */
-#define DDG4	4
-#define DDG3	3
-#define DDG2	2
-#define DDG1	1
-#define DDG0	0
-
-/* PING */
-#define PING5	5
-#define PING4	4
-#define PING3	3
-#define PING2	2
-#define PING1	1
-#define PING0	0
-
-/* TIFR0 */
-#define OCF0A	1
-#define TOV0	0
-
-/* TIFR1 */
-#define ICF1   5
-#define OCF1B  2
-#define OCF1A	1
-#define TOV1	0
-
-/* TIFR2 */
-#define OCF2A	1
-#define TOV2	0
-
-/* EIFR */
-#define PCIF1  7
-#define PCIF0  6
-#define INTF0  0
-
-/* EIMSK */
-#define PCIE1  7
-#define PCIE0  6
-#define INT0   0
-
-/* EECR */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* GTCCR */
-#define TSM    7
-#define PSR2   1
-#define PSR10  0
-
-/* TCCR0A */
-#define FOC0A	7
-#define WGM00	6
-#define COM0A1	5
-#define COM0A0	4
-#define WGM01	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	   6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* ACSR */
-#define ACD	   7
-#define ACBG	6
-#define ACO	   5
-#define ACI	   4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* OCDR */
-#define IDRD   7
-#define OCD    7
-#define OCDR6  6
-#define OCDR5  5
-#define OCDR4  4
-#define OCDR3  3
-#define OCDR2  2
-#define OCDR1  1
-#define OCDR0  0
-
-/* SMCR */
-#define SM2    3
-#define SM1    2
-#define SM0    1
-#define SE     0
-
-/* MCUSR */
-#define JTRF   4
-#define WDRF   3
-#define BORF   2
-#define EXTRF  1
-#define PORF   0
-
-/* MCUCR */
-#define JTD    7
-#define PUD    4
-#define IVSEL  1
-#define IVCE   0
-
-/* SPMCSR */
-#define SPMIE  7
-#define RWWSB  6
-#define RWWSRE 4
-#define BLBSET 3
-#define PGWRT  2
-#define PGERS  1
-#define SPMEN  0
-
-/* WDTCR */
-#define WDCE	4
-#define WDE	   3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* CLKPR */
-#define CLKPCE 7
-#define CLKPS3 3
-#define CLKPS2 2
-#define CLKPS1 1
-#define CLKPS0 0
-
-/* EICRA */
-#define ISC01  1
-#define ISC00  0
-
-/* PCMSK0 */
-#define PCINT7 7
-#define PCINT6 6
-#define PCINT5 5
-#define PCINT4 4
-#define PCINT3 3
-#define PCINT2 2
-#define PCINT1 1
-#define PCINT0 0
-
-/* PCMSK1 */
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9 1
-#define PCINT8 0
-
-/* TIMSK0 */
-#define OCIE0A 1
-#define TOIE0  0
-
-/* TIMSK1 */
-#define ICIE1  5
-#define OCIE1B 2
-#define OCIE1A 1
-#define TOIE1  0
-
-/* TIMSK2 */
-#define OCIE2A 1
-#define TOIE2  0
-
-/* ADCSRA */
-#define ADEN   7
-#define ADSC   6
-#define ADATE  5
-#define ADIF   4
-#define ADIE   3
-#define ADPS2  2
-#define ADPS1  1
-#define ADPS0  0
-
-/* ADCSRB */
-#define ACME   6
-#define ADTS2  2
-#define ADTS1  1
-#define ADTS0  0
-
-/* ADMUX */
-#define REFS1  7
-#define REFS0  6
-#define ADLAR  5
-#define MUX4   4
-#define MUX3   3
-#define MUX2   2
-#define MUX1   1
-#define MUX0   0
-
-/* DIDR1 */
-#define AIN1D  1
-#define AIN0D  0
-
-/* DIDR0 */
-#define ADC7D  7
-#define ADC6D  6
-#define ADC5D  5
-#define ADC4D  4
-#define ADC3D  3
-#define ADC2D  2
-#define ADC1D  1
-#define ADC0D  0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define WGM11	1
-#define WGM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-#define WGM13  4
-#define WGM12	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* TCCR1C */
-#define FOC1A  7
-#define FOC1B  6
-
-/* TCCR2A */
-#define FOC2A	7
-#define WGM20	6
-#define COM2A1	5
-#define COM2A0	4
-#define WGM21	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-#define EXCLK  4
-#define AS2	   3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* USICR */
-#define USISIE 7
-#define USIOIE 6
-#define USIWM1 5
-#define USIWM0 4
-#define USICS1 3
-#define USICS0 2
-#define USICLK 1
-#define USITC  0
-
-/* USISR */
-#define USISIF 7
-#define USIOIF 6
-#define USIPF  5
-#define USIDC  4
-#define USICNT3 3
-#define USICNT2 2
-#define USICNT1 1
-#define USICNT0 0
-
-/* UCSRA */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-#define UPE 	2
-#define U2X     1
-#define MPCM	0
-
-/* UCSRB */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define TXEN	3
-#define UCSZ2   2
-#define RXB8	1
-#define TXB8	0
-
-/* UCSRC */
-#define UMSEL   6
-#define UPM1    5
-#define UPM0    4
-#define USBS    3
-#define UCSZ1   2
-#define UCSZ0   1
-#define UCPOL   0
-
-/* LCDCRA */
-#define LCDEN  7
-#define LCDAB  6
-#define LCDIF  4
-#define LCDIE  3
-#define LCDBD  2 /* Only in Rev. F */
-#define LCDCCD 1 /* Only in Rev. F */
-#define LCDBL  0
-
-/* LCDCRB */
-#define LCDCS  7
-#define LCD2B  6
-#define LCDMUX1 5
-#define LCDMUX0 4
-#define LCDPM2 2
-#define LCDPM1 1
-#define LCDPM0 0
-
-/* LCDFRR */
-#define LCDPS2 6
-#define LCDPS1 5
-#define LCDPS0 4
-#define LCDCD2 2
-#define LCDCD1 1
-#define LCDCD0 0
-
-/* LCDCCR */
-#define LCDDC2 7
-#define LCDDC1 6
-#define LCDDC0 5
-#define LCDMDT 4 /* Only in Rev. F */
-#define LCDCC3 3
-#define LCDCC2 2
-#define LCDCC1 1
-#define LCDCC0 0
-
-/* LCDDR0-18 */
-#define SEG24  0
-
-#define SEG23  7
-#define SEG22  6
-#define SEG21  5
-#define SEG20  4
-#define SEG19  3
-#define SEG18  2
-#define SEG17  1
-#define SEG16  0
-
-#define SEG15  7
-#define SEG14  6
-#define SEG13  5
-#define SEG12  4
-#define SEG11  3
-#define SEG10  2
-#define SEG9   1
-#define SEG8   0
-
-#define SEG7   7
-#define SEG6   6
-#define SEG5   5
-#define SEG4   4
-#define SEG3   3
-#define SEG2   2
-#define SEG1   1
-#define SEG0   0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x4FF
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x05
-
-/** @} */
-
-#endif  /* _AVR_IOM169_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169p.h b/cpukit/score/cpu/avr/avr/iom169p.h
deleted file mode 100644
index 3d7995a3f5..0000000000
--- a/cpukit/score/cpu/avr/avr/iom169p.h
+++ /dev/null
@@ -1,1046 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega169P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, 2003, 2004, 2005, 2006
-   Juergen Schilling <juergen.schilling@honeywell.com>
-   Eric B. Weddington <ericw@evcohs.com>
-   Anatoly Sokolov <aesok@post.ru>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iom169p.h - definitions for ATmega169P */
-
-#ifndef _AVR_IOM169P_H_
-#define _AVR_IOM169P_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom169p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom169p ATmega169P Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port A */
-#define PINA   _SFR_IO8(0x00)
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-#define DDRA   _SFR_IO8(0x01)
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-#define PORTA  _SFR_IO8(0x02)
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* Port B */
-#define PINB   _SFR_IO8(0x03)
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-#define DDRB   _SFR_IO8(0x04)
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-#define PORTB  _SFR_IO8(0x05)
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* Port C */
-#define PINC   _SFR_IO8(0x06)
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-#define DDRC   _SFR_IO8(0x07)
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-#define PORTC  _SFR_IO8(0x08)
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* Port D */
-#define PIND   _SFR_IO8(0x09)
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-#define DDRD   _SFR_IO8(0x0A)
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-#define PORTD  _SFR_IO8(0x0B)
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* Port E */
-#define PINE   _SFR_IO8(0x0C)
-#define PINE7	7
-#define PINE6	6
-#define PINE5	5
-#define PINE4	4
-#define PINE3	3
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-#define DDRE   _SFR_IO8(0x0D)
-#define DDE7	7
-#define DDE6	6
-#define DDE5	5
-#define DDE4	4
-#define DDE3	3
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-#define PORTE  _SFR_IO8(0x0E)
-#define PE7	7
-#define PE6	6
-#define PE5	5
-#define PE4	4
-#define PE3	3
-#define PE2	2
-#define PE1	1
-#define PE0	0
-
-/* Port F */
-#define PINF   _SFR_IO8(0x0F)
-#define PINF7	7
-#define PINF6	6
-#define PINF5	5
-#define PINF4	4
-#define PINF3	3
-#define PINF2	2
-#define PINF1	1
-#define PINF0	0
-
-#define DDRF   _SFR_IO8(0x10)
-#define DDF7	7
-#define DDF6	6
-#define DDF5	5
-#define DDF4	4
-#define DDF3	3
-#define DDF2	2
-#define DDF1	1
-#define DDF0	0
-
-#define PORTF  _SFR_IO8(0x11)
-#define PF7	7
-#define PF6	6
-#define PF5	5
-#define PF4	4
-#define PF3	3
-#define PF2	2
-#define PF1	1
-#define PF0	0
-
-/* Port G */
-#define PING   _SFR_IO8(0x12)
-#define PING5	5
-#define PING4	4
-#define PING3	3
-#define PING2	2
-#define PING1	1
-#define PING0	0
-
-#define DDRG   _SFR_IO8(0x13)
-#define DDG4	4
-#define DDG3	3
-#define DDG2	2
-#define DDG1	1
-#define DDG0	0
-
-#define PORTG  _SFR_IO8(0x14)
-#define PG4	4
-#define PG3	3
-#define PG2	2
-#define PG1	1
-#define PG0	0
-
-/* Timer/Counter 0 interrupt Flag Register */
-#define TIFR0  _SFR_IO8(0x15)
-#define OCF0A	1
-#define TOV0	0
-
-/* Timer/Counter 1 interrupt Flag Register */
-#define TIFR1  _SFR_IO8(0x16)
-#define ICF1	5
-#define OCF1B	2
-#define OCF1A	1
-#define TOV1	0
-
-/* Timer/Counter 2 interrupt Flag Register */
-#define TIFR2  _SFR_IO8(0x17)
-#define OCF2A	1
-#define TOV2	0
-
-/* External Interrupt Flag Register */
-#define EIFR   _SFR_IO8(0x1C)
-#define PCIF1  7
-#define PCIF0  6
-#define INTF0  0
-
-/* External Interrupt Mask Register */
-#define EIMSK  _SFR_IO8(0x1D)
-#define PCIE1  7
-#define PCIE0  6
-#define INT0   0
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0 _SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR  _SFR_IO8(0x23)
-#define TSM    7
-#define PSR2   1
-#define PSR10  0
-
-/* Timer/Counter Control Register A */
-#define TCCR0A _SFR_IO8(0x24)
-#define FOC0A	7
-#define WGM00	6
-#define COM0A1	5
-#define COM0A0	4
-#define WGM01	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* Timer/Counter Register */
-#define TCNT0  _SFR_IO8(0x26)
-
-/* Output Compare Register A */
-#define OCR0A  _SFR_IO8(0x27)
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1 _SFR_IO8(0x2A)
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2 _SFR_IO8(0x2B)
-
-/* SPI Control Register */
-#define SPCR   _SFR_IO8(0x2C)
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* SPI Status Register */
-#define SPSR   _SFR_IO8(0x2D)
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* SPI Data Register */
-#define SPDR   _SFR_IO8(0x2E)
-
-/* Analog Comperator Control and Status Register */
-#define ACSR   _SFR_IO8(0x30)
-#define ACD	7
-#define ACBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* On-chip Debug Register */
-#define OCDR   _SFR_IO8(0x31)
-#define IDRD   7
-#define OCDR7  7
-#define OCDR6  6
-#define OCDR5  5
-#define OCDR4  4
-#define OCDR3  3
-#define OCDR2  2
-#define OCDR1  1
-#define OCDR0  0
-
-/* Sleep Mode Control Register */
-#define SMCR   _SFR_IO8(0x33)
-#define SM2    3
-#define SM1    2
-#define SM0    1
-#define SE     0
-
-/* MCU Status Register */
-#define MCUSR  _SFR_IO8(0x34)
-#define JTRF   4
-#define WDRF   3
-#define BORF   2
-#define EXTRF  1
-#define PORF   0
-
-/* MCU Control Rgeister */
-#define MCUCR  _SFR_IO8(0x35)
-#define JTD    7
-#define PUD    4
-#define IVSEL  1
-#define IVCE   0
-
-/* Store Program Memory Control and Status Register */
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMIE  7
-#define RWWSB  6
-#define RWWSRE 4
-#define BLBSET 3
-#define PGWRT  2
-#define PGERS  1
-#define SPMEN  0
-
-/* Watchdog Timer Control Register */
-#define WDTCR  _SFR_MEM8(0x60)
-#define WDCE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* Clock Prescale Register */
-#define CLKPR  _SFR_MEM8(0x61)
-#define CLKPCE 7
-#define CLKPS3 3
-#define CLKPS2 2
-#define CLKPS1 1
-#define CLKPS0 0
-
-#define PRR    _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Oscillator Calibration Register */
-#define OSCCAL _SFR_MEM8(0x66)
-
-/* External Interrupt Control Register A */
-#define EICRA  _SFR_MEM8(0x69)
-#define ISC01  1
-#define ISC00  0
-
-/* Pin Change Mask Register */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9  1
-#define PCINT8  0
-
-/* Timer/Counter 0 Interrupt Mask Register */
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define OCIE0A 1
-#define TOIE0  0
-
-/* Timer/Counter 1 Interrupt Mask Register */
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define ICIE1  5
-#define OCIE1B 2
-#define OCIE1A 1
-#define TOIE1  0
-
-/* Timer/Counter 2 Interrupt Mask Register */
-#define TIMSK2 _SFR_MEM8(0x70)
-#define OCIE2A 1
-#define TOIE2  0
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC    _SFR_MEM16(0x78)
-#endif
-#define ADCW   _SFR_MEM16(0x78)
-#define ADCL   _SFR_MEM8(0x78)
-#define ADCH   _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADEN   7
-#define ADSC   6
-#define ADATE  5
-#define ADIF   4
-#define ADIE   3
-#define ADPS2  2
-#define ADPS1  1
-#define ADPS0  0
-
-
-/* ADC Control and Status Register B */
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ACME   6
-#define ADTS2  2
-#define ADTS1  1
-#define ADTS0  0
-
-/* ADC Multiplex Selection Register */
-#define ADMUX  _SFR_MEM8(0x7C)
-/* ADMUX */
-#define REFS1  7
-#define REFS0  6
-#define ADLAR  5
-#define MUX4   4
-#define MUX3   3
-#define MUX2   2
-#define MUX1   1
-#define MUX0   0
-
-/* Digital Input Disable Register 0 */
-#define DIDR0  _SFR_MEM8(0x7E)
-#define ADC7D  7
-#define ADC6D  6
-#define ADC5D  5
-#define ADC4D  4
-#define ADC3D  3
-#define ADC2D  2
-#define ADC1D  1
-#define ADC0D  0
-
-/* Digital Input Disable Register 1 */
-#define DIDR1  _SFR_MEM8(0x7F)
-#define AIN1D  1
-#define AIN0D  0
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A _SFR_MEM8(0x80)
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define WGM11	1
-#define WGM10	0
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B _SFR_MEM8(0x81)
-#define ICNC1	7
-#define ICES1	6
-#define WGM13	4
-#define WGM12	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1A  7
-#define FOC1B  6
-
-/* Timer/Counter1 Register */
-#define TCNT1  _SFR_MEM16(0x84)
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1H _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1   _SFR_MEM16(0x86)
-#define ICR1L  _SFR_MEM8(0x86)
-#define ICR1H  _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A  _SFR_MEM16(0x88)
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AH _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Registare B */
-#define OCR1B  _SFR_MEM16(0x8A)
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BH _SFR_MEM8(0x8B)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A _SFR_MEM8(0xB0)
-#define FOC2A	7
-#define WGM20	6
-#define COM2A1	5
-#define COM2A0	4
-#define WGM21	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* Timer/Counter2 Register */
-#define TCNT2  _SFR_MEM8(0xB2)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2A  _SFR_MEM8(0xB3)
-
-/* Asynchronous Status Register */
-#define ASSR   _SFR_MEM8(0xB6)
-#define EXCLK	4
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* USI Control Register */
-#define USICR  _SFR_MEM8(0xB8)
-#define USISIE 7
-#define USIOIE 6
-#define USIWM1 5
-#define USIWM0 4
-#define USICS1 3
-#define USICS0 2
-#define USICLK 1
-#define USITC  0
-
-/* USI Status Register */
-#define USISR  _SFR_MEM8(0xB9)
-#define USISIF  7
-#define USIOIF  6
-#define USIPF   5
-#define USIDC   4
-#define USICNT3 3
-#define USICNT2 2
-#define USICNT1 1
-#define USICNT0 0
-
-/* USI Data Register */
-#define USIDR  _SFR_MEM8(0xBA)
-
-/* USART0 Control and Status Register A */
-#define UCSR0A	_SFR_MEM8(0xC0)
-#define RXC0	7
-#define TXC0	6
-#define UDRE0	5
-#define FE0	4
-#define DOR0	3
-#define UPE0 	2
-#define U2X0	1
-#define MPCM0	0
-
-/* USART0 Control and Status Register B */
-#define UCSR0B	_SFR_MEM8(0xC1)
-#define RXCIE0	7
-#define TXCIE0	6
-#define UDRIE0	5
-#define RXEN0	4
-#define TXEN0	3
-#define UCSZ02	2
-#define RXB80	1
-#define TXB80	0
-
-/* USART0 Control and Status Register C */
-#define UCSR0C	_SFR_MEM8(0xC2)
-#define UMSEL0	6
-#define UPM01	5
-#define UPM00	4
-#define USBS0	3
-#define UCSZ01	2
-#define UCSZ00	1
-#define UCPOL0	0
-
-/* USART0 Baud Rate Register */
-#define UBRR0	_SFR_MEM16(0xC4)
-#define UBRR0L	_SFR_MEM8(0xC4)
-#define UBRR0H	_SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0	_SFR_MEM8(0xC6)
-
-/* LCD Control and Status Register A */
-#define LCDCRA	_SFR_MEM8(0xE4)
-#define LCDEN	7
-#define LCDAB	6
-#define LCDIF	4
-#define LCDIE	3
-#define LCDBD	2
-#define LCDCCD	1
-#define LCDBL	0
-
-/* LCD Control and Status Register B */
-#define LCDCRB	_SFR_MEM8(0xE5)
-#define LCDCS	7
-#define LCD2B	6
-#define LCDMUX1	5
-#define LCDMUX0	4
-#define LCDPM2	2
-#define LCDPM1	1
-#define LCDPM0	0
-
-/* LCD Frame Rate Register */
-#define LCDFRR	_SFR_MEM8(0xE6)
-#define LCDPS2	6
-#define LCDPS1	5
-#define LCDPS0	4
-#define LCDCD2	2
-#define LCDCD1	1
-#define LCDCD0	0
-
-/* LCD Contrast Control Register */
-#define LCDCCR	_SFR_MEM8(0xE7)
-#define LCDDC2	7
-#define LCDDC1	6
-#define LCDDC0	5
-#define LCDMDT	4
-#define LCDCC3	3
-#define LCDCC2	2
-#define LCDCC1	1
-#define LCDCC0	0
-
-/* LCD Memory mapping */
-#define LCDDR0 _SFR_MEM8(0xEC)
-#define SEG007 7
-#define SEG006 6
-#define SEG005 5
-#define SEG004 4
-#define SEG003 3
-#define SEG002 2
-#define SEG001 1
-#define SEG000 0
-
-#define LCDDR1 _SFR_MEM8(0xED)
-#define SEG015 7
-#define SEG014 6
-#define SEG013 5
-#define SEG012 4
-#define SEG011 3
-#define SEG010 2
-#define SEG009 1
-#define SEG008 0
-
-#define LCDDR2 _SFR_MEM8(0xEE)
-#define SEG023 7
-#define SEG022 6
-#define SEG021 5
-#define SEG020 4
-#define SEG019 3
-#define SEG018 2
-#define SEG017 1
-#define SEG016 0
-
-#define LCDDR3 _SFR_MEM8(0xEF)
-#define SEG024 0
-
-#define LCDDR5 _SFR_MEM8(0xF1)
-#define SEG107 7
-#define SEG106 6
-#define SEG105 5
-#define SEG104 4
-#define SEG103 3
-#define SEG102 2
-#define SEG101 1
-#define SEG100 0
-
-#define LCDDR6 _SFR_MEM8(0xF2)
-#define SEG115 7
-#define SEG114 6
-#define SEG113 5
-#define SEG112 4
-#define SEG111 3
-#define SEG110 2
-#define SEG109 1
-#define SEG108 0
-
-#define LCDDR7 _SFR_MEM8(0xF3)
-#define SEG123 7
-#define SEG122 6
-#define SEG121 5
-#define SEG120 4
-#define SEG119 3
-#define SEG118 2
-#define SEG117 1
-#define SEG116 0
-
-#define LCDDR8 _SFR_MEM8(0xF4)
-#define SEG124 0
-
-#define LCDDR10 _SFR_MEM8(0xF6)
-#define SEG207 7
-#define SEG206 6
-#define SEG205 5
-#define SEG204 4
-#define SEG203 3
-#define SEG202 2
-#define SEG201 1
-#define SEG200 0
-
-#define LCDDR11 _SFR_MEM8(0xF7)
-#define SEG215 7
-#define SEG214 6
-#define SEG213 5
-#define SEG212 4
-#define SEG211 3
-#define SEG210 2
-#define SEG209 1
-#define SEG208 0
-
-#define LCDDR12 _SFR_MEM8(0xF8)
-#define SEG223 7
-#define SEG222 6
-#define SEG221 5
-#define SEG220 4
-#define SEG219 3
-#define SEG218 2
-#define SEG217 1
-#define SEG216 0
-
-#define LCDDR13 _SFR_MEM8(0xF9)
-#define SEG224 0
-
-#define LCDDR15 _SFR_MEM8(0xFB)
-#define SEG307 7
-#define SEG306 6
-#define SEG305 5
-#define SEG304 4
-#define SEG303 3
-#define SEG302 2
-#define SEG301 1
-#define SEG300 0
-
-#define LCDDR16 _SFR_MEM8(0xFC)
-#define SEG315 7
-#define SEG314 6
-#define SEG313 5
-#define SEG312 4
-#define SEG311 3
-#define SEG310 2
-#define SEG309 1
-#define SEG308 0
-
-#define LCDDR17 _SFR_MEM8(0xFD)
-#define SEG323 7
-#define SEG322 6
-#define SEG321 5
-#define SEG320 4
-#define SEG319 3
-#define SEG318 2
-#define SEG317 1
-#define SEG316 0
-
-#define LCDDR18 _SFR_MEM8(0xFE)
-#define SEG324 0
-
-/* LCDDR0-18 */
-#define SEG24  0
-
-#define SEG23  7
-#define SEG22  6
-#define SEG21  5
-#define SEG20  4
-#define SEG19  3
-#define SEG18  2
-#define SEG17  1
-#define SEG16  0
-
-#define SEG15  7
-#define SEG14  6
-#define SEG13  5
-#define SEG12  4
-#define SEG11  3
-#define SEG10  2
-#define SEG9   1
-#define SEG8   0
-
-#define SEG7   7
-#define SEG6   6
-#define SEG5   5
-#define SEG4   4
-#define SEG3   3
-#define SEG2   2
-#define SEG1   1
-#define SEG0   0
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_USART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_USART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_USART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-#define _VECTORS_SIZE 92
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x4FF
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x05
-
-/** @} */
-
-#endif  /* _AVR_IOM169P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169pa.h b/cpukit/score/cpu/avr/avr/iom169pa.h
deleted file mode 100644
index 4f457db5dd..0000000000
--- a/cpukit/score/cpu/avr/avr/iom169pa.h
+++ /dev/null
@@ -1,1483 +0,0 @@
-/**
- * @file avr/iom169pa.h
- *
- * @brief Definitions for ATmega169PA
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom169pa.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_iom169pa ATmega169PA Defintions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_ATmega169PA_H_
-#define _AVR_ATmega169PA_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-#define PINE3 3
-#define PINE4 4
-#define PINE5 5
-#define PINE6 6
-#define PINE7 7
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-#define DDE3 3
-#define DDE4 4
-#define DDE5 5
-#define DDE6 6
-#define DDE7 7
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-#define PORTE3 3
-#define PORTE4 4
-#define PORTE5 5
-#define PORTE6 6
-#define PORTE7 7
-
-#define PINF _SFR_IO8(0x0F)
-#define PINF0 0
-#define PINF1 1
-#define PINF2 2
-#define PINF3 3
-#define PINF4 4
-#define PINF5 5
-#define PINF6 6
-#define PINF7 7
-
-#define DDRF _SFR_IO8(0x10)
-#define DDF0 0
-#define DDF1 1
-#define DDF2 2
-#define DDF3 3
-#define DDF4 4
-#define DDF5 5
-#define DDF6 6
-#define DDF7 7
-
-#define PORTF _SFR_IO8(0x11)
-#define PORTF0 0
-#define PORTF1 1
-#define PORTF2 2
-#define PORTF3 3
-#define PORTF4 4
-#define PORTF5 5
-#define PORTF6 6
-#define PORTF7 7
-
-#define PING _SFR_IO8(0x12)
-#define PING0 0
-#define PING1 1
-#define PING2 2
-#define PING3 3
-#define PING4 4
-#define PING5 5
-
-#define DDRG _SFR_IO8(0x13)
-#define DDG0 0
-#define DDG1 1
-#define DDG2 2
-#define DDG3 3
-#define DDG4 4
-#define DDG5 5
-
-#define PORTG _SFR_IO8(0x14)
-#define PORTG0 0
-#define PORTG1 1
-#define PORTG2 2
-#define PORTG3 3
-#define PORTG4 4
-#define PORTG5 5
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define PCIF0 4
-#define PCIF1 5
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define PCIE0 4
-#define PCIE1 5
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR310 0
-#define PSR2 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM01 3
-#define COM0A0 4
-#define COM0A1 5
-#define WGM00 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRLCD 4
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM21 3
-#define COM2A0 4
-#define COM2A1 5
-#define WGM20 6
-#define FOC2A 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A0 0
-#define OCR2A1 1
-#define OCR2A2 2
-#define OCR2A3 3
-#define OCR2A4 4
-#define OCR2A5 5
-#define OCR2A6 6
-#define OCR2A7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2UB 0
-#define OCR2UB 1
-#define TCN2UB 2
-#define AS2 3
-#define EXCLK 4
-
-#define USICR _SFR_MEM8(0xB8)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_MEM8(0xBA)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL0 6
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR00 0
-#define UDR01 1
-#define UDR02 2
-#define UDR03 3
-#define UDR04 4
-#define UDR05 5
-#define UDR06 6
-#define UDR07 7
-
-#define LCDCRA _SFR_MEM8(0xE4)
-#define LCDBL 0
-#define LCDCCD 1
-#define LCDBD 2
-#define LCDIE 3
-#define LCDIF 4
-#define LCDAB 6
-#define LCDEN 7
-
-#define LCDCRB _SFR_MEM8(0xE5)
-#define LCDPM0 0
-#define LCDPM1 1
-#define LCDPM2 2
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B 6
-#define LCDCS 7
-
-#define LCDFRR _SFR_MEM8(0xE6)
-#define LCDCD0 0
-#define LCDCD1 1
-#define LCDCD2 2
-#define LCDPS0 4
-#define LCDPS1 5
-#define LCDPS2 6
-
-#define LCDCCR _SFR_MEM8(0xE7)
-#define LCDCC0 0
-#define LCDCC1 1
-#define LCDCC2 2
-#define LCDCC3 3
-#define LCDMDT 4
-#define LCDDC0 5
-#define LCDDC1 6
-#define LCDDC2 7
-
-#define LCDDR0 _SFR_MEM8(0xEC)
-#define SEG000 0
-#define SEG001 1
-#define SEG002 2
-#define SEG003 3
-#define SEG004 4
-#define SEG005 5
-#define SEG006 6
-#define SEG007 7
-
-#define LCDDR1 _SFR_MEM8(0xED)
-#define SEG008 0
-#define SEG009 1
-#define SEG010 2
-#define SEG011 3
-#define SEG012 4
-#define SEG013 5
-#define SEG014 6
-#define SEG015 7
-
-#define LCDDR2 _SFR_MEM8(0xEE)
-#define SEG016 0
-#define SEG017 1
-#define SEG018 2
-#define SEG019 3
-#define SEG020 4
-#define SEG021 5
-#define SEG022 6
-#define SEG023 7
-
-#define LCDDR3 _SFR_MEM8(0xEF)
-#define SEG024 0
-
-#define LCDDR5 _SFR_MEM8(0xF1)
-#define SEG100 0
-#define SEG101 1
-#define SEG102 2
-#define SEG103 3
-#define SEG104 4
-#define SEG105 5
-#define SEG106 6
-#define SEG107 7
-
-#define LCDDR6 _SFR_MEM8(0xF2)
-#define SEG108 0
-#define SEG109 1
-#define SEG110 2
-#define SEG111 3
-#define SEG112 4
-#define SEG113 5
-#define SEG114 6
-#define SEG115 7
-
-#define LCDDR7 _SFR_MEM8(0xF3)
-#define SEG116 0
-#define SEG117 1
-#define SEG118 2
-#define SEG119 3
-#define SEG120 4
-#define SEG121 5
-#define SEG122 6
-#define SEG123 7
-
-#define LCDDR8 _SFR_MEM8(0xF4)
-#define SEG124 0
-
-#define LCDDR10 _SFR_MEM8(0xF6)
-#define SEG200 0
-#define SEG201 1
-#define SEG202 2
-#define SEG203 3
-#define SEG204 4
-#define SEG205 5
-#define SEG206 6
-#define SEG207 7
-
-#define LCDDR11 _SFR_MEM8(0xF7)
-#define SEG208 0
-#define SEG209 1
-#define SEG210 2
-#define SEG211 3
-#define SEG212 4
-#define SEG213 5
-#define SEG214 6
-#define SEG215 7
-
-#define LCDDR12 _SFR_MEM8(0xF8)
-#define SEG216 0
-#define SEG217 1
-#define SEG218 2
-#define SEG219 3
-#define SEG220 4
-#define SEG221 5
-#define SEG222 6
-#define SEG223 7
-
-#define LCDDR13 _SFR_MEM8(0xF9)
-#define SEG224 0
-
-#define LCDDR15 _SFR_MEM8(0xFB)
-#define SEG300 0
-#define SEG301 1
-#define SEG302 2
-#define SEG303 3
-#define SEG304 4
-#define SEG305 5
-#define SEG306 6
-#define SEG307 7
-
-#define LCDDR16 _SFR_MEM8(0xFC)
-#define SEG308 0
-#define SEG309 1
-#define SEG310 2
-#define SEG311 3
-#define SEG312 4
-#define SEG313 5
-#define SEG314 6
-#define SEG315 7
-
-#define LCDDR17 _SFR_MEM8(0xFD)
-#define SEG316 0
-#define SEG317 1
-#define SEG318 2
-#define SEG319 3
-#define SEG320 4
-#define SEG321 5
-#define SEG322 6
-#define SEG323 7
-
-#define LCDDR18 _SFR_MEM8(0xFE)
-#define SEG324 0
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  3
-#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
-#define TIMER2_COMP_vect_num  4
-#define TIMER2_COMP_vect      _VECTOR(4)  /* Timer/Counter2 Compare Match */
-#define TIMER2_OVF_vect_num  5
-#define TIMER2_OVF_vect      _VECTOR(5)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  6
-#define TIMER1_CAPT_vect      _VECTOR(6)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  7
-#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  8
-#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer/Counter Compare Match B */
-#define TIMER1_OVF_vect_num  9
-#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMP_vect_num  10
-#define TIMER0_COMP_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match */
-#define TIMER0_OVF_vect_num  11
-#define TIMER0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  12
-#define SPI_STC_vect      _VECTOR(12)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  13
-#define USART0_RX_vect      _VECTOR(13)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  14
-#define USART0_UDRE_vect      _VECTOR(14)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  15
-#define USART0_TX_vect      _VECTOR(15)  /* USART0, Tx Complete */
-#define USI_START_vect_num  16
-#define USI_START_vect      _VECTOR(16)  /* USI Start Condition */
-#define USI_OVERFLOW_vect_num  17
-#define USI_OVERFLOW_vect      _VECTOR(17)  /* USI Overflow */
-#define ANALOG_COMP_vect_num  18
-#define ANALOG_COMP_vect      _VECTOR(18)  /* Analog Comparator */
-#define ADC_vect_num  19
-#define ADC_vect      _VECTOR(19)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  20
-#define EE_READY_vect      _VECTOR(20)  /* EEPROM Ready */
-#define SPM_READY_vect_num  21
-#define SPM_READY_vect      _VECTOR(21)  /* Store Program Memory Read */
-#define LCD_vect_num  22
-#define LCD_vect      _VECTOR(22)  /* LCD Start of Frame */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (23 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(0)  /* Disable external reset */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(3)  /* Brown out detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x05
-
-
-/* Device Pin Definitions */
-#define RXD_DDR   DDRE
-#define RXD_PORT  PORTE
-#define RXD_PIN   PINE
-#define RXD_BIT   0
-
-#define PCINT0_DDR   DDRE
-#define PCINT0_PORT  PORTE
-#define PCINT0_PIN   PINE
-#define PCINT0_BIT   0
-
-#define TXD_DDR   DDRE
-#define TXD_PORT  PORTE
-#define TXD_PIN   PINE
-#define TXD_BIT   1
-
-#define PCINT1_DDR   DDRE
-#define PCINT1_PORT  PORTE
-#define PCINT1_PIN   PINE
-#define PCINT1_BIT   1
-
-#define XCK_DDR   DDRE
-#define XCK_PORT  PORTE
-#define XCK_PIN   PINE
-#define XCK_BIT   2
-
-#define AIN0_DDR   DDRE
-#define AIN0_PORT  PORTE
-#define AIN0_PIN   PINE
-#define AIN0_BIT   2
-
-#define PCINT2_DDR   DDRE
-#define PCINT2_PORT  PORTE
-#define PCINT2_PIN   PINE
-#define PCINT2_BIT   2
-
-#define AIN1_DDR   DDRE
-#define AIN1_PORT  PORTE
-#define AIN1_PIN   PINE
-#define AIN1_BIT   3
-
-#define PCINT3_DDR   DDRE
-#define PCINT3_PORT  PORTE
-#define PCINT3_PIN   PINE
-#define PCINT3_BIT   3
-
-#define USCK_DDR   DDRE
-#define USCK_PORT  PORTE
-#define USCK_PIN   PINE
-#define USCK_BIT   4
-
-#define SCL_DDR   DDRE
-#define SCL_PORT  PORTE
-#define SCL_PIN   PINE
-#define SCL_BIT   4
-
-#define PCINT4_DDR   DDRE
-#define PCINT4_PORT  PORTE
-#define PCINT4_PIN   PINE
-#define PCINT4_BIT   4
-
-#define DI_DDR   DDRE
-#define DI_PORT  PORTE
-#define DI_PIN   PINE
-#define DI_BIT   5
-
-#define SDA_DDR   DDRE
-#define SDA_PORT  PORTE
-#define SDA_PIN   PINE
-#define SDA_BIT   5
-
-#define PCINT5_DDR   DDRE
-#define PCINT5_PORT  PORTE
-#define PCINT5_PIN   PINE
-#define PCINT5_BIT   5
-
-#define DO_DDR   DDRE
-#define DO_PORT  PORTE
-#define DO_PIN   PINE
-#define DO_BIT   6
-
-#define PCINT6_DDR   DDRE
-#define PCINT6_PORT  PORTE
-#define PCINT6_PIN   PINE
-#define PCINT6_BIT   6
-
-#define PCINT7_DDR   DDRE
-#define PCINT7_PORT  PORTE
-#define PCINT7_PIN   PINE
-#define PCINT7_BIT   7
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   1
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   2
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   3
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define OC0_DDR   DDRB
-#define OC0_PORT  PORTB
-#define OC0_PIN   PINB
-#define OC0_BIT   4
-
-#define PCINT12_DDR   DDRB
-#define PCINT12_PORT  PORTB
-#define PCINT12_PIN   PINB
-#define PCINT12_BIT   4
-
-#define OC1A_DDR   DDRB
-#define OC1A_PORT  PORTB
-#define OC1A_PIN   PINB
-#define OC1A_BIT   5
-
-#define PCINT13_DDR   DDRB
-#define PCINT13_PORT  PORTB
-#define PCINT13_PIN   PINB
-#define PCINT13_BIT   5
-
-#define OC1B_DDR   DDRB
-#define OC1B_PORT  PORTB
-#define OC1B_PIN   PINB
-#define OC1B_BIT   6
-
-#define PCINT14_DDR   DDRB
-#define PCINT14_PORT  PORTB
-#define PCINT14_PIN   PINB
-#define PCINT14_BIT   6
-
-#define OC2_DDR   DDRB
-#define OC2_PORT  PORTB
-#define OC2_PIN   PINB
-#define OC2_BIT   7
-
-#define PCINT15_DDR   DDRB
-#define PCINT15_PORT  PORTB
-#define PCINT15_PIN   PINB
-#define PCINT15_BIT   7
-
-#define T1_DDR   DDRG
-#define T1_PORT  PORTG
-#define T1_PIN   PING
-#define T1_BIT   3
-
-#define SEG24_DDR   DDRG
-#define SEG24_PORT  PORTG
-#define SEG24_PIN   PING
-#define SEG24_BIT   3
-
-#define T0_DDR   DDRG
-#define T0_PORT  PORTG
-#define T0_PIN   PING
-#define T0_BIT   4
-
-#define SEG23_DDR   DDRG
-#define SEG23_PORT  PORTG
-#define SEG23_PIN   PING
-#define SEG23_BIT   4
-
-#define ICP/SEG22_DDR   DDRD
-#define ICP/SEG22_PORT  PORTD
-#define ICP/SEG22_PIN   PIND
-#define ICP/SEG22_BIT   0
-
-#define INT0/SEG21_DDR   DDRD
-#define INT0/SEG21_PORT  PORTD
-#define INT0/SEG21_PIN   PIND
-#define INT0/SEG21_BIT   1
-
-#define SEG20_DDR   DDRD
-#define SEG20_PORT  PORTD
-#define SEG20_PIN   PIND
-#define SEG20_BIT   2
-
-#define SEG19_DDR   DDRD
-#define SEG19_PORT  PORTD
-#define SEG19_PIN   PIND
-#define SEG19_BIT   3
-
-#define SEG18_DDR   DDRD
-#define SEG18_PORT  PORTD
-#define SEG18_PIN   PIND
-#define SEG18_BIT   4
-
-#define SEG17_DDR   DDRD
-#define SEG17_PORT  PORTD
-#define SEG17_PIN   PIND
-#define SEG17_BIT   5
-
-#define SEG16_DDR   DDRD
-#define SEG16_PORT  PORTD
-#define SEG16_PIN   PIND
-#define SEG16_BIT   6
-
-#define SEG15_DDR   DDRD
-#define SEG15_PORT  PORTD
-#define SEG15_PIN   PIND
-#define SEG15_BIT   7
-
-#define SEG14_DDR   DDRG
-#define SEG14_PORT  PORTG
-#define SEG14_PIN   PING
-#define SEG14_BIT   0
-
-#define SEG13_DDR   DDRG
-#define SEG13_PORT  PORTG
-#define SEG13_PIN   PING
-#define SEG13_BIT   1
-
-#define SEG12_DDR   DDRC
-#define SEG12_PORT  PORTC
-#define SEG12_PIN   PINC
-#define SEG12_BIT   0
-
-#define SEG11_DDR   DDRC
-#define SEG11_PORT  PORTC
-#define SEG11_PIN   PINC
-#define SEG11_BIT   1
-
-#define SEG10_DDR   DDRC
-#define SEG10_PORT  PORTC
-#define SEG10_PIN   PINC
-#define SEG10_BIT   2
-
-#define SEG9_DDR   DDRC
-#define SEG9_PORT  PORTC
-#define SEG9_PIN   PINC
-#define SEG9_BIT   3
-
-#define SEG8_DDR   DDRC
-#define SEG8_PORT  PORTC
-#define SEG8_PIN   PINC
-#define SEG8_BIT   4
-
-#define SEG7_DDR   DDRC
-#define SEG7_PORT  PORTC
-#define SEG7_PIN   PINC
-#define SEG7_BIT   5
-
-#define SEG6_DDR   DDRC
-#define SEG6_PORT  PORTC
-#define SEG6_PIN   PINC
-#define SEG6_BIT   6
-
-#define SEG5_DDR   DDRC
-#define SEG5_PORT  PORTC
-#define SEG5_PIN   PINC
-#define SEG5_BIT   7
-
-#define SEG4_DDR   DDRG
-#define SEG4_PORT  PORTG
-#define SEG4_PIN   PING
-#define SEG4_BIT   2
-
-#define SEG3_DDR   DDRA
-#define SEG3_PORT  PORTA
-#define SEG3_PIN   PINA
-#define SEG3_BIT   7
-
-#define SEG2_DDR   DDRA
-#define SEG2_PORT  PORTA
-#define SEG2_PIN   PINA
-#define SEG2_BIT   6
-
-#define SEG1_DDR   DDRA
-#define SEG1_PORT  PORTA
-#define SEG1_PIN   PINA
-#define SEG1_BIT   5
-
-#define SEG0_DDR   DDRA
-#define SEG0_PORT  PORTA
-#define SEG0_PIN   PINA
-#define SEG0_BIT   4
-
-#define COM3_DDR   DDRA
-#define COM3_PORT  PORTA
-#define COM3_PIN   PINA
-#define COM3_BIT   3
-
-#define COM2_DDR   DDRA
-#define COM2_PORT  PORTA
-#define COM2_PIN   PINA
-#define COM2_BIT   2
-
-#define COM1_DDR   DDRA
-#define COM1_PORT  PORTA
-#define COM1_PIN   PINA
-#define COM1_BIT   1
-
-#define COM0_DDR   DDRA
-#define COM0_PORT  PORTA
-#define COM0_PIN   PINA
-#define COM0_BIT   0
-
-#define ADC7_DDR   DDRF
-#define ADC7_PORT  PORTF
-#define ADC7_PIN   PINF
-#define ADC7_BIT   7
-
-#define ADC6_DDR   DDRF
-#define ADC6_PORT  PORTF
-#define ADC6_PIN   PINF
-#define ADC6_BIT   6
-
-#define TD0_DDR   DDRF
-#define TD0_PORT  PORTF
-#define TD0_PIN   PINF
-#define TD0_BIT   6
-
-#define ADC5_DDR   DDRF
-#define ADC5_PORT  PORTF
-#define ADC5_PIN   PINF
-#define ADC5_BIT   5
-
-#define ADC4_DDR   DDRF
-#define ADC4_PORT  PORTF
-#define ADC4_PIN   PINF
-#define ADC4_BIT   4
-
-#define ADC3_DDR   DDRF
-#define ADC3_PORT  PORTF
-#define ADC3_PIN   PINF
-#define ADC3_BIT   3
-
-#define ADC2_DDR   DDRF
-#define ADC2_PORT  PORTF
-#define ADC2_PIN   PINF
-#define ADC2_BIT   2
-
-#define ADC1_DDR   DDRF
-#define ADC1_PORT  PORTF
-#define ADC1_PIN   PINF
-#define ADC1_BIT   1
-
-#define ADC0_DDR   DDRF
-#define ADC0_PORT  PORTF
-#define ADC0_PIN   PINF
-#define ADC0_BIT   0
-
-/** @} */
-#endif /* _AVR_ATmega169PA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16a.h b/cpukit/score/cpu/avr/avr/iom16a.h
deleted file mode 100644
index ddfb220b99..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16a.h
+++ /dev/null
@@ -1,937 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16a.h - definitions for ATmega16A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega16A_H_
-#define _AVR_ATmega16A_H_ 1
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define TWBR _SFR_IO8(0x00)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_IO8(0x01)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_IO8(0x02)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_IO8(0x03)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSR _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define UBRRL _SFR_IO8(0x09)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UCSRB _SFR_IO8(0x0A)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRA _SFR_IO8(0x0B)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UDR _SFR_IO8(0x0C)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define SPCR _SFR_IO8(0x0D)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x0E)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x0F)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define PIND _SFR_IO8(0x10)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x11)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x12)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINC _SFR_IO8(0x13)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x14)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x15)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define UBRRH _SFR_IO8(0x20)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UCSRC _SFR_IO8(0x20)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL 6
-#define URSEL 7
-
-#define WDTCR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDTOE 4
-
-#define ASSR _SFR_IO8(0x22)
-#define TCR2UB 0
-#define OCR2UB 1
-#define TCN2UB 2
-#define AS2 3
-
-#define OCR2 _SFR_IO8(0x23)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define TCNT2 _SFR_IO8(0x24)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define TCCR2 _SFR_IO8(0x25)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM21 3
-#define COM20 4
-#define COM21 5
-#define WGM20 6
-#define FOC2 7
-
-#define ICR1 _SFR_IO16(0x26)
-
-#define ICR1L _SFR_IO8(0x26)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_IO8(0x27)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1B _SFR_IO16(0x28)
-
-#define OCR1BL _SFR_IO8(0x28)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_IO8(0x29)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1A _SFR_IO16(0x2A)
-
-#define OCR1AL _SFR_IO8(0x2A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_IO8(0x2B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCNT1 _SFR_IO16(0x2C)
-
-#define TCNT1L _SFR_IO8(0x2C)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x2D)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define TCCR1B _SFR_IO8(0x2E)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1A _SFR_IO8(0x2F)
-#define WGM10 0
-#define WGM11 1
-#define FOC1B 2
-#define FOC1A 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define SFIOR _SFR_IO8(0x30)
-#define PSR10 0
-#define PSR2 1
-#define PUD 2
-#define ACME 3
-#define ADTS0 5
-#define ADTS1 6
-#define ADTS2 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define TCNT0 _SFR_IO8(0x32)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0 _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM01 3
-#define COM00 4
-#define COM01 5
-#define WGM00 6
-#define FOC0 7
-
-#define MCUCSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-#define ISC2 6
-#define JTD 7
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define SM0 4
-#define SM1 5
-#define SE 6
-#define SM2 7
-
-#define TWCR _SFR_IO8(0x36)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define TIFR _SFR_IO8(0x38)
-#define TOV0 0
-#define OCF0 1
-#define TOV1 2
-#define OCF1B 3
-#define OCF1A 4
-#define ICF1 5
-#define TOV2 6
-#define OCF2 7
-
-#define TIMSK _SFR_IO8(0x39)
-#define TOIE0 0
-#define OCIE0 1
-#define TOIE1 2
-#define OCIE1B 3
-#define OCIE1A 4
-#define TICIE1 5
-#define TOIE2 6
-#define OCIE2 7
-
-#define GIFR _SFR_IO8(0x3A)
-#define INTF2 5
-#define INTF0 6
-#define INTF1 7
-
-#define GICR _SFR_IO8(0x3B)
-#define IVCE 0
-#define IVSEL 1
-#define INT2 5
-#define INT0 6
-#define INT1 7
-
-#define OCR0 _SFR_IO8(0x3C)
-#define OCR0_0 0
-#define OCR0_1 1
-#define OCR0_2 2
-#define OCR0_3 3
-#define OCR0_4 4
-#define OCR0_5 5
-#define OCR0_6 6
-#define OCR0_7 7
-
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define TIMER2_COMP_vect_num  3
-#define TIMER2_COMP_vect      _VECTOR(3)  /* Timer/Counter2 Compare Match */
-#define TIMER2_OVF_vect_num  4
-#define TIMER2_OVF_vect      _VECTOR(4)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  5
-#define TIMER1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  6
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect      _VECTOR(6)  
-#define TIMER1_COMPB_vect_num  7
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect      _VECTOR(7)  
-#define TIMER1_OVF_vect_num  8
-#define TIMER1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  9
-#define TIMER0_OVF_vect      _VECTOR(9)  /* Timer/Counter0 Overflow */
-#define SPISTC_vect_num  10
-#define SPISTC_vect      _VECTOR(10)  /* Serial Transfer Complete */
-#define USARTRXC_vect_num  11
-#define USARTRXC_vect      _VECTOR(11)  /* USART, Rx Complete */
-#define USARTUDRE_vect_num  12
-#define USARTUDRE_vect      _VECTOR(12)  /* USART Data Register Empty */
-#define USARTTXC_vect_num  13
-#define USARTTXC_vect      _VECTOR(13)  /* USART, Tx Complete */
-#define ADC_vect_num  14
-#define ADC_vect      _VECTOR(14)  /* ADC Conversion Complete */
-#define EE_RDY_vect_num  15
-#define EE_RDY_vect      _VECTOR(15)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  16
-#define ANA_COMP_vect      _VECTOR(16)  /* Analog Comparator */
-#define TWI_vect_num  17
-#define TWI_vect      _VECTOR(17)  /* 2-wire Serial Interface */
-#define INT2_vect_num  18
-#define INT2_vect      _VECTOR(18)  /* External Interrupt Request 2 */
-#define TIMER0_COMP_vect_num  19
-#define TIMER0_COMP_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match */
-#define SPM_RDY_vect_num  20
-#define SPM_RDY_vect      _VECTOR(20)  /* Store Program Memory Ready */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_BODEN  (unsigned char)~_BV(6)  /* Brown out detector enable */
-/* Brown out detector trigger level */
-#define FUSE_BODLEVEL  (unsigned char)~_BV(7)  
-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
-                       FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-/* EEPROM memory is preserved through chip erase */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  
-#define FUSE_CKOPT  (unsigned char)~_BV(4)  /* Oscillator Options */
-/* Enable Serial programming and Data Downloading */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x03
-/** @} */
-
-/**
- * @name Device Pin Definitions
- * 
- */
-/**@{**/
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   5
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   6
-
-#define PB7_SCK_DDR   DDRB7_SCK
-#define PB7_SCK_PORT  PORTB7_SCK
-#define PB7_SCK_PIN   PINB7_SCK
-#define PB7_SCK_BIT   7_SCK
-
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define OC1B_DDR   DDRD
-#define OC1B_PORT  PORTD
-#define OC1B_PIN   PIND
-#define OC1B_BIT   4
-
-#define OC1A_DDR   DDRD
-#define OC1A_PORT  PORTD
-#define OC1A_PIN   PIND
-#define OC1A_BIT   5
-
-#define ICP_DDR   DDRD
-#define ICP_PORT  PORTD
-#define ICP_PIN   PIND
-#define ICP_BIT   6
-
-#define OC2_DDR   DDRD
-#define OC2_PORT  PORTD
-#define OC2_PIN   PIND
-#define OC2_BIT   7
-
-#define SCL_DDR   DDRC
-#define SCL_PORT  PORTC
-#define SCL_PIN   PINC
-#define SCL_BIT   0
-
-#define SDA_DDR   DDRC
-#define SDA_PORT  PORTC
-#define SDA_PIN   PINC
-#define SDA_BIT   1
-
-#define PC3_DDR   DDRC
-#define PC3_PORT  PORTC
-#define PC3_PIN   PINC
-#define PC3_BIT   3
-
-#define PC4_DDR   DDRC
-#define PC4_PORT  PORTC
-#define PC4_PIN   PINC
-#define PC4_BIT   4
-
-#define PC5_DDR   DDRC
-#define PC5_PORT  PORTC
-#define PC5_PIN   PINC
-#define PC5_BIT   5
-
-#define ADC7_DDR   DDRA
-#define ADC7_PORT  PORTA
-#define ADC7_PIN   PINA
-#define ADC7_BIT   7
-
-#define ADC6_DDR   DDRA
-#define ADC6_PORT  PORTA
-#define ADC6_PIN   PINA
-#define ADC6_BIT   6
-
-#define ADc5_DDR   DDRA
-#define ADc5_PORT  PORTA
-#define ADc5_PIN   PINA
-#define ADc5_BIT   5
-
-#define ADC4_DDR   DDRA
-#define ADC4_PORT  PORTA
-#define ADC4_PIN   PINA
-#define ADC4_BIT   4
-
-#define ADC3_DDR   DDRA
-#define ADC3_PORT  PORTA
-#define ADC3_PIN   PINA
-#define ADC3_BIT   3
-
-#define ADC2_DDR   DDRA
-#define ADC2_PORT  PORTA
-#define ADC2_PIN   PINA
-#define ADC2_BIT   2
-
-#define ADC1_DDR   DDRA
-#define ADC1_PORT  PORTA
-#define ADC1_PIN   PINA
-#define ADC1_BIT   1
-
-#define ADC0_DDR   DDRA
-#define ADC0_PORT  PORTA
-#define ADC0_PIN   PINA
-#define ADC0_BIT   0
-
-#define T0_DDR   DDRB
-#define T0_PORT  PORTB
-#define T0_PIN   PINB
-#define T0_BIT   0
-
-#define T1_DDR   DDRB
-#define T1_PORT  PORTB
-#define T1_PIN   PINB
-#define T1_BIT   1
-
-#define AIN0_DDR   DDRB
-#define AIN0_PORT  PORTB
-#define AIN0_PIN   PINB
-#define AIN0_BIT   2
-
-#define AIN1_DDR   DDRB
-#define AIN1_PORT  PORTB
-#define AIN1_PIN   PINB
-#define AIN1_BIT   3
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   4
-/** @} */
-
-#endif /* _AVR_ATmega16A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16hva.h b/cpukit/score/cpu/avr/avr/iom16hva.h
deleted file mode 100644
index 7dcad90e37..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16hva.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega16HVA
- */
-
-/* Copyright (c) 2007, Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iom16hva.h - definitions for ATmega16HVA.  */
-
-#ifndef _AVR_IOM16HVA_H_
-#define _AVR_IOM16HVA_H_ 1
-
-#include <avr/iomxxhva.h>
-
-/**
- * @defgroup AvrDef_iom16hva ATmega16HVA Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND      0x2FF
-#define XRAMEND     RAMEND
-#define E2END       0xFF
-#define E2PAGESIZE  4
-#define FLASHEND    0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SUT0        (unsigned char)~_BV(0)
-#define FUSE_SUT1        (unsigned char)~_BV(1)
-#define FUSE_SUT2        (unsigned char)~_BV(2)
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(3)
-#define FUSE_DWEN        (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_EESAVE      (unsigned char)~_BV(6)
-#define FUSE_WDTON       (unsigned char)~_BV(7)
-#define FUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0C
-
-/** @} */
-
-#endif /* _AVR_IOM16HVA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16hva2.h b/cpukit/score/cpu/avr/avr/iom16hva2.h
deleted file mode 100644
index bca3d20d87..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16hva2.h
+++ /dev/null
@@ -1,881 +0,0 @@
-/**
- * @file avr/iom16hva2.h
- *
- * @brief Definitions for ATmega16HVA2
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16hva2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega16HVA2_H_
-#define _AVR_ATmega16HVA2_H_ 1
-
-/**
- *  @defgroup Avr_iom16hva2 ATmega16HVA2 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-#define ICF0 3
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 3
-
-#define OSICSR _SFR_IO8(0x17)
-#define OSIEN 0
-#define OSIST 1
-#define OSISEL0 4
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define ICS0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-
-#define TCNT0 _SFR_IO16(0x26)
-
-#define TCNT0L _SFR_IO8(0x26)
-#define TCNT0L0 0
-#define TCNT0L1 1
-#define TCNT0L2 2
-#define TCNT0L3 3
-#define TCNT0L4 4
-#define TCNT0L5 5
-#define TCNT0L6 6
-#define TCNT0L7 7
-
-#define TCNT0H _SFR_IO8(0x27)
-#define TCNT0H0 0
-#define TCNT0H1 1
-#define TCNT0H2 2
-#define TCNT0H3 3
-#define TCNT0H4 4
-#define TCNT0H5 5
-#define TCNT0H6 6
-#define TCNT0H7 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define OCR0B _SFR_IO8(0x29)
-#define OCR0B0 0
-#define OCR0B1 1
-#define OCR0B2 2
-#define OCR0B3 3
-#define OCR0B4 4
-#define OCR0B5 5
-#define OCR0B6 6
-#define OCR0B7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BODRF 2
-#define WDRF 3
-#define OCDRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define CKOE 5
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-#define SIGRD 5
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRVADC 0
-#define PRTIM0 1
-#define PRTIM1 2
-#define PRSPI 3
-#define PRVRM 5
-
-#define FOSCCAL _SFR_MEM8(0x66)
-#define FCAL0 0
-#define FCAL1 1
-#define FCAL2 2
-#define FCAL3 3
-#define FCAL4 4
-#define FCAL5 5
-#define FCAL6 6
-#define FCAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-#define ICIE0 3
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 3
-
-#define VADC _SFR_MEM16(0x78)
-
-#define VADCL _SFR_MEM8(0x78)
-#define VADC0 0
-#define VADC1 1
-#define VADC2 2
-#define VADC3 3
-#define VADC4 4
-#define VADC5 5
-#define VADC6 6
-#define VADC7 7
-
-#define VADCH _SFR_MEM8(0x79)
-#define VADC8 0
-#define VADC9 1
-#define VADC10 2
-#define VADC11 3
-
-#define VADCSR _SFR_MEM8(0x7A)
-#define VADCCIE 0
-#define VADCCIF 1
-#define VADSC 2
-#define VADEN 3
-
-#define VADMUX _SFR_MEM8(0x7C)
-#define VADMUX0 0
-#define VADMUX1 1
-#define VADMUX2 2
-#define VADMUX3 3
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define PA0DID 0
-#define PA1DID 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define ICS1 3
-#define ICES1 4
-#define ICNC1 5
-#define ICEN1 6
-#define TCW1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR1A _SFR_MEM8(0x88)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define OCR1B _SFR_MEM8(0x89)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define ROCR _SFR_MEM8(0xC8)
-#define ROCWIE 0
-#define ROCWIF 1
-#define ROCS 7
-
-#define BGCCR _SFR_MEM8(0xD0)
-#define BGCC0 0
-#define BGCC1 1
-#define BGCC2 2
-#define BGCC3 3
-#define BGCC4 4
-#define BGCC5 5
-#define BGD 7
-
-#define BGCRR _SFR_MEM8(0xD1)
-#define BGCR0 0
-#define BGCR1 1
-#define BGCR2 2
-#define BGCR3 3
-#define BGCR4 4
-#define BGCR5 5
-#define BGCR6 6
-#define BGCR7 7
-
-#define CADAC0 _SFR_MEM8(0xE0)
-#define CADAC00 0
-#define CADAC01 1
-#define CADAC02 2
-#define CADAC03 3
-#define CADAC04 4
-#define CADAC05 5
-#define CADAC06 6
-#define CADAC07 7
-
-#define CADAC1 _SFR_MEM8(0xE1)
-#define CADAC08 0
-#define CADAC09 1
-#define CADAC10 2
-#define CADAC11 3
-#define CADAC12 4
-#define CADAC13 5
-#define CADAC14 6
-#define CADAC15 7
-
-#define CADAC2 _SFR_MEM8(0xE2)
-#define CADAC16 0
-#define CADAC17 1
-#define CADAC18 2
-#define CADAC19 3
-#define CADAC20 4
-#define CADAC21 5
-#define CADAC22 6
-#define CADAC23 7
-
-#define CADAC3 _SFR_MEM8(0xE3)
-#define CADAC24 0
-#define CADAC25 1
-#define CADAC26 2
-#define CADAC27 3
-#define CADAC28 4
-#define CADAC29 5
-#define CADAC30 6
-#define CADAC31 7
-
-#define CADCSRA _SFR_MEM8(0xE4)
-#define CADSE 0
-#define CADSI0 1
-#define CADSI1 2
-#define CADAS0 3
-#define CADAS1 4
-#define CADUB 5
-#define CADPOL 6
-#define CADEN 7
-
-#define CADCSRB _SFR_MEM8(0xE5)
-#define CADICIF 0
-#define CADRCIF 1
-#define CADACIF 2
-#define CADICIE 4
-#define CADRCIE 5
-#define CADACIE 6
-
-#define CADRC _SFR_MEM8(0xE6)
-#define CADRC0 0
-#define CADRC1 1
-#define CADRC2 2
-#define CADRC3 3
-#define CADRC4 4
-#define CADRC5 5
-#define CADRC6 6
-#define CADRC7 7
-
-#define CADIC _SFR_MEM16(0xE8)
-
-#define CADICL _SFR_MEM8(0xE8)
-#define CADICL0 0
-#define CADICL1 1
-#define CADICL2 2
-#define CADICL3 3
-#define CADICL4 4
-#define CADICL5 5
-#define CADICL6 6
-#define CADICL7 7
-
-#define CADICH _SFR_MEM8(0xE9)
-#define CADICH0 0
-#define CADICH1 1
-#define CADICH2 2
-#define CADICH3 3
-#define CADICH4 4
-#define CADICH5 5
-#define CADICH6 6
-#define CADICH7 7
-
-#define FCSR _SFR_MEM8(0xF0)
-#define CFE 0
-#define DFE 1
-#define CPS 2
-#define DUVRD 3
-
-#define BPIMSK _SFR_MEM8(0xF2)
-#define CHCIE 0
-#define DHCIE 1
-#define COCIE 2
-#define DOCIE 3
-#define SCIE 4
-
-#define BPIFR _SFR_MEM8(0xF3)
-#define CHCIF 0
-#define DHCIF 1
-#define COCIF 2
-#define DOCIF 3
-#define SCIF 4
-
-#define BPSCD _SFR_MEM8(0xF5)
-#define SCDL0 0
-#define SCDL1 1
-#define SCDL2 2
-#define SCDL3 3
-#define SCDL4 4
-#define SCDL5 5
-#define SCDL6 6
-#define SCDL7 7
-
-#define BPDOCD _SFR_MEM8(0xF6)
-#define DOCDL0 0
-#define DOCDL1 1
-#define DOCDL2 2
-#define DOCDL3 3
-#define DOCDL4 4
-#define DOCDL5 5
-#define DOCDL6 6
-#define DOCDL7 7
-
-#define BPCOCD _SFR_MEM8(0xF7)
-#define COCDL0 0
-#define COCDL1 1
-#define COCDL2 2
-#define COCDL3 3
-#define COCDL4 4
-#define COCDL5 5
-#define COCDL6 6
-#define COCDL7 7
-
-#define BPDHCD _SFR_MEM8(0xF8)
-#define DHCDL0 0
-#define DHCDL1 1
-#define DHCDL2 2
-#define DHCDL3 3
-#define DHCDL4 4
-#define DHCDL5 5
-#define DHCDL6 6
-#define DHCDL7 7
-
-#define BPCHCD _SFR_MEM8(0xF9)
-#define CHCDL0 0
-#define CHCDL1 1
-#define CHCDL2 2
-#define CHCDL3 3
-#define CHCDL4 4
-#define CHCDL5 5
-#define CHCDL6 6
-#define CHCDL7 7
-
-#define BPSCTR _SFR_MEM8(0xFA)
-#define SCPT0 0
-#define SCPT1 1
-#define SCPT2 2
-#define SCPT3 3
-#define SCPT4 4
-#define SCPT5 5
-#define SCPT6 6
-
-#define BPOCTR _SFR_MEM8(0xFB)
-#define OCPT0 0
-#define OCPT1 1
-#define OCPT2 2
-#define OCPT3 3
-#define OCPT4 4
-#define OCPT5 5
-
-#define BPHCTR _SFR_MEM8(0xFC)
-#define HCPT0 0
-#define HCPT1 1
-#define HCPT2 2
-#define HCPT3 3
-#define HCPT4 4
-#define HCPT5 5
-
-#define BPCR _SFR_MEM8(0xFD)
-#define CHCD 0
-#define DHCD 1
-#define COCD 2
-#define DOCD 3
-#define SCD 4
-#define PRMD 7
-
-#define BPPLR _SFR_MEM8(0xFE)
-#define BPPL 0
-#define BPPLE 1
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define BPINT_vect_num  1
-#define BPINT_vect      _VECTOR(1)  /* Battery Protection Interrupt */
-#define VREGMON_vect_num  2
-#define VREGMON_vect      _VECTOR(2)  /* Voltage regulator monitor interrupt */
-#define INT0_vect_num  3
-#define INT0_vect      _VECTOR(3)  /* External Interrupt Request 0 */
-#define INT1_vect_num  4
-#define INT1_vect      _VECTOR(4)  /* External Interrupt Request 1 */
-#define INT2_vect_num  5
-#define INT2_vect      _VECTOR(5)  /* External Interrupt Request 2 */
-#define PCINT0_vect_num  6
-#define PCINT0_vect      _VECTOR(6)  /* Pin Change Interrupt Request 0 */
-#define WDT_vect_num  7
-#define WDT_vect      _VECTOR(7)  /* Watchdog Timeout Interrupt */
-#define TIMER1_IC_vect_num  8
-#define TIMER1_IC_vect      _VECTOR(8)  /* Timer 1 Input capture */
-#define TIMER1_COMPA_vect_num  9
-#define TIMER1_COMPA_vect      _VECTOR(9)  /* Timer 1 Compare Match A */
-#define TIMER1_COMPB_vect_num  10
-#define TIMER1_COMPB_vect      _VECTOR(10)  /* Timer 1 Compare Match B */
-#define TIMER1_OVF_vect_num  11
-#define TIMER1_OVF_vect      _VECTOR(11)  /* Timer 1 overflow */
-#define TIMER0_IC_vect_num  12
-#define TIMER0_IC_vect      _VECTOR(12)  /* Timer 0 Input Capture */
-#define TIMER0_COMPA_vect_num  13
-#define TIMER0_COMPA_vect      _VECTOR(13)  /* Timer 0 Comapre Match A */
-#define TIMER0_COMPB_vect_num  14
-#define TIMER0_COMPB_vect      _VECTOR(14)  /* Timer 0 Compare Match B */
-#define TIMER0_OVF_vect_num  15
-#define TIMER0_OVF_vect      _VECTOR(15)  /* Timer 0 Overflow */
-#define SPI;STC_vect_num  16
-#define SPI;STC_vect      _VECTOR(16)  /* SPI Serial transfer complete */
-#define VADC_vect_num  17
-#define VADC_vect      _VECTOR(17)  /* Voltage ADC Conversion Complete */
-#define CCADC_CONV_vect_num  18
-#define CCADC_CONV_vect      _VECTOR(18)  /* Coulomb Counter ADC Conversion Complete */
-#define CCADC_REG_CUR_vect_num  19
-#define CCADC_REG_CUR_vect      _VECTOR(19)  /* Coloumb Counter ADC Regular Current */
-#define CCADC_ACC_vect_num  20
-#define CCADC_ACC_vect      _VECTOR(20)  /* Coloumb Counter ADC Accumulator */
-#define EE_READY_vect_num  21
-#define EE_READY_vect      _VECTOR(21)  /* EEPROM Ready */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (22 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (NA)
-#define XRAMEND      (RAMEND)
-#define E2END        (0xFF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_SUT0  (unsigned char)~_BV(0)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(1)  /* Select start-up time */
-#define FUSE_SUT2  (unsigned char)~_BV(2)  /* Select start-up time */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(3)  /* Enable self programming */
-#define FUSE_DWEN  (unsigned char)~_BV(4)  /* Enable debugWIRE */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
-#define LFUSE_DEFAULT (FUSE_SPIEN)
-
-/* High Fuse Byte */
-#define FUSE_OSCSEL0  (unsigned char)~_BV(0)  /* Oscillator Select 0 */
-#define FUSE_OSCSEL1  (unsigned char)~_BV(1)  /* Oscillator Select 1 */
-#define FUSE_COMPMODE  (unsigned char)~_BV(2)  /* Compatibility mode */
-#define HFUSE_DEFAULT (FUSE_COMPMODE & FUSE_OSCSEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0E
-
-
-/* Device Pin Definitions */
-#define PV2_DDR   DDRV
-#define PV2_PORT  PORTV
-#define PV2_PIN   PINV
-#define PV2_BIT   2
-
-#define PV1_DDR   DDRV
-#define PV1_PORT  PORTV
-#define PV1_PIN   PINV
-#define PV1_BIT   1
-
-#define NV_DDR   DDRNV
-#define NV_PORT  PORTNV
-#define NV_PIN   PINNV
-#define NV_BIT   NV
-
-#define VFET_DDR   DDRVFET
-#define VFET_PORT  PORTVFET
-#define VFET_PIN   PINVFET
-#define VFET_BIT   VFET
-
-#define CF1P_DDR   DDRCF1P
-#define CF1P_PORT  PORTCF1P
-#define CF1P_PIN   PINCF1P
-#define CF1P_BIT   CF1P
-
-#define CF1N_DDR   DDRCF1N
-#define CF1N_PORT  PORTCF1N
-#define CF1N_PIN   PINCF1N
-#define CF1N_BIT   CF1N
-
-#define CF2P_DDR   DDRCF2P
-#define CF2P_PORT  PORTCF2P
-#define CF2P_PIN   PINCF2P
-#define CF2P_BIT   CF2P
-
-#define CF2N_DDR   DDRCF2N
-#define CF2N_PORT  PORTCF2N
-#define CF2N_PIN   PINCF2N
-#define CF2N_BIT   CF2N
-
-#define VREG_DDR   DDRVREG
-#define VREG_PORT  PORTVREG
-#define VREG_PIN   PINVREG
-#define VREG_BIT   VREG
-
-#define VREF_DDR   DDRVREF
-#define VREF_PORT  PORTVREF
-#define VREF_PIN   PINVREF
-#define VREF_BIT   VREF
-
-#define VREFGND_DDR   DDRVREFGND
-#define VREFGND_PORT  PORTVREFGND
-#define VREFGND_PIN   PINVREFGND
-#define VREFGND_BIT   VREFGND
-
-#define PI_DDR   DDRI
-#define PI_PORT  PORTI
-#define PI_PIN   PINI
-#define PI_BIT
-
-#define NI_DDR   DDRNI
-#define NI_PORT  PORTNI
-#define NI_PIN   PINNI
-#define NI_BIT   NI
-
-#define PA0_DDR   DDRA
-#define PA0_PORT  PORTA
-#define PA0_PIN   PINA
-#define PA0_BIT   0
-
-#define PA1_DDR   DDRA
-#define PA1_PORT  PORTA
-#define PA1_PIN   PINA
-#define PA1_BIT   1
-
-#define PA2_DDR   DDRA
-#define PA2_PORT  PORTA
-#define PA2_PIN   PINA
-#define PA2_BIT   2
-
-#define PB0_DDR   DDRB
-#define PB0_PORT  PORTB
-#define PB0_PIN   PINB
-#define PB0_BIT   0
-
-#define PB1_DDR   DDRB
-#define PB1_PORT  PORTB
-#define PB1_PIN   PINB
-#define PB1_BIT   1
-
-#define PB2_DDR   DDRB
-#define PB2_PORT  PORTB
-#define PB2_PIN   PINB
-#define PB2_BIT   2
-
-#define PB3_DDR   DDRB
-#define PB3_PORT  PORTB
-#define PB3_PIN   PINB
-#define PB3_BIT   3
-
-#define PC0_DDR   DDRC
-#define PC0_PORT  PORTC
-#define PC0_PIN   PINC
-#define PC0_BIT   0
-
-#define BATT_DDR   DDRBATT
-#define BATT_PORT  PORTBATT
-#define BATT_PIN   PINBATT
-#define BATT_BIT   BATT
-
-#define OC_DDR   DDROC
-#define OC_PORT  PORTOC
-#define OC_PIN   PINOC
-#define OC_BIT   OC
-
-/**@}*/
-#endif /* _AVR_ATmega16HVA2_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16hvb.h b/cpukit/score/cpu/avr/avr/iom16hvb.h
deleted file mode 100644
index ad6720eb45..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16hvb.h
+++ /dev/null
@@ -1,1049 +0,0 @@
-/**
- * @file avr/iom16hvb.h
- *
- * @brief Definitions for ATmega16HVB
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16hvb.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega16HVB_H_
-#define _AVR_ATmega16HVB_H_ 1
-
-/**
- *  @defgroup Avr_iom16hvb ATmega16HVB Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-#define ICF0 3
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 3
-
-#define OSICSR _SFR_IO8(0x17)
-#define OSIEN 0
-#define OSIST 1
-#define OSISEL0 4
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define ICS0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-
-#define TCNT0 _SFR_IO16(0x26)
-
-#define TCNT0L _SFR_IO8(0x26)
-#define TCNT0L0 0
-#define TCNT0L1 1
-#define TCNT0L2 2
-#define TCNT0L3 3
-#define TCNT0L4 4
-#define TCNT0L5 5
-#define TCNT0L6 6
-#define TCNT0L7 7
-
-#define TCNT0H _SFR_IO8(0x27)
-#define TCNT0H0 0
-#define TCNT0H1 1
-#define TCNT0H2 2
-#define TCNT0H3 3
-#define TCNT0H4 4
-#define TCNT0H5 5
-#define TCNT0H6 6
-#define TCNT0H7 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define OCR0B _SFR_IO8(0x29)
-#define OCR0B0 0
-#define OCR0B1 1
-#define OCR0B2 2
-#define OCR0B3 3
-#define OCR0B4 4
-#define OCR0B5 5
-#define OCR0B6 6
-#define OCR0B7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BODRF 2
-#define WDRF 3
-#define OCDRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define CKOE 5
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define LBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRVADC 0
-#define PRTIM0 1
-#define PRTIM1 2
-#define PRSPI 3
-#define PRVRM 5
-#define PRTWI 6
-
-#define FOSCCAL _SFR_MEM8(0x66)
-#define FCAL0 0
-#define FCAL1 1
-#define FCAL2 2
-#define FCAL3 3
-#define FCAL4 4
-#define FCAL5 5
-#define FCAL6 6
-#define FCAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT4 0
-#define PCINT5 1
-#define PCINT6 2
-#define PCINT7 3
-#define PCINT8 4
-#define PCINT9 5
-#define PCINT10 6
-#define PCINT11 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-#define ICIE0 3
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 3
-
-#define VADC _SFR_MEM16(0x78)
-
-#define VADCL _SFR_MEM8(0x78)
-#define VADC0 0
-#define VADC1 1
-#define VADC2 2
-#define VADC3 3
-#define VADC4 4
-#define VADC5 5
-#define VADC6 6
-#define VADC7 7
-
-#define VADCH _SFR_MEM8(0x79)
-#define VADC8 0
-#define VADC9 1
-#define VADC10 2
-#define VADC11 3
-
-#define VADCSR _SFR_MEM8(0x7A)
-#define VADCCIE 0
-#define VADCCIF 1
-#define VADSC 2
-#define VADEN 3
-
-#define VADMUX _SFR_MEM8(0x7C)
-#define VADMUX0 0
-#define VADMUX1 1
-#define VADMUX2 2
-#define VADMUX3 3
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define PA0DID 0
-#define PA1DID 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define ICS1 3
-#define ICES1 4
-#define ICNC1 5
-#define ICEN1 6
-#define TCW1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR1A _SFR_MEM8(0x88)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define OCR1B _SFR_MEM8(0x89)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define TWBCSR _SFR_MEM8(0xBE)
-#define TWBCIP 0
-#define TWBDT0 1
-#define TWBDT1 2
-#define TWBCIE 6
-#define TWBCIF 7
-
-#define ROCR _SFR_MEM8(0xC8)
-#define ROCWIE 0
-#define ROCWIF 1
-#define ROCD 4
-#define ROCS 7
-
-#define BGCCR _SFR_MEM8(0xD0)
-#define BGCC0 0
-#define BGCC1 1
-#define BGCC2 2
-#define BGCC3 3
-#define BGCC4 4
-#define BGCC5 5
-
-#define BGCRR _SFR_MEM8(0xD1)
-#define BGCR0 0
-#define BGCR1 1
-#define BGCR2 2
-#define BGCR3 3
-#define BGCR4 4
-#define BGCR5 5
-#define BGCR6 6
-#define BGCR7 7
-
-#define BGCSR _SFR_MEM8(0xD2)
-#define BGSCDIE 0
-#define BGSCDIF 1
-#define BGSCDE 4
-#define BGD 5
-
-#define CHGDCSR _SFR_MEM8(0xD4)
-#define CHGDIE 0
-#define CHGDIF 1
-#define CHGDISC0 2
-#define CHGDISC1 3
-#define BATTPVL 4
-
-#define CADAC0 _SFR_MEM8(0xE0)
-#define CADAC00 0
-#define CADAC01 1
-#define CADAC02 2
-#define CADAC03 3
-#define CADAC04 4
-#define CADAC05 5
-#define CADAC06 6
-#define CADAC07 7
-
-#define CADAC1 _SFR_MEM8(0xE1)
-#define CADAC08 0
-#define CADAC09 1
-#define CADAC10 2
-#define CADAC11 3
-#define CADAC12 4
-#define CADAC13 5
-#define CADAC14 6
-#define CADAC15 7
-
-#define CADAC2 _SFR_MEM8(0xE2)
-#define CADAC16 0
-#define CADAC17 1
-#define CADAC18 2
-#define CADAC19 3
-#define CADAC20 4
-#define CADAC21 5
-#define CADAC22 6
-#define CADAC23 7
-
-#define CADAC3 _SFR_MEM8(0xE3)
-#define CADAC24 0
-#define CADAC25 1
-#define CADAC26 2
-#define CADAC27 3
-#define CADAC28 4
-#define CADAC29 5
-#define CADAC30 6
-#define CADAC31 7
-
-#define CADIC _SFR_MEM16(0xE4)
-
-#define CADICL _SFR_MEM8(0xE4)
-#define CADICL0 0
-#define CADICL1 1
-#define CADICL2 2
-#define CADICL3 3
-#define CADICL4 4
-#define CADICL5 5
-#define CADICL6 6
-#define CADICL7 7
-
-#define CADICH _SFR_MEM8(0xE5)
-#define CADICH0 0
-#define CADICH1 1
-#define CADICH2 2
-#define CADICH3 3
-#define CADICH4 4
-#define CADICH5 5
-#define CADICH6 6
-#define CADICH7 7
-
-#define CADCSRA _SFR_MEM8(0xE6)
-#define CADSE 0
-#define CADSI0 1
-#define CADSI1 2
-#define CADAS0 3
-#define CADAS1 4
-#define CADUB 5
-#define CADPOL 6
-#define CADEN 7
-
-#define CADCSRB _SFR_MEM8(0xE7)
-#define CADICIF 0
-#define CADRCIF 1
-#define CADACIF 2
-#define CADICIE 4
-#define CADRCIE 5
-#define CADACIE 6
-
-#define CADCSRC _SFR_MEM8(0xE8)
-#define CADVSE 0
-
-#define CADRCC _SFR_MEM8(0xE9)
-#define CADRCC0 0
-#define CADRCC1 1
-#define CADRCC2 2
-#define CADRCC3 3
-#define CADRCC4 4
-#define CADRCC5 5
-#define CADRCC6 6
-#define CADRCC7 7
-
-#define CADRDC _SFR_MEM8(0xEA)
-#define CADRDC0 0
-#define CADRDC1 1
-#define CADRDC2 2
-#define CADRDC3 3
-#define CADRDC4 4
-#define CADRDC5 5
-#define CADRDC6 6
-#define CADRDC7 7
-
-#define FCSR _SFR_MEM8(0xF0)
-#define CFE 0
-#define DFE 1
-#define CPS 2
-#define DUVRD 3
-
-#define CBCR _SFR_MEM8(0xF1)
-#define CBE1 0
-#define CBE2 1
-#define CBE3 2
-#define CBE4 3
-
-#define BPIMSK _SFR_MEM8(0xF2)
-#define CHCIE 0
-#define DHCIE 1
-#define COCIE 2
-#define DOCIE 3
-#define SCIE 4
-
-#define BPIFR _SFR_MEM8(0xF3)
-#define CHCIF 0
-#define DHCIF 1
-#define COCIF 2
-#define DOCIF 3
-#define SCIF 4
-
-#define BPSCD _SFR_MEM8(0xF5)
-#define SCDL0 0
-#define SCDL1 1
-#define SCDL2 2
-#define SCDL3 3
-#define SCDL4 4
-#define SCDL5 5
-#define SCDL6 6
-#define SCDL7 7
-
-#define BPDOCD _SFR_MEM8(0xF6)
-#define DOCDL0 0
-#define DOCDL1 1
-#define DOCDL2 2
-#define DOCDL3 3
-#define DOCDL4 4
-#define DOCDL5 5
-#define DOCDL6 6
-#define DOCDL7 7
-
-#define BPCOCD _SFR_MEM8(0xF7)
-#define COCDL0 0
-#define COCDL1 1
-#define COCDL2 2
-#define COCDL3 3
-#define COCDL4 4
-#define COCDL5 5
-#define COCDL6 6
-#define COCDL7 7
-
-#define BPDHCD _SFR_MEM8(0xF8)
-#define DHCDL0 0
-#define DHCDL1 1
-#define DHCDL2 2
-#define DHCDL3 3
-#define DHCDL4 4
-#define DHCDL5 5
-#define DHCDL6 6
-#define DHCDL7 7
-
-#define BPCHCD _SFR_MEM8(0xF9)
-#define CHCDL0 0
-#define CHCDL1 1
-#define CHCDL2 2
-#define CHCDL3 3
-#define CHCDL4 4
-#define CHCDL5 5
-#define CHCDL6 6
-#define CHCDL7 7
-
-#define BPSCTR _SFR_MEM8(0xFA)
-#define SCPT0 0
-#define SCPT1 1
-#define SCPT2 2
-#define SCPT3 3
-#define SCPT4 4
-#define SCPT5 5
-#define SCPT6 6
-
-#define BPOCTR _SFR_MEM8(0xFB)
-#define OCPT0 0
-#define OCPT1 1
-#define OCPT2 2
-#define OCPT3 3
-#define OCPT4 4
-#define OCPT5 5
-
-#define BPHCTR _SFR_MEM8(0xFC)
-#define HCPT0 0
-#define HCPT1 1
-#define HCPT2 2
-#define HCPT3 3
-#define HCPT4 4
-#define HCPT5 5
-
-#define BPCR _SFR_MEM8(0xFD)
-#define CHCD 0
-#define DHCD 1
-#define COCD 2
-#define DOCD 3
-#define SCD 4
-#define EPID 5
-
-#define BPPLR _SFR_MEM8(0xFE)
-#define BPPL 0
-#define BPPLE 1
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define BPINT_vect_num  1
-#define BPINT_vect      _VECTOR(1)  /* Battery Protection Interrupt */
-#define VREGMON_vect_num  2
-#define VREGMON_vect      _VECTOR(2)  /* Voltage regulator monitor interrupt */
-#define INT0_vect_num  3
-#define INT0_vect      _VECTOR(3)  /* External Interrupt Request 0 */
-#define INT1_vect_num  4
-#define INT1_vect      _VECTOR(4)  /* External Interrupt Request 1 */
-#define INT2_vect_num  5
-#define INT2_vect      _VECTOR(5)  /* External Interrupt Request 2 */
-#define INT3_vect_num  6
-#define INT3_vect      _VECTOR(6)  /* External Interrupt Request 3 */
-#define PCINT0_vect_num  7
-#define PCINT0_vect      _VECTOR(7)  /* Pin Change Interrupt 0 */
-#define PCINT1_vect_num  8
-#define PCINT1_vect      _VECTOR(8)  /* Pin Change Interrupt 1 */
-#define WDT_vect_num  9
-#define WDT_vect      _VECTOR(9)  /* Watchdog Timeout Interrupt */
-#define BGSCD_vect_num  10
-#define BGSCD_vect      _VECTOR(10)  /* Bandgap Buffer Short Circuit Detected */
-#define CHDET_vect_num  11
-#define CHDET_vect      _VECTOR(11)  /* Charger Detect */
-#define TIMER1_IC_vect_num  12
-#define TIMER1_IC_vect      _VECTOR(12)  /* Timer 1 Input capture */
-#define TIMER1_COMPA_vect_num  13
-#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer 1 Compare Match A */
-#define TIMER1_COMPB_vect_num  14
-#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer 1 Compare Match B */
-#define TIMER1_OVF_vect_num  15
-#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer 1 overflow */
-#define TIMER0_IC_vect_num  16
-#define TIMER0_IC_vect      _VECTOR(16)  /* Timer 0 Input Capture */
-#define TIMER0_COMPA_vect_num  17
-#define TIMER0_COMPA_vect      _VECTOR(17)  /* Timer 0 Comapre Match A */
-#define TIMER0_COMPB_vect_num  18
-#define TIMER0_COMPB_vect      _VECTOR(18)  /* Timer 0 Compare Match B */
-#define TIMER0_OVF_vect_num  19
-#define TIMER0_OVF_vect      _VECTOR(19)  /* Timer 0 Overflow */
-#define TWIBUSCD_vect_num  20
-#define TWIBUSCD_vect      _VECTOR(20)  /* Two-Wire Bus Connect/Disconnect */
-#define TWI_vect_num  21
-#define TWI_vect      _VECTOR(21)  /* Two-Wire Serial Interface */
-#define SPI_STC_vect_num  22
-#define SPI_STC_vect      _VECTOR(22)  /* SPI Serial transfer complete */
-#define VADC_vect_num  23
-#define VADC_vect      _VECTOR(23)  /* Voltage ADC Conversion Complete */
-#define CCADC_CONV_vect_num  24
-#define CCADC_CONV_vect      _VECTOR(24)  /* Coulomb Counter ADC Conversion Complete */
-#define CCADC_REG_CUR_vect_num  25
-#define CCADC_REG_CUR_vect      _VECTOR(25)  /* Coloumb Counter ADC Regular Current */
-#define CCADC_ACC_vect_num  26
-#define CCADC_ACC_vect      _VECTOR(26)  /* Coloumb Counter ADC Accumulator */
-#define EE_READY_vect_num  27
-#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
-#define SPM_vect_num  28
-#define SPM_vect      _VECTOR(28)  /* SPM Ready */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (29 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (NA)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_OSCSEL0  (unsigned char)~_BV(0)  /* Oscillator Select */
-#define FUSE_OSCSEL1  (unsigned char)~_BV(1)  /* Oscillator Select */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Select start-up time */
-#define FUSE_SUT2  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_DWEN  (unsigned char)~_BV(3)  /* Enable debugWire */
-#define FUSE_DUVRDINIT  (unsigned char)~_BV(4)  /* Reset Value of DUVRDRegister */
-#define HFUSE_DEFAULT (FUSE_DUVRDINIT & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0D
-
-
-/* Device Pin Definitions */
-#define PV2_DDR   DDRV
-#define PV2_PORT  PORTV
-#define PV2_PIN   PINV
-#define PV2_BIT   2
-
-#define PV1_DDR   DDRV
-#define PV1_PORT  PORTV
-#define PV1_PIN   PINV
-#define PV1_BIT   1
-
-#define NV_DDR   DDRNV
-#define NV_PORT  PORTNV
-#define NV_PIN   PINNV
-#define NV_BIT   NV
-
-#define VFET_DDR   DDRVFET
-#define VFET_PORT  PORTVFET
-#define VFET_PIN   PINVFET
-#define VFET_BIT   VFET
-
-#define CF1P_DDR   DDRCF1P
-#define CF1P_PORT  PORTCF1P
-#define CF1P_PIN   PINCF1P
-#define CF1P_BIT   CF1P
-
-#define CF1N_DDR   DDRCF1N
-#define CF1N_PORT  PORTCF1N
-#define CF1N_PIN   PINCF1N
-#define CF1N_BIT   CF1N
-
-#define CF2P_DDR   DDRCF2P
-#define CF2P_PORT  PORTCF2P
-#define CF2P_PIN   PINCF2P
-#define CF2P_BIT   CF2P
-
-#define CF2N_DDR   DDRCF2N
-#define CF2N_PORT  PORTCF2N
-#define CF2N_PIN   PINCF2N
-#define CF2N_BIT   CF2N
-
-#define VREG_DDR   DDRVREG
-#define VREG_PORT  PORTVREG
-#define VREG_PIN   PINVREG
-#define VREG_BIT   VREG
-
-#define VREF_DDR   DDRVREF
-#define VREF_PORT  PORTVREF
-#define VREF_PIN   PINVREF
-#define VREF_BIT   VREF
-
-#define VREFGND_DDR   DDRVREFGND
-#define VREFGND_PORT  PORTVREFGND
-#define VREFGND_PIN   PINVREFGND
-#define VREFGND_BIT   VREFGND
-
-#define PI_DDR   DDRI
-#define PI_PORT  PORTI
-#define PI_PIN   PINI
-#define PI_BIT
-
-#define NI_DDR   DDRNI
-#define NI_PORT  PORTNI
-#define NI_PIN   PINNI
-#define NI_BIT   NI
-
-#define PA0_DDR   DDRA
-#define PA0_PORT  PORTA
-#define PA0_PIN   PINA
-#define PA0_BIT   0
-
-#define PA1_DDR   DDRA
-#define PA1_PORT  PORTA
-#define PA1_PIN   PINA
-#define PA1_BIT   1
-
-#define PA2_DDR   DDRA
-#define PA2_PORT  PORTA
-#define PA2_PIN   PINA
-#define PA2_BIT   2
-
-#define PB0_DDR   DDRB
-#define PB0_PORT  PORTB
-#define PB0_PIN   PINB
-#define PB0_BIT   0
-
-#define PB1_DDR   DDRB
-#define PB1_PORT  PORTB
-#define PB1_PIN   PINB
-#define PB1_BIT   1
-
-#define PB2_DDR   DDRB
-#define PB2_PORT  PORTB
-#define PB2_PIN   PINB
-#define PB2_BIT   2
-
-#define PB3_DDR   DDRB
-#define PB3_PORT  PORTB
-#define PB3_PIN   PINB
-#define PB3_BIT   3
-
-#define PC0_DDR   DDRC
-#define PC0_PORT  PORTC
-#define PC0_PIN   PINC
-#define PC0_BIT   0
-
-#define BATT_DDR   DDRBATT
-#define BATT_PORT  PORTBATT
-#define BATT_PIN   PINBATT
-#define BATT_BIT   BATT
-
-#define OC_DDR   DDROC
-#define OC_PORT  PORTOC
-#define OC_PIN   PINOC
-#define OC_BIT   OC
-
-/**@}*/
-#endif /* _AVR_ATmega16HVB_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16m1.h b/cpukit/score/cpu/avr/avr/iom16m1.h
deleted file mode 100644
index 4ca8f1e40c..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16m1.h
+++ /dev/null
@@ -1,1557 +0,0 @@
-/**
- * @file avr/iom16m1.h
- *
- * @brief Definitions for ATmega16M1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16m1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega16M1_H_
-#define _AVR_ATmega16M1_H_ 1
-
-/**
- *  @defgroup Avr_iom16m1 ATmega16M1 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 6
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRLIN 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC 5
-#define PRCAN 6
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define PCMSK3 _SFR_MEM8(0x6D)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x75)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0TS2 2
-#define AMPCMP0 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x76)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1TS2 2
-#define AMPCMP1 3
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#define AMP2CSR _SFR_MEM8(0x77)
-#define AMP2TS0 0
-#define AMP2TS1 1
-#define AMP2TS2 2
-#define AMPCMP2 3
-#define AMP2G0 4
-#define AMP2G1 5
-#define AMP2IS 6
-#define AMP2EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define AREFEN 5
-#define ISRCEN 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-#define AMP2PD 6
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define DACON _SFR_MEM8(0x90)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0x91)
-
-#define DACL _SFR_MEM8(0x91)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0x92)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0x94)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define ACCKSEL 3
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0x95)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x96)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x97)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define POCR0SA _SFR_MEM16(0xA0)
-
-#define POCR0SAL _SFR_MEM8(0xA0)
-#define POCR0SA_0 0
-#define POCR0SA_1 1
-#define POCR0SA_2 2
-#define POCR0SA_3 3
-#define POCR0SA_4 4
-#define POCR0SA_5 5
-#define POCR0SA_6 6
-#define POCR0SA_7 7
-
-#define POCR0SAH _SFR_MEM8(0xA1)
-#define POCR0SA_8 0
-#define POCR0SA_9 1
-#define POCR0SA_10 2
-#define POCR0SA_11 3
-
-#define POCR0RA _SFR_MEM16(0xA2)
-
-#define POCR0RAL _SFR_MEM8(0xA2)
-#define POCR0RA_0 0
-#define POCR0RA_1 1
-#define POCR0RA_2 2
-#define POCR0RA_3 3
-#define POCR0RA_4 4
-#define POCR0RA_5 5
-#define POCR0RA_6 6
-#define POCR0RA_7 7
-
-#define POCR0RAH _SFR_MEM8(0xA3)
-#define POCR0RA_8 0
-#define POCR0RA_9 1
-#define POCR0RA_10 2
-#define POCR0RA_11 3
-
-#define POCR0SB _SFR_MEM16(0xA4)
-
-#define POCR0SBL _SFR_MEM8(0xA4)
-#define POCR0SB_0 0
-#define POCR0SB_1 1
-#define POCR0SB_2 2
-#define POCR0SB_3 3
-#define POCR0SB_4 4
-#define POCR0SB_5 5
-#define POCR0SB_6 6
-#define POCR0SB_7 7
-
-#define POCR0SBH _SFR_MEM8(0xA5)
-#define POCR0SB_8 0
-#define POCR0SB_9 1
-#define POCR0SB_10 2
-#define POCR0SB_11 3
-
-#define POCR1SA _SFR_MEM16(0xA6)
-
-#define POCR1SAL _SFR_MEM8(0xA6)
-#define POCR1SA_0 0
-#define POCR1SA_1 1
-#define POCR1SA_2 2
-#define POCR1SA_3 3
-#define POCR1SA_4 4
-#define POCR1SA_5 5
-#define POCR1SA_6 6
-#define POCR1SA_7 7
-
-#define POCR1SAH _SFR_MEM8(0xA7)
-#define POCR1SA_8 0
-#define POCR1SA_9 1
-#define POCR1SA_10 2
-#define POCR1SA_11 3
-
-#define POCR1RA _SFR_MEM16(0xA8)
-
-#define POCR1RAL _SFR_MEM8(0xA8)
-#define POCR1RA_0 0
-#define POCR1RA_1 1
-#define POCR1RA_2 2
-#define POCR1RA_3 3
-#define POCR1RA_4 4
-#define POCR1RA_5 5
-#define POCR1RA_6 6
-#define POCR1RA_7 7
-
-#define POCR1RAH _SFR_MEM8(0xA9)
-#define POCR1RA_8 0
-#define POCR1RA_9 1
-#define POCR1RA_10 2
-#define POCR1RA_11 3
-
-#define POCR1SB _SFR_MEM16(0xAA)
-
-#define POCR1SBL _SFR_MEM8(0xAA)
-#define POCR1SB_0 0
-#define POCR1SB_1 1
-#define POCR1SB_2 2
-#define POCR1SB_3 3
-#define POCR1SB_4 4
-#define POCR1SB_5 5
-#define POCR1SB_6 6
-#define POCR1SB_7 7
-
-#define POCR1SBH _SFR_MEM8(0xAB)
-#define POCR1SB_8 0
-#define POCR1SB_9 1
-#define POCR1SB_10 2
-#define POCR1SB_11 3
-
-#define POCR2SA _SFR_MEM16(0xAC)
-
-#define POCR2SAL _SFR_MEM8(0xAC)
-#define POCR2SA_0 0
-#define POCR2SA_1 1
-#define POCR2SA_2 2
-#define POCR2SA_3 3
-#define POCR2SA_4 4
-#define POCR2SA_5 5
-#define POCR2SA_6 6
-#define POCR2SA_7 7
-
-#define POCR2SAH _SFR_MEM8(0xAD)
-#define POCR2SA_8 0
-#define POCR2SA_9 1
-#define POCR2SA_10 2
-#define POCR2SA_11 3
-
-#define POCR2RA _SFR_MEM16(0xAE)
-
-#define POCR2RAL _SFR_MEM8(0xAE)
-#define POCR2RA_0 0
-#define POCR2RA_1 1
-#define POCR2RA_2 2
-#define POCR2RA_3 3
-#define POCR2RA_4 4
-#define POCR2RA_5 5
-#define POCR2RA_6 6
-#define POCR2RA_7 7
-
-#define POCR2RAH _SFR_MEM8(0xAF)
-#define POCR2RA_8 0
-#define POCR2RA_9 1
-#define POCR2RA_10 2
-#define POCR2RA_11 3
-
-#define POCR2SB _SFR_MEM16(0xB0)
-
-#define POCR2SBL _SFR_MEM8(0xB0)
-#define POCR2SB_0 0
-#define POCR2SB_1 1
-#define POCR2SB_2 2
-#define POCR2SB_3 3
-#define POCR2SB_4 4
-#define POCR2SB_5 5
-#define POCR2SB_6 6
-#define POCR2SB_7 7
-
-#define POCR2SBH _SFR_MEM8(0xB1)
-#define POCR2SB_8 0
-#define POCR2SB_9 1
-#define POCR2SB_10 2
-#define POCR2SB_11 3
-
-#define POCR_RB _SFR_MEM16(0xB2)
-
-#define POCR_RBL _SFR_MEM8(0xB2)
-#define POCR_RB_0 0
-#define POCR_RB_1 1
-#define POCR_RB_2 2
-#define POCR_RB_3 3
-#define POCR_RB_4 4
-#define POCR_RB_5 5
-#define POCR_RB_6 6
-#define POCR_RB_7 7
-
-#define POCR_RBH _SFR_MEM8(0xB3)
-#define POCR_RB_8 0
-#define POCR_RB_9 1
-#define POCR_RB_10 2
-#define POCR_RB_11 3
-
-#define PSYNC _SFR_MEM8(0xB4)
-#define PSYNC00 0
-#define PSYNC01 1
-#define PSYNC10 2
-#define PSYNC11 3
-#define PSYNC20 4
-#define PSYNC21 5
-
-#define PCNF _SFR_MEM8(0xB5)
-#define POPA 2
-#define POPB 3
-#define PMODE 4
-#define PULOCK 5
-
-#define POC _SFR_MEM8(0xB6)
-#define POEN0A 0
-#define POEN0B 1
-#define POEN1A 2
-#define POEN1B 3
-#define POEN2A 4
-#define POEN2B 5
-
-#define PCTL _SFR_MEM8(0xB7)
-#define PRUN 0
-#define PCCYC 1
-#define PCLKSEL 5
-#define PPRE0 6
-#define PPRE1 7
-
-#define PMIC0 _SFR_MEM8(0xB8)
-#define PRFM00 0
-#define PRFM01 1
-#define PRFM02 2
-#define PAOC0 3
-#define PFLTE0 4
-#define PELEV0 5
-#define PISEL0 6
-#define POVEN0 7
-
-#define PMIC1 _SFR_MEM8(0xB9)
-#define PRFM10 0
-#define PRFM11 1
-#define PRFM12 2
-#define PAOC1 3
-#define PFLTE1 4
-#define PELEV1 5
-#define PISEL1 6
-#define POVEN1 7
-
-#define PMIC2 _SFR_MEM8(0xBA)
-#define PRFM20 0
-#define PRFM21 1
-#define PRFM22 2
-#define PAOC2 3
-#define PFLTE2 4
-#define PELEV2 5
-#define PISEL2 6
-#define POVEN2 7
-
-#define PIM _SFR_MEM8(0xBB)
-#define PEOPE 0
-#define PEVE0 1
-#define PEVE1 2
-#define PEVE2 3
-
-#define PIFR _SFR_MEM8(0xBC)
-#define PEOP 0
-#define PEV0 1
-#define PEV1 2
-#define PEV2 3
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define CANGCON _SFR_MEM8(0xD8)
-#define SWRES 0
-#define ENASTB 1
-#define TEST 2
-#define LISTEN 3
-#define SYNTTC 4
-#define TTC 5
-#define OVRQ 6
-#define ABRQ 7
-
-#define CANGSTA _SFR_MEM8(0xD9)
-#define ERRP 0
-#define BOFF 1
-#define ENFG 2
-#define RXBSY 3
-#define TXBSY 4
-#define OVFG 6
-
-#define CANGIT _SFR_MEM8(0xDA)
-#define AERG 0
-#define FERG 1
-#define CERG 2
-#define SERG 3
-#define BXOK 4
-#define OVRTIM 5
-#define BOFFIT 6
-#define CANIT 7
-
-#define CANGIE _SFR_MEM8(0xDB)
-#define ENOVRT 0
-#define ENERG 1
-#define ENBX 2
-#define ENERR 3
-#define ENTX 4
-#define ENRX 5
-#define ENBOFF 6
-#define ENIT 7
-
-#define CANEN2 _SFR_MEM8(0xDC)
-#define ENMOB0 0
-#define ENMOB1 1
-#define ENMOB2 2
-#define ENMOB3 3
-#define ENMOB4 4
-#define ENMOB5 5
-
-#define CANEN1 _SFR_MEM8(0xDD)
-
-#define CANIE2 _SFR_MEM8(0xDE)
-#define IEMOB0 0
-#define IEMOB1 1
-#define IEMOB2 2
-#define IEMOB3 3
-#define IEMOB4 4
-#define IEMOB5 5
-
-#define CANIE1 _SFR_MEM8(0xDF)
-
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define SIT0 0
-#define SIT1 1
-#define SIT2 2
-#define SIT3 3
-#define SIT4 4
-#define SIT5 5
-
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-#define CANBT1 _SFR_MEM8(0xE2)
-#define BRP0 1
-#define BRP1 2
-#define BRP2 3
-#define BRP3 4
-#define BRP4 5
-#define BRP5 6
-
-#define CANBT2 _SFR_MEM8(0xE3)
-#define PRS0 1
-#define PRS1 2
-#define PRS2 3
-#define SJW0 5
-#define SJW1 6
-
-#define CANBT3 _SFR_MEM8(0xE4)
-#define SMP 0
-#define PHS10 1
-#define PHS11 2
-#define PHS12 3
-#define PHS20 4
-#define PHS21 5
-#define PHS22 6
-
-#define CANTCON _SFR_MEM8(0xE5)
-#define TPRSC0 0
-#define TPRSC1 1
-#define TPRSC2 2
-#define TPRSC3 3
-#define TPRSC4 4
-#define TPRSC5 5
-#define TPRSC6 6
-#define TPRSC7 7
-
-#define CANTIM _SFR_MEM16(0xE6)
-
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIM0 0
-#define CANTIM1 1
-#define CANTIM2 2
-#define CANTIM3 3
-#define CANTIM4 4
-#define CANTIM5 5
-#define CANTIM6 6
-#define CANTIM7 7
-
-#define CANTIMH _SFR_MEM8(0xE7)
-#define CANTIM8 0
-#define CANTIM9 1
-#define CANTIM10 2
-#define CANTIM11 3
-#define CANTIM12 4
-#define CANTIM13 5
-#define CANTIM14 6
-#define CANTIM15 7
-
-#define CANTTC _SFR_MEM16(0xE8)
-
-#define CANTTCL _SFR_MEM8(0xE8)
-#define TIMTCC0 0
-#define TIMTCC1 1
-#define TIMTCC2 2
-#define TIMTCC3 3
-#define TIMTCC4 4
-#define TIMTCC5 5
-#define TIMTCC6 6
-#define TIMTCC7 7
-
-#define CANTTCH _SFR_MEM8(0xE9)
-#define TIMTCC8 0
-#define TIMTCC9 1
-#define TIMTCC10 2
-#define TIMTCC11 3
-#define TIMTCC12 4
-#define TIMTCC13 5
-#define TIMTCC14 6
-#define TIMTCC15 7
-
-#define CANTEC _SFR_MEM8(0xEA)
-#define TEC0 0
-#define TEC1 1
-#define TEC2 2
-#define TEC3 3
-#define TEC4 4
-#define TEC5 5
-#define TEC6 6
-#define TEC7 7
-
-#define CANREC _SFR_MEM8(0xEB)
-#define REC0 0
-#define REC1 1
-#define REC2 2
-#define REC3 3
-#define REC4 4
-#define REC5 5
-#define REC6 6
-#define REC7 7
-
-#define CANHPMOB _SFR_MEM8(0xEC)
-#define CGP0 0
-#define CGP1 1
-#define CGP2 2
-#define CGP3 3
-#define HPMOB0 4
-#define HPMOB1 5
-#define HPMOB2 6
-#define HPMOB3 7
-
-#define CANPAGE _SFR_MEM8(0xED)
-#define INDX0 0
-#define INDX1 1
-#define INDX2 2
-#define AINC 3
-#define MOBNB0 4
-#define MOBNB1 5
-#define MOBNB2 6
-#define MOBNB3 7
-
-#define CANSTMOB _SFR_MEM8(0xEE)
-#define AERR 0
-#define FERR 1
-#define CERR 2
-#define SERR 3
-#define BERR 4
-#define RXOK 5
-#define TXOK 6
-#define DLCW 7
-
-#define CANCDMOB _SFR_MEM8(0xEF)
-#define DLC0 0
-#define DLC1 1
-#define DLC2 2
-#define DLC3 3
-#define IDE 4
-#define RPLV 5
-#define CONMOB0 6
-#define CONMOB1 7
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define RB0TAG 0
-#define RB1TAG 1
-#define RTRTAG 2
-#define IDT0 3
-#define IDT1 4
-#define IDT2 5
-#define IDT3 6
-#define IDT4 7
-
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define IDT5 0
-#define IDT6 1
-#define IDT7 2
-#define IDT8 3
-#define IDT9 4
-#define IDT10 5
-#define IDT11 6
-#define IDT12 7
-
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define IDT13 0
-#define IDT14 1
-#define IDT15 2
-#define IDT16 3
-#define IDT17 4
-#define IDT18 5
-#define IDT19 6
-#define IDT20 7
-
-#define CANIDT1 _SFR_MEM8(0xF3)
-#define IDT21 0
-#define IDT22 1
-#define IDT23 2
-#define IDT24 3
-#define IDT25 4
-#define IDT26 5
-#define IDT27 6
-#define IDT28 7
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define IDEMSK 0
-#define RTRMSK 2
-#define IDMSK0 3
-#define IDMSK1 4
-#define IDMSK2 5
-#define IDMSK3 6
-#define IDMSK4 7
-
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define IDMSK5 0
-#define IDMSK6 1
-#define IDMSK7 2
-#define IDMSK8 3
-#define IDMSK9 4
-#define IDMSK10 5
-#define IDMSK11 6
-#define IDMSK12 7
-
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define IDMSK13 0
-#define IDMSK14 1
-#define IDMSK15 2
-#define IDMSK16 3
-#define IDMSK17 4
-#define IDMSK18 5
-#define IDMSK19 6
-#define IDMSK20 7
-
-#define CANIDM1 _SFR_MEM8(0xF7)
-#define IDMSK21 0
-#define IDMSK22 1
-#define IDMSK23 2
-#define IDMSK24 3
-#define IDMSK25 4
-#define IDMSK26 5
-#define IDMSK27 6
-#define IDMSK28 7
-
-#define CANSTM _SFR_MEM16(0xF8)
-
-#define CANSTML _SFR_MEM8(0xF8)
-#define TIMSTM0 0
-#define TIMSTM1 1
-#define TIMSTM2 2
-#define TIMSTM3 3
-#define TIMSTM4 4
-#define TIMSTM5 5
-#define TIMSTM6 6
-#define TIMSTM7 7
-
-#define CANSTMH _SFR_MEM8(0xF9)
-#define TIMSTM8 0
-#define TIMSTM9 1
-#define TIMSTM10 2
-#define TIMSTM11 3
-#define TIMSTM12 4
-#define TIMSTM13 5
-#define TIMSTM14 6
-#define TIMSTM15 7
-
-#define CANMSG _SFR_MEM8(0xFA)
-#define MSG0 0
-#define MSG1 1
-#define MSG2 2
-#define MSG3 3
-#define MSG4 4
-#define MSG5 5
-#define MSG6 6
-#define MSG7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define ANACOMP0_vect_num  1
-#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
-#define ANACOMP1_vect_num  2
-#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
-#define ANACOMP2_vect_num  3
-#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
-#define ANACOMP3_vect_num  4
-#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
-#define PSC_FAULT_vect_num  5
-#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
-#define PSC_EC_vect_num  6
-#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
-#define INT0_vect_num  7
-#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
-#define INT1_vect_num  8
-#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
-#define INT2_vect_num  9
-#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
-#define INT3_vect_num  10
-#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  12
-#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  13
-#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  14
-#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  15
-#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  16
-#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  17
-#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define CAN_INT_vect_num  18
-#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
-#define CAN_TOVF_vect_num  19
-#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
-#define LIN_TC_vect_num  20
-#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  21
-#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
-#define PCINT0_vect_num  22
-#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  23
-#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  24
-#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  25
-#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
-#define SPI_STC_vect_num  26
-#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  27
-#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
-#define WDT_vect_num  28
-#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
-#define EE_READY_vect_num  29
-#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
-#define SPM_READY_vect_num  30
-#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
-#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
-#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
-#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x84
-
-/**@}*/
-#endif /* _AVR_ATmega16M1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16u2.h b/cpukit/score/cpu/avr/avr/iom16u2.h
deleted file mode 100644
index bae63fa594..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16u2.h
+++ /dev/null
@@ -1,990 +0,0 @@
-/**
- * @file avr/iom16u2.h
- *
- * @brief Definitions for ATmega16U2
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16u2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega16U2_H_
-#define _AVR_ATmega16U2_H_ 1
-
-/**
- *  @defgroup Avr_iom16u2 ATmega16U2 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLP0 2
-#define PLLP1 3
-#define PLLP2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define DWDR _SFR_IO8(0x31)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define USBRF 5
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define EIND _SFR_IO8(0x3C)
-#define EIND0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define WDTCKD _SFR_MEM8(0x62)
-#define WCLKD0 0
-#define WCLKD1 1
-#define WDEWIE 2
-#define WDEWIF 3
-
-#define REGCR _SFR_MEM8(0x63)
-#define REGDIS 0
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UCSR1D _SFR_MEM8(0xCB)
-#define RTSEN 0
-#define CTSEN 1
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define CLKSEL0 _SFR_MEM8(0xD0)
-#define CLKS 0
-#define EXTE 2
-#define RCE 3
-#define EXSUT0 4
-#define EXSUT1 5
-#define RCSUT0 6
-#define RCSUT1 7
-
-#define CLKSEL1 _SFR_MEM8(0xD1)
-#define EXCKSEL0 0
-#define EXCKSEL1 1
-#define EXCKSEL2 2
-#define EXCKSEL3 3
-#define RCCKSEL0 4
-#define RCCKSEL1 5
-#define RCCKSEL2 6
-#define RCCKSEL3 7
-
-#define CLKSTA _SFR_MEM8(0xD2)
-#define EXTON 0
-#define RCON 1
-
-#define USBCON _SFR_MEM8(0xD8)
-#define FRZCLK 5
-#define USBE 7
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define RSTCPU 2
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define EPNUM0 0
-#define EPNUM1 1
-#define EPNUM2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define DAT0 0
-#define DAT1 1
-#define DAT2 2
-#define DAT3 3
-#define DAT4 4
-#define DAT5 5
-#define DAT6 6
-#define DAT7 7
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define BYCT0 0
-#define BYCT1 1
-#define BYCT2 2
-#define BYCT3 3
-#define BYCT4 4
-#define BYCT5 5
-#define BYCT6 6
-#define BYCT7 7
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-
-#define PS2CON _SFR_MEM8(0xFA)
-#define PS2EN 0
-
-#define UPOE _SFR_MEM8(0xFB)
-#define DMI 0
-#define DPI 1
-#define DATAI 2
-#define SCKI 3
-#define UPDRV0 4
-#define UPDRV1 5
-#define UPWE0 6
-#define UPWE1 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT4_vect_num  5
-#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
-#define INT5_vect_num  6
-#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
-#define INT6_vect_num  7
-#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
-#define INT7_vect_num  8
-#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
-#define PCINT0_vect_num  9
-#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  10
-#define PCINT1_vect      _VECTOR(10)  /* Pin Change Interrupt Request 1 */
-#define USB_GEN_vect_num  11
-#define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
-#define USB_COM_vect_num  12
-#define USB_COM_vect      _VECTOR(12)  /* USB Endpoint/Pipe Interrupt Communication Request */
-#define WDT_vect_num  13
-#define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
-#define TIMER1_CAPT_vect_num  14
-#define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
-#define TIMER1_COMPA_vect_num  15
-#define TIMER1_COMPA_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match B */
-#define TIMER0_COMPA_vect_num  19
-#define TIMER0_COMPA_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  20
-#define TIMER0_COMPB_vect      _VECTOR(20)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  21
-#define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  22
-#define SPI_STC_vect      _VECTOR(22)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect_num  23
-#define USART1_RX_vect      _VECTOR(23)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect_num  24
-#define USART1_UDRE_vect      _VECTOR(24)  /* USART1 Data register Empty */
-#define USART1_TX_vect_num  25
-#define USART1_TX_vect      _VECTOR(25)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect_num  26
-#define ANALOG_COMP_vect      _VECTOR(26)  /* Analog Comparator */
-#define EE_READY_vect_num  27
-#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
-#define SPM_READY_vect_num  28
-#define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
-#define TIMER1_COMPB_vect_num  16
-#define TIMER1_COMPB_vect      _VECTOR(16)  /* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPC_vect_num  17
-#define TIMER1_COMPC_vect      _VECTOR(17)  /* Timer/Counter2 Compare Match C */
-#define TIMER1_OVF_vect_num  18
-#define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
-#define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x89
-
-/**@}*/
-
-/* Device Pin Definitions */
-#endif /* _AVR_ATmega16U2_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16u4.h b/cpukit/score/cpu/avr/avr/iom16u4.h
deleted file mode 100644
index 79e577919b..0000000000
--- a/cpukit/score/cpu/avr/avr/iom16u4.h
+++ /dev/null
@@ -1,1366 +0,0 @@
-/**
- * @file aavr/iom16u4.h
- *
- * @brief Definitions for ATmega16U4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16u4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega16U4_H_
-#define _AVR_ATmega16U4_H_ 1
-
-/**
- *  @defgroup Avr_iom16u4 ATmega16U4 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE2 2
-#define PINE6 6
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE2 2
-#define DDE6 6
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE2 2
-#define PORTE6 6
-
-#define PINF _SFR_IO8(0x0F)
-#define PINF0 0
-#define PINF1 1
-#define PINF4 4
-#define PINF5 5
-#define PINF6 6
-#define PINF7 7
-
-#define DDRF _SFR_IO8(0x10)
-#define DDF0 0
-#define DDF1 1
-#define DDF4 4
-#define DDF5 5
-#define DDF6 6
-#define DDF7 7
-
-#define PORTF _SFR_IO8(0x11)
-#define PORTF0 0
-#define PORTF1 1
-#define PORTF4 4
-#define PORTF5 5
-#define PORTF6 6
-#define PORTF7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define OCF3C 3
-#define ICF3 5
-
-#define TIFR4 _SFR_IO8(0x19)
-#define TOV4 2
-#define OCF4B 5
-#define OCF4A 6
-#define OCF4D 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCROA_0 0
-#define OCROA_1 1
-#define OCROA_2 2
-#define OCROA_3 3
-#define OCROA_4 4
-#define OCROA_5 5
-#define OCROA_6 6
-#define OCROA_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PINDIV 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define PLLFRQ _SFR_IO8(0x32)
-#define PDIV0 0
-#define PDIV1 1
-#define PDIV2 2
-#define PDIV3 3
-#define PLLTM0 4
-#define PLLTM1 5
-#define PLLUSB 6
-#define PINMUX 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define EIND _SFR_IO8(0x3C)
-#define EIND0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRTIM3 3
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define RCCTRL _SFR_MEM8(0x67)
-#define RCFREQ 0
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define OCIE3C 3
-#define ICIE3 5
-
-#define TIMSK4 _SFR_MEM8(0x72)
-#define TOIE4 2
-#define OCIE4B 5
-#define OCIE4A 6
-#define OCIE4D 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 4
-#define MUX5 5
-#define ACME 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR2 _SFR_MEM8(0x7D)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define ADC11D 3
-#define ADC12D 4
-#define ADC13D 5
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3C0 2
-#define COM3C1 3
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3C 5
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3BL0 0
-#define OCR3BL1 1
-#define OCR3BL2 2
-#define OCR3BL3 3
-#define OCR3BL4 4
-#define OCR3BL5 5
-#define OCR3BL6 6
-#define OCR3BL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3BH0 0
-#define OCR3BH1 1
-#define OCR3BH2 2
-#define OCR3BH3 3
-#define OCR3BH4 4
-#define OCR3BH5 5
-#define OCR3BH6 6
-#define OCR3BH7 7
-
-#define OCR3C _SFR_MEM16(0x9C)
-
-#define OCR3CL _SFR_MEM8(0x9C)
-#define OCR3CL0 0
-#define OCR3CL1 1
-#define OCR3CL2 2
-#define OCR3CL3 3
-#define OCR3CL4 4
-#define OCR3CL5 5
-#define OCR3CL6 6
-#define OCR3CL7 7
-
-#define OCR3CH _SFR_MEM8(0x9D)
-#define OCR3CH0 0
-#define OCR3CH1 1
-#define OCR3CH2 2
-#define OCR3CH3 3
-#define OCR3CH4 4
-#define OCR3CH5 5
-#define OCR3CH6 6
-#define OCR3CH7 7
-
-#define TCNT4 _SFR_MEM8(0xBE)
-#define TC40 0
-#define TC41 1
-#define TC42 2
-#define TC43 3
-#define TC44 4
-#define TC45 5
-#define TC46 6
-#define TC47 7
-
-#define TC4H _SFR_MEM8(0xBF)
-#define TC48 0
-#define TC49 1
-#define TC410 2
-
-#define TCCR4A _SFR_MEM8(0xC0)
-#define PWM4B 0
-#define PWM4A 1
-#define FOC4B 2
-#define FOC4A 3
-#define COM4B0 4
-#define COM4B1 5
-#define COM4A0 6
-#define COM4A1 7
-
-#define TCCR4B _SFR_MEM8(0xC1)
-#define CS40 0
-#define CS41 1
-#define CS42 2
-#define CS43 3
-#define DTPS40 4
-#define DTPS41 5
-#define PSR4 6
-#define PWM4X 7
-
-#define TCCR4C _SFR_MEM8(0xC2)
-#define PWM4D 0
-#define FOC4D 1
-#define COM4D0 2
-#define COM4D1 3
-#define COM4B0S 4
-#define COM4B1S 5
-#define COM4A0S 6
-#define COM4A1S 7
-
-#define TCCR4D _SFR_MEM8(0xC3)
-#define WGM40 0
-#define WGM41 1
-#define FPF4 2
-#define FPAC4 3
-#define FPES4 4
-#define FPNC4 5
-#define FPEN4 6
-#define FPIE4 7
-
-#define TCCR4E _SFR_MEM8(0xC4)
-#define OC4OE0 0
-#define OC4OE1 1
-#define OC4OE2 2
-#define OC4OE3 3
-#define OC4OE4 4
-#define OC4OE5 5
-#define ENHC4 6
-#define TLOCK4 7
-
-#define CLKSEL0 _SFR_MEM8(0xC5)
-#define CLKS 0
-#define EXTE 2
-#define RCE 3
-#define EXSUT0 4
-#define EXSUT1 5
-#define RCSUT0 6
-#define RCSUT1 7
-
-#define CLKSEL1 _SFR_MEM8(0xC6)
-#define EXCKSEL0 0
-#define EXCKSEL1 1
-#define EXCKSEL2 2
-#define EXCKSEL3 3
-#define RCCKSEL0 4
-#define RCCKSEL1 5
-#define RCCKSEL2 6
-#define RCCKSEL3 7
-
-#define CLKSTA _SFR_MEM8(0xC7)
-#define EXTON 0
-#define RCON 1
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-
-#define UBRR1H _SFR_MEM8(0xCD)
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define OCR4A _SFR_MEM8(0xCF)
-#define OCR4A0 0
-#define OCR4A1 1
-#define OCR4A2 2
-#define OCR4A3 3
-#define OCR4A4 4
-#define OCR4A5 5
-#define OCR4A6 6
-#define OCR4A7 7
-
-#define OCR4B _SFR_MEM8(0xD0)
-#define OCR4B0 0
-#define OCR4B1 1
-#define OCR4B2 2
-#define OCR4B3 3
-#define OCR4B4 4
-#define OCR4B5 5
-#define OCR4B6 6
-#define OCR4B7 7
-
-#define OCR4C _SFR_MEM8(0xD1)
-#define OCR4C0 0
-#define OCR4C1 1
-#define OCR4C2 2
-#define OCR4C3 3
-#define OCR4C4 4
-#define OCR4C5 5
-#define OCR4C6 6
-#define OCR4C7 7
-
-#define OCR4D _SFR_MEM8(0xD2)
-#define OCR4D0 0
-#define OCR4D1 1
-#define OCR4D2 2
-#define OCR4D3 3
-#define OCR4D4 4
-#define OCR4D5 5
-#define OCR4D6 6
-#define OCR4D7 7
-
-#define DT4 _SFR_MEM8(0xD4)
-#define DT4L0 0
-#define DT4L1 1
-#define DT4L2 2
-#define DT4L3 3
-#define DT4L4 4
-#define DT4L5 5
-#define DT4L6 6
-#define DT4L7 7
-
-#define UHWCON _SFR_MEM8(0xD7)
-#define UVREGE 0
-
-#define USBCON _SFR_MEM8(0xD8)
-#define VBUSTE 0
-#define OTGPADE 4
-#define FRZCLK 5
-#define USBE 7
-
-#define USBSTA _SFR_MEM8(0xD9)
-#define VBUS 0
-#define SPEED 3
-
-#define USBINT _SFR_MEM8(0xDA)
-#define VBUSTI 0
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define LSM 2
-#define RSTCPU 3
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define UENUM_0 0
-#define UENUM_1 1
-#define UENUM_2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-#define EPRST5 5
-#define EPRST6 6
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define DAT0 0
-#define DAT1 1
-#define DAT2 2
-#define DAT3 3
-#define DAT4 4
-#define DAT5 5
-#define DAT6 6
-#define DAT7 7
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define BYCT0 0
-#define BYCT1 1
-#define BYCT2 2
-#define BYCT3 3
-#define BYCT4 4
-#define BYCT5 5
-#define BYCT6 6
-#define BYCT7 7
-
-#define UEBCHX _SFR_MEM8(0xF3)
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-#define EPINT5 5
-#define EPINT6 6
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT6_vect_num  7
-#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
-#define PCINT0_vect_num  9
-#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define USB_GEN_vect_num  10
-#define USB_GEN_vect      _VECTOR(10)  /* USB General Interrupt Request */
-#define USB_COM_vect_num  11
-#define USB_COM_vect      _VECTOR(11)  /* USB Endpoint/Pipe Interrupt Communication Request */
-#define WDT_vect_num  12
-#define WDT_vect      _VECTOR(12)  /* Watchdog Time-out Interrupt */
-#define TIMER1_CAPT_vect_num  16
-#define TIMER1_CAPT_vect      _VECTOR(16)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  17
-#define TIMER1_COMPA_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  18
-#define TIMER1_COMPB_vect      _VECTOR(18)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPC_vect_num  19
-#define TIMER1_COMPC_vect      _VECTOR(19)  /* Timer/Counter1 Compare Match C */
-#define TIMER1_OVF_vect_num  20
-#define TIMER1_OVF_vect      _VECTOR(20)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  21
-#define TIMER0_COMPA_vect      _VECTOR(21)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  22
-#define TIMER0_COMPB_vect      _VECTOR(22)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  23
-#define TIMER0_OVF_vect      _VECTOR(23)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  24
-#define SPI_STC_vect      _VECTOR(24)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect_num  25
-#define USART1_RX_vect      _VECTOR(25)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect_num  26
-#define USART1_UDRE_vect      _VECTOR(26)  /* USART1 Data register Empty */
-#define USART1_TX_vect_num  27
-#define USART1_TX_vect      _VECTOR(27)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect_num  28
-#define ANALOG_COMP_vect      _VECTOR(28)  /* Analog Comparator */
-#define ADC_vect_num  29
-#define ADC_vect      _VECTOR(29)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  30
-#define EE_READY_vect      _VECTOR(30)  /* EEPROM Ready */
-#define TIMER3_CAPT_vect_num  31
-#define TIMER3_CAPT_vect      _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect_num  32
-#define TIMER3_COMPA_vect      _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect_num  33
-#define TIMER3_COMPB_vect      _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPC_vect_num  34
-#define TIMER3_COMPC_vect      _VECTOR(34)  /* Timer/Counter3 Compare Match C */
-#define TIMER3_OVF_vect_num  35
-#define TIMER3_OVF_vect      _VECTOR(35)  /* Timer/Counter3 Overflow */
-#define TWI_vect_num  36
-#define TWI_vect      _VECTOR(36)  /* 2-wire Serial Interface         */
-#define SPM_READY_vect_num  37
-#define SPM_READY_vect      _VECTOR(37)  /* Store Program Memory Read */
-#define TIMER4_COMPA_vect_num  38
-#define TIMER4_COMPA_vect      _VECTOR(38)  /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPB_vect_num  39
-#define TIMER4_COMPB_vect      _VECTOR(39)  /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPD_vect_num  40
-#define TIMER4_COMPD_vect      _VECTOR(40)  /* Timer/Counter4 Compare Match D */
-#define TIMER4_OVF_vect_num  41
-#define TIMER4_OVF_vect      _VECTOR(41)  /* Timer/Counter4 Overflow */
-#define TIMER4_FPF_vect_num  42
-#define TIMER4_FPF_vect      _VECTOR(42)  /* Timer/Counter4 Fault Protection Interrupt */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (43 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1280)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x3FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x88
-
-/**@}*/
-#endif /* _AVR_ATmega16U4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom2560.h b/cpukit/score/cpu/avr/avr/iom2560.h
deleted file mode 100644
index 461f93611f..0000000000
--- a/cpukit/score/cpu/avr/avr/iom2560.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom2560.h - definitions for ATmega2560 */
-
-#ifndef _AVR_IOM2560_H_
-#define _AVR_IOM2560_H_ 1
-
-#include <avr/iomxx0_1.h>
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x3FFFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x98
-#define SIGNATURE_2 0x01
-/** @} */
-
-#endif /* _AVR_IOM2560_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom2561.h b/cpukit/score/cpu/avr/avr/iom2561.h
deleted file mode 100644
index 3514efcd62..0000000000
--- a/cpukit/score/cpu/avr/avr/iom2561.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom2561.h - definitions for ATmega2561 */
-
-#ifndef _AVR_IOM2561_H_
-#define _AVR_IOM2561_H_ 1
-
-#include <avr/iomxx0_1.h>
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x3FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x98
-#define SIGNATURE_2 0x02
-
-
-#endif /* _AVR_IOM2561_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32.h b/cpukit/score/cpu/avr/avr/iom32.h
deleted file mode 100644
index 88465252d6..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/**
- * @file avr/iom32.h
- *
- * @brief Definitions for ATmega32
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Steinar Haugen
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM32_H_
-#define _AVR_IOM32_H_ 1
-
-/**
- *  @defgroup Avr_iom32 ATmega32 Definitons
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-#define TWBR    _SFR_IO8(0x00)
-#define TWSR    _SFR_IO8(0x01)
-#define TWAR    _SFR_IO8(0x02)
-#define TWDR    _SFR_IO8(0x03)
-
-/* ADC */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-#define ADCW    _SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-#define ADCSRA  _SFR_IO8(0x06)
-#define ADMUX   _SFR_IO8(0x07)
-
-/* analog comparator */
-#define ACSR    _SFR_IO8(0x08)
-
-/* USART */
-#define UBRRL   _SFR_IO8(0x09)
-#define UCSRB   _SFR_IO8(0x0A)
-#define UCSRA   _SFR_IO8(0x0B)
-#define UDR     _SFR_IO8(0x0C)
-
-/* SPI */
-#define SPCR    _SFR_IO8(0x0D)
-#define SPSR    _SFR_IO8(0x0E)
-#define SPDR    _SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND    _SFR_IO8(0x10)
-#define DDRD    _SFR_IO8(0x11)
-#define PORTD   _SFR_IO8(0x12)
-
-/* Port C */
-#define PINC    _SFR_IO8(0x13)
-#define DDRC    _SFR_IO8(0x14)
-#define PORTC   _SFR_IO8(0x15)
-
-/* Port B */
-#define PINB    _SFR_IO8(0x16)
-#define DDRB    _SFR_IO8(0x17)
-#define PORTB   _SFR_IO8(0x18)
-
-/* Port A */
-#define PINA    _SFR_IO8(0x19)
-#define DDRA    _SFR_IO8(0x1A)
-#define PORTA   _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UBRRH   _SFR_IO8(0x20)
-#define UCSRC   UBRRH
-
-#define WDTCR   _SFR_IO8(0x21)
-
-#define ASSR    _SFR_IO8(0x22)
-
-/* Timer 2 */
-#define OCR2    _SFR_IO8(0x23)
-#define TCNT2   _SFR_IO8(0x24)
-#define TCCR2   _SFR_IO8(0x25)
-
-/* Timer 1 */
-#define ICR1    _SFR_IO16(0x26)
-#define ICR1L   _SFR_IO8(0x26)
-#define ICR1H   _SFR_IO8(0x27)
-#define OCR1B   _SFR_IO16(0x28)
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-#define OCR1A   _SFR_IO16(0x2A)
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-#define TCNT1   _SFR_IO16(0x2C)
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-#define TCCR1B  _SFR_IO8(0x2E)
-#define TCCR1A  _SFR_IO8(0x2F)
-
-#define SFIOR   _SFR_IO8(0x30)
-
-#define OSCCAL  _SFR_IO8(0x31)
-#define OCDR    OSCCAL
-
-/* Timer 0 */
-#define TCNT0   _SFR_IO8(0x32)
-#define TCCR0   _SFR_IO8(0x33)
-
-#define MCUSR   _SFR_IO8(0x34)
-#define MCUCSR  MCUSR
-#define MCUCR   _SFR_IO8(0x35)
-
-#define TWCR    _SFR_IO8(0x36)
-
-#define SPMCR   _SFR_IO8(0x37)
-
-#define TIFR    _SFR_IO8(0x38)
-#define TIMSK   _SFR_IO8(0x39)
-
-#define GIFR    _SFR_IO8(0x3A)
-#define GIMSK   _SFR_IO8(0x3B)
-#define GICR    GIMSK
-
-#define OCR0    _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RXC_vect			_VECTOR(13)
-#define SIG_USART_RECV			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define SIG_USART_DATA			_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART, Tx Complete */
-#define USART_TXC_vect			_VECTOR(15)
-#define SIG_USART_TRANS			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(16)
-#define SIG_ADC				_VECTOR(16)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(17)
-#define SIG_EEPROM_READY		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(19)
-#define SIG_2WIRE_SERIAL		_VECTOR(19)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(20)
-#define SIG_SPM_READY			_VECTOR(20)
-
-#define _VECTORS_SIZE 84
-
-/* Bit numbers */
-
-/* GICR */
-#define INT1    7
-#define INT0    6
-#define INT2    5
-#define IVSEL   1
-#define IVCE    0
-
-/* GIFR */
-#define INTF1   7
-#define INTF0   6
-#define INTF2   5
-
-/* TIMSK */
-#define OCIE2   7
-#define TOIE2   6
-#define TICIE1  5
-#define OCIE1A  4
-#define OCIE1B  3
-#define TOIE1   2
-#define OCIE0   1
-#define TOIE0   0
-
-/* TIFR */
-#define OCF2    7
-#define TOV2    6
-#define ICF1    5
-#define OCF1A   4
-#define OCF1B   3
-#define TOV1    2
-#define OCF0    1
-#define TOV0    0
-
-/* SPMCR */
-#define SPMIE   7
-#define RWWSB   6
-/* bit 5 reserved */
-#define RWWSRE  4
-#define BLBSET  3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* TWCR */
-#define TWINT   7
-#define TWEA    6
-#define TWSTA   5
-#define TWSTO   4
-#define TWWC    3
-#define TWEN    2
-/* bit 1 reserved */
-#define TWIE    0
-
-/* TWAR */
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE   0
-
-/* TWSR */
-#define TWS7    7
-#define TWS6    6
-#define TWS5    5
-#define TWS4    4
-#define TWS3    3
-/* bit 2 reserved */
-#define TWPS1   1
-#define TWPS0   0
-
-/* MCUCR */
-#define SE      7
-#define SM2     6
-#define SM1     5
-#define SM0     4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* MCUCSR */
-#define JTD     7
-#define ISC2    6
-/* bit 5 reserved */
-#define JTRF    4
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-/* SFIOR */
-#define ADTS2   7
-#define ADTS1   6
-#define ADTS0   5
-/* bit 4 reserved */
-#define ACME    3
-#define PUD     2
-#define PSR2    1
-#define PSR10   0
-
-/* TCCR0 */
-#define FOC0    7
-#define WGM00   6
-#define COM01   5
-#define COM00   4
-#define WGM01   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-/* TCCR2 */
-#define FOC2    7
-#define WGM20   6
-#define COM21   5
-#define COM20   4
-#define WGM21   3
-#define CS22    2
-#define CS21    1
-#define CS20    0
-
-/* ASSR */
-/* bits 7-4 reserved */
-#define AS2     3
-#define TCN2UB  2
-#define OCR2UB  1
-#define TCR2UB  0
-
-/* TCCR1A */
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define FOC1A   3
-#define FOC1B   2
-#define WGM11   1
-#define WGM10   0
-
-/* TCCR1B */
-#define ICNC1   7
-#define ICES1   6
-/* bit 5 reserved */
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE   4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-/* PA7-PA0 = ADC7-ADC0 */
-/* PORTA */
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-/* DDRA */
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-/* PINA */
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = OC0/AIN1
-   PB2 = INT2/AIN0
-   PB1 = T1
-   PB0 = XCK/T0
- */
-
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/*
-   PC7 = TOSC2
-   PC6 = TOSC1
-   PC1 = SDA
-   PC0 = SCL
- */
-/* PORTC */
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-/* DDRC */
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-/* PINC */
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-/*
-   PD7 = OC2
-   PD6 = ICP
-   PD5 = OC1A
-   PD4 = OC1B
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* SPSR */
-#define SPIF    7
-#define WCOL    6
-/* bits 5-1 reserved */
-#define SPI2X   0
-
-/* SPCR */
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-/* UCSRA */
-#define RXC     7
-#define TXC     6
-#define UDRE    5
-#define FE      4
-#define DOR     3
-#define PE      2
-#define U2X     1
-#define MPCM    0
-
-/* UCSRB */
-#define RXCIE   7
-#define TXCIE   6
-#define UDRIE   5
-#define RXEN    4
-#define TXEN    3
-#define UCSZ2   2
-#define RXB8    1
-#define TXB8    0
-
-/* UCSRC */
-#define URSEL   7
-#define UMSEL   6
-#define UPM1    5
-#define UPM0    4
-#define USBS    3
-#define UCSZ1   2
-#define UCSZ0   1
-#define UCPOL   0
-
-/* ACSR */
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-/* ADCSRA */
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-/* ADMUX */
-#define REFS1   7
-#define REFS0   6
-#define ADLAR   5
-#define MUX4    4
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND      0x85F
-#define XRAMEND     RAMEND
-#define E2END       0x3FF
-#define E2PAGESIZE  4
-#define FLASHEND    0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x02
-
-/**@}*/
-#endif /* _AVR_IOM32_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom323.h b/cpukit/score/cpu/avr/avr/iom323.h
deleted file mode 100644
index d631ab5e06..0000000000
--- a/cpukit/score/cpu/avr/avr/iom323.h
+++ /dev/null
@@ -1,699 +0,0 @@
-/**
- * @file avr/iom323.h
- *
- * @brief Definitions for ATmega323
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM323_H_
-#define _AVR_IOM323_H_ 1
-
-/**
- *  @defgroup Avr_iom323 ATmega323 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom323.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-#define TWBR	_SFR_IO8(0x00)
-#define TWSR	_SFR_IO8(0x01)
-#define TWAR	_SFR_IO8(0x02)
-#define TWDR	_SFR_IO8(0x03)
-
-/* ADC */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-#define ADCSR	_SFR_IO8(0x06)
-#define ADMUX	_SFR_IO8(0x07)
-
-/* analog comparator */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART */
-#define UBRR	_SFR_IO8(0x09)
-#define UBRRL	UBRR
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Port C */
-#define PINC	_SFR_IO8(0x13)
-#define DDRC	_SFR_IO8(0x14)
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* Port A */
-#define PINA	_SFR_IO8(0x19)
-#define DDRA	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UBRRH	_SFR_IO8(0x20)
-#define UCSRC	UBRRH
-
-#define WDTCR	_SFR_IO8(0x21)
-
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer 2 */
-#define OCR2	_SFR_IO8(0x23)
-#define TCNT2	_SFR_IO8(0x24)
-#define TCCR2	_SFR_IO8(0x25)
-
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-#define SFIOR	_SFR_IO8(0x30)
-
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer 0 */
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUSR	_SFR_IO8(0x34)
-#define MCUCSR	MCUSR
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TWCR	_SFR_IO8(0x36)
-
-#define SPMCR	_SFR_IO8(0x37)
-
-#define TIFR	_SFR_IO8(0x38)
-#define TIMSK	_SFR_IO8(0x39)
-
-#define GIFR	_SFR_IO8(0x3A)
-#define GIMSK	_SFR_IO8(0x3B)
-#define GICR	GIMSK
-
-#define OCR0	_SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RXC_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART, Tx Complete */
-#define USART_TXC_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(16)
-#define SIG_ADC				_VECTOR(16)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(17)
-#define SIG_EEPROM_READY		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(19)
-#define SIG_2WIRE_SERIAL		_VECTOR(19)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(20)
-
-#define _VECTORS_SIZE 80
-
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-#define INT2	5
-#define IVSEL	1
-#define IVCE	0
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-#define INTF2	5
-
-/* TIMSK */
-#define OCIE2	7
-#define TOIE2	6
-#define TICIE1	5
-#define OCIE1A	4
-#define OCIE1B	3
-#define TOIE1	2
-#define OCIE0	1
-#define TOIE0	0
-
-/* TIFR */
-#define OCF2	7
-#define TOV2	6
-#define ICF1	5
-#define OCF1A	4
-#define OCF1B	3
-#define TOV1	2
-#define OCF0	1
-#define TOV0	0
-
-/* SPMCR */
-#define SPMIE	7
-#define ASB	6
-/* bit 5 reserved */
-#define ASRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* TWCR */
-#define TWINT	7
-#define TWEA	6
-#define TWSTA	5
-#define TWSTO	4
-#define TWWC	3
-#define TWEN	2
-#define TWI_TST	1
-#define TWIE	0
-
-/* TWAR */
-#define TWGCE	0
-
-/* TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-/* bits 2-0 reserved */
-
-/* MCUCR */
-/* bit 7 reserved (SM2?) */
-#define SE	7
-#define SM2	6
-#define SM1	5
-#define SM0	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* MCUCSR */
-#define JTD	7
-#define ISC2	6
-#define EIH	5
-#define JTRF	4
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-/* SFIOR */
-#define RPDD	7
-#define RPDC	6
-#define RPDB	5
-#define RPDA	4
-#define ACME	3
-#define PUD	2
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-#define FOC0	7
-#define PWM0	6
-#define COM01	5
-#define COM00	4
-#define CTC0	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define PWM2	6
-#define COM21	5
-#define COM20	4
-#define CTC2	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-/* bits 7-4 reserved */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define PWM11	1
-#define PWM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bit 5 reserved */
-#define CTC11	4
-#define CTC10	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* PA7-PA0 = ADC7-ADC0 */
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = AIN1
-   PB2 = AIN0
-   PB1 = T1
-   PB0 = T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/*
-   PC7 = TOSC2
-   PC6 = TOSC1
-   PC1 = SDA
-   PC0 = SCL
- */
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = OC2
-   PD6 = ICP
-   PD5 = OC1A
-   PD4 = OC1B
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/*
-   PE2 = ALE
-   PE1 = OC1B
-   PE0 = ICP / INT2
- */
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSRA */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-#define PE	2
-#define U2X	1
-#define MPCM	0
-
-/* UCSRB */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define UCSZ2	2
-#define CHR9	2
-#define RXB8	1
-#define TXB8	0
-
-/* UCSRC */
-#define URSEL	7
-#define UMSEL	6
-#define UPM1	5
-#define UPM0	4
-#define USBS	3
-#define UCSZ1	2
-#define UCSZ0	1
-#define UCPOL	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* ADCSR */
-#define ADEN	7
-#define ADSC	6
-#define ADFR	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-/* ADMUX */
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-#define MUX4	4
-#define MUX3	3
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x85F
-#define XRAMEND		RAMEND
-#define E2END		0x3FF
-#define E2PAGESIZE  0
-#define FLASHEND	0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x01
-
-/**@}*/
-#endif /* _AVR_IOM323_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom324.h b/cpukit/score/cpu/avr/avr/iom324.h
deleted file mode 100644
index 09fbd51f66..0000000000
--- a/cpukit/score/cpu/avr/avr/iom324.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * @file avr/iom324.h
- *
- * @brief Definitions for ATmega324
- */
-
-/*
- *   Copyright (c) 2005, 2006 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM324_H_
-#define _AVR_IOM324_H_ 1
-
-/**
- *  @defgroup Avr_iom324 ATmega324 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomxx4.h>
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x08FF
-#define XRAMEND         RAMEND
-#define E2END           0x3FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature (ATmega324P) */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x08
-
-/**@}*/
-#endif /* _AVR_IOM324_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom324pa.h b/cpukit/score/cpu/avr/avr/iom324pa.h
deleted file mode 100644
index e28d887cf5..0000000000
--- a/cpukit/score/cpu/avr/avr/iom324pa.h
+++ /dev/null
@@ -1,1354 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom324pa.h - definitions for ATmega324PA */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom324pa.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega324PA_H_
-#define _AVR_ATmega324PA_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR0 _SFR_IO8(0x2C)
-#define SPR00 0
-#define SPR10 1
-#define CPHA0 2
-#define CPOL0 3
-#define MSTR0 4
-#define DORD0 5
-#define SPE0 6
-#define SPIE0 7
-
-#define SPSR0 _SFR_IO8(0x2D)
-#define SPI2X0 0
-#define WCOL0 6
-#define SPIF0 7
-
-#define SPDR0 _SFR_IO8(0x2E)
-#define SPDRB0 0
-#define SPDRB1 1
-#define SPDRB2 2
-#define SPDRB3 3
-#define SPDRB4 4
-#define SPDRB5 5
-#define SPDRB6 6
-#define SPDRB7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRUSART1 4
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define PCMSK3 _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A_0 0
-#define OCR2A_1 1
-#define OCR2A_2 2
-#define OCR2A_3 3
-#define OCR2A_4 4
-#define OCR2A_5 5
-#define OCR2A_6 6
-#define OCR2A_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B_0 0
-#define OCR2B_1 1
-#define OCR2B_2 2
-#define OCR2B_3 3
-#define OCR2B_4 4
-#define OCR2B_5 5
-#define OCR2B_6 6
-#define OCR2B_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define _UBRR0 0
-#define _UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR_0 0
-#define UBRR_1 1
-#define UBRR_2 2
-#define UBRR_3 3
-#define UBRR_4 4
-#define UBRR_5 5
-#define UBRR_6 6
-#define UBRR_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR_8 0
-#define UBRR_9 1
-#define UBRR_10 2
-#define UBRR_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define PCINT0_vect_num  4
-#define PCINT0_vect      _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  5
-#define PCINT1_vect      _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  6
-#define PCINT2_vect      _VECTOR(6)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  7
-#define PCINT3_vect      _VECTOR(7)  /* Pin Change Interrupt Request 3 */
-#define WDT_vect_num  8
-#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  9
-#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  10
-#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect_num  11
-#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  12
-#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  13
-#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  14
-#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  15
-#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  16
-#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  17
-#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  18
-#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  19
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  20
-#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  21
-#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  22
-#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
-#define ANALOG_COMP_vect_num  23
-#define ANALOG_COMP_vect      _VECTOR(23)  /* Analog Comparator */
-#define ADC_vect_num  24
-#define ADC_vect      _VECTOR(24)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  25
-#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect_num  26
-#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect_num  27
-#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
-#define USART1_RX_vect_num  28
-#define USART1_RX_vect      _VECTOR(28)  /* USART1 RX complete */
-#define USART1_UDRE_vect_num  29
-#define USART1_UDRE_vect      _VECTOR(29)  /* USART1 Data Register Empty */
-#define USART1_TX_vect_num  30
-#define USART1_TX_vect      _VECTOR(30)  /* USART1 TX complete */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (2048)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x11
-
-
-/* Device Pin Definitions */
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   5
-
-#define PCINT13_DDR   DDRB
-#define PCINT13_PORT  PORTB
-#define PCINT13_PIN   PINB
-#define PCINT13_BIT   5
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   6
-
-#define PCINT14_DDR   DDRB
-#define PCINT14_PORT  PORTB
-#define PCINT14_PIN   PINB
-#define PCINT14_BIT   6
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   7
-
-#define PCINT15_DDR   DDRB
-#define PCINT15_PORT  PORTB
-#define PCINT15_PIN   PINB
-#define PCINT15_BIT   7
-
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define PCINT24_DDR   DDRD
-#define PCINT24_PORT  PORTD
-#define PCINT24_PIN   PIND
-#define PCINT24_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define PCINT25_DDR   DDRD
-#define PCINT25_PORT  PORTD
-#define PCINT25_PIN   PIND
-#define PCINT25_BIT   1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define PCINT26_DDR   DDRD
-#define PCINT26_PORT  PORTD
-#define PCINT26_PIN   PIND
-#define PCINT26_BIT   2
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define PCINT27_DDR   DDRD
-#define PCINT27_PORT  PORTD
-#define PCINT27_PIN   PIND
-#define PCINT27_BIT   3
-
-#define OC1B_DDR   DDRD
-#define OC1B_PORT  PORTD
-#define OC1B_PIN   PIND
-#define OC1B_BIT   4
-
-#define PCINT28_DDR   DDRD
-#define PCINT28_PORT  PORTD
-#define PCINT28_PIN   PIND
-#define PCINT28_BIT   4
-
-#define OC1A_DDR   DDRD
-#define OC1A_PORT  PORTD
-#define OC1A_PIN   PIND
-#define OC1A_BIT   5
-
-#define PCINT29_DDR   DDRD
-#define PCINT29_PORT  PORTD
-#define PCINT29_PIN   PIND
-#define PCINT29_BIT   5
-
-#define ICP_DDR   DDRD
-#define ICP_PORT  PORTD
-#define ICP_PIN   PIND
-#define ICP_BIT   6
-
-#define OC2B_DDR   DDRD
-#define OC2B_PORT  PORTD
-#define OC2B_PIN   PIND
-#define OC2B_BIT   6
-
-#define PCINT30_DDR   DDRD
-#define PCINT30_PORT  PORTD
-#define PCINT30_PIN   PIND
-#define PCINT30_BIT   6
-
-#define OC2A_DDR   DDRD
-#define OC2A_PORT  PORTD
-#define OC2A_PIN   PIND
-#define OC2A_BIT   7
-
-#define PCINT31_DDR   DDRD
-#define PCINT31_PORT  PORTD
-#define PCINT31_PIN   PIND
-#define PCINT31_BIT   7
-
-#define SCL_DDR   DDRC
-#define SCL_PORT  PORTC
-#define SCL_PIN   PINC
-#define SCL_BIT   0
-
-#define PCINT16_DDR   DDRC
-#define PCINT16_PORT  PORTC
-#define PCINT16_PIN   PINC
-#define PCINT16_BIT   0
-
-#define SDA_DDR   DDRC
-#define SDA_PORT  PORTC
-#define SDA_PIN   PINC
-#define SDA_BIT   1
-
-#define PCINT17_DDR   DDRC
-#define PCINT17_PORT  PORTC
-#define PCINT17_PIN   PINC
-#define PCINT17_BIT   1
-
-#define PCINT18_DDR   DDRC
-#define PCINT18_PORT  PORTC
-#define PCINT18_PIN   PINC
-#define PCINT18_BIT   2
-
-#define PCINT19_DDR   DDRC
-#define PCINT19_PORT  PORTC
-#define PCINT19_PIN   PINC
-#define PCINT19_BIT   3
-
-#define PCINT20_DDR   DDRC
-#define PCINT20_PORT  PORTC
-#define PCINT20_PIN   PINC
-#define PCINT20_BIT   4
-
-#define PCINT21_DDR   DDRC
-#define PCINT21_PORT  PORTC
-#define PCINT21_PIN   PINC
-#define PCINT21_BIT   5
-
-#define PCINT22_DDR   DDRC
-#define PCINT22_PORT  PORTC
-#define PCINT22_PIN   PINC
-#define PCINT22_BIT   6
-
-#define PCINT23_DDR   DDRC
-#define PCINT23_PORT  PORTC
-#define PCINT23_PIN   PINC
-#define PCINT23_BIT   7
-
-#define ADC7_DDR   DDRA
-#define ADC7_PORT  PORTA
-#define ADC7_PIN   PINA
-#define ADC7_BIT   7
-
-#define PCINT7_DDR   DDRA
-#define PCINT7_PORT  PORTA
-#define PCINT7_PIN   PINA
-#define PCINT7_BIT   7
-
-#define ADC6_DDR   DDRA
-#define ADC6_PORT  PORTA
-#define ADC6_PIN   PINA
-#define ADC6_BIT   6
-
-#define PCINT6_DDR   DDRA
-#define PCINT6_PORT  PORTA
-#define PCINT6_PIN   PINA
-#define PCINT6_BIT   6
-
-#define ADC5_DDR   DDRA
-#define ADC5_PORT  PORTA
-#define ADC5_PIN   PINA
-#define ADC5_BIT   5
-
-#define PCINT5_DDR   DDRA
-#define PCINT5_PORT  PORTA
-#define PCINT5_PIN   PINA
-#define PCINT5_BIT   5
-
-#define ADC4_DDR   DDRA
-#define ADC4_PORT  PORTA
-#define ADC4_PIN   PINA
-#define ADC4_BIT   4
-
-#define PCINT4_DDR   DDRA
-#define PCINT4_PORT  PORTA
-#define PCINT4_PIN   PINA
-#define PCINT4_BIT   4
-
-#define ADC3_DDR   DDRA
-#define ADC3_PORT  PORTA
-#define ADC3_PIN   PINA
-#define ADC3_BIT   3
-
-#define PCINT3_DDR   DDRA
-#define PCINT3_PORT  PORTA
-#define PCINT3_PIN   PINA
-#define PCINT3_BIT   3
-
-#define ADC2_DDR   DDRA
-#define ADC2_PORT  PORTA
-#define ADC2_PIN   PINA
-#define ADC2_BIT   2
-
-#define PCINT2_DDR   DDRA
-#define PCINT2_PORT  PORTA
-#define PCINT2_PIN   PINA
-#define PCINT2_BIT   2
-
-#define ADC1_DDR   DDRA
-#define ADC1_PORT  PORTA
-#define ADC1_PIN   PINA
-#define ADC1_BIT   1
-
-#define PCINT1_DDR   DDRA
-#define PCINT1_PORT  PORTA
-#define PCINT1_PIN   PINA
-#define PCINT1_BIT   1
-
-#define ADC0_DDR   DDRA
-#define ADC0_PORT  PORTA
-#define ADC0_PIN   PINA
-#define ADC0_BIT   0
-
-#define PCINT0_DDR   DDRA
-#define PCINT0_PORT  PORTA
-#define PCINT0_PIN   PINA
-#define PCINT0_BIT   0
-
-#define XCK_DDR   DDRB
-#define XCK_PORT  PORTB
-#define XCK_PIN   PINB
-#define XCK_BIT   0
-
-#define T0_DDR   DDRB
-#define T0_PORT  PORTB
-#define T0_PIN   PINB
-#define T0_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define T1_DDR   DDRB
-#define T1_PORT  PORTB
-#define T1_PIN   PINB
-#define T1_BIT   1
-
-#define CLKO_DDR   DDRB
-#define CLKO_PORT  PORTB
-#define CLKO_PIN   PINB
-#define CLKO_BIT   1
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define AIN0_DDR   DDRB
-#define AIN0_PORT  PORTB
-#define AIN0_PIN   PINB
-#define AIN0_BIT   2
-
-#define INT2_DDR   DDRB
-#define INT2_PORT  PORTB
-#define INT2_PIN   PINB
-#define INT2_BIT   2
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define AIN1_DDR   DDRB
-#define AIN1_PORT  PORTB
-#define AIN1_PIN   PINB
-#define AIN1_BIT   3
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   3
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   4
-
-#define OC0B_DDR   DDRB
-#define OC0B_PORT  PORTB
-#define OC0B_PIN   PINB
-#define OC0B_BIT   4
-
-#define PCINT12_DDR   DDRB
-#define PCINT12_PORT  PORTB
-#define PCINT12_PIN   PINB
-#define PCINT12_BIT   4
-
-#endif /* _AVR_ATmega324PA_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom325.h b/cpukit/score/cpu/avr/avr/iom325.h
deleted file mode 100644
index 7d4f582aaf..0000000000
--- a/cpukit/score/cpu/avr/avr/iom325.h
+++ /dev/null
@@ -1,837 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega325 and ATmega325P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom325.h - definitions for ATmega325 and ATmega325P.  */
-
-#ifndef _AVR_IOM325_H_
-#define _AVR_IOM325_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom325.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom325  ATmega325 and ATmega325P Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#if defined(__AVR_ATmega325P__)
-#define BODSE   5
-#define BODS    6
-#endif
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* Vector 22 is Reserved */
-
-#define _VECTORS_SIZE 92
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x8FF
-#define XRAMEND         RAMEND
-#define E2END           0x3FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x05
-
-/** @} */
-
-#endif /* _AVR_IOM325_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom3250.h b/cpukit/score/cpu/avr/avr/iom3250.h
deleted file mode 100644
index 6c3cb35a0f..0000000000
--- a/cpukit/score/cpu/avr/avr/iom3250.h
+++ /dev/null
@@ -1,936 +0,0 @@
-/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P.  */
-
-#ifndef _AVR_IOM3250_H_
-#define _AVR_IOM3250_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom3250.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-#define PCIF2   6
-#define PCIF3   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-#define PCIE2   6
-#define PCIE3   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/*
- * 6-char sequence denoting where to find the EEPROM registers in 
- * memory space.
- * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
- * subroutines.
- * First two letters:  EECR address.
- * Second two letters: EEDR address.
- * Last two letters:   EEAR address.  
- */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#if defined(__AVR_ATmega3250P__)
-#define BODSE   5
-#define BODS    6
-#endif
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3  _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xD7] */
-
-#define PINH    _SFR_MEM8(0xD8)
-#define PINH7   7
-#define PINH6   6
-#define PINH5   5
-#define PINH4   4
-#define PINH3   3
-#define PINH2   2
-#define PINH1   1
-#define PINH0   0
-
-#define DDRH    _SFR_MEM8(0xD9)
-#define DDH7    7
-#define DDH6    6
-#define DDH5    5
-#define DDH4    4
-#define DDH3    3
-#define DDH2    2
-#define DDH1    1
-#define DDH0    0
-
-#define PORTH   _SFR_MEM8(0xDA)
-#define PH7     7
-#define PH6     6
-#define PH5     5
-#define PH4     4
-#define PH3     3
-#define PH2     2
-#define PH1     1
-#define PH0     0
-
-#define PINJ    _SFR_MEM8(0xDB)
-#define PINJ6   6
-#define PINJ5   5
-#define PINJ4   4
-#define PINJ3   3
-#define PINJ2   2
-#define PINJ1   1
-#define PINJ0   0
-
-#define DDRJ    _SFR_MEM8(0xDC)
-#define DDJ6    6
-#define DDJ5    5
-#define DDJ4    4
-#define DDJ3    3
-#define DDJ2    2
-#define DDJ1    1
-#define DDJ0    0
-
-#define PORTJ   _SFR_MEM8(0xDD)
-#define PJ6     6
-#define PJ5     5
-#define PJ4     4
-#define PJ3     3
-#define PJ2     2
-#define PJ1     1
-#define PJ0     0
-
-/* Reserved [0xDE..0xFF] */
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(13)
-#define USART0_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define USART0_UDRE_vect		_VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(23)
-#define SIG_PIN_CHANGE2			_VECTOR(23)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect			_VECTOR(24)
-#define SIG_PIN_CHANGE3			_VECTOR(24)
-
-#define _VECTORS_SIZE 100
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE    128
-#define RAMEND          0x8FF
-#define XRAMEND         RAMEND
-#define E2END           0x3FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x7FFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x06
-/** @} */
-
-#endif /* _AVR_IOM3250_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom328p.h b/cpukit/score/cpu/avr/avr/iom328p.h
deleted file mode 100644
index b2bb6b58bf..0000000000
--- a/cpukit/score/cpu/avr/avr/iom328p.h
+++ /dev/null
@@ -1,891 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega328P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom328p.h - definitions for ATmega328P. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom328p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IOM328P_H_
-#define _AVR_IOM328P_H_ 1
-
-/**
- * @defgroup AvrDef_iom328p ATmega328P Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define _EEPROM_REG_LOCATIONS_ 1F2021
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCPHA0 1
-#define UCSZ01 2
-#define UDORD0 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect         _VECTOR(1)   /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)   /* External Interrupt Request 1 */
-#define PCINT0_vect       _VECTOR(3)   /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(4)   /* Pin Change Interrupt Request 0 */
-#define PCINT2_vect       _VECTOR(5)   /* Pin Change Interrupt Request 1 */
-#define WDT_vect          _VECTOR(6)   /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(7)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(8)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */ 
-#define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(16)  /* Timer/Couner0 Overflow */
-#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect     _VECTOR(18)  /* USART Rx Complete */
-#define USART_UDRE_vect   _VECTOR(19)  /* USART, Data Register Empty */
-#define USART_TX_vect     _VECTOR(20)  /* USART Tx Complete */
-#define ADC_vect          _VECTOR(21)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(22)  /* EEPROM Ready */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define TWI_vect          _VECTOR(24)  /* Two-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(25)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE (26 * 4)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND       0x8FF     /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x3FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x7FFF
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x0F
-
-/** @} */
-
-#endif  /* _AVR_IOM328P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom329.h b/cpukit/score/cpu/avr/avr/iom329.h
deleted file mode 100644
index a7b5efdfd1..0000000000
--- a/cpukit/score/cpu/avr/avr/iom329.h
+++ /dev/null
@@ -1,1031 +0,0 @@
-/* Copyright (c) 2004 Eric B. Weddington
-   Copyright (c) 2005, 2006, 2007 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom329.h - definitions for ATmega329 and ATmega329P.  */
-
-#ifndef _AVR_IOM329_H_
-#define _AVR_IOM329_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom329.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 
- * 6-char sequence denoting where to find the EEPROM registers in 
- * memory space.
- * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
- * subroutines.
- * First two letters:  EECR address.
- * Second two letters: EEDR address.
- * Last two letters:   EEAR address.  
- */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#if defined(__AVR_ATmega329P__)
-#define BODSE   5
-#define BODS    6
-#endif
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xE3] */
-
-#define LCDCRA  _SFR_MEM8(0XE4)
-#define LCDBL   0
-#if defined(__AVR_ATmega329P__)
-#define LCDCCD  1
-#define LCDBD   2
-#endif
-#define LCDIE   3
-#define LCDIF   4
-#define LCDAB   6
-#define LCDEN   7
-
-#define LCDCRB  _SFR_MEM8(0XE5)
-#define LCDPM0  0
-#define LCDPM1  1
-#define LCDPM2  2
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B   6
-#define LCDCS   7
-
-#define LCDFRR  _SFR_MEM8(0XE6)
-#define LCDCD0  0
-#define LCDCD1  1
-#define LCDCD2  2
-#define LCDPS0  4
-#define LCDPS1  5
-#define LCDPS2  6
-
-#define LCDCCR  _SFR_MEM8(0XE7)
-#define LCDCC0  0
-#define LCDCC1  1
-#define LCDCC2  2
-#define LCDCC3  3
-#if defined(__AVR_ATmega329P__)
-#define LCDMDT  4
-#endif
-#define LCDDC0  5
-#define LCDDC1  6
-#define LCDDC2  7
-
-/* Reserved [0xE8..0xEB] */
-
-#define LCDDR00 _SFR_MEM8(0XEC)
-#define SEG000  0
-#define SEG001  1
-#define SEG002  2
-#define SEG003  3
-#define SEG004  4
-#define SEG005  5
-#define SEG006  6
-#define SEG007  7
-
-#define LCDDR01 _SFR_MEM8(0XED)
-#define SEG008  0
-#define SEG009  1
-#define SEG010  2
-#define SEG011  3
-#define SEG012  4
-#define SEG013  5
-#define SEG014  6
-#define SEG015  7
-
-#define LCDDR02 _SFR_MEM8(0XEE)
-#define SEG016  0
-#define SEG017  1
-#define SEG018  2
-#define SEG019  3
-#define SEG020  4
-#define SEG021  5
-#define SEG022  6
-#define SEG023  7
-
-#define LCDDR03 _SFR_MEM8(0XEF)
-#define SEG024  0
-
-/* Reserved [0xF0] */
-
-#define LCDDR05 _SFR_MEM8(0XF1)
-#define SEG100  0
-#define SEG101  1
-#define SEG102  2
-#define SEG103  3
-#define SEG104  4
-#define SEG105  5
-#define SEG106  6
-#define SEG107  7
-
-#define LCDDR06 _SFR_MEM8(0XF2)
-#define SEG108  0
-#define SEG109  1
-#define SEG110  2
-#define SEG111  3
-#define SEG112  4
-#define SEG113  5
-#define SEG114  6
-#define SEG115  7
-
-#define LCDDR07 _SFR_MEM8(0XF3)
-#define SEG116  0
-#define SEG117  1
-#define SEG118  2
-#define SEG119  3
-#define SEG120  4
-#define SEG121  5
-#define SEG122  6
-#define SEG123  7
-
-#define LCDDR08 _SFR_MEM8(0XF4)
-#define SEG124  0
-
-/* Reserved [0xF5] */
-
-#define LCDDR10 _SFR_MEM8(0XF6)
-#define SEG200  0
-#define SEG201  1
-#define SEG202  2
-#define SEG203  3
-#define SEG204  4
-#define SEG205  5
-#define SEG206  6
-#define SEG207  7
-
-#define LCDDR11 _SFR_MEM8(0XF7)
-#define SEG208  0
-#define SEG209  1
-#define SEG210  2
-#define SEG211  3
-#define SEG212  4
-#define SEG213  5
-#define SEG214  6
-#define SEG215  7
-
-#define LCDDR12 _SFR_MEM8(0XF8)
-#define SEG216  0
-#define SEG217  1
-#define SEG218  2
-#define SEG219  3
-#define SEG220  4
-#define SEG221  5
-#define SEG222  6
-#define SEG223  7
-
-#define LCDDR13 _SFR_MEM8(0XF9)
-#define SEG224  0
-
-/* Reserved [0xFA] */
-
-#define LCDDR15 _SFR_MEM8(0XFB)
-#define SEG300  0
-#define SEG301  1
-#define SEG302  2
-#define SEG303  3
-#define SEG304  4
-#define SEG305  5
-#define SEG306  6
-#define SEG307  7
-
-#define LCDDR16 _SFR_MEM8(0XFC)
-#define SEG308  0
-#define SEG309  1
-#define SEG310  2
-#define SEG311  3
-#define SEG312  4
-#define SEG313  5
-#define SEG314  6
-#define SEG315  7
-
-#define LCDDR17 _SFR_MEM8(0XFD)
-#define SEG316  0
-#define SEG217  1
-#define SEG318  2
-#define SEG319  3
-#define SEG320  4
-#define SEG321  5
-#define SEG322  6
-#define SEG323  7
-
-#define LCDDR18 _SFR_MEM8(0XFE)
-#define SEG324  0
-
-/* Reserved [0xFF] */
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-#define _VECTORS_SIZE 92
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE    128
-#define RAMEND          0x8FF
-#define XRAMEND         RAMEND
-#define E2END           0x3FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x7FFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & \
-                       FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x03
-/** @} */
-
-#endif /* _AVR_IOM329_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom3290.h b/cpukit/score/cpu/avr/avr/iom3290.h
deleted file mode 100644
index f349821f77..0000000000
--- a/cpukit/score/cpu/avr/avr/iom3290.h
+++ /dev/null
@@ -1,1169 +0,0 @@
-/**
- * @file avr/iom3290.h
- *
- * @brief Definitions for ATmega3290 and ATmega3290P
- */
-
-/*
- *   Copyright (c) 2004 Eric B. Weddington
- *   Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM3290_H_
-#define _AVR_IOM3290_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom3290.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_iom3290 ATmega3290, ATmega3290P Defintions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-#define PCIF2   6
-#define PCIF3   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-#define PCIE2   6
-#define PCIE3   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#if defined(__AVR_ATmega3290P__)
-#define BODSE   5
-#define BODS    6
-#endif
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3  _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xD7] */
-
-#define PINH    _SFR_MEM8(0xD8)
-#define PINH7   7
-#define PINH6   6
-#define PINH5   5
-#define PINH4   4
-#define PINH3   3
-#define PINH2   2
-#define PINH1   1
-#define PINH0   0
-
-#define DDRH    _SFR_MEM8(0xD9)
-#define DDH7    7
-#define DDH6    6
-#define DDH5    5
-#define DDH4    4
-#define DDH3    3
-#define DDH2    2
-#define DDH1    1
-#define DDH0    0
-
-#define PORTH   _SFR_MEM8(0xDA)
-#define PH7     7
-#define PH6     6
-#define PH5     5
-#define PH4     4
-#define PH3     3
-#define PH2     2
-#define PH1     1
-#define PH0     0
-
-#define PINJ    _SFR_MEM8(0xDB)
-#define PINJ6   6
-#define PINJ5   5
-#define PINJ4   4
-#define PINJ3   3
-#define PINJ2   2
-#define PINJ1   1
-#define PINJ0   0
-
-#define DDRJ    _SFR_MEM8(0xDC)
-#define DDJ6    6
-#define DDJ5    5
-#define DDJ4    4
-#define DDJ3    3
-#define DDJ2    2
-#define DDJ1    1
-#define DDJ0    0
-
-#define PORTJ   _SFR_MEM8(0xDD)
-#define PJ6     6
-#define PJ5     5
-#define PJ4     4
-#define PJ3     3
-#define PJ2     2
-#define PJ1     1
-#define PJ0     0
-
-/* Reserved [0xDE..0xE3] */
-
-#define LCDCRA  _SFR_MEM8(0XE4)
-#define LCDBL   0
-#if defined(__AVR_ATmega3290P__)
-#define LCDCCD  1
-#define LCDBD   2
-#endif
-#define LCDIE   3
-#define LCDIF   4
-#define LCDAB   6
-#define LCDEN   7
-
-#define LCDCRB  _SFR_MEM8(0XE5)
-#define LCDPM0  0
-#define LCDPM1  1
-#define LCDPM2  2
-#define LCDPM3  3
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B   6
-#define LCDCS   7
-
-#define LCDFRR  _SFR_MEM8(0XE6)
-#define LCDCD0  0
-#define LCDCD1  1
-#define LCDCD2  2
-#define LCDPS0  4
-#define LCDPS1  5
-#define LCDPS2  6
-
-#define LCDCCR  _SFR_MEM8(0XE7)
-#define LCDCC0  0
-#define LCDCC1  1
-#define LCDCC2  2
-#define LCDCC3  3
-#if defined(__AVR_ATmega3290P__)
-#define LCDMDT  4
-#endif
-#define LCDDC0  5
-#define LCDDC1  6
-#define LCDDC2  7
-
-/* Reserved [0xE8..0xEB] */
-
-#define LCDDR00 _SFR_MEM8(0XEC)
-#define SEG000  0
-#define SEG001  1
-#define SEG002  2
-#define SEG003  3
-#define SEG004  4
-#define SEG005  5
-#define SEG006  6
-#define SEG007  7
-
-#define LCDDR01 _SFR_MEM8(0XED)
-#define SEG008  0
-#define SEG009  1
-#define SEG010  2
-#define SEG011  3
-#define SEG012  4
-#define SEG013  5
-#define SEG014  6
-#define SEG015  7
-
-#define LCDDR02 _SFR_MEM8(0XEE)
-#define SEG016  0
-#define SEG017  1
-#define SEG018  2
-#define SEG019  3
-#define SEG020  4
-#define SEG021  5
-#define SEG022  6
-#define SEG023  7
-
-#define LCDDR03 _SFR_MEM8(0XEF)
-#define SEG024  0
-#define SEG025  1
-#define SEG026  2
-#define SEG027  3
-#define SEG028  4
-#define SEG029  5
-#define SEG030  6
-#define SEG031  7
-
-#define LCDDR04 _SFR_MEM8(0XF0)
-#define SEG032  0
-#define SEG033  1
-#define SEG034  2
-#define SEG035  3
-#define SEG036  4
-#define SEG037  5
-#define SEG038  6
-#define SEG039  7
-
-#define LCDDR05 _SFR_MEM8(0XF1)
-#define SEG100  0
-#define SEG101  1
-#define SEG102  2
-#define SEG103  3
-#define SEG104  4
-#define SEG105  5
-#define SEG106  6
-#define SEG107  7
-
-#define LCDDR06 _SFR_MEM8(0XF2)
-#define SEG108  0
-#define SEG109  1
-#define SEG110  2
-#define SEG111  3
-#define SEG112  4
-#define SEG113  5
-#define SEG114  6
-#define SEG115  7
-
-#define LCDDR07 _SFR_MEM8(0XF3)
-#define SEG116  0
-#define SEG117  1
-#define SEG118  2
-#define SEG119  3
-#define SEG120  4
-#define SEG121  5
-#define SEG122  6
-#define SEG123  7
-
-#define LCDDR08 _SFR_MEM8(0XF4)
-#define SEG124  0
-#define SEG125  1
-#define SEG126  2
-#define SEG127  3
-#define SEG128  4
-#define SEG129  5
-#define SEG130  6
-#define SEG131  7
-
-#define LCDDR09 _SFR_MEM8(0XF5)
-#define SEG132  0
-#define SEG133  1
-#define SEG134  2
-#define SEG135  3
-#define SEG136  4
-#define SEG137  5
-#define SEG138  6
-#define SEG139  7
-
-#define LCDDR10 _SFR_MEM8(0XF6)
-#define SEG200  0
-#define SEG201  1
-#define SEG202  2
-#define SEG203  3
-#define SEG204  4
-#define SEG205  5
-#define SEG206  6
-#define SEG207  7
-
-#define LCDDR11 _SFR_MEM8(0XF7)
-#define SEG208  0
-#define SEG209  1
-#define SEG210  2
-#define SEG211  3
-#define SEG212  4
-#define SEG213  5
-#define SEG214  6
-#define SEG215  7
-
-#define LCDDR12 _SFR_MEM8(0XF8)
-#define SEG216  0
-#define SEG217  1
-#define SEG218  2
-#define SEG219  3
-#define SEG220  4
-#define SEG221  5
-#define SEG222  6
-#define SEG223  7
-
-#define LCDDR13 _SFR_MEM8(0XF9)
-#define SEG224  0
-#define SEG225  1
-#define SEG226  2
-#define SEG227  3
-#define SEG228  4
-#define SEG229  5
-#define SEG230  6
-#define SEG231  7
-
-#define LCDDR14 _SFR_MEM8(0XFA)
-#define SEG232  0
-#define SEG233  1
-#define SEG234  2
-#define SEG235  3
-#define SEG236  4
-#define SEG237  5
-#define SEG238  6
-#define SEG239  7
-
-#define LCDDR15 _SFR_MEM8(0XFB)
-#define SEG300  0
-#define SEG301  1
-#define SEG302  2
-#define SEG303  3
-#define SEG304  4
-#define SEG305  5
-#define SEG306  6
-#define SEG307  7
-
-#define LCDDR16 _SFR_MEM8(0XFC)
-#define SEG308  0
-#define SEG309  1
-#define SEG310  2
-#define SEG311  3
-#define SEG312  4
-#define SEG313  5
-#define SEG314  6
-#define SEG315  7
-
-#define LCDDR17 _SFR_MEM8(0XFD)
-#define SEG316  0
-#define SEG217  1
-#define SEG318  2
-#define SEG319  3
-#define SEG320  4
-#define SEG321  5
-#define SEG322  6
-#define SEG323  7
-
-#define LCDDR18 _SFR_MEM8(0XFE)
-#define SEG324  0
-#define SEG325  1
-#define SEG326  2
-#define SEG327  3
-#define SEG328  4
-#define SEG329  5
-#define SEG330  6
-#define SEG331  7
-
-#define LCDDR19 _SFR_MEM8(0XFF)
-#define SEG332  0
-#define SEG333  1
-#define SEG334  2
-#define SEG335  3
-#define SEG336  4
-#define SEG337  5
-#define SEG338  6
-#define SEG339  7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(23)
-#define SIG_PIN_CHANGE2			_VECTOR(23)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect			_VECTOR(24)
-#define SIG_PIN_CHANGE3			_VECTOR(24)
-
-#define _VECTORS_SIZE 100
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x8FF
-#define XRAMEND         RAMEND
-#define E2END           0x3FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x04
-
-/** @} */
-#endif /* _AVR_IOM3290_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32c1.h b/cpukit/score/cpu/avr/avr/iom32c1.h
deleted file mode 100644
index a0d4017026..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32c1.h
+++ /dev/null
@@ -1,1308 +0,0 @@
-/**
- * @file avr/iom32c1.h
- *
- * @brief Definitions for ATmega32C1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32c1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega32C1_H_
-#define _AVR_ATmega32C1_H_ 1
-
-/**
- * @defgroup Avr_iom32c1 ATmega32C1 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 6
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRLIN 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC 5
-#define PRCAN 6
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define PCMSK3 _SFR_MEM8(0x6D)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x75)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0TS2 2
-#define AMPCMP0 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x76)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1TS2 2
-#define AMPCMP1 3
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#define AMP2CSR _SFR_MEM8(0x77)
-#define AMP2TS0 0
-#define AMP2TS1 1
-#define AMP2TS2 2
-#define AMPCMP2 3
-#define AMP2G0 4
-#define AMP2G1 5
-#define AMP2IS 6
-#define AMP2EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define AREFEN 5
-#define ISRCEN 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-#define AMP2PD 6
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define DACON _SFR_MEM8(0x90)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0x91)
-
-#define DACL _SFR_MEM8(0x91)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0x92)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0x94)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define ACCKSEL 3
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0x95)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x96)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x97)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define CANGCON _SFR_MEM8(0xD8)
-#define SWRES 0
-#define ENASTB 1
-#define TEST 2
-#define LISTEN 3
-#define SYNTTC 4
-#define TTC 5
-#define OVRQ 6
-#define ABRQ 7
-
-#define CANGSTA _SFR_MEM8(0xD9)
-#define ERRP 0
-#define BOFF 1
-#define ENFG 2
-#define RXBSY 3
-#define TXBSY 4
-#define OVFG 6
-
-#define CANGIT _SFR_MEM8(0xDA)
-#define AERG 0
-#define FERG 1
-#define CERG 2
-#define SERG 3
-#define BXOK 4
-#define OVRTIM 5
-#define BOFFIT 6
-#define CANIT 7
-
-#define CANGIE _SFR_MEM8(0xDB)
-#define ENOVRT 0
-#define ENERG 1
-#define ENBX 2
-#define ENERR 3
-#define ENTX 4
-#define ENRX 5
-#define ENBOFF 6
-#define ENIT 7
-
-#define CANEN2 _SFR_MEM8(0xDC)
-#define ENMOB0 0
-#define ENMOB1 1
-#define ENMOB2 2
-#define ENMOB3 3
-#define ENMOB4 4
-#define ENMOB5 5
-
-#define CANEN1 _SFR_MEM8(0xDD)
-
-#define CANIE2 _SFR_MEM8(0xDE)
-#define IEMOB0 0
-#define IEMOB1 1
-#define IEMOB2 2
-#define IEMOB3 3
-#define IEMOB4 4
-#define IEMOB5 5
-
-#define CANIE1 _SFR_MEM8(0xDF)
-
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define SIT0 0
-#define SIT1 1
-#define SIT2 2
-#define SIT3 3
-#define SIT4 4
-#define SIT5 5
-
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-#define CANBT1 _SFR_MEM8(0xE2)
-#define BRP0 1
-#define BRP1 2
-#define BRP2 3
-#define BRP3 4
-#define BRP4 5
-#define BRP5 6
-
-#define CANBT2 _SFR_MEM8(0xE3)
-#define PRS0 1
-#define PRS1 2
-#define PRS2 3
-#define SJW0 5
-#define SJW1 6
-
-#define CANBT3 _SFR_MEM8(0xE4)
-#define SMP 0
-#define PHS10 1
-#define PHS11 2
-#define PHS12 3
-#define PHS20 4
-#define PHS21 5
-#define PHS22 6
-
-#define CANTCON _SFR_MEM8(0xE5)
-#define TPRSC0 0
-#define TPRSC1 1
-#define TPRSC2 2
-#define TPRSC3 3
-#define TPRSC4 4
-#define TPRSC5 5
-#define TPRSC6 6
-#define TPRSC7 7
-
-#define CANTIM _SFR_MEM16(0xE6)
-
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIM0 0
-#define CANTIM1 1
-#define CANTIM2 2
-#define CANTIM3 3
-#define CANTIM4 4
-#define CANTIM5 5
-#define CANTIM6 6
-#define CANTIM7 7
-
-#define CANTIMH _SFR_MEM8(0xE7)
-#define CANTIM8 0
-#define CANTIM9 1
-#define CANTIM10 2
-#define CANTIM11 3
-#define CANTIM12 4
-#define CANTIM13 5
-#define CANTIM14 6
-#define CANTIM15 7
-
-#define CANTTC _SFR_MEM16(0xE8)
-
-#define CANTTCL _SFR_MEM8(0xE8)
-#define TIMTCC0 0
-#define TIMTCC1 1
-#define TIMTCC2 2
-#define TIMTCC3 3
-#define TIMTCC4 4
-#define TIMTCC5 5
-#define TIMTCC6 6
-#define TIMTCC7 7
-
-#define CANTTCH _SFR_MEM8(0xE9)
-#define TIMTCC8 0
-#define TIMTCC9 1
-#define TIMTCC10 2
-#define TIMTCC11 3
-#define TIMTCC12 4
-#define TIMTCC13 5
-#define TIMTCC14 6
-#define TIMTCC15 7
-
-#define CANTEC _SFR_MEM8(0xEA)
-#define TEC0 0
-#define TEC1 1
-#define TEC2 2
-#define TEC3 3
-#define TEC4 4
-#define TEC5 5
-#define TEC6 6
-#define TEC7 7
-
-#define CANREC _SFR_MEM8(0xEB)
-#define REC0 0
-#define REC1 1
-#define REC2 2
-#define REC3 3
-#define REC4 4
-#define REC5 5
-#define REC6 6
-#define REC7 7
-
-#define CANHPMOB _SFR_MEM8(0xEC)
-#define CGP0 0
-#define CGP1 1
-#define CGP2 2
-#define CGP3 3
-#define HPMOB0 4
-#define HPMOB1 5
-#define HPMOB2 6
-#define HPMOB3 7
-
-#define CANPAGE _SFR_MEM8(0xED)
-#define INDX0 0
-#define INDX1 1
-#define INDX2 2
-#define AINC 3
-#define MOBNB0 4
-#define MOBNB1 5
-#define MOBNB2 6
-#define MOBNB3 7
-
-#define CANSTMOB _SFR_MEM8(0xEE)
-#define AERR 0
-#define FERR 1
-#define CERR 2
-#define SERR 3
-#define BERR 4
-#define RXOK 5
-#define TXOK 6
-#define DLCW 7
-
-#define CANCDMOB _SFR_MEM8(0xEF)
-#define DLC0 0
-#define DLC1 1
-#define DLC2 2
-#define DLC3 3
-#define IDE 4
-#define RPLV 5
-#define CONMOB0 6
-#define CONMOB1 7
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define RB0TAG 0
-#define RB1TAG 1
-#define RTRTAG 2
-#define IDT0 3
-#define IDT1 4
-#define IDT2 5
-#define IDT3 6
-#define IDT4 7
-
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define IDT5 0
-#define IDT6 1
-#define IDT7 2
-#define IDT8 3
-#define IDT9 4
-#define IDT10 5
-#define IDT11 6
-#define IDT12 7
-
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define IDT13 0
-#define IDT14 1
-#define IDT15 2
-#define IDT16 3
-#define IDT17 4
-#define IDT18 5
-#define IDT19 6
-#define IDT20 7
-
-#define CANIDT1 _SFR_MEM8(0xF3)
-#define IDT21 0
-#define IDT22 1
-#define IDT23 2
-#define IDT24 3
-#define IDT25 4
-#define IDT26 5
-#define IDT27 6
-#define IDT28 7
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define IDEMSK 0
-#define RTRMSK 2
-#define IDMSK0 3
-#define IDMSK1 4
-#define IDMSK2 5
-#define IDMSK3 6
-#define IDMSK4 7
-
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define IDMSK5 0
-#define IDMSK6 1
-#define IDMSK7 2
-#define IDMSK8 3
-#define IDMSK9 4
-#define IDMSK10 5
-#define IDMSK11 6
-#define IDMSK12 7
-
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define IDMSK13 0
-#define IDMSK14 1
-#define IDMSK15 2
-#define IDMSK16 3
-#define IDMSK17 4
-#define IDMSK18 5
-#define IDMSK19 6
-#define IDMSK20 7
-
-#define CANIDM1 _SFR_MEM8(0xF7)
-#define IDMSK21 0
-#define IDMSK22 1
-#define IDMSK23 2
-#define IDMSK24 3
-#define IDMSK25 4
-#define IDMSK26 5
-#define IDMSK27 6
-#define IDMSK28 7
-
-#define CANSTM _SFR_MEM16(0xF8)
-
-#define CANSTML _SFR_MEM8(0xF8)
-#define TIMSTM0 0
-#define TIMSTM1 1
-#define TIMSTM2 2
-#define TIMSTM3 3
-#define TIMSTM4 4
-#define TIMSTM5 5
-#define TIMSTM6 6
-#define TIMSTM7 7
-
-#define CANSTMH _SFR_MEM8(0xF9)
-#define TIMSTM8 0
-#define TIMSTM9 1
-#define TIMSTM10 2
-#define TIMSTM11 3
-#define TIMSTM12 4
-#define TIMSTM13 5
-#define TIMSTM14 6
-#define TIMSTM15 7
-
-#define CANMSG _SFR_MEM8(0xFA)
-#define MSG0 0
-#define MSG1 1
-#define MSG2 2
-#define MSG3 3
-#define MSG4 4
-#define MSG5 5
-#define MSG6 6
-#define MSG7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define ANACOMP0_vect_num  1
-#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
-#define ANACOMP1_vect_num  2
-#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
-#define ANACOMP2_vect_num  3
-#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
-#define ANACOMP3_vect_num  4
-#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
-#define PSC_FAULT_vect_num  5
-#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
-#define PSC_EC_vect_num  6
-#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
-#define INT0_vect_num  7
-#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
-#define INT1_vect_num  8
-#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
-#define INT2_vect_num  9
-#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
-#define INT3_vect_num  10
-#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  12
-#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  13
-#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  14
-#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  15
-#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  16
-#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  17
-#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define CAN_INT_vect_num  18
-#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
-#define CAN_TOVF_vect_num  19
-#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
-#define LIN_TC_vect_num  20
-#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  21
-#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
-#define PCINT0_vect_num  22
-#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  23
-#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  24
-#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  25
-#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
-#define SPI_STC_vect_num  26
-#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  27
-#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
-#define WDT_vect_num  28
-#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
-#define EE_READY_vect_num  29
-#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
-#define SPM_READY_vect_num  30
-#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (2048)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
-#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
-#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
-#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x86
-
-
-/** @} */
-#endif /* _AVR_ATmega32C1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32hvb.h b/cpukit/score/cpu/avr/avr/iom32hvb.h
deleted file mode 100644
index f97031727c..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32hvb.h
+++ /dev/null
@@ -1,884 +0,0 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom32hvb.h - definitions for ATmega32HVB. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32hvb.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IOM32HVB_H_
-#define _AVR_IOM32HVB_H_ 1
-
-/* Registers and associated bit numbers */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-#define ICF0 3
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 3
-
-#define OSICSR _SFR_IO8(0x17)
-#define OSIEN 0
-#define OSIST 1
-#define OSISEL0 4
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define ICS0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-
-#define TCNT0 _SFR_IO16(0x26)
-
-#define TCNT0L _SFR_IO8(0x26)
-#define TCNT0L0 0
-#define TCNT0L1 1
-#define TCNT0L2 2
-#define TCNT0L3 3
-#define TCNT0L4 4
-#define TCNT0L5 5
-#define TCNT0L6 6
-#define TCNT0L7 7
-
-#define TCNT0H _SFR_IO8(0x27)
-#define TCNT0H0 0
-#define TCNT0H1 1
-#define TCNT0H2 2
-#define TCNT0H3 3
-#define TCNT0H4 4
-#define TCNT0H5 5
-#define TCNT0H6 6
-#define TCNT0H7 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define OCR0B _SFR_IO8(0x29)
-#define OCR0B0 0
-#define OCR0B1 1
-#define OCR0B2 2
-#define OCR0B3 3
-#define OCR0B4 4
-#define OCR0B5 5
-#define OCR0B6 6
-#define OCR0B7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BODRF 2
-#define WDRF 3
-#define OCDRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define CKOE 5
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define LBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRVADC 0
-#define PRTIM0 1
-#define PRTIM1 2
-#define PRSPI 3
-#define PRVRM 5
-#define PRTWI 6
-
-#define FOSCCAL _SFR_MEM8(0x66)
-#define FCAL0 0
-#define FCAL1 1
-#define FCAL2 2
-#define FCAL3 3
-#define FCAL4 4
-#define FCAL5 5
-#define FCAL6 6
-#define FCAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT4 0
-#define PCINT5 1
-#define PCINT6 2
-#define PCINT7 3
-#define PCINT8 4
-#define PCINT9 5
-#define PCINT10 6
-#define PCINT11 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-#define ICIE0 3
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 3
-
-#define VADC _SFR_MEM16(0x78)
-
-#define VADCL _SFR_MEM8(0x78)
-#define VADC0 0
-#define VADC1 1
-#define VADC2 2
-#define VADC3 3
-#define VADC4 4
-#define VADC5 5
-#define VADC6 6
-#define VADC7 7
-
-#define VADCH _SFR_MEM8(0x79)
-#define VADC8 0
-#define VADC9 1
-#define VADC10 2
-#define VADC11 3
-
-#define VADCSR _SFR_MEM8(0x7A)
-#define VADCCIE 0
-#define VADCCIF 1
-#define VADSC 2
-#define VADEN 3
-
-#define VADMUX _SFR_MEM8(0x7C)
-#define VADMUX0 0
-#define VADMUX1 1
-#define VADMUX2 2
-#define VADMUX3 3
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define PA0DID 0
-#define PA1DID 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define ICS1 3
-#define ICES1 4
-#define ICNC1 5
-#define ICEN1 6
-#define TCW1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR1A _SFR_MEM8(0x88)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define OCR1B _SFR_MEM8(0x89)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define TWBCSR _SFR_MEM8(0xBE)
-#define TWBCIP 0
-#define TWBDT0 1
-#define TWBDT1 2
-#define TWBCIE 6
-#define TWBCIF 7
-
-#define ROCR _SFR_MEM8(0xC8)
-#define ROCWIE 0
-#define ROCWIF 1
-#define ROCD 4
-#define ROCS 7
-
-#define BGCCR _SFR_MEM8(0xD0)
-#define BGCC0 0
-#define BGCC1 1
-#define BGCC2 2
-#define BGCC3 3
-#define BGCC4 4
-#define BGCC5 5
-
-#define BGCRR _SFR_MEM8(0xD1)
-#define BGCR0 0
-#define BGCR1 1
-#define BGCR2 2
-#define BGCR3 3
-#define BGCR4 4
-#define BGCR5 5
-#define BGCR6 6
-#define BGCR7 7
-
-#define BGCSR _SFR_MEM8(0xD2)
-#define BGSCDIE 0
-#define BGSCDIF 1
-#define BGSCDE 4
-#define BGD 5
-
-#define CHGDCSR _SFR_MEM8(0xD4)
-#define CHGDIE 0
-#define CHGDIF 1
-#define CHGDISC0 2
-#define CHGDISC1 3
-#define BATTPVL 4
-
-#define CADAC _SFR_MEM32(0xE0)
-
-#define CADAC0 _SFR_MEM8(0xE0)
-#define CADAC00 0
-#define CADAC01 1
-#define CADAC02 2
-#define CADAC03 3
-#define CADAC04 4
-#define CADAC05 5
-#define CADAC06 6
-#define CADAC07 7
-
-#define CADAC1 _SFR_MEM8(0xE1)
-#define CADAC08 0
-#define CADAC09 1
-#define CADAC10 2
-#define CADAC11 3
-#define CADAC12 4
-#define CADAC13 5
-#define CADAC14 6
-#define CADAC15 7
-
-#define CADAC2 _SFR_MEM8(0xE2)
-#define CADAC16 0
-#define CADAC17 1
-#define CADAC18 2
-#define CADAC19 3
-#define CADAC20 4
-#define CADAC21 5
-#define CADAC22 6
-#define CADAC23 7
-
-#define CADAC3 _SFR_MEM8(0xE3)
-#define CADAC24 0
-#define CADAC25 1
-#define CADAC26 2
-#define CADAC27 3
-#define CADAC28 4
-#define CADAC29 5
-#define CADAC30 6
-#define CADAC31 7
-
-#define CADIC _SFR_MEM16(0xE4)
-
-#define CADICL _SFR_MEM8(0xE4)
-#define CADICL0 0
-#define CADICL1 1
-#define CADICL2 2
-#define CADICL3 3
-#define CADICL4 4
-#define CADICL5 5
-#define CADICL6 6
-#define CADICL7 7
-
-#define CADICH _SFR_MEM8(0xE5)
-#define CADICH0 0
-#define CADICH1 1
-#define CADICH2 2
-#define CADICH3 3
-#define CADICH4 4
-#define CADICH5 5
-#define CADICH6 6
-#define CADICH7 7
-
-#define CADCSRA _SFR_MEM8(0xE6)
-#define CADSE 0
-#define CADSI0 1
-#define CADSI1 2
-#define CADAS0 3
-#define CADAS1 4
-#define CADUB 5
-#define CADPOL 6
-#define CADEN 7
-
-#define CADCSRB _SFR_MEM8(0xE7)
-#define CADICIF 0
-#define CADRCIF 1
-#define CADACIF 2
-#define CADICIE 4
-#define CADRCIE 5
-#define CADACIE 6
-
-#define CADCSRC _SFR_MEM8(0xE8)
-#define CADVSE 0
-
-#define CADRCC _SFR_MEM8(0xE9)
-#define CADRCC0 0
-#define CADRCC1 1
-#define CADRCC2 2
-#define CADRCC3 3
-#define CADRCC4 4
-#define CADRCC5 5
-#define CADRCC6 6
-#define CADRCC7 7
-
-#define CADRDC _SFR_MEM8(0xEA)
-#define CADRDC0 0
-#define CADRDC1 1
-#define CADRDC2 2
-#define CADRDC3 3
-#define CADRDC4 4
-#define CADRDC5 5
-#define CADRDC6 6
-#define CADRDC7 7
-
-#define FCSR _SFR_MEM8(0xF0)
-#define CFE 0
-#define DFE 1
-#define CPS 2
-#define DUVRD 3
-
-#define CBCR _SFR_MEM8(0xF1)
-#define CBE1 0
-#define CBE2 1
-#define CBE3 2
-#define CBE4 3
-
-#define BPIMSK _SFR_MEM8(0xF2)
-#define CHCIE 0
-#define DHCIE 1
-#define COCIE 2
-#define DOCIE 3
-#define SCIE 4
-
-#define BPIFR _SFR_MEM8(0xF3)
-#define CHCIF 0
-#define DHCIF 1
-#define COCIF 2
-#define DOCIF 3
-#define SCIF 4
-
-#define BPSCD _SFR_MEM8(0xF5)
-#define SCDL0 0
-#define SCDL1 1
-#define SCDL2 2
-#define SCDL3 3
-#define SCDL4 4
-#define SCDL5 5
-#define SCDL6 6
-#define SCDL7 7
-
-#define BPDOCD _SFR_MEM8(0xF6)
-#define DOCDL0 0
-#define DOCDL1 1
-#define DOCDL2 2
-#define DOCDL3 3
-#define DOCDL4 4
-#define DOCDL5 5
-#define DOCDL6 6
-#define DOCDL7 7
-
-#define BPCOCD _SFR_MEM8(0xF7)
-#define COCDL0 0
-#define COCDL1 1
-#define COCDL2 2
-#define COCDL3 3
-#define COCDL4 4
-#define COCDL5 5
-#define COCDL6 6
-#define COCDL7 7
-
-#define BPDHCD _SFR_MEM8(0xF8)
-#define DHCDL0 0
-#define DHCDL1 1
-#define DHCDL2 2
-#define DHCDL3 3
-#define DHCDL4 4
-#define DHCDL5 5
-#define DHCDL6 6
-#define DHCDL7 7
-
-#define BPCHCD _SFR_MEM8(0xF9)
-#define CHCDL0 0
-#define CHCDL1 1
-#define CHCDL2 2
-#define CHCDL3 3
-#define CHCDL4 4
-#define CHCDL5 5
-#define CHCDL6 6
-#define CHCDL7 7
-
-#define BPSCTR _SFR_MEM8(0xFA)
-#define SCPT0 0
-#define SCPT1 1
-#define SCPT2 2
-#define SCPT3 3
-#define SCPT4 4
-#define SCPT5 5
-#define SCPT6 6
-
-#define BPOCTR _SFR_MEM8(0xFB)
-#define OCPT0 0
-#define OCPT1 1
-#define OCPT2 2
-#define OCPT3 3
-#define OCPT4 4
-#define OCPT5 5
-
-#define BPHCTR _SFR_MEM8(0xFC)
-#define HCPT0 0
-#define HCPT1 1
-#define HCPT2 2
-#define HCPT3 3
-#define HCPT4 4
-#define HCPT5 5
-
-#define BPCR _SFR_MEM8(0xFD)
-#define CHCD 0
-#define DHCD 1
-#define COCD 2
-#define DOCD 3
-#define SCD 4
-#define EPID 5
-
-#define BPPLR _SFR_MEM8(0xFE)
-#define BPPL 0
-#define BPPLE 1
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-
-#define BPINT_vect         _VECTOR(1)  /* Battery Protection Interrupt */
-#define VREGMON_vect       _VECTOR(2)  /* Voltage regulator monitor interrupt */
-#define INT0_vect          _VECTOR(3)  /* External Interrupt Request 0 */
-#define INT1_vect          _VECTOR(4)  /* External Interrupt Request 1 */
-#define INT2_vect          _VECTOR(5)  /* External Interrupt Request 2 */
-#define INT3_vect          _VECTOR(6)  /* External Interrupt Request 3 */
-#define PCINT0_vect        _VECTOR(7)  /* Pin Change Interrupt 0 */
-#define PCINT1_vect        _VECTOR(8)  /* Pin Change Interrupt 1 */
-#define WDT_vect           _VECTOR(9)  /* Watchdog Timeout Interrupt */
-#define BGSCD_vect         _VECTOR(10)  /* Bandgap Buffer Short Circuit Detected */
-#define CHDET_vect         _VECTOR(11)  /* Charger Detect */
-#define TIMER1_IC_vect     _VECTOR(12)  /* Timer 1 Input capture */
-#define TIMER1_COMPA_vect  _VECTOR(13)  /* Timer 1 Compare Match A */
-#define TIMER1_COMPB_vect  _VECTOR(14)  /* Timer 1 Compare Match B */
-#define TIMER1_OVF_vect    _VECTOR(15)  /* Timer 1 overflow */
-#define TIMER0_IC_vect     _VECTOR(16)  /* Timer 0 Input Capture */
-#define TIMER0_COMPA_vect  _VECTOR(17)  /* Timer 0 Comapre Match A */
-#define TIMER0_COMPB_vect  _VECTOR(18)  /* Timer 0 Compare Match B */
-#define TIMER0_OVF_vect    _VECTOR(19)  /* Timer 0 Overflow */
-#define TWIBUSCD_vect      _VECTOR(20)  /* Two-Wire Bus Connect/Disconnect */
-#define TWI_vect           _VECTOR(21)  /* Two-Wire Serial Interface */
-#define SPI_STC_vect       _VECTOR(22)  /* SPI Serial transfer complete */
-#define VADC_vect          _VECTOR(23)  /* Voltage ADC Conversion Complete */
-#define CCADC_CONV_vect    _VECTOR(24)  /* Coulomb Counter ADC Conversion Complete */
-#define CCADC_REG_CUR_vect _VECTOR(25)  /* Coloumb Counter ADC Regular Current */
-#define CCADC_ACC_vect     _VECTOR(26)  /* Coloumb Counter ADC Accumulator */
-#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
-#define SPM_vect           _VECTOR(28)  /* SPM Ready */
-
-#define _VECTORS_SIZE (29 * 4)
-
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x8FF     /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x3FF
-#define FLASHEND     0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_WDTON   (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
-#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_SUT2    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(3)  /* Select start-up time */
-#define FUSE_SUT0    (unsigned char)~_BV(2)  /* Select start-up time */
-#define FUSE_OSCSEL1 (unsigned char)~_BV(1)  /* Oscillator Select */
-#define FUSE_OSCSEL0 (unsigned char)~_BV(0)  /* Oscillator Select */
-#define LFUSE_DEFAULT (FUSE_OSCSEL0 & FUSE_SPIEN)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST   (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0   (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1   (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_DWEN      (unsigned char)~_BV(3)  /* Enable debugWire */
-#define FUSE_DUVRDINIT (unsigned char)~_BV(4)  /* Reset Value of DUVRDRegister */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_DUVRDINIT)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-#endif  /* _AVR_IOM32HVB_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32m1.h b/cpukit/score/cpu/avr/avr/iom32m1.h
deleted file mode 100644
index f8bf88396e..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32m1.h
+++ /dev/null
@@ -1,1582 +0,0 @@
-/**
- * @file avr/iom32m1.h
- *
- * @brief Definitions for ATmega32M1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2008-2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32m1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega32M1_H_
-#define _AVR_ATmega32M1_H_ 1
-
-/**
- * @defgroup AvrDef_iom32m1 ATmega32M1 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 6
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRLIN 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC 5
-#define PRCAN 6
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define PCMSK3 _SFR_MEM8(0x6D)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x75)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0TS2 2
-#define AMPCMP0 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x76)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1TS2 2
-#define AMPCMP1 3
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#define AMP2CSR _SFR_MEM8(0x77)
-#define AMP2TS0 0
-#define AMP2TS1 1
-#define AMP2TS2 2
-#define AMPCMP2 3
-#define AMP2G0 4
-#define AMP2G1 5
-#define AMP2IS 6
-#define AMP2EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define AREFEN 5
-#define ISRCEN 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-#define AMP2PD 6
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define DACON _SFR_MEM8(0x90)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0x91)
-
-#define DACL _SFR_MEM8(0x91)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0x92)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0x94)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define ACCKSEL 3
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0x95)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x96)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x97)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define POCR0SA _SFR_MEM16(0xA0)
-
-#define POCR0SAL _SFR_MEM8(0xA0)
-#define POCR0SA_0 0
-#define POCR0SA_1 1
-#define POCR0SA_2 2
-#define POCR0SA_3 3
-#define POCR0SA_4 4
-#define POCR0SA_5 5
-#define POCR0SA_6 6
-#define POCR0SA_7 7
-
-#define POCR0SAH _SFR_MEM8(0xA1)
-#define POCR0SA_8 0
-#define POCR0SA_9 1
-#define POCR0SA_10 2
-#define POCR0SA_11 3
-#define POCR0SA_00 2    /* Deprecated */
-#define POCR0SA_01 3    /* Deprecated */
-
-#define POCR0RA _SFR_MEM16(0xA2)
-
-#define POCR0RAL _SFR_MEM8(0xA2)
-#define POCR0RA_0 0
-#define POCR0RA_1 1
-#define POCR0RA_2 2
-#define POCR0RA_3 3
-#define POCR0RA_4 4
-#define POCR0RA_5 5
-#define POCR0RA_6 6
-#define POCR0RA_7 7
-
-#define POCR0RAH _SFR_MEM8(0xA3)
-#define POCR0RA_8 0
-#define POCR0RA_9 1
-#define POCR0RA_10 2
-#define POCR0RA_11 3
-#define POCR0RA_00 2    /* Deprecated */
-#define POCR0RA_01 3    /* Deprecated */
-
-#define POCR0SB _SFR_MEM16(0xA4)
-
-#define POCR0SBL _SFR_MEM8(0xA4)
-#define POCR0SB_0 0
-#define POCR0SB_1 1
-#define POCR0SB_2 2
-#define POCR0SB_3 3
-#define POCR0SB_4 4
-#define POCR0SB_5 5
-#define POCR0SB_6 6
-#define POCR0SB_7 7
-
-#define POCR0SBH _SFR_MEM8(0xA5)
-#define POCR0SB_8 0
-#define POCR0SB_9 1
-#define POCR0SB_10 2
-#define POCR0SB_11 3
-#define POCR0SB_00 2    /* Deprecated */
-#define POCR0SB_01 3    /* Deprecated */
-
-#define POCR1SA _SFR_MEM16(0xA6)
-
-#define POCR1SAL _SFR_MEM8(0xA6)
-#define POCR1SA_0 0
-#define POCR1SA_1 1
-#define POCR1SA_2 2
-#define POCR1SA_3 3
-#define POCR1SA_4 4
-#define POCR1SA_5 5
-#define POCR1SA_6 6
-#define POCR1SA_7 7
-
-#define POCR1SAH _SFR_MEM8(0xA7)
-#define POCR1SA_8 0
-#define POCR1SA_9 1
-#define POCR1SA_10 2
-#define POCR1SA_11 3
-#define POCR1SA_00 2    /* Deprecated */
-#define POCR1SA_01 3    /* Deprecated */
-
-#define POCR1RA _SFR_MEM16(0xA8)
-
-#define POCR1RAL _SFR_MEM8(0xA8)
-#define POCR1RA_0 0
-#define POCR1RA_1 1
-#define POCR1RA_2 2
-#define POCR1RA_3 3
-#define POCR1RA_4 4
-#define POCR1RA_5 5
-#define POCR1RA_6 6
-#define POCR1RA_7 7
-
-#define POCR1RAH _SFR_MEM8(0xA9)
-#define POCR1RA_8 0
-#define POCR1RA_9 1
-#define POCR1RA_10 2
-#define POCR1RA_11 3
-#define POCR1RA_00 2    /* Deprecated */
-
-#define POCR1SB _SFR_MEM16(0xAA)
-
-#define POCR1SBL _SFR_MEM8(0xAA)
-#define POCR1SB_0 0
-#define POCR1SB_1 1
-#define POCR1SB_2 2
-#define POCR1SB_3 3
-#define POCR1SB_4 4
-#define POCR1SB_5 5
-#define POCR1SB_6 6
-#define POCR1SB_7 7
-
-#define POCR1SBH _SFR_MEM8(0xAB)
-#define POCR1SB_8 0
-#define POCR1SB_9 1
-#define POCR1SB_10 2
-#define POCR1SB_11 3
-#define POCR1SB_00 2    /* Deprecated */
-#define POCR1SB_01 3    /* Deprecated */
-
-#define POCR2SA _SFR_MEM16(0xAC)
-
-#define POCR2SAL _SFR_MEM8(0xAC)
-#define POCR2SA_0 0
-#define POCR2SA_1 1
-#define POCR2SA_2 2
-#define POCR2SA_3 3
-#define POCR2SA_4 4
-#define POCR2SA_5 5
-#define POCR2SA_6 6
-#define POCR2SA_7 7
-
-#define POCR2SAH _SFR_MEM8(0xAD)
-#define POCR2SA_8 0
-#define POCR2SA_9 1
-#define POCR2SA_10 2
-#define POCR2SA_11 3
-#define POCR2SA_00 2    /* Deprecated */
-#define POCR2SA_01 3    /* Deprecated */
-
-#define POCR2RA _SFR_MEM16(0xAE)
-
-#define POCR2RAL _SFR_MEM8(0xAE)
-#define POCR2RA_0 0
-#define POCR2RA_1 1
-#define POCR2RA_2 2
-#define POCR2RA_3 3
-#define POCR2RA_4 4
-#define POCR2RA_5 5
-#define POCR2RA_6 6
-#define POCR2RA_7 7
-
-#define POCR2RAH _SFR_MEM8(0xAF)
-#define POCR2RA_8 0
-#define POCR2RA_9 1
-#define POCR2RA_10 2
-#define POCR2RA_11 3
-#define POCR2RA_00 2    /* Deprecated */
-#define POCR2RA_01 3    /* Deprecated */
-
-#define POCR2SB _SFR_MEM16(0xB0)
-
-#define POCR2SBL _SFR_MEM8(0xB0)
-#define POCR2SB_0 0
-#define POCR2SB_1 1
-#define POCR2SB_2 2
-#define POCR2SB_3 3
-#define POCR2SB_4 4
-#define POCR2SB_5 5
-#define POCR2SB_6 6
-#define POCR2SB_7 7
-
-#define POCR2SBH _SFR_MEM8(0xB1)
-#define POCR2SB_8 0
-#define POCR2SB_9 1
-#define POCR2SB_10 2
-#define POCR2SB_11 3
-#define POCR2SB_00 2    /* Deprecated */
-#define POCR2SB_01 3    /* Deprecated */
-
-
-#define POCRxRB _SFR_MEM16(0xB2)  /* Deprecated */
-#define POCR_RB _SFR_MEM16(0xB2)
-
-#define POCRxRBL _SFR_MEM8(0xB2)  /* Deprecated */
-#define POCR_RBL _SFR_MEM8(0xB2)
-#define POCR_RB_0 0
-#define POCR_RB_1 1
-#define POCR_RB_2 2
-#define POCR_RB_3 3
-#define POCR_RB_4 4
-#define POCR_RB_5 5
-#define POCR_RB_6 6
-#define POCR_RB_7 7
-
-#define POCRxRBH _SFR_MEM8(0xB3)  /* Deprecated */
-#define POCR_RBH _SFR_MEM8(0xB3)
-#define POCR_RB_8 0
-#define POCR_RB_9 1
-#define POCR_RB_10 2
-#define POCR_RB_11 3
-#define POCR_RB_00 2    /* Deprecated */
-#define POCR_RB_01 3    /* Deprecated */
-
-#define PSYNC _SFR_MEM8(0xB4)
-#define PSYNC00 0
-#define PSYNC01 1
-#define PSYNC10 2
-#define PSYNC11 3
-#define PSYNC20 4
-#define PSYNC21 5
-
-#define PCNF _SFR_MEM8(0xB5)
-#define POPA 2
-#define POPB 3
-#define PMODE 4
-#define PULOCK 5
-
-#define POC _SFR_MEM8(0xB6)
-#define POEN0A 0
-#define POEN0B 1
-#define POEN1A 2
-#define POEN1B 3
-#define POEN2A 4
-#define POEN2B 5
-
-#define PCTL _SFR_MEM8(0xB7)
-#define PRUN 0
-#define PCCYC 1
-#define PCLKSEL 5
-#define PPRE0 6
-#define PPRE1 7
-
-#define PMIC0 _SFR_MEM8(0xB8)
-#define PRFM00 0
-#define PRFM01 1
-#define PRFM02 2
-#define PAOC0 3
-#define PFLTE0 4
-#define PELEV0 5
-#define PISEL0 6
-#define POVEN0 7
-
-#define PMIC1 _SFR_MEM8(0xB9)
-#define PRFM10 0
-#define PRFM11 1
-#define PRFM12 2
-#define PAOC1 3
-#define PFLTE1 4
-#define PELEV1 5
-#define PISEL1 6
-#define POVEN1 7
-
-#define PMIC2 _SFR_MEM8(0xBA)
-#define PRFM20 0
-#define PRFM21 1
-#define PRFM22 2
-#define PAOC2 3
-#define PFLTE2 4
-#define PELEV2 5
-#define PISEL2 6
-#define POVEN2 7
-
-#define PIM _SFR_MEM8(0xBB)
-#define PEOPE 0
-#define PEVE0 1
-#define PEVE1 2
-#define PEVE2 3
-
-#define PIFR _SFR_MEM8(0xBC)
-#define PEOP 0
-#define PEV0 1
-#define PEV1 2
-#define PEV2 3
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define CANGCON _SFR_MEM8(0xD8)
-#define SWRES 0
-#define ENASTB 1
-#define TEST 2
-#define LISTEN 3
-#define SYNTTC 4
-#define TTC 5
-#define OVRQ 6
-#define ABRQ 7
-
-#define CANGSTA _SFR_MEM8(0xD9)
-#define ERRP 0
-#define BOFF 1
-#define ENFG 2
-#define RXBSY 3
-#define TXBSY 4
-#define OVFG 6
-
-#define CANGIT _SFR_MEM8(0xDA)
-#define AERG 0
-#define FERG 1
-#define CERG 2
-#define SERG 3
-#define BXOK 4
-#define OVRTIM 5
-#define BOFFIT 6
-#define CANIT 7
-
-#define CANGIE _SFR_MEM8(0xDB)
-#define ENOVRT 0
-#define ENERG 1
-#define ENBX 2
-#define ENERR 3
-#define ENTX 4
-#define ENRX 5
-#define ENBOFF 6
-#define ENIT 7
-
-#define CANEN2 _SFR_MEM8(0xDC)
-#define ENMOB0 0
-#define ENMOB1 1
-#define ENMOB2 2
-#define ENMOB3 3
-#define ENMOB4 4
-#define ENMOB5 5
-
-#define CANEN1 _SFR_MEM8(0xDD)
-
-#define CANIE2 _SFR_MEM8(0xDE)
-#define IEMOB0 0
-#define IEMOB1 1
-#define IEMOB2 2
-#define IEMOB3 3
-#define IEMOB4 4
-#define IEMOB5 5
-
-#define CANIE1 _SFR_MEM8(0xDF)
-
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define SIT0 0
-#define SIT1 1
-#define SIT2 2
-#define SIT3 3
-#define SIT4 4
-#define SIT5 5
-
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-#define CANBT1 _SFR_MEM8(0xE2)
-#define BRP0 1
-#define BRP1 2
-#define BRP2 3
-#define BRP3 4
-#define BRP4 5
-#define BRP5 6
-
-#define CANBT2 _SFR_MEM8(0xE3)
-#define PRS0 1
-#define PRS1 2
-#define PRS2 3
-#define SJW0 5
-#define SJW1 6
-
-#define CANBT3 _SFR_MEM8(0xE4)
-#define SMP 0
-#define PHS10 1
-#define PHS11 2
-#define PHS12 3
-#define PHS20 4
-#define PHS21 5
-#define PHS22 6
-
-#define CANTCON _SFR_MEM8(0xE5)
-#define TPRSC0 0
-#define TPRSC1 1
-#define TPRSC2 2
-#define TPRSC3 3
-#define TPRSC4 4
-#define TPRSC5 5
-#define TPRSC6 6
-#define TPRSC7 7
-
-#define CANTIM _SFR_MEM16(0xE6)
-
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIM0 0
-#define CANTIM1 1
-#define CANTIM2 2
-#define CANTIM3 3
-#define CANTIM4 4
-#define CANTIM5 5
-#define CANTIM6 6
-#define CANTIM7 7
-
-#define CANTIMH _SFR_MEM8(0xE7)
-#define CANTIM8 0
-#define CANTIM9 1
-#define CANTIM10 2
-#define CANTIM11 3
-#define CANTIM12 4
-#define CANTIM13 5
-#define CANTIM14 6
-#define CANTIM15 7
-
-#define CANTTC _SFR_MEM16(0xE8)
-
-#define CANTTCL _SFR_MEM8(0xE8)
-#define TIMTCC0 0
-#define TIMTCC1 1
-#define TIMTCC2 2
-#define TIMTCC3 3
-#define TIMTCC4 4
-#define TIMTCC5 5
-#define TIMTCC6 6
-#define TIMTCC7 7
-
-#define CANTTCH _SFR_MEM8(0xE9)
-#define TIMTCC8 0
-#define TIMTCC9 1
-#define TIMTCC10 2
-#define TIMTCC11 3
-#define TIMTCC12 4
-#define TIMTCC13 5
-#define TIMTCC14 6
-#define TIMTCC15 7
-
-#define CANTEC _SFR_MEM8(0xEA)
-#define TEC0 0
-#define TEC1 1
-#define TEC2 2
-#define TEC3 3
-#define TEC4 4
-#define TEC5 5
-#define TEC6 6
-#define TEC7 7
-
-#define CANREC _SFR_MEM8(0xEB)
-#define REC0 0
-#define REC1 1
-#define REC2 2
-#define REC3 3
-#define REC4 4
-#define REC5 5
-#define REC6 6
-#define REC7 7
-
-#define CANHPMOB _SFR_MEM8(0xEC)
-#define CGP0 0
-#define CGP1 1
-#define CGP2 2
-#define CGP3 3
-#define HPMOB0 4
-#define HPMOB1 5
-#define HPMOB2 6
-#define HPMOB3 7
-
-#define CANPAGE _SFR_MEM8(0xED)
-#define INDX0 0
-#define INDX1 1
-#define INDX2 2
-#define AINC 3
-#define MOBNB0 4
-#define MOBNB1 5
-#define MOBNB2 6
-#define MOBNB3 7
-
-#define CANSTMOB _SFR_MEM8(0xEE)
-#define AERR 0
-#define FERR 1
-#define CERR 2
-#define SERR 3
-#define BERR 4
-#define RXOK 5
-#define TXOK 6
-#define DLCW 7
-
-#define CANCDMOB _SFR_MEM8(0xEF)
-#define DLC0 0
-#define DLC1 1
-#define DLC2 2
-#define DLC3 3
-#define IDE 4
-#define RPLV 5
-#define CONMOB0 6
-#define CONMOB1 7
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define RB0TAG 0
-#define RB1TAG 1
-#define RTRTAG 2
-#define IDT0 3
-#define IDT1 4
-#define IDT2 5
-#define IDT3 6
-#define IDT4 7
-
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define IDT5 0
-#define IDT6 1
-#define IDT7 2
-#define IDT8 3
-#define IDT9 4
-#define IDT10 5
-#define IDT11 6
-#define IDT12 7
-
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define IDT13 0
-#define IDT14 1
-#define IDT15 2
-#define IDT16 3
-#define IDT17 4
-#define IDT18 5
-#define IDT19 6
-#define IDT20 7
-
-#define CANIDT1 _SFR_MEM8(0xF3)
-#define IDT21 0
-#define IDT22 1
-#define IDT23 2
-#define IDT24 3
-#define IDT25 4
-#define IDT26 5
-#define IDT27 6
-#define IDT28 7
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define IDEMSK 0
-#define RTRMSK 2
-#define IDMSK0 3
-#define IDMSK1 4
-#define IDMSK2 5
-#define IDMSK3 6
-#define IDMSK4 7
-
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define IDMSK5 0
-#define IDMSK6 1
-#define IDMSK7 2
-#define IDMSK8 3
-#define IDMSK9 4
-#define IDMSK10 5
-#define IDMSK11 6
-#define IDMSK12 7
-
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define IDMSK13 0
-#define IDMSK14 1
-#define IDMSK15 2
-#define IDMSK16 3
-#define IDMSK17 4
-#define IDMSK18 5
-#define IDMSK19 6
-#define IDMSK20 7
-
-#define CANIDM1 _SFR_MEM8(0xF7)
-#define IDMSK21 0
-#define IDMSK22 1
-#define IDMSK23 2
-#define IDMSK24 3
-#define IDMSK25 4
-#define IDMSK26 5
-#define IDMSK27 6
-#define IDMSK28 7
-
-#define CANSTM _SFR_MEM16(0xF8)
-
-#define CANSTML _SFR_MEM8(0xF8)
-#define TIMSTM0 0
-#define TIMSTM1 1
-#define TIMSTM2 2
-#define TIMSTM3 3
-#define TIMSTM4 4
-#define TIMSTM5 5
-#define TIMSTM6 6
-#define TIMSTM7 7
-
-#define CANSTMH _SFR_MEM8(0xF9)
-#define TIMSTM8 0
-#define TIMSTM9 1
-#define TIMSTM10 2
-#define TIMSTM11 3
-#define TIMSTM12 4
-#define TIMSTM13 5
-#define TIMSTM14 6
-#define TIMSTM15 7
-
-#define CANMSG _SFR_MEM8(0xFA)
-#define MSG0 0
-#define MSG1 1
-#define MSG2 2
-#define MSG3 3
-#define MSG4 4
-#define MSG5 5
-#define MSG6 6
-#define MSG7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define ANACOMP0_vect_num  1
-#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
-#define ANACOMP1_vect_num  2
-#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
-#define ANACOMP2_vect_num  3
-#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
-#define ANACOMP3_vect_num  4
-#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
-#define PSC_FAULT_vect_num  5
-#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
-#define PSC_EC_vect_num  6
-#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
-#define INT0_vect_num  7
-#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
-#define INT1_vect_num  8
-#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
-#define INT2_vect_num  9
-#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
-#define INT3_vect_num  10
-#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  12
-#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  13
-#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  14
-#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  15
-#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  16
-#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  17
-#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define CAN_INT_vect_num  18
-#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
-#define CAN_TOVF_vect_num  19
-#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
-#define LIN_TC_vect_num  20
-#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  21
-#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
-#define PCINT0_vect_num  22
-#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  23
-#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  24
-#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  25
-#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
-#define SPI_STC_vect_num  26
-#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  27
-#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
-#define WDT_vect_num  28
-#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
-#define EE_READY_vect_num  29
-#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
-#define SPM_READY_vect_num  30
-#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (2048)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
-#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
-#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
-#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x84
-
-
-/** @} */
-#endif /* _AVR_ATmega32M1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32u2.h b/cpukit/score/cpu/avr/avr/iom32u2.h
deleted file mode 100644
index 10e835e6ed..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32u2.h
+++ /dev/null
@@ -1,1009 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom32u2.h - definitions for ATmega32U2 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32u2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega32U2_H_
-#define _AVR_ATmega32U2_H_ 1
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLP0 2
-#define PLLP1 3
-#define PLLP2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define DWDR _SFR_IO8(0x31)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define USBRF 5
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define EIND _SFR_IO8(0x3C)
-#define EIND0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define WDTCKD _SFR_MEM8(0x62)
-#define WCLKD0 0
-#define WCLKD1 1
-#define WDEWIE 2
-#define WDEWIF 3
-
-#define REGCR _SFR_MEM8(0x63)
-#define REGDIS 0
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UCSR1D _SFR_MEM8(0xCB)
-#define RTSEN 0
-#define CTSEN 1
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define CLKSEL0 _SFR_MEM8(0xD0)
-#define CLKS 0
-#define EXTE 2
-#define RCE 3
-#define EXSUT0 4
-#define EXSUT1 5
-#define RCSUT0 6
-#define RCSUT1 7
-
-#define CLKSEL1 _SFR_MEM8(0xD1)
-#define EXCKSEL0 0
-#define EXCKSEL1 1
-#define EXCKSEL2 2
-#define EXCKSEL3 3
-#define RCCKSEL0 4
-#define RCCKSEL1 5
-#define RCCKSEL2 6
-#define RCCKSEL3 7
-
-#define CLKSTA _SFR_MEM8(0xD2)
-#define EXTON 0
-#define RCON 1
-
-#define USBCON _SFR_MEM8(0xD8)
-#define FRZCLK 5
-#define USBE 7
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define RSTCPU 2
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define EPNUM0 0
-#define EPNUM1 1
-#define EPNUM2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define DAT0 0
-#define DAT1 1
-#define DAT2 2
-#define DAT3 3
-#define DAT4 4
-#define DAT5 5
-#define DAT6 6
-#define DAT7 7
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define BYCT0 0
-#define BYCT1 1
-#define BYCT2 2
-#define BYCT3 3
-#define BYCT4 4
-#define BYCT5 5
-#define BYCT6 6
-#define BYCT7 7
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-
-#define PS2CON _SFR_MEM8(0xFA)
-#define PS2EN 0
-
-#define UPOE _SFR_MEM8(0xFB)
-#define DMI 0
-#define DPI 1
-#define DATAI 2
-#define SCKI 3
-#define UPDRV0 4
-#define UPDRV1 5
-#define UPWE0 6
-#define UPWE1 7
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT4_vect_num  5
-#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
-#define INT5_vect_num  6
-#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
-#define INT6_vect_num  7
-#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
-#define INT7_vect_num  8
-#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
-#define PCINT0_vect_num  9
-#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  10
-#define PCINT1_vect      _VECTOR(10)  /* Pin Change Interrupt Request 1 */
-#define USB_GEN_vect_num  11
-#define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
-#define USB_COM_vect_num  12
-/* USB Endpoint/Pipe Interrupt Communication Request */
-#define USB_COM_vect      _VECTOR(12)  
-#define WDT_vect_num  13
-#define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
-#define TIMER1_CAPT_vect_num  14
-#define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
-#define TIMER1_COMPA_vect_num  15
-/* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPA_vect      _VECTOR(15)  
-#define TIMER0_COMPA_vect_num  19
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect      _VECTOR(19)  
-#define TIMER0_COMPB_vect_num  20
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect      _VECTOR(20)  
-#define TIMER0_OVF_vect_num  21
-#define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  22
-#define SPI_STC_vect      _VECTOR(22)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect_num  23
-#define USART1_RX_vect      _VECTOR(23)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect_num  24
-#define USART1_UDRE_vect      _VECTOR(24)  /* USART1 Data register Empty */
-#define USART1_TX_vect_num  25
-#define USART1_TX_vect      _VECTOR(25)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect_num  26
-#define ANALOG_COMP_vect      _VECTOR(26)  /* Analog Comparator */
-#define EE_READY_vect_num  27
-#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
-#define SPM_READY_vect_num  28
-#define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
-#define TIMER1_COMPB_vect_num  16
-/* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPB_vect      _VECTOR(16)  
-#define TIMER1_COMPC_vect_num  17
-/* Timer/Counter2 Compare Match C */
-#define TIMER1_COMPC_vect      _VECTOR(17)  
-#define TIMER1_OVF_vect_num  18
-#define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-/** @} */
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FFF)
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
-                       FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-/* EEPROM memory is preserved through chip erase */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-/* Enable Serial programming and Data Downloading */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  
-#define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
-#define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-/* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  
-/* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  
-/* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  
-#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x8A
-/** @} */
-
-/* Device Pin Definitions */
-#endif /* _AVR_ATmega32U2_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom32u4.h b/cpukit/score/cpu/avr/avr/iom32u4.h
deleted file mode 100644
index 263d40f9b2..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32u4.h
+++ /dev/null
@@ -1,1518 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega32U4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2008 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom32u4.h - definitions for ATmega32U4. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32u4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IOM32U4_H_
-#define _AVR_IOM32U4_H_ 1
-
-/**
- * @defgroup AvrDef_iom32u4 ATmega32U4 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE2 2
-#define PINE6 6
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE2 2
-#define DDE6 6
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE2 2
-#define PORTE6 6
-
-#define PINF _SFR_IO8(0x0F)
-#define PINF0 0
-#define PINF1 1
-#define PINF4 4
-#define PINF5 5
-#define PINF6 6
-#define PINF7 7
-
-#define DDRF _SFR_IO8(0x10)
-#define DDF0 0
-#define DDF1 1
-#define DDF4 4
-#define DDF5 5
-#define DDF6 6
-#define DDF7 7
-
-#define PORTF _SFR_IO8(0x11)
-#define PORTF0 0
-#define PORTF1 1
-#define PORTF4 4
-#define PORTF5 5
-#define PORTF6 6
-#define PORTF7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define OCF3C 3
-#define ICF3 5
-
-#define TIFR4 _SFR_IO8(0x19)
-#define TOV4 2
-#define OCF4B 5
-#define OCF4A 6
-#define OCF4D 7
-
-#define TIFR5 _SFR_IO8(0x1A)
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PINDIV 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define PLLFRQ _SFR_IO8(0x32)
-#define PDIV0 0
-#define PDIV1 1
-#define PDIV2 2
-#define PDIV3 3
-#define PLLTM0 4
-#define PLLTM1 5
-#define PLLUSB 6
-#define PINMUX 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define EIND _SFR_IO8(0x3C)
-#define EIND0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRTIM3 3
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define RCCTRL _SFR_MEM8(0x67)
-#define RCFREQ 0
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define OCIE3C 3
-#define ICIE3 5
-
-#define TIMSK4 _SFR_MEM8(0x72)
-#define TOIE4 2
-#define OCIE4B 5
-#define OCIE4A 6
-#define OCIE4D 7
-
-#define TIMSK5 _SFR_MEM8(0x73)
-
-#define ADC _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 4
-#define MUX5 5
-#define ACME 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR2 _SFR_MEM8(0x7D)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define ADC11D 3
-#define ADC12D 4
-#define ADC13D 5
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5 
-#define FOC1B 6 
-#define FOC1A 7 
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3C0 2
-#define COM3C1 3
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3C 5
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3BL0 0
-#define OCR3BL1 1
-#define OCR3BL2 2
-#define OCR3BL3 3
-#define OCR3BL4 4
-#define OCR3BL5 5
-#define OCR3BL6 6
-#define OCR3BL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3BH0 0
-#define OCR3BH1 1
-#define OCR3BH2 2
-#define OCR3BH3 3
-#define OCR3BH4 4
-#define OCR3BH5 5
-#define OCR3BH6 6
-#define OCR3BH7 7
-
-#define OCR3C _SFR_MEM16(0x9C)
-
-#define OCR3CL _SFR_MEM8(0x9C)
-#define OCR3CL0 0
-#define OCR3CL1 1
-#define OCR3CL2 2
-#define OCR3CL3 3
-#define OCR3CL4 4
-#define OCR3CL5 5
-#define OCR3CL6 6
-#define OCR3CL7 7
-
-#define OCR3CH _SFR_MEM8(0x9D)
-#define OCR3CH0 0
-#define OCR3CH1 1
-#define OCR3CH2 2
-#define OCR3CH3 3
-#define OCR3CH4 4
-#define OCR3CH5 5
-#define OCR3CH6 6
-#define OCR3CH7 7
-
-#define UHCON _SFR_MEM8(0x9E)
-
-#define UHINT _SFR_MEM8(0x9F)
-
-#define UHIEN _SFR_MEM8(0xA0)
-
-#define UHADDR _SFR_MEM8(0xA1)
-
-#define UHFNUM _SFR_MEM16(0xA2)
-
-#define UHFNUML _SFR_MEM8(0xA2)
-
-#define UHFNUMH _SFR_MEM8(0xA3)
-
-#define UHFLEN _SFR_MEM8(0xA4)
-
-#define UPINRQX _SFR_MEM8(0xA5)
-
-#define UPINTX _SFR_MEM8(0xA6)
-
-#define UPNUM _SFR_MEM8(0xA7)
-
-#define UPRST _SFR_MEM8(0xA8)
-
-#define UPCONX _SFR_MEM8(0xA9)
-
-#define UPCFG0X _SFR_MEM8(0xAA)
-
-#define UPCFG1X _SFR_MEM8(0xAB)
-
-#define UPSTAX _SFR_MEM8(0xAC)
-
-#define UPCFG2X _SFR_MEM8(0xAD)
-
-#define UPIENX _SFR_MEM8(0xAE)
-
-#define UPDATX _SFR_MEM8(0xAF)
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define TCNT4 _SFR_MEM16(0xBE)
-
-#define TCNT4L _SFR_MEM8(0xBE)
-#define TC40 0
-#define TC41 1
-#define TC42 2
-#define TC43 3
-#define TC44 4
-#define TC45 5
-#define TC46 6
-#define TC47 7
-
-#define TCNT4H _SFR_MEM8(0xBF)  /* Alias for naming consistency. */
-#define TC4H _SFR_MEM8(0xBF)    /* Per XML device file. */
-#define TC48 0
-#define TC49 1
-#define TC410 2
-
-#define TCCR4A _SFR_MEM8(0xC0)
-#define PWM4B 0
-#define PWM4A 1
-#define FOC4B 2
-#define FOC4A 3
-#define COM4B0 4
-#define COM4B1 5
-#define COM4A0 6
-#define COM4A1 7
-
-#define TCCR4B _SFR_MEM8(0xC1)
-#define CS40 0
-#define CS41 1
-#define CS42 2
-#define CS43 3
-#define DTPS40 4
-#define DTPS41 5
-#define PSR4 6
-#define PWM4X 7
-
-#define TCCR4C _SFR_MEM8(0xC2)
-#define PWM4D 0
-#define FOC4D 1
-#define COM4D0 2
-#define COM4D1 3
-#define COM4B0S 4
-#define COM4B1S 5
-#define COM4A0S 6
-#define COM4A1S 7
-
-#define TCCR4D _SFR_MEM8(0xC3)
-#define WGM40 0
-#define WGM41 1
-#define FPF4 2
-#define FPAC4 3
-#define FPES4 4
-#define FPNC4 5
-#define FPEN4 6
-#define FPIE4 7
-
-#define TCCR4E _SFR_MEM8(0xC4)
-#define OC4OE0 0
-#define OC4OE1 1
-#define OC4OE2 2
-#define OC4OE3 3
-#define OC4OE4 4
-#define OC4OE5 5
-#define ENHC4 6
-#define TLOCK4 7
-
-#define CLKSEL0 _SFR_MEM8(0xC5)
-#define CLKS 0
-#define EXTE 2
-#define RCE 3
-#define EXSUT0 4
-#define EXSUT1 5
-#define RCSUT0 6
-#define RCSUT1 7
-
-#define CLKSEL1 _SFR_MEM8(0xC6)
-#define EXCKSEL0 0
-#define EXCKSEL1 1
-#define EXCKSEL2 2
-#define EXCKSEL3 3
-#define RCCKSEL0 4
-#define RCCKSEL1 5
-#define RCCKSEL2 6
-#define RCCKSEL3 7
-
-#define CLKSTA _SFR_MEM8(0xC7)
-#define EXTON 0
-#define RCON 1
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-
-#define UBRR1H _SFR_MEM8(0xCD)
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define OCR4A _SFR_MEM8(0xCF)
-#define OCR4A0 0
-#define OCR4A1 1
-#define OCR4A2 2
-#define OCR4A3 3
-#define OCR4A4 4
-#define OCR4A5 5
-#define OCR4A6 6
-#define OCR4A7 7
-
-#define OCR4B _SFR_MEM8(0xD0)
-#define OCR4B0 0
-#define OCR4B1 1
-#define OCR4B2 2
-#define OCR4B3 3
-#define OCR4B4 4
-#define OCR4B5 5
-#define OCR4B6 6
-#define OCR4B7 7
-
-#define OCR4C _SFR_MEM8(0xD1)
-#define OCR4C0 0
-#define OCR4C1 1
-#define OCR4C2 2
-#define OCR4C3 3
-#define OCR4C4 4
-#define OCR4C5 5
-#define OCR4C6 6
-#define OCR4C7 7
-
-#define OCR4D _SFR_MEM8(0xD2)
-#define OCR4D0 0
-#define OCR4D1 1
-#define OCR4D2 2
-#define OCR4D3 3
-#define OCR4D4 4
-#define OCR4D5 5
-#define OCR4D6 6
-#define OCR4D7 7
-
-#define DT4 _SFR_MEM8(0xD4)
-#define DT4L0 0
-#define DT4L1 1
-#define DT4L2 2
-#define DT4L3 3
-#define DT4L4 4
-#define DT4L5 5
-#define DT4L6 6
-#define DT4L7 7
-
-#define UHWCON _SFR_MEM8(0xD7)
-#define UVREGE 0
-
-#define USBCON _SFR_MEM8(0xD8)
-#define VBUSTE 0
-#define OTGPADE 4
-#define FRZCLK 5
-#define USBE 7
-
-#define USBSTA _SFR_MEM8(0xD9)
-#define VBUS 0
-#define SPEED 3
-
-#define USBINT _SFR_MEM8(0xDA)
-#define VBUSTI 0
-
-#define OTGCON _SFR_MEM8(0xDD)
-
-#define OTGIEN _SFR_MEM8(0xDE)
-
-#define OTGINT _SFR_MEM8(0xDF)
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define LSM 2
-#define RSTCPU 3
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UDTST _SFR_MEM8(0xE7)
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define UENUM_0 0
-#define UENUM_1 1
-#define UENUM_2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-#define EPRST5 5
-#define EPRST6 6
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define DAT0 0
-#define DAT1 1
-#define DAT2 2
-#define DAT3 3
-#define DAT4 4
-#define DAT5 5
-#define DAT6 6
-#define DAT7 7
-
-#define UEBCX _SFR_MEM16(0xF2)
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define BYCT0 0
-#define BYCT1 1
-#define BYCT2 2
-#define BYCT3 3
-#define BYCT4 4
-#define BYCT5 5
-#define BYCT6 6
-#define BYCT7 7
-
-#define UEBCHX _SFR_MEM8(0xF3)
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-#define EPINT5 5
-#define EPINT6 6
-
-#define UPERRX _SFR_MEM8(0xF5)
-
-#define UPBCLX _SFR_MEM8(0xF6)
-
-#define UPBCHX _SFR_MEM8(0xF7)
-
-#define UPINT _SFR_MEM8(0xF8)
-
-#define OTGTCON _SFR_MEM8(0xF9)
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect           _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect           _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect           _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect           _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT6_vect           _VECTOR(7)  /* External Interrupt Request 6 */
-#define PCINT0_vect         _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define USB_GEN_vect        _VECTOR(10)  /* USB General Interrupt Request */
-#define USB_COM_vect        _VECTOR(11)  /* USB Endpoint/Pipe Interrupt Communication Request */
-#define WDT_vect            _VECTOR(12)  /* Watchdog Time-out Interrupt */
-#define TIMER1_CAPT_vect    _VECTOR(16)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(17)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect   _VECTOR(18)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPC_vect   _VECTOR(19)  /* Timer/Counter1 Compare Match C */
-#define TIMER1_OVF_vect     _VECTOR(20)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(21)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect   _VECTOR(22)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect     _VECTOR(23)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect        _VECTOR(24)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect      _VECTOR(25)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect    _VECTOR(26)  /* USART1 Data register Empty */
-#define USART1_TX_vect      _VECTOR(27)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect    _VECTOR(28)  /* Analog Comparator */
-#define ADC_vect            _VECTOR(29)  /* ADC Conversion Complete */
-#define EE_READY_vect       _VECTOR(30)  /* EEPROM Ready */
-#define TIMER3_CAPT_vect    _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect   _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect   _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPC_vect   _VECTOR(34)  /* Timer/Counter3 Compare Match C */
-#define TIMER3_OVF_vect     _VECTOR(35)  /* Timer/Counter3 Overflow */
-#define TWI_vect            _VECTOR(36)  /* 2-wire Serial Interface         */
-#define SPM_READY_vect      _VECTOR(37)  /* Store Program Memory Read */
-#define TIMER4_COMPA_vect   _VECTOR(38)  /* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPB_vect   _VECTOR(39)  /* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPD_vect   _VECTOR(40)  /* Timer/Counter4 Compare Match D */
-#define TIMER4_OVF_vect     _VECTOR(41)  /* Timer/Counter4 Overflow */
-#define TIMER4_FPF_vect     _VECTOR(42)  /* Timer/Counter4 Fault Protection Interrupt */
-
-#define _VECTORS_SIZE (43 * 4)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (0xA00)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)  /* Last On-Chip SRAM Location */
-#define XRAMSTART    (0x2200)
-#define XRAMSIZE     (0x10000)
-#define XRAMEND      (XRAMSIZE - 1)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4) 
-#define FLASHEND     (0x7FFF)
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_HWBE      (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x87
-
-/** @} */
-
-#endif  /* _AVR_IOM32U4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32u6.h b/cpukit/score/cpu/avr/avr/iom32u6.h
deleted file mode 100644
index 9f4211dd80..0000000000
--- a/cpukit/score/cpu/avr/avr/iom32u6.h
+++ /dev/null
@@ -1,1421 +0,0 @@
-/**
- * @file avr/iom32u6.h
- *
- * @brief Definitions for ATmega32U6
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2008 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom32u6.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega32U6_H_
-#define _AVR_ATmega32U6_H_ 1
-
-/**
- *  @defgroup Avr_iom32u6 ATmega32U6 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-#define PINE3 3
-#define PINE4 4
-#define PINE5 5
-#define PINE6 6
-#define PINE7 7
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-#define DDE3 3
-#define DDE4 4
-#define DDE5 5
-#define DDE6 6
-#define DDE7 7
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-#define PORTE3 3
-#define PORTE4 4
-#define PORTE5 5
-#define PORTE6 6
-#define PORTE7 7
-
-#define PINF _SFR_IO8(0x0F)
-#define PINF0 0
-#define PINF1 1
-#define PINF2 2
-#define PINF3 3
-#define PINF4 4
-#define PINF5 5
-#define PINF6 6
-#define PINF7 7
-
-#define DDRF _SFR_IO8(0x10)
-#define DDF0 0
-#define DDF1 1
-#define DDF2 2
-#define DDF3 3
-#define DDF4 4
-#define DDF5 5
-#define DDF6 6
-#define DDF7 7
-
-#define PORTF _SFR_IO8(0x11)
-#define PORTF0 0
-#define PORTF1 1
-#define PORTF2 2
-#define PORTF3 3
-#define PORTF4 4
-#define PORTF5 5
-#define PORTF6 6
-#define PORTF7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define OCF3C 3
-#define ICF3 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLP0 2
-#define PLLP1 3
-#define PLLP2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRTIM3 3
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define OCIE3C 3
-#define ICIE3 5
-
-#define XMCRA _SFR_MEM8(0x74)
-#define SRW00 0
-#define SRW01 1
-#define SRW10 2
-#define SRW11 3
-#define SRL0 4
-#define SRL1 5
-#define SRL2 6
-#define SRE 7
-
-#define XMCRB _SFR_MEM8(0x75)
-#define XMM0 0
-#define XMM1 1
-#define XMM2 2
-#define XMBK 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3C0 2
-#define COM3C1 3
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3C 5
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3BL0 0
-#define OCR3BL1 1
-#define OCR3BL2 2
-#define OCR3BL3 3
-#define OCR3BL4 4
-#define OCR3BL5 5
-#define OCR3BL6 6
-#define OCR3BL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3BH0 0
-#define OCR3BH1 1
-#define OCR3BH2 2
-#define OCR3BH3 3
-#define OCR3BH4 4
-#define OCR3BH5 5
-#define OCR3BH6 6
-#define OCR3BH7 7
-
-#define OCR3C _SFR_MEM16(0x9C)
-
-#define OCR3CL _SFR_MEM8(0x9C)
-#define OCR3CL0 0
-#define OCR3CL1 1
-#define OCR3CL2 2
-#define OCR3CL3 3
-#define OCR3CL4 4
-#define OCR3CL5 5
-#define OCR3CL6 6
-#define OCR3CL7 7
-
-#define OCR3CH _SFR_MEM8(0x9D)
-#define OCR3CH0 0
-#define OCR3CH1 1
-#define OCR3CH2 2
-#define OCR3CH3 3
-#define OCR3CH4 4
-#define OCR3CH5 5
-#define OCR3CH6 6
-#define OCR3CH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A_0 0
-#define OCR2A_1 1
-#define OCR2A_2 2
-#define OCR2A_3 3
-#define OCR2A_4 4
-#define OCR2A_5 5
-#define OCR2A_6 6
-#define OCR2A_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B_0 0
-#define OCR2B_1 1
-#define OCR2B_2 2
-#define OCR2B_3 3
-#define OCR2B_4 4
-#define OCR2B_5 5
-#define OCR2B_6 6
-#define OCR2B_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR_0 0
-#define UBRR_1 1
-#define UBRR_2 2
-#define UBRR_3 3
-#define UBRR_4 4
-#define UBRR_5 5
-#define UBRR_6 6
-#define UBRR_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR_8 0
-#define UBRR_9 1
-#define UBRR_10 2
-#define UBRR_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define UHWCON _SFR_MEM8(0xD7)
-#define UVREGE 0
-#define UVCONE 4
-#define UIDE 6
-#define UIMOD 7
-
-#define USBCON _SFR_MEM8(0xD8)
-#define VBUSTE 0
-#define IDTE 1
-#define OTGPADE 4
-#define FRZCLK 5
-#define HOST 6
-#define USBE 7
-
-#define USBSTA _SFR_MEM8(0xD9)
-#define VBUS 0
-#define ID 1
-#define SPEED 3
-
-#define USBINT _SFR_MEM8(0xDA)
-#define VBUSTI 0
-#define IDTI 1
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define LSM 2
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define UDFNUML_0 0
-#define UDFNUML_1 1
-#define UDFNUML_2 2
-#define UDFNUML_3 3
-#define UDFNUML_4 4
-#define UDFNUML_5 5
-#define UDFNUML_6 6
-#define UDFNUML_7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define UDFNUMH_0 0
-#define UDFNUMH_1 1
-#define UDFNUMH_2 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define UENUM_0 0
-#define UENUM_1 1
-#define UENUM_2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-#define EPRST5 5
-#define EPRST6 6
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define UEDATX_0 0
-#define UEDATX_1 1
-#define UEDATX_2 2
-#define UEDATX_3 3
-#define UEDATX_4 4
-#define UEDATX_5 5
-#define UEDATX_6 6
-#define UEDATX_7 7
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define UEBCLX_0 0
-#define UEBCLX_1 1
-#define UEBCLX_2 2
-#define UEBCLX_3 3
-#define UEBCLX_4 4
-#define UEBCLX_5 5
-#define UEBCLX_6 6
-#define UEBCLX_7 7
-
-#define UEBCHX _SFR_MEM8(0xF3)
-#define UEBCHX_0 0
-#define UEBCHX_1 1
-#define UEBCHX_2 2
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-#define EPINT5 5
-#define EPINT6 6
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT4_vect_num  5
-#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
-#define INT5_vect_num  6
-#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
-#define INT6_vect_num  7
-#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
-#define INT7_vect_num  8
-#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
-#define PCINT0_vect_num  9
-#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define USB_GEN_vect_num  10
-#define USB_GEN_vect      _VECTOR(10)  /* USB General Interrupt Request */
-#define USB_COM_vect_num  11
-#define USB_COM_vect      _VECTOR(11)  /* USB Endpoint/Pipe Interrupt Communication Request */
-#define WDT_vect_num  12
-#define WDT_vect      _VECTOR(12)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  13
-#define TIMER2_COMPA_vect      _VECTOR(13)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  14
-#define TIMER2_COMPB_vect      _VECTOR(14)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect_num  15
-#define TIMER2_OVF_vect      _VECTOR(15)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  16
-#define TIMER1_CAPT_vect      _VECTOR(16)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  17
-#define TIMER1_COMPA_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  18
-#define TIMER1_COMPB_vect      _VECTOR(18)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPC_vect_num  19
-#define TIMER1_COMPC_vect      _VECTOR(19)  /* Timer/Counter1 Compare Match C */
-#define TIMER1_OVF_vect_num  20
-#define TIMER1_OVF_vect      _VECTOR(20)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  21
-#define TIMER0_COMPA_vect      _VECTOR(21)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  22
-#define TIMER0_COMPB_vect      _VECTOR(22)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  23
-#define TIMER0_OVF_vect      _VECTOR(23)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  24
-#define SPI_STC_vect      _VECTOR(24)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect_num  25
-#define USART1_RX_vect      _VECTOR(25)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect_num  26
-#define USART1_UDRE_vect      _VECTOR(26)  /* USART1 Data register Empty */
-#define USART1_TX_vect_num  27
-#define USART1_TX_vect      _VECTOR(27)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect_num  28
-#define ANALOG_COMP_vect      _VECTOR(28)  /* Analog Comparator */
-#define ADC_vect_num  29
-#define ADC_vect      _VECTOR(29)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  30
-#define EE_READY_vect      _VECTOR(30)  /* EEPROM Ready */
-#define TIMER3_CAPT_vect_num  31
-#define TIMER3_CAPT_vect      _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect_num  32
-#define TIMER3_COMPA_vect      _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect_num  33
-#define TIMER3_COMPB_vect      _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPC_vect_num  34
-#define TIMER3_COMPC_vect      _VECTOR(34)  /* Timer/Counter3 Compare Match C */
-#define TIMER3_OVF_vect_num  35
-#define TIMER3_OVF_vect      _VECTOR(35)  /* Timer/Counter3 Overflow */
-#define TWI_vect_num  36
-#define TWI_vect      _VECTOR(36)  /* 2-wire Serial Interface         */
-#define SPM_READY_vect_num  37
-#define SPM_READY_vect      _VECTOR(37)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (2560)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x2200)
-#define XRAMSIZE     (65536)
-#define XRAMEND      (XRAMSIZE - 1)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x88
-
-
-/**@}*/
-#endif /* _AVR_ATmega32U6_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom406.h b/cpukit/score/cpu/avr/avr/iom406.h
deleted file mode 100644
index b0baafd024..0000000000
--- a/cpukit/score/cpu/avr/avr/iom406.h
+++ /dev/null
@@ -1,780 +0,0 @@
-/**
- * @file avr/iom406.h
- *
- * @brief Definitions for ATmega406
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2006, Pieter Conradie
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM406_H_
-#define _AVR_IOM406_H_ 1
-
-/**
- *  @defgroup Avr_iom406 ATmega406 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom406.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Reserved [0x06..0x07] */
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD1     1
-#define PD0     0
-
-/* Reserved [0x0C..0x14] */
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-#define OCF1A   1
-#define TOV1    0
-
-/* Reserved [0x17..0x1A] */
-
-/* Pin Change Interrupt Control Register */
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF1   1
-#define PCIF0   0
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-/* External Interrupt MaSK register */
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT3    3
-#define INT2    2
-#define INT1    1
-#define INT0    0
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1F)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x20)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x21)
-#define EEARL	_SFR_IO8(0x21)
-#define EEARH	_SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR	_SFR_IO8(0x23)
-#define TSM     7
-#define PSRSYNC 0
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-/* Timer/Counter 0 */
-#define TCNT0   _SFR_IO8(0x26)
-
-/* Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-
-/* Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-
-/* Reserved [0x29] */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x2A)
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x2B)
-
-/* Reserved [0x2C..0x30] */
-
-/* On-chip Debug Register */
-#define OCDR    _SFR_IO8(0x31)
-
-/* Reserved [0x32] */
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-#define JTRF    4
-#define WDRF    3
-#define BODRF   2
-#define EXTRF   1
-#define PORF    0
-
-/* MCU general Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-#define JTD     7
-#define PUD     4
-#define IVSEL   1
-#define IVCE    0
-
-/* Reserved [0x36] */
-
-/* Store Program Memory Control and Status Register */
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMIE   7
-#define RWWSB   6
-#define SIGRD   5
-#define RWWSRE  4
-#define BLBSET  3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* Reserved [0x36..0x3C] */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Extended I/O registers */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-/* Reserved [0x61] */
-
-/* Wake-up Timer Control and Status Register */
-#define WUTCSR  _SFR_MEM8(0x62)
-#define WUTIF   7
-#define WUTIE   6
-#define WUTCF   5
-#define WUTR    4
-#define WUTE    3
-#define WUTP2   2
-#define WUTP1   1
-#define WUTP0   0
-
-/* Reserved [0x63] */
-
-/* Power Reduction Register 0 */
-#define PRR0    _SFR_MEM8(0x64)
-#define PRTWI   3
-#define PRTIM1  2
-#define PRTIM0  1
-#define PRVADC  0
-
-/* Reserved [0x65] */
-
-/* Fast Oscillator Calibration Register */
-#define FOSCCAL _SFR_MEM8(0x66)
-
-/* Reserved [0x67] */
-
-/* Pin Change Interrupt Control Register */
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE1   1
-#define PCIE0   0
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Reserved [0x6A] */
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9  1
-#define PCINT8  0
-
-/* Reserved [0x6D] */
-
-/* Timer/Counter Interrupt MaSK register 0 */
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-/* Timer/Counter Interrupt MaSK register 1 */
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define OCIE1A  1
-#define TOIE1   0
-
-/* Reserved [0x70..0x77] */
-
-/* V-ADC Data Register */
-#define VADC	_SFR_MEM16(0x78)
-#define VADCL	_SFR_MEM8(0x78)
-#define VADCH	_SFR_MEM8(0x79)
-
-/* V-ADC Control and Status Register */
-#define VADCSR	_SFR_MEM8(0x7A)
-#define VADEN   3
-#define VADSC   2
-#define VADCCIF 1
-#define VADCCIE 0
-
-/* Reserved [0x7B] */
-
-/* V-ADC Multiplexer Selection Register */
-#define VADMUX	_SFR_MEM8(0x7C)
-#define VADMUX3 3
-#define VADMUX2 2
-#define VADMUX1 1
-#define VADMUX0 0
-
-/* Reserved [0x7D] */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0	_SFR_MEM8(0x7E)
-#define VADC3D  3
-#define VADC2D  2
-#define VADC1D  1
-#define VADC0D  0
-
-/* Reserved [0x82..0x83] */
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CTC1    3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-/* Reserved [0x82..0x83] */
-
-/* Timer/Counter 1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Reserved [0x86..0x87] */
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Reserved [0x8A..0xB7] */
-
-/* 2-wire Serial Interface Bit Rate Register */
-#define TWBR    _SFR_MEM8(0xB8)
-
-/* 2-wire Serial Interface Status Register */
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWS7    7
-#define TWS6    6
-#define TWS5    5
-#define TWS4    4
-#define TWS3    3
-#define TWPS1   1
-#define TWPS0   0
-
-/* 2-wire Serial Interface Address Register */
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE   0
-
-/* 2-wire Serial Interface Data Register */
-#define TWDR    _SFR_MEM8(0xBB)
-
-/* 2-wire Serial Interface Control Register */
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWINT   7
-#define TWEA    6
-#define TWSTA   5
-#define TWSTO   4
-#define TWWC    3
-#define TWEN    2
-#define TWIE    0
-
-/* 2-wire Serial (Slave) Address Mask Register */
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM6   7
-#define TWAM5   6
-#define TWAM4   5
-#define TWAM3   4
-#define TWAM2   3
-#define TWAM1   2
-#define TWAM0   1
-
-/* 2-wire Serial Bus Control and Status Register */
-#define TWBCSR  _SFR_MEM8(0xBE)
-#define TWBCIF  7
-#define TWBCIE  6
-#define TWBDT1  2
-#define TWBDT0  1
-#define TWBCIP  0
-
-/* Reserved [0xBF] */
-
-/* Clock Control Status Register */
-#define CCSR    _SFR_MEM8(0xC0)
-#define XOE     1
-#define ACS     0
-
-/* Reserved [0xC1..0xCF] */
-
-/* Bandgap Calibration C Register */
-#define BGCCR   _SFR_MEM8(0xD0)
-#define BGEN    7
-#define BGCC5   5
-#define BGCC4   4
-#define BGCC3   3
-#define BGCC2   2
-#define BGCC1   1
-#define BGCC0   0
-
-/* Bandgap Calibration R Register */
-#define BGCRR   _SFR_MEM8(0xD1)
-#define BGCR7   7
-#define BGCR6   6
-#define BGCR5   5
-#define BGCR4   4
-#define BGCR3   3
-#define BGCR2   2
-#define BGCR1   1
-#define BGCR0   0
-
-/* Reserved [0xD2..0xDF] */
-
-/* CC-ADC Accumulate Current */
-/* TODO: Add _SFR_MEM32 */
-/* #define CADAC   _SFR_MEM32(0xE0) */
-#define CADAC0  _SFR_MEM8(0xE0)
-#define CADAC1  _SFR_MEM8(0xE1)
-#define CADAC2  _SFR_MEM8(0xE2)
-#define CADAC3  _SFR_MEM8(0xE3)
-
-/* CC-ADC Control and Status Register A */
-#define CADCSRA _SFR_MEM8(0xE4)
-#define CADEN   7
-#define CADUB   5
-#define CADAS1  4
-#define CADAS0  3
-#define CADSI1  2
-#define CADSI0  1
-#define CADSE   0
-
-/* CC-ADC Control and Status Register B */
-#define CADCSRB _SFR_MEM8(0xE5)
-#define CADACIE 6
-#define CADRCIE 5
-#define CADICIE 4
-#define CADACIF 2
-#define CADRCIF 1
-#define CADICIF 0
-
-/* CC-ADC Regular Charge Current */
-#define CADRCC  _SFR_MEM8(0xE6)
-
-/* CC-ADC Regular Discharge Current */
-#define CADRDC  _SFR_MEM8(0xE7)
-
-/* CC-ADC Instantaneous Current */
-#define CADIC   _SFR_MEM16(0xE8)
-#define CADICL  _SFR_MEM8(0xE8)
-#define CADICH  _SFR_MEM8(0xE9)
-
-/* Reserved [0xEA..0xEF] */
-
-/* FET Control and Status Register */
-#define FCSR    _SFR_MEM8(0xF0)
-#define PWMOC   5
-#define PWMOPC  4
-#define CPS     3
-#define DFE     2
-#define CFE     1
-#define PFD     0
-
-/* Cell Balancing Control Register */
-#define CBCR    _SFR_MEM8(0xF1)
-#define CBE4    3
-#define CBE3    2
-#define CBE2    1
-#define CBE1    0
-
-/* Battery Protection Interrupt Register */
-#define BPIR    _SFR_MEM8(0xF2)
-#define DUVIF   7
-#define COCIF   6
-#define DOCIF   5
-#define SCIF    4
-#define DUVIE   3
-#define COCIE   2
-#define DOCIE   1
-#define SCIE    0
-
-/* Battery Protection Deep Under Voltage Register */
-#define BPDUV   _SFR_MEM8(0xF3)
-#define DUVT1   5
-#define DUVT0   4
-#define DUDL3   3
-#define DUDL2   2
-#define DUDL1   1
-#define DUDL0   0
-
-/* Battery Protection Short-circuit Detection Level Register */
-#define BPSCD   _SFR_MEM8(0xF4)
-#define SCDL3   3
-#define SCDL2   2
-#define SCDL1   1
-#define SCDL0   0
-
-/* Battery Protection Over-current Detection Level Register */
-#define BPOCD   _SFR_MEM8(0xF5)
-#define DCDL3   7
-#define DCDL2   6
-#define DCDL1   5
-#define DCDL0   4
-#define CCDL3   3
-#define CCDL2   2
-#define CCDL1   1
-#define CCDL0   0
-
-/* Current Battery Protection Timing Register */
-#define CBPTR   _SFR_MEM8(0xF6)
-#define SCPT3   7
-#define SCPT2   6
-#define SCPT1   5
-#define SCPT0   4
-#define OCPT3   3
-#define OCPT2   2
-#define OCPT1   1
-#define OCPT0   0
-
-/* Battery Protection Control Register */
-#define BPCR    _SFR_MEM8(0xF7)
-#define DUVD    3
-#define SCD     2
-#define DCD     1
-#define CCD     0
-
-/* Battery Protection Parameter Lock Register */
-#define BPPLR   _SFR_MEM8(0xF8)
-#define BPPLE   1
-#define BPPL    0
-
-/* Reserved [0xF9..0xFF] */
-
-/* Interrupt vectors */
-/* Battery Protection Interrupt */
-#define BPINT_vect			_VECTOR(1)
-
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(2)
-
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(3)
-
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(4)
-
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(5)
-
-
-/* Pin Change Interrupt 0 */
-#define PCINT0_vect			_VECTOR(6)
-
-
-/* Pin Change Interrupt 1 */
-#define PCINT1_vect			_VECTOR(7)
-
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(8)
-
-
-/* Wakeup timer overflow */
-#define WAKE_UP_vect			_VECTOR(9)
-
-
-/* Timer/Counter 1 Compare Match */
-#define TIM1_COMP_vect			_VECTOR(10)
-
-
-/* Timer/Counter 1 Overflow */
-#define TIM1_OVF_vect			_VECTOR(11)
-
-
-/* Timer/Counter0 Compare A Match */
-#define TIM0_COMPA_vect			_VECTOR(12)
-
-
-/* Timer/Counter0 Compare B Match */
-#define TIM0_COMPB_vect			_VECTOR(13)
-
-
-/* Timer/Counter0 Overflow */
-#define TIM0_OVF_vect			_VECTOR(14)
-
-
-/* Two-Wire Bus Connect/Disconnect */
-#define TWI_BUS_CD_vect			_VECTOR(15)
-
-
-/* Two-Wire Serial Interface */
-#define TWI_vect			_VECTOR(16)
-
-
-/* Voltage ADC Conversion Complete */
-#define VADC_vect			_VECTOR(17)
-
-
-/* Coulomb Counter ADC Conversion Complete */
-#define CCADC_CONV_vect			_VECTOR(18)
-
-/* Coloumb Counter ADC Regular Current */
-#define CCADC_REG_CUR_vect		_VECTOR(19)
-
-
-/* Coloumb Counter ADC Accumulator */
-#define CCADC_ACC_vect			_VECTOR(20)
-
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(21)
-
-
-/* Store Program Memory Ready */
-#define SPM_READY_vect			_VECTOR(22)
-
-#define _VECTORS_SIZE 92
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND       0x8FF
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x9FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL   (unsigned char)~_BV(0)
-#define FUSE_SUT0    (unsigned char)~_BV(1)
-#define FUSE_SUT1    (unsigned char)~_BV(2)
-#define FUSE_BOOTRST (unsigned char)~_BV(3)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(4)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(5)
-#define FUSE_EESAVE  (unsigned char)~_BV(6)
-#define FUSE_WDTON   (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-/* High Fuse Byte */
-#define FUSE_JTAGEN      (unsigned char)~_BV(0)
-#define FUSE_OCDEN       (unsigned char)~_BV(1)
-#define HFUSE_DEFAULT (FUSE_JTAGEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x07
-
-
-/**@}*/
-#endif /* _AVR_IOM406_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom48.h b/cpukit/score/cpu/avr/avr/iom48.h
deleted file mode 100644
index 2840dff539..0000000000
--- a/cpukit/score/cpu/avr/avr/iom48.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for iom48
- */
-
-/*
- *  Copyright (c) 2004, Theodore A. Roth
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM48_H_
-#define _AVR_IOM48_H_ 1
-
-/**
- *  @defgroup Avr_iom48 iom48 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomx8.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND      0x2FF
-#define XRAMEND     RAMEND
-#define E2END       0xFF
-#define E2PAGESIZE  4
-#define FLASHEND    0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0 (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1 (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN (unsigned char)~_BV(0)  /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x05
-
-/**@}*/
-#endif /* _AVR_IOM48_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom48p.h b/cpukit/score/cpu/avr/avr/iom48p.h
deleted file mode 100644
index db48949ae3..0000000000
--- a/cpukit/score/cpu/avr/avr/iom48p.h
+++ /dev/null
@@ -1,879 +0,0 @@
-/**
- * @file avr/iom48p.h
- *
- * @brief Definitions for ATmega48P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2007 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom48p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM48P_H_
-#define _AVR_IOM48P_H_ 1
-
-/**
- *  @defgroup Avr_iom48p ATmega48P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-/* Only valid for ATmega88P-168P-328P */
-/* EEARH _SFR_IO8(0x22) */
-
-#define EEPROM_REG_LOCATIONS 1F2021
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCPHA0 1
-#define UCSZ01 2
-#define UDORD0 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect         _VECTOR(1)   /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)   /* External Interrupt Request 1 */
-#define PCINT0_vect       _VECTOR(3)   /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(4)   /* Pin Change Interrupt Request 0 */
-#define PCINT2_vect       _VECTOR(5)   /* Pin Change Interrupt Request 1 */
-#define WDT_vect          _VECTOR(6)   /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(7)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(8)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(16)  /* Timer/Couner0 Overflow */
-#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect     _VECTOR(18)  /* USART Rx Complete */
-#define USART_UDRE_vect   _VECTOR(19)  /* USART, Data Register Empty */
-#define USART_TX_vect     _VECTOR(20)  /* USART Tx Complete */
-#define ADC_vect          _VECTOR(21)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(22)  /* EEPROM Ready */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define TWI_vect          _VECTOR(24)  /* Two-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(25)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE (26 * 2)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x2FF     /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0xFF
-#define E2PAGESIZE   4
-#define FLASHEND     0xFFF
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN (unsigned char)~_BV(0)  /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x0A
-
-
-/**@}*/
-#endif  /* _AVR_IOM48P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom64.h b/cpukit/score/cpu/avr/avr/iom64.h
deleted file mode 100644
index 8164d6a420..0000000000
--- a/cpukit/score/cpu/avr/avr/iom64.h
+++ /dev/null
@@ -1,1226 +0,0 @@
-/* Copyright (c) 2002, Steinar Haugen
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom64.h - defines for ATmega64 
-
-   As of 2002-11-23:
-   - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */
-
-#ifndef _AVR_IOM64_H_
-#define _AVR_IOM64_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom64.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Input Pins, Port F */
-#define PINF      _SFR_IO8(0x00)
-
-/* Input Pins, Port E */
-#define PINE      _SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE      _SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE     _SFR_IO8(0x03)
-
-/* ADC Data Register */
-#define ADCW      _SFR_IO16(0x04) /* for backwards compatibility */
-#ifndef __ASSEMBLER__
-#define ADC       _SFR_IO16(0x04)
-#endif
-#define ADCL      _SFR_IO8(0x04)
-#define ADCH      _SFR_IO8(0x05)
-
-/* ADC Control and Status Register A */
-#define ADCSR     _SFR_IO8(0x06) /* for backwards compatibility */
-#define ADCSRA    _SFR_IO8(0x06) 
-
-/* ADC Multiplexer select */
-#define ADMUX     _SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR      _SFR_IO8(0x08)
-
-/* USART0 Baud Rate Register Low */
-#define UBRR0L    _SFR_IO8(0x09)
-
-/* USART0 Control and Status Register B */
-#define UCSR0B    _SFR_IO8(0x0A)
-
-/* USART0 Control and Status Register A */
-#define UCSR0A    _SFR_IO8(0x0B)
-
-/* USART0 I/O Data Register */
-#define UDR0      _SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR      _SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR      _SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR      _SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND      _SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD      _SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD     _SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC      _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC      _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC     _SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB      _SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB      _SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB     _SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA      _SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA      _SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA     _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Special Function I/O Register */
-#define SFIOR     _SFR_IO8(0x20)
-
-/* Watchdog Timer Control Register */
-#define WDTCR     _SFR_IO8(0x21)
-
-/* On-chip Debug Register */
-#define OCDR      _SFR_IO8(0x22)
-
-/* Timer2 Output Compare Register */
-#define OCR2      _SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2     _SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control register */
-#define TCCR2     _SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1      _SFR_IO16(0x26)
-#define ICR1L     _SFR_IO8(0x26)
-#define ICR1H     _SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B     _SFR_IO16(0x28)
-#define OCR1BL    _SFR_IO8(0x28)
-#define OCR1BH    _SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A     _SFR_IO16(0x2A)
-#define OCR1AL    _SFR_IO8(0x2A)
-#define OCR1AH    _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1     _SFR_IO16(0x2C)
-#define TCNT1L    _SFR_IO8(0x2C)
-#define TCNT1H    _SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B    _SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A    _SFR_IO8(0x2F)
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define ASSR      _SFR_IO8(0x30)
-
-/* Output Compare Register 0 */
-#define OCR0      _SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0     _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0     _SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR     _SFR_IO8(0x34) /* for backwards compatibility */
-#define MCUCSR    _SFR_IO8(0x34) 
-
-/* MCU general Control Register */
-#define MCUCR     _SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR      _SFR_IO8(0x36)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK     _SFR_IO8(0x37)
-
-/* External Interrupt Flag Register */
-#define EIFR      _SFR_IO8(0x38)
-
-/* External Interrupt MaSK register */
-#define EIMSK     _SFR_IO8(0x39)
-
-/* External Interrupt Control Register B */
-#define EICRB     _SFR_IO8(0x3A)
-
-/* XDIV Divide control register */
-#define XDIV      _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Extended I/O registers */
-
-/* Data Direction Register, Port F */
-#define DDRF      _SFR_MEM8(0x61)
-
-/* Data Register, Port F */
-#define PORTF     _SFR_MEM8(0x62)
-
-/* Input Pins, Port G */
-#define PING      _SFR_MEM8(0x63)
-
-/* Data Direction Register, Port G */
-#define DDRG      _SFR_MEM8(0x64)
-
-/* Data Register, Port G */
-#define PORTG     _SFR_MEM8(0x65)
-
-/* Store Program Memory Control and Status Register */
-#define SPMCR     _SFR_MEM8(0x68) 
-#define SPMCSR    _SFR_MEM8(0x68) /* for backwards compatibility with m128*/
-
-/* External Interrupt Control Register A */
-#define EICRA     _SFR_MEM8(0x6A)
-
-/* External Memory Control Register B */
-#define XMCRB     _SFR_MEM8(0x6C)
-
-/* External Memory Control Register A */
-#define XMCRA     _SFR_MEM8(0x6D)
-
-/* Oscillator Calibration Register */
-#define OSCCAL    _SFR_MEM8(0x6F)
-
-/* 2-wire Serial Interface Bit Rate Register */
-#define TWBR      _SFR_MEM8(0x70)
-
-/* 2-wire Serial Interface Status Register */
-#define TWSR      _SFR_MEM8(0x71)
-
-/* 2-wire Serial Interface Address Register */
-#define TWAR      _SFR_MEM8(0x72)
-
-/* 2-wire Serial Interface Data Register */
-#define TWDR      _SFR_MEM8(0x73)
-
-/* 2-wire Serial Interface Control Register */
-#define TWCR      _SFR_MEM8(0x74)
-
-/* Time Counter 1 Output Compare Register C */
-#define OCR1C     _SFR_MEM16(0x78)
-#define OCR1CL    _SFR_MEM8(0x78)
-#define OCR1CH    _SFR_MEM8(0x79)
-
-/* Timer/Counter 1 Control Register C */
-#define TCCR1C    _SFR_MEM8(0x7A)
-
-/* Extended Timer Interrupt Flag Register */
-#define ETIFR     _SFR_MEM8(0x7C)
-
-/* Extended Timer Interrupt Mask Register */
-#define ETIMSK    _SFR_MEM8(0x7D)
-
-/* Timer/Counter 3 Input Capture Register */
-#define ICR3      _SFR_MEM16(0x80)
-#define ICR3L     _SFR_MEM8(0x80)
-#define ICR3H     _SFR_MEM8(0x81)
-
-/* Timer/Counter 3 Output Compare Register C */
-#define OCR3C     _SFR_MEM16(0x82)
-#define OCR3CL    _SFR_MEM8(0x82)
-#define OCR3CH    _SFR_MEM8(0x83)
-
-/* Timer/Counter 3 Output Compare Register B */
-#define OCR3B     _SFR_MEM16(0x84)
-#define OCR3BL    _SFR_MEM8(0x84)
-#define OCR3BH    _SFR_MEM8(0x85)
-
-/* Timer/Counter 3 Output Compare Register A */
-#define OCR3A     _SFR_MEM16(0x86)
-#define OCR3AL    _SFR_MEM8(0x86)
-#define OCR3AH    _SFR_MEM8(0x87)
-
-/* Timer/Counter 3 Counter Register */
-#define TCNT3     _SFR_MEM16(0x88)
-#define TCNT3L    _SFR_MEM8(0x88)
-#define TCNT3H    _SFR_MEM8(0x89)
-
-/* Timer/Counter 3 Control Register B */
-#define TCCR3B    _SFR_MEM8(0x8A)
-
-/* Timer/Counter 3 Control Register A */
-#define TCCR3A    _SFR_MEM8(0x8B)
-
-/* Timer/Counter 3 Control Register C */
-#define TCCR3C    _SFR_MEM8(0x8C)
-
-/* ADC Control and Status Register B */
-#define ADCSRB    _SFR_MEM8(0x8E)
-
-/* USART0 Baud Rate Register High */
-#define UBRR0H    _SFR_MEM8(0x90)
-
-/* USART0 Control and Status Register C */
-#define UCSR0C    _SFR_MEM8(0x95)
-
-/* USART1 Baud Rate Register High */
-#define UBRR1H    _SFR_MEM8(0x98)
-
-/* USART1 Baud Rate Register Low*/
-#define UBRR1L    _SFR_MEM8(0x99)
-
-/* USART1 Control and Status Register B */
-#define UCSR1B    _SFR_MEM8(0x9A)
-
-/* USART1 Control and Status Register A */
-#define UCSR1A    _SFR_MEM8(0x9B)
-
-/* USART1 I/O Data Register */
-#define UDR1      _SFR_MEM8(0x9C)
-
-/* USART1 Control and Status Register C */
-#define UCSR1C    _SFR_MEM8(0x9D)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(14)
-#define SIG_OVERFLOW1			_VECTOR(14)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(15)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(18)
-#define SIG_UART0_RECV			_VECTOR(18)
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect		_VECTOR(19)
-#define SIG_UART0_DATA			_VECTOR(19)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(20)
-#define SIG_UART0_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(24)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(24)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(25)
-#define SIG_INPUT_CAPTURE3		_VECTOR(25)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(26)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(26)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(27)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(28)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(28)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(29)
-#define SIG_OVERFLOW3			_VECTOR(29)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(30)
-#define SIG_UART1_RECV			_VECTOR(30)
-
-/* USART1, Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(31)
-#define SIG_UART1_DATA			_VECTOR(31)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(32)
-#define SIG_UART1_TRANS			_VECTOR(32)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(33)
-#define SIG_2WIRE_SERIAL		_VECTOR(33)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(34)
-#define SIG_SPM_READY			_VECTOR(34)
-
-#define _VECTORS_SIZE 140
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* 2-wire Control Register - TWCR */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-
-/* 2-wire Address Register - TWAR */
-#define    TWA6         7
-#define    TWA5         6
-#define    TWA4         5
-#define    TWA3         4
-#define    TWA2         3
-#define    TWA1         2
-#define    TWA0         1
-#define    TWGCE        0
-
-/* 2-wire Status Register - TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-
-/* External Memory Control Register A - XMCRA */
-#define    SRL2         6
-#define    SRL1         5
-#define    SRL0         4
-#define    SRW01        3
-#define    SRW00        2
-#define    SRW11        1
-
-/* External Memory Control Register B - XMCRA */
-#define    XMBK         7
-#define    XMM2         2
-#define    XMM1         1
-#define    XMM0         0
-
-/* XDIV Divide control register - XDIV */
-#define    XDIVEN       7
-#define    XDIV6        6
-#define    XDIV5        5
-#define    XDIV4        4
-#define    XDIV3        3
-#define    XDIV2        2
-#define    XDIV1        1
-#define    XDIV0        0
-
-/* External Interrupt Control Register A - EICRA */
-#define    ISC31        7
-#define    ISC30        6
-#define    ISC21        5
-#define    ISC20        4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* External Interrupt Control Register B - EICRB */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-
-/* Store Program Memory Control Register - SPMCSR, SPMCR */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-
-/* External Interrupt MaSK register - EIMSK */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-
-/* External Interrupt Flag Register - EIFR */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-#define    INTF3        3
-#define    INTF2        2
-#define    INTF1        1
-#define    INTF0        0
-
-/* Timer/Counter Interrupt MaSK register - TIMSK */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag Register - TIFR */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* Extended Timer Interrupt MaSK register - ETIMSK */
-#define    TICIE3       5
-#define    OCIE3A       4
-#define    OCIE3B       3
-#define    TOIE3        2
-#define    OCIE3C       1
-#define    OCIE1C       0
-
-/* Extended Timer Interrupt Flag Register - ETIFR */
-#define    ICF3         5
-#define    OCF3A        4
-#define    OCF3B        3
-#define    TOV3         2
-#define    OCF3C        1
-#define    OCF1C        0
-
-/* MCU Control Register - MCUCR */
-#define    SRE          7
-#define    SRW10        6
-#define    SE           5
-#define    SM1          4
-#define    SM0          3
-#define    SM2          2
-#define    IVSEL        1
-#define    IVCE         0
-
-/* MCU Control And Status Register - MCUCSR */
-#define    JTD          7
-#define    JTRF         4
-#define    WDRF         3
-#define    BORF         2
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter Control Register (generic) */
-#define    FOC          7
-#define    WGM0         6
-#define    COM1         5
-#define    COM0         4
-#define    WGM1         3
-#define    CS2          2
-#define    CS1          1
-#define    CS0          0
-
-/* Timer/Counter 0 Control Register - TCCR0 */
-#define    FOC0         7
-#define    WGM00        6
-#define    COM01        5
-#define    COM00        4
-#define    WGM01        3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 2 Control Register - TCCR2 */
-#define    FOC2         7
-#define    WGM20        6
-#define    COM21        5
-#define    COM20        4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */
-#define    AS0          3
-#define    TCN0UB       2
-#define    OCR0UB       1
-#define    TCR0UB       0
-
-/* Timer/Counter Control Register A (generic) */
-#define    COMA1        7
-#define    COMA0        6
-#define    COMB1        5
-#define    COMB0        4
-#define    COMC1        3
-#define    COMC0        2
-#define    WGMA1        1
-#define    WGMA0        0
-
-/* Timer/Counter 1 Control and Status Register A - TCCR1A */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    COM1C1       3
-#define    COM1C0       2
-#define    WGM11        1
-#define    WGM10        0
-
-/* Timer/Counter 3 Control and Status Register A - TCCR3A */
-#define    COM3A1       7
-#define    COM3A0       6
-#define    COM3B1       5
-#define    COM3B0       4
-#define    COM3C1       3
-#define    COM3C0       2
-#define    WGM31        1
-#define    WGM30        0
-
-/* Timer/Counter Control and Status Register B (generic) */
-#define    ICNC         7
-#define    ICES         6
-#define    WGMB3        4
-#define    WGMB2        3
-#define    CSB2         2
-#define    CSB1         1
-#define    CSB0         0
-
-/* Timer/Counter 1 Control and Status Register B - TCCR1B */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 3 Control and Status Register B - TCCR3B */
-#define    ICNC3        7
-#define    ICES3        6
-#define    WGM33        4
-#define    WGM32        3
-#define    CS32         2
-#define    CS31         1
-#define    CS30         0
-
-/* Timer/Counter Control Register C (generic) */
-#define    FOCA         7
-#define    FOCB         6
-#define    FOCC         5
-
-/* Timer/Counter 3 Control Register C - TCCR3C */
-#define    FOC3A        7
-#define    FOC3B        6
-#define    FOC3C        5
-
-/* Timer/Counter 1 Control Register C - TCCR1C */
-#define    FOC1A        7
-#define    FOC1B        6
-#define    FOC1C        5
-
-/* On-chip Debug Register - OCDR */
-#define    IDRD         7
-#define    OCDR7        7
-#define    OCDR6        6
-#define    OCDR5        5
-#define    OCDR4        4
-#define    OCDR3        3
-#define    OCDR2        2
-#define    OCDR1        1
-#define    OCDR0        0
-
-/* Watchdog Timer Control Register - WDTCR */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
-   to be fast enough even without feeding it more power.
-*/
-
-/* Special Function I/O Register - SFIOR */
-#define    TSM          7
-#define    ACME         3
-#define    PUD          2
-#define    PSR0         1
-#define    PSR321       0
-
-/* Port Data Register (generic) */
-#define    PORT7        7
-#define    PORT6        6
-#define    PORT5        5
-#define    PORT4        4
-#define    PORT3        3
-#define    PORT2        2
-#define    PORT1        1
-#define    PORT0        0
-
-/* Port Data Direction Register (generic) */
-#define    DD7          7
-#define    DD6          6
-#define    DD5          5
-#define    DD4          4
-#define    DD3          3
-#define    DD2          2
-#define    DD1          1
-#define    DD0          0
-
-/* Port Input Pins (generic) */
-#define    PIN7         7
-#define    PIN6         6
-#define    PIN5         5
-#define    PIN4         4
-#define    PIN3         3
-#define    PIN2         2
-#define    PIN1         1
-#define    PIN0         0
-
-/* SPI Status Register - SPSR */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-
-/* SPI Control Register - SPCR */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* USART Register C (generic) */
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* USART1 Register C - UCSR1C */
-#define    UMSEL1       6
-#define    UPM11        5
-#define    UPM10        4
-#define    USBS1        3
-#define    UCSZ11       2
-#define    UCSZ10       1
-#define    UCPOL1       0
-
-/* USART0 Register C - UCSR0C */
-#define    UMSEL0       6
-#define    UPM01        5
-#define    UPM00        4
-#define    USBS0        3
-#define    UCSZ01       2
-#define    UCSZ00       1
-#define    UCPOL0       0
-
-/* USART Status Register A (generic) */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    UPE          2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART1 Status Register A - UCSR1A */
-#define    RXC1         7
-#define    TXC1         6
-#define    UDRE1        5
-#define    FE1          4
-#define    DOR1         3
-#define    UPE1         2
-#define    U2X1         1
-#define    MPCM1        0
-
-/* USART0 Status Register A - UCSR0A */
-#define    RXC0         7
-#define    TXC0         6
-#define    UDRE0        5
-#define    FE0          4
-#define    DOR0         3
-#define    UPE0         2
-#define    U2X0         1
-#define    MPCM0        0
-
-/* USART Control Register B (generic) */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ         2
-#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
-#define    RXB8         1
-#define    TXB8         0
-
-/* USART1 Control Register B - UCSR1B */
-#define    RXCIE1       7
-#define    TXCIE1       6
-#define    UDRIE1       5
-#define    RXEN1        4
-#define    TXEN1        3
-#define    UCSZ12       2
-#define    RXB81        1
-#define    TXB81        0
-
-/* USART0 Control Register B - UCSR0B */
-#define    RXCIE0       7
-#define    TXCIE0       6
-#define    UDRIE0       5
-#define    RXEN0        4
-#define    TXEN0        3
-#define    UCSZ02       2
-#define    RXB80        1
-#define    TXB80        0
-
-/* Analog Comparator Control and Status Register - ACSR */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Control and Status Register B - ADCSRB */
-#define    ADTS2        2
-#define    ADTS1        1
-#define    ADTS0        0
-
-/* ADC Control and status Register A - ADCSRA */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADATE        5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* ADC Multiplexer select - ADMUX */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* Port A Data Register - PORTA */
-#define    PA7       7
-#define    PA6       6
-#define    PA5       5
-#define    PA4       4
-#define    PA3       3
-#define    PA2       2
-#define    PA1       1
-#define    PA0       0
-
-/* Port A Data Direction Register - DDRA */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Port A Input Pins - PINA */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2 
-#define    PINA1        1
-#define    PINA0        0
-
-/* Port B Data Register - PORTB */
-#define    PB7       7
-#define    PB6       6
-#define    PB5       5
-#define    PB4       4
-#define    PB3       3
-#define    PB2       2
-#define    PB1       1
-#define    PB0       0
-
-/* Port B Data Direction Register - DDRB */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Port B Input Pins - PINB */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2 
-#define    PINB1        1
-#define    PINB0        0
-
-/* Port C Data Register - PORTC */
-#define    PC7       7
-#define    PC6       6
-#define    PC5       5
-#define    PC4       4
-#define    PC3       3
-#define    PC2       2
-#define    PC1       1
-#define    PC0       0
-
-/* Port C Data Direction Register - DDRC */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Port C Input Pins - PINC */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2 
-#define    PINC1        1
-#define    PINC0        0
-
-/* Port D Data Register - PORTD */
-#define    PD7       7
-#define    PD6       6
-#define    PD5       5
-#define    PD4       4
-#define    PD3       3
-#define    PD2       2
-#define    PD1       1
-#define    PD0       0
-
-/* Port D Data Direction Register - DDRD */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Port D Input Pins - PIND */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2 
-#define    PIND1        1
-#define    PIND0        0
-
-/* Port E Data Register - PORTE */
-#define    PE7       7
-#define    PE6       6
-#define    PE5       5
-#define    PE4       4
-#define    PE3       3
-#define    PE2       2
-#define    PE1       1
-#define    PE0       0
-
-/* Port E Data Direction Register - DDRE */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Port E Input Pins - PINE */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2 
-#define    PINE1        1
-#define    PINE0        0
-
-/* Port F Data Register - PORTF */
-#define    PF7       7
-#define    PF6       6
-#define    PF5       5
-#define    PF4       4
-#define    PF3       3
-#define    PF2       2
-#define    PF1       1
-#define    PF0       0
-
-/* Port F Data Direction Register - DDRF */
-#define    DDF7         7
-#define    DDF6         6
-#define    DDF5         5
-#define    DDF4         4
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-#define    DDF0         0
-
-/* Port F Input Pins - PINF */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2 
-#define    PINF1        1
-#define    PINF0        0
-
-/* Port G Data Register - PORTG */
-#define    PG4       4
-#define    PG3       3
-#define    PG2       2
-#define    PG1       1
-#define    PG0       0
-
-/* Port G Data Direction Register - DDRG */
-#define    DDG4         4
-#define    DDG3         3
-#define    DDG2         2
-#define    DDG1         1
-#define    DDG0         0
-
-/* Port G Input Pins - PING */
-#define    PING4        4
-#define    PING3        3
-#define    PING2        2 
-#define    PING1        1
-#define    PING0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND     0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND    0xFFFF
-#define E2END      0x07FF
-#define E2PAGESIZE 8
-#define FLASHEND   0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_WDTON       (unsigned char)~_BV(0)
-#define FUSE_M103C       (unsigned char)~_BV(1)
-#define EFUSE_DEFAULT (FUSE_M103C)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x02
-
-
-#endif /* _AVR_IOM64_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom640.h b/cpukit/score/cpu/avr/avr/iom640.h
deleted file mode 100644
index d542d2eed5..0000000000
--- a/cpukit/score/cpu/avr/avr/iom640.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file avr/iom640.h
- *
- * @brief Definitions for ATmega640
- */
-
-/*
- * Copyright (c) 2005 Anatoly Sokolov
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM640_H_
-#define _AVR_IOM640_H_ 1
-
-/**
- * @defgroup Avr_iom640 ATmega640 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iomxx0_1.h>
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x08
-
-/** @} */
-#endif /* _AVR_IOM640_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644.h b/cpukit/score/cpu/avr/avr/iom644.h
deleted file mode 100644
index dcfab293ef..0000000000
--- a/cpukit/score/cpu/avr/avr/iom644.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega644
- */
-
-/* Copyright (c) 2005 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom644.h - definitions for ATmega644 */
-
-
-#ifndef _AVR_IOM644_H_
-#define _AVR_IOM644_H_ 1
-
-#include <avr/iomxx4.h>
-
-/**
- * @defgroup AvrDef_iom644 ATmega644 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x09
-
-/** @} */
-
-#endif /* _AVR_IOM644_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644p.h b/cpukit/score/cpu/avr/avr/iom644p.h
deleted file mode 100644
index 5c42b09c6d..0000000000
--- a/cpukit/score/cpu/avr/avr/iom644p.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright (c) 2005 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom644p.h - definitions for ATmega644P */
-
-
-#ifndef _AVR_IOM644P_H_
-#define _AVR_IOM644P_H_ 1
-
-#include <avr/iomxx4.h>
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x0A
-/** @} */
-
-#endif /* _AVR_IOM644P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644pa.h b/cpukit/score/cpu/avr/avr/iom644pa.h
deleted file mode 100644
index e794e089a5..0000000000
--- a/cpukit/score/cpu/avr/avr/iom644pa.h
+++ /dev/null
@@ -1,1380 +0,0 @@
-/**
- * @file avr/iom644PA.h
- *
- * @brief Definitions for ATmega644PA
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom644PA.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega644PA_H_
-#define _AVR_ATmega644PA_H_ 1
-
-/**
- *  @defgroup Avr_iom644PA ATmega644PA Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRUSART1 4
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define PCMSK3 _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A_0 0
-#define OCR2A_1 1
-#define OCR2A_2 2
-#define OCR2A_3 3
-#define OCR2A_4 4
-#define OCR2A_5 5
-#define OCR2A_6 6
-#define OCR2A_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B_0 0
-#define OCR2B_1 1
-#define OCR2B_2 2
-#define OCR2B_3 3
-#define OCR2B_4 4
-#define OCR2B_5 5
-#define OCR2B_6 6
-#define OCR2B_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define _UBRR0 0
-#define _UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR_0 0
-#define UBRR_1 1
-#define UBRR_2 2
-#define UBRR_3 3
-#define UBRR_4 4
-#define UBRR_5 5
-#define UBRR_6 6
-#define UBRR_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR_8 0
-#define UBRR_9 1
-#define UBRR_10 2
-#define UBRR_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define PCINT0_vect_num  4
-#define PCINT0_vect      _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  5
-#define PCINT1_vect      _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  6
-#define PCINT2_vect      _VECTOR(6)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  7
-#define PCINT3_vect      _VECTOR(7)  /* Pin Change Interrupt Request 3 */
-#define WDT_vect_num  8
-#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  9
-#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  10
-#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect_num  11
-#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  12
-#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  13
-#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  14
-#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  15
-#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  16
-#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  17
-#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  18
-#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  19
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  20
-#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  21
-#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  22
-#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
-#define ANALOG_COMP_vect_num  23
-#define ANALOG_COMP_vect      _VECTOR(23)  /* Analog Comparator */
-#define ADC_vect_num  24
-#define ADC_vect      _VECTOR(24)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  25
-#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect_num  26
-#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect_num  27
-#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
-#define USART1_RX_vect_num  28
-#define USART1_RX_vect      _VECTOR(28)  /* USART1 RX complete */
-#define USART1_UDRE_vect_num  29
-#define USART1_UDRE_vect      _VECTOR(29)  /* USART1 Data Register Empty */
-#define USART1_TX_vect_num  30
-#define USART1_TX_vect      _VECTOR(30)  /* USART1 TX complete */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (8)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x0A
-
-
-/* Device Pin Definitions */
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   5
-
-#define PCINT13_DDR   DDRB
-#define PCINT13_PORT  PORTB
-#define PCINT13_PIN   PINB
-#define PCINT13_BIT   5
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   6
-
-#define PCINT14_DDR   DDRB
-#define PCINT14_PORT  PORTB
-#define PCINT14_PIN   PINB
-#define PCINT14_BIT   6
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   7
-
-#define PCINT15_DDR   DDRB
-#define PCINT15_PORT  PORTB
-#define PCINT15_PIN   PINB
-#define PCINT15_BIT   7
-
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define PCINT24_DDR   DDRD
-#define PCINT24_PORT  PORTD
-#define PCINT24_PIN   PIND
-#define PCINT24_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define PCINT25_DDR   DDRD
-#define PCINT25_PORT  PORTD
-#define PCINT25_PIN   PIND
-#define PCINT25_BIT   1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define RDX1_DDR   DDRD
-#define RDX1_PORT  PORTD
-#define RDX1_PIN   PIND
-#define RDX1_BIT   2
-
-#define PCINT26_DDR   DDRD
-#define PCINT26_PORT  PORTD
-#define PCINT26_PIN   PIND
-#define PCINT26_BIT   2
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define TXD1_DDR   DDRD
-#define TXD1_PORT  PORTD
-#define TXD1_PIN   PIND
-#define TXD1_BIT   3
-
-#define PCINT27_DDR   DDRD
-#define PCINT27_PORT  PORTD
-#define PCINT27_PIN   PIND
-#define PCINT27_BIT   3
-
-#define OC1B_DDR   DDRD
-#define OC1B_PORT  PORTD
-#define OC1B_PIN   PIND
-#define OC1B_BIT   4
-
-#define XCK1_DDR   DDRD
-#define XCK1_PORT  PORTD
-#define XCK1_PIN   PIND
-#define XCK1_BIT   4
-
-#define PCINT28_DDR   DDRD
-#define PCINT28_PORT  PORTD
-#define PCINT28_PIN   PIND
-#define PCINT28_BIT   4
-
-#define OC1A_DDR   DDRD
-#define OC1A_PORT  PORTD
-#define OC1A_PIN   PIND
-#define OC1A_BIT   5
-
-#define PCINT29_DDR   DDRD
-#define PCINT29_PORT  PORTD
-#define PCINT29_PIN   PIND
-#define PCINT29_BIT   5
-
-#define ICP_DDR   DDRD
-#define ICP_PORT  PORTD
-#define ICP_PIN   PIND
-#define ICP_BIT   6
-
-#define OC2B_DDR   DDRD
-#define OC2B_PORT  PORTD
-#define OC2B_PIN   PIND
-#define OC2B_BIT   6
-
-#define PCINT30_DDR   DDRD
-#define PCINT30_PORT  PORTD
-#define PCINT30_PIN   PIND
-#define PCINT30_BIT   6
-
-#define OC2A_DDR   DDRD
-#define OC2A_PORT  PORTD
-#define OC2A_PIN   PIND
-#define OC2A_BIT   7
-
-#define PCINT31_DDR   DDRD
-#define PCINT31_PORT  PORTD
-#define PCINT31_PIN   PIND
-#define PCINT31_BIT   7
-
-#define SCL_DDR   DDRC
-#define SCL_PORT  PORTC
-#define SCL_PIN   PINC
-#define SCL_BIT   0
-
-#define PCINT16_DDR   DDRC
-#define PCINT16_PORT  PORTC
-#define PCINT16_PIN   PINC
-#define PCINT16_BIT   0
-
-#define SDA_DDR   DDRC
-#define SDA_PORT  PORTC
-#define SDA_PIN   PINC
-#define SDA_BIT   1
-
-#define PCINT17_DDR   DDRC
-#define PCINT17_PORT  PORTC
-#define PCINT17_PIN   PINC
-#define PCINT17_BIT   1
-
-#define PCINT18_DDR   DDRC
-#define PCINT18_PORT  PORTC
-#define PCINT18_PIN   PINC
-#define PCINT18_BIT   2
-
-#define PCINT19_DDR   DDRC
-#define PCINT19_PORT  PORTC
-#define PCINT19_PIN   PINC
-#define PCINT19_BIT   3
-
-#define PCINT20_DDR   DDRC
-#define PCINT20_PORT  PORTC
-#define PCINT20_PIN   PINC
-#define PCINT20_BIT   4
-
-#define PCINT21_DDR   DDRC
-#define PCINT21_PORT  PORTC
-#define PCINT21_PIN   PINC
-#define PCINT21_BIT   5
-
-#define PCINT22_DDR   DDRC
-#define PCINT22_PORT  PORTC
-#define PCINT22_PIN   PINC
-#define PCINT22_BIT   6
-
-#define PCINT23_DDR   DDRC
-#define PCINT23_PORT  PORTC
-#define PCINT23_PIN   PINC
-#define PCINT23_BIT   7
-
-#define ADC7_DDR   DDRA
-#define ADC7_PORT  PORTA
-#define ADC7_PIN   PINA
-#define ADC7_BIT   7
-
-#define PCINT7_DDR   DDRA
-#define PCINT7_PORT  PORTA
-#define PCINT7_PIN   PINA
-#define PCINT7_BIT   7
-
-#define ADC6_DDR   DDRA
-#define ADC6_PORT  PORTA
-#define ADC6_PIN   PINA
-#define ADC6_BIT   6
-
-#define PCINT6_DDR   DDRA
-#define PCINT6_PORT  PORTA
-#define PCINT6_PIN   PINA
-#define PCINT6_BIT   6
-
-#define ADC5_DDR   DDRA
-#define ADC5_PORT  PORTA
-#define ADC5_PIN   PINA
-#define ADC5_BIT   5
-
-#define PCINT5_DDR   DDRA
-#define PCINT5_PORT  PORTA
-#define PCINT5_PIN   PINA
-#define PCINT5_BIT   5
-
-#define ADC4_DDR   DDRA
-#define ADC4_PORT  PORTA
-#define ADC4_PIN   PINA
-#define ADC4_BIT   4
-
-#define PCINT4_DDR   DDRA
-#define PCINT4_PORT  PORTA
-#define PCINT4_PIN   PINA
-#define PCINT4_BIT   4
-
-#define ADC3_DDR   DDRA
-#define ADC3_PORT  PORTA
-#define ADC3_PIN   PINA
-#define ADC3_BIT   3
-
-#define PCINT3_DDR   DDRA
-#define PCINT3_PORT  PORTA
-#define PCINT3_PIN   PINA
-#define PCINT3_BIT   3
-
-#define ADC2_DDR   DDRA
-#define ADC2_PORT  PORTA
-#define ADC2_PIN   PINA
-#define ADC2_BIT   2
-
-#define PCINT2_DDR   DDRA
-#define PCINT2_PORT  PORTA
-#define PCINT2_PIN   PINA
-#define PCINT2_BIT   2
-
-#define ADC1_DDR   DDRA
-#define ADC1_PORT  PORTA
-#define ADC1_PIN   PINA
-#define ADC1_BIT   1
-
-#define PCINT1_DDR   DDRA
-#define PCINT1_PORT  PORTA
-#define PCINT1_PIN   PINA
-#define PCINT1_BIT   1
-
-#define ADC0_DDR   DDRA
-#define ADC0_PORT  PORTA
-#define ADC0_PIN   PINA
-#define ADC0_BIT   0
-
-#define PCINT0_DDR   DDRA
-#define PCINT0_PORT  PORTA
-#define PCINT0_PIN   PINA
-#define PCINT0_BIT   0
-
-#define XCK_DDR   DDRB
-#define XCK_PORT  PORTB
-#define XCK_PIN   PINB
-#define XCK_BIT   0
-
-#define T0_DDR   DDRB
-#define T0_PORT  PORTB
-#define T0_PIN   PINB
-#define T0_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define T1_DDR   DDRB
-#define T1_PORT  PORTB
-#define T1_PIN   PINB
-#define T1_BIT   1
-
-#define CLKO_DDR   DDRB
-#define CLKO_PORT  PORTB
-#define CLKO_PIN   PINB
-#define CLKO_BIT   1
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define AIN0_DDR   DDRB
-#define AIN0_PORT  PORTB
-#define AIN0_PIN   PINB
-#define AIN0_BIT   2
-
-#define INT2_DDR   DDRB
-#define INT2_PORT  PORTB
-#define INT2_PIN   PINB
-#define INT2_BIT   2
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define AIN1_DDR   DDRB
-#define AIN1_PORT  PORTB
-#define AIN1_PIN   PINB
-#define AIN1_BIT   3
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   3
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   4
-
-#define OC0B_DDR   DDRB
-#define OC0B_PORT  PORTB
-#define OC0B_PIN   PINB
-#define OC0B_BIT   4
-
-#define PCINT12_DDR   DDRB
-#define PCINT12_PORT  PORTB
-#define PCINT12_PIN   PINB
-#define PCINT12_BIT   4
-
-/**@}*/
-#endif /* _AVR_ATmega644PA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom645.h b/cpukit/score/cpu/avr/avr/iom645.h
deleted file mode 100644
index 991ff821fd..0000000000
--- a/cpukit/score/cpu/avr/avr/iom645.h
+++ /dev/null
@@ -1,827 +0,0 @@
-/**
- * @file avr/iom645.h
- *
- * @brief Definitions for ATmega645
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2004,2005,2006 Eric B. Weddington
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM645_H_
-#define _AVR_IOM645_H_ 1
-
-/**
- *  @defgroup Avr_iom645 ATmega645 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom645.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* Vector 22 is Reserved */
-
-#define _VECTORS_SIZE 92
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x05
-
-/**@}*/
-#endif /* _AVR_IOM645_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom6450.h b/cpukit/score/cpu/avr/avr/iom6450.h
deleted file mode 100644
index fa2203e527..0000000000
--- a/cpukit/score/cpu/avr/avr/iom6450.h
+++ /dev/null
@@ -1,923 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega6450
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom6450.h - definitions for ATmega6450 */
-
-#ifndef _AVR_IOM6450_H_
-#define _AVR_IOM6450_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom6450.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom6450 ATmega6450 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-#define PCIF2   6
-#define PCIF3   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-#define PCIE2   6
-#define PCIE3   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3  _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xD7] */
-
-#define PINH    _SFR_MEM8(0xD8)
-#define PINH7   7
-#define PINH6   6
-#define PINH5   5
-#define PINH4   4
-#define PINH3   3
-#define PINH2   2
-#define PINH1   1
-#define PINH0   0
-
-#define DDRH    _SFR_MEM8(0xD9)
-#define DDH7    7
-#define DDH6    6
-#define DDH5    5
-#define DDH4    4
-#define DDH3    3
-#define DDH2    2
-#define DDH1    1
-#define DDH0    0
-
-#define PORTH   _SFR_MEM8(0xDA)
-#define PH7     7
-#define PH6     6
-#define PH5     5
-#define PH4     4
-#define PH3     3
-#define PH2     2
-#define PH1     1
-#define PH0     0
-
-#define PINJ    _SFR_MEM8(0xDB)
-#define PINJ6   6
-#define PINJ5   5
-#define PINJ4   4
-#define PINJ3   3
-#define PINJ2   2
-#define PINJ1   1
-#define PINJ0   0
-
-#define DDRJ    _SFR_MEM8(0xDC)
-#define DDJ6    6
-#define DDJ5    5
-#define DDJ4    4
-#define DDJ3    3
-#define DDJ2    2
-#define DDJ1    1
-#define DDJ0    0
-
-#define PORTJ   _SFR_MEM8(0xDD)
-#define PJ6     6
-#define PJ5     5
-#define PJ4     4
-#define PJ3     3
-#define PJ2     2
-#define PJ1     1
-#define PJ0     0
-
-/* Reserved [0xDE..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(13)
-#define USART0_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define USART0_UDRE_vect		_VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(23)
-#define SIG_PIN_CHANGE2			_VECTOR(23)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect			_VECTOR(24)
-#define SIG_PIN_CHANGE3			_VECTOR(24)
-
-#define _VECTORS_SIZE 100
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x06
-
-/** @} */
-
-#endif /* _AVR_IOM6450_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom649.h b/cpukit/score/cpu/avr/avr/iom649.h
deleted file mode 100644
index 2064573933..0000000000
--- a/cpukit/score/cpu/avr/avr/iom649.h
+++ /dev/null
@@ -1,1005 +0,0 @@
-/**
- * @file avr/iom649.h
- *
- * @brief Definitions for ATmega649
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004 Eric B. Weddington
- *  Copyright (c) 2005,2006 Anatoly Sokolov
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM649_H_
-#define _AVR_IOM649_H_ 1
-
-/**
- *  @defgroup Avr_iom649 ATmega649 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom649.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xE3] */
-
-#define LCDCRA  _SFR_MEM8(0XE4)
-#define LCDBL   0
-#define LCDIE   3
-#define LCDIF   4
-#define LCDAB   6
-#define LCDEN   7
-
-#define LCDCRB  _SFR_MEM8(0XE5)
-#define LCDPM0  0
-#define LCDPM1  1
-#define LCDPM2  2
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B   6
-#define LCDCS   7
-
-#define LCDFRR  _SFR_MEM8(0XE6)
-#define LCDCD0  0
-#define LCDCD1  1
-#define LCDCD2  2
-#define LCDPS0  4
-#define LCDPS1  5
-#define LCDPS2  6
-
-#define LCDCCR  _SFR_MEM8(0XE7)
-#define LCDCC0  0
-#define LCDCC1  1
-#define LCDCC2  2
-#define LCDCC3  3
-#define LCDDC0  5
-#define LCDDC1  6
-#define LCDDC2  7
-
-/* Reserved [0xE8..0xEB] */
-
-#define LCDDR00 _SFR_MEM8(0XEC)
-#define SEG000  0
-#define SEG001  1
-#define SEG002  2
-#define SEG003  3
-#define SEG004  4
-#define SEG005  5
-#define SEG006  6
-#define SEG007  7
-
-#define LCDDR01 _SFR_MEM8(0XED)
-#define SEG008  0
-#define SEG009  1
-#define SEG010  2
-#define SEG011  3
-#define SEG012  4
-#define SEG013  5
-#define SEG014  6
-#define SEG015  7
-
-#define LCDDR02 _SFR_MEM8(0XEE)
-#define SEG016  0
-#define SEG017  1
-#define SEG018  2
-#define SEG019  3
-#define SEG020  4
-#define SEG021  5
-#define SEG022  6
-#define SEG023  7
-
-#define LCDDR03 _SFR_MEM8(0XEF)
-#define SEG024  0
-
-/* Reserved [0xF0] */
-
-#define LCDDR05 _SFR_MEM8(0XF1)
-#define SEG100  0
-#define SEG101  1
-#define SEG102  2
-#define SEG103  3
-#define SEG104  4
-#define SEG105  5
-#define SEG106  6
-#define SEG107  7
-
-#define LCDDR06 _SFR_MEM8(0XF2)
-#define SEG108  0
-#define SEG109  1
-#define SEG110  2
-#define SEG111  3
-#define SEG112  4
-#define SEG113  5
-#define SEG114  6
-#define SEG115  7
-
-#define LCDDR07 _SFR_MEM8(0XF3)
-#define SEG116  0
-#define SEG117  1
-#define SEG118  2
-#define SEG119  3
-#define SEG120  4
-#define SEG121  5
-#define SEG122  6
-#define SEG123  7
-
-#define LCDDR08 _SFR_MEM8(0XF4)
-#define SEG124  0
-
-/* Reserved [0xF5] */
-
-#define LCDDR10 _SFR_MEM8(0XF6)
-#define SEG200  0
-#define SEG201  1
-#define SEG202  2
-#define SEG203  3
-#define SEG204  4
-#define SEG205  5
-#define SEG206  6
-#define SEG207  7
-
-#define LCDDR11 _SFR_MEM8(0XF7)
-#define SEG208  0
-#define SEG209  1
-#define SEG210  2
-#define SEG211  3
-#define SEG212  4
-#define SEG213  5
-#define SEG214  6
-#define SEG215  7
-
-#define LCDDR12 _SFR_MEM8(0XF8)
-#define SEG216  0
-#define SEG217  1
-#define SEG218  2
-#define SEG219  3
-#define SEG220  4
-#define SEG221  5
-#define SEG222  6
-#define SEG223  7
-
-#define LCDDR13 _SFR_MEM8(0XF9)
-#define SEG224  0
-
-/* Reserved [0xFA] */
-
-#define LCDDR15 _SFR_MEM8(0XFB)
-#define SEG300  0
-#define SEG301  1
-#define SEG302  2
-#define SEG303  3
-#define SEG304  4
-#define SEG305  5
-#define SEG306  6
-#define SEG307  7
-
-#define LCDDR16 _SFR_MEM8(0XFC)
-#define SEG308  0
-#define SEG309  1
-#define SEG310  2
-#define SEG311  3
-#define SEG312  4
-#define SEG313  5
-#define SEG314  6
-#define SEG315  7
-
-#define LCDDR17 _SFR_MEM8(0XFD)
-#define SEG316  0
-#define SEG217  1
-#define SEG318  2
-#define SEG319  3
-#define SEG320  4
-#define SEG321  5
-#define SEG322  6
-#define SEG323  7
-
-#define LCDDR18 _SFR_MEM8(0XFE)
-#define SEG324  0
-
-/* Reserved [0xFF] */
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-#define _VECTORS_SIZE 92
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IOM649_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom6490.h b/cpukit/score/cpu/avr/avr/iom6490.h
deleted file mode 100644
index 10334d7677..0000000000
--- a/cpukit/score/cpu/avr/avr/iom6490.h
+++ /dev/null
@@ -1,1158 +0,0 @@
-/**
- * @file avr/iom6490.h
- *
- * @brief Definitions for ATmega6490
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004 Eric B. Weddington
- *  Copyright (c) 2005,2006 Anatoly Sokolov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM6490_H_
-#define _AVR_IOM6490_H_ 1
-
-/**
- *  @defgroup Avr_iom6490 ATmega6490 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom6490.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   4
-#define PCIF1   5
-#define PCIF2   6
-#define PCIF3   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   4
-#define PCIE1   5
-#define PCIE2   6
-#define PCIE3   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-#define PRLCD       4
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2  _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3  _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xD7] */
-
-#define PINH    _SFR_MEM8(0xD8)
-#define PINH7   7
-#define PINH6   6
-#define PINH5   5
-#define PINH4   4
-#define PINH3   3
-#define PINH2   2
-#define PINH1   1
-#define PINH0   0
-
-#define DDRH    _SFR_MEM8(0xD9)
-#define DDH7    7
-#define DDH6    6
-#define DDH5    5
-#define DDH4    4
-#define DDH3    3
-#define DDH2    2
-#define DDH1    1
-#define DDH0    0
-
-#define PORTH   _SFR_MEM8(0xDA)
-#define PH7     7
-#define PH6     6
-#define PH5     5
-#define PH4     4
-#define PH3     3
-#define PH2     2
-#define PH1     1
-#define PH0     0
-
-#define PINJ    _SFR_MEM8(0xDB)
-#define PINJ6   6
-#define PINJ5   5
-#define PINJ4   4
-#define PINJ3   3
-#define PINJ2   2
-#define PINJ1   1
-#define PINJ0   0
-
-#define DDRJ    _SFR_MEM8(0xDC)
-#define DDJ6    6
-#define DDJ5    5
-#define DDJ4    4
-#define DDJ3    3
-#define DDJ2    2
-#define DDJ1    1
-#define DDJ0    0
-
-#define PORTJ   _SFR_MEM8(0xDD)
-#define PJ6     6
-#define PJ5     5
-#define PJ4     4
-#define PJ3     3
-#define PJ2     2
-#define PJ1     1
-#define PJ0     0
-
-/* Reserved [0xDE..0xE3] */
-
-#define LCDCRA  _SFR_MEM8(0XE4)
-#define LCDBL   0
-#define LCDIE   3
-#define LCDIF   4
-#define LCDAB   6
-#define LCDEN   7
-
-#define LCDCRB  _SFR_MEM8(0XE5)
-#define LCDPM0  0
-#define LCDPM1  1
-#define LCDPM2  2
-#define LCDPM3  3
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B   6
-#define LCDCS   7
-
-#define LCDFRR  _SFR_MEM8(0XE6)
-#define LCDCD0  0
-#define LCDCD1  1
-#define LCDCD2  2
-#define LCDPS0  4
-#define LCDPS1  5
-#define LCDPS2  6
-
-#define LCDCCR  _SFR_MEM8(0XE7)
-#define LCDCC0  0
-#define LCDCC1  1
-#define LCDCC2  2
-#define LCDCC3  3
-#define LCDDC0  5
-#define LCDDC1  6
-#define LCDDC2  7
-
-/* Reserved [0xE8..0xEB] */
-
-#define LCDDR00 _SFR_MEM8(0XEC)
-#define SEG000  0
-#define SEG001  1
-#define SEG002  2
-#define SEG003  3
-#define SEG004  4
-#define SEG005  5
-#define SEG006  6
-#define SEG007  7
-
-#define LCDDR01 _SFR_MEM8(0XED)
-#define SEG008  0
-#define SEG009  1
-#define SEG010  2
-#define SEG011  3
-#define SEG012  4
-#define SEG013  5
-#define SEG014  6
-#define SEG015  7
-
-#define LCDDR02 _SFR_MEM8(0XEE)
-#define SEG016  0
-#define SEG017  1
-#define SEG018  2
-#define SEG019  3
-#define SEG020  4
-#define SEG021  5
-#define SEG022  6
-#define SEG023  7
-
-#define LCDDR03 _SFR_MEM8(0XEF)
-#define SEG024  0
-#define SEG025  1
-#define SEG026  2
-#define SEG027  3
-#define SEG028  4
-#define SEG029  5
-#define SEG030  6
-#define SEG031  7
-
-#define LCDDR04 _SFR_MEM8(0XF0)
-#define SEG032  0
-#define SEG033  1
-#define SEG034  2
-#define SEG035  3
-#define SEG036  4
-#define SEG037  5
-#define SEG038  6
-#define SEG039  7
-
-#define LCDDR05 _SFR_MEM8(0XF1)
-#define SEG100  0
-#define SEG101  1
-#define SEG102  2
-#define SEG103  3
-#define SEG104  4
-#define SEG105  5
-#define SEG106  6
-#define SEG107  7
-
-#define LCDDR06 _SFR_MEM8(0XF2)
-#define SEG108  0
-#define SEG109  1
-#define SEG110  2
-#define SEG111  3
-#define SEG112  4
-#define SEG113  5
-#define SEG114  6
-#define SEG115  7
-
-#define LCDDR07 _SFR_MEM8(0XF3)
-#define SEG116  0
-#define SEG117  1
-#define SEG118  2
-#define SEG119  3
-#define SEG120  4
-#define SEG121  5
-#define SEG122  6
-#define SEG123  7
-
-#define LCDDR08 _SFR_MEM8(0XF4)
-#define SEG124  0
-#define SEG125  1
-#define SEG126  2
-#define SEG127  3
-#define SEG128  4
-#define SEG129  5
-#define SEG130  6
-#define SEG131  7
-
-#define LCDDR09 _SFR_MEM8(0XF5)
-#define SEG132  0
-#define SEG133  1
-#define SEG134  2
-#define SEG135  3
-#define SEG136  4
-#define SEG137  5
-#define SEG138  6
-#define SEG139  7
-
-#define LCDDR10 _SFR_MEM8(0XF6)
-#define SEG200  0
-#define SEG201  1
-#define SEG202  2
-#define SEG203  3
-#define SEG204  4
-#define SEG205  5
-#define SEG206  6
-#define SEG207  7
-
-#define LCDDR11 _SFR_MEM8(0XF7)
-#define SEG208  0
-#define SEG209  1
-#define SEG210  2
-#define SEG211  3
-#define SEG212  4
-#define SEG213  5
-#define SEG214  6
-#define SEG215  7
-
-#define LCDDR12 _SFR_MEM8(0XF8)
-#define SEG216  0
-#define SEG217  1
-#define SEG218  2
-#define SEG219  3
-#define SEG220  4
-#define SEG221  5
-#define SEG222  6
-#define SEG223  7
-
-#define LCDDR13 _SFR_MEM8(0XF9)
-#define SEG224  0
-#define SEG225  1
-#define SEG226  2
-#define SEG227  3
-#define SEG228  4
-#define SEG229  5
-#define SEG230  6
-#define SEG231  7
-
-#define LCDDR14 _SFR_MEM8(0XFA)
-#define SEG232  0
-#define SEG233  1
-#define SEG234  2
-#define SEG235  3
-#define SEG236  4
-#define SEG237  5
-#define SEG238  6
-#define SEG239  7
-
-#define LCDDR15 _SFR_MEM8(0XFB)
-#define SEG300  0
-#define SEG301  1
-#define SEG302  2
-#define SEG303  3
-#define SEG304  4
-#define SEG305  5
-#define SEG306  6
-#define SEG307  7
-
-#define LCDDR16 _SFR_MEM8(0XFC)
-#define SEG308  0
-#define SEG309  1
-#define SEG310  2
-#define SEG311  3
-#define SEG312  4
-#define SEG313  5
-#define SEG314  6
-#define SEG315  7
-
-#define LCDDR17 _SFR_MEM8(0XFD)
-#define SEG316  0
-#define SEG217  1
-#define SEG318  2
-#define SEG319  3
-#define SEG320  4
-#define SEG321  5
-#define SEG322  6
-#define SEG323  7
-
-#define LCDDR18 _SFR_MEM8(0XFE)
-#define SEG324  0
-#define SEG325  1
-#define SEG326  2
-#define SEG327  3
-#define SEG328  4
-#define SEG329  5
-#define SEG330  6
-#define SEG331  7
-
-#define LCDDR19 _SFR_MEM8(0XFF)
-#define SEG332  0
-#define SEG333  1
-#define SEG334  2
-#define SEG335  3
-#define SEG336  4
-#define SEG337  5
-#define SEG338  6
-#define SEG339  7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(13)
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART Data register Empty */
-#define USART_UDRE_vect			_VECTOR(14)
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-/* LCD Start of Frame */
-#define LCD_vect			_VECTOR(22)
-#define SIG_LCD				_VECTOR(22)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(23)
-#define SIG_PIN_CHANGE2			_VECTOR(23)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect			_VECTOR(24)
-#define SIG_PIN_CHANGE3			_VECTOR(24)
-
-#define _VECTORS_SIZE 100
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      RAMEND
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x04
-
-
-/**@}*/
-#endif /* _AVR_IOM6490_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom649p.h b/cpukit/score/cpu/avr/avr/iom649p.h
deleted file mode 100644
index e544ab930e..0000000000
--- a/cpukit/score/cpu/avr/avr/iom649p.h
+++ /dev/null
@@ -1,1476 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom649p.h - definitions for ATmega649 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom649p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega649_H_
-#define _AVR_ATmega649_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-#define PINE3 3
-#define PINE4 4
-#define PINE5 5
-#define PINE6 6
-#define PINE7 7
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-#define DDE3 3
-#define DDE4 4
-#define DDE5 5
-#define DDE6 6
-#define DDE7 7
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-#define PORTE3 3
-#define PORTE4 4
-#define PORTE5 5
-#define PORTE6 6
-#define PORTE7 7
-
-#define PINF _SFR_IO8(0x0F)
-#define PINF0 0
-#define PINF1 1
-#define PINF2 2
-#define PINF3 3
-#define PINF4 4
-#define PINF5 5
-#define PINF6 6
-#define PINF7 7
-
-#define DDRF _SFR_IO8(0x10)
-#define DDF0 0
-#define DDF1 1
-#define DDF2 2
-#define DDF3 3
-#define DDF4 4
-#define DDF5 5
-#define DDF6 6
-#define DDF7 7
-
-#define PORTF _SFR_IO8(0x11)
-#define PORTF0 0
-#define PORTF1 1
-#define PORTF2 2
-#define PORTF3 3
-#define PORTF4 4
-#define PORTF5 5
-#define PORTF6 6
-#define PORTF7 7
-
-#define PING _SFR_IO8(0x12)
-#define PING0 0
-#define PING1 1
-#define PING2 2
-#define PING3 3
-#define PING4 4
-#define PING5 5
-
-#define DDRG _SFR_IO8(0x13)
-#define DDG0 0
-#define DDG1 1
-#define DDG2 2
-#define DDG3 3
-#define DDG4 4
-
-#define PORTG _SFR_IO8(0x14)
-#define PORTG0 0
-#define PORTG1 1
-#define PORTG2 2
-#define PORTG3 3
-#define PORTG4 4
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define PCIF0 4
-#define PCIF1 5
-#define PCIF2 6
-#define PCIF3 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define PCIE0 4
-#define PCIE1 5
-#define PCIE2 6
-#define PCIE3 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR310 0
-#define PSR2 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM01 3
-#define COM0A0 4
-#define COM0A1 5
-#define WGM00 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRLCD 4
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM21 3
-#define COM2A0 4
-#define COM2A1 5
-#define WGM20 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A0 0
-#define OCR2A1 1
-#define OCR2A2 2
-#define OCR2A3 3
-#define OCR2A4 4
-#define OCR2A5 5
-#define OCR2A6 6
-#define OCR2A7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2UB 0
-#define OCR2UB 1
-#define TCN2UB 2
-#define AS2 3
-#define EXCLK 4
-
-#define USICR _SFR_MEM8(0xB8)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_MEM8(0xBA)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL0 6
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR00 0
-#define UDR01 1
-#define UDR02 2
-#define UDR03 3
-#define UDR04 4
-#define UDR05 5
-#define UDR06 6
-#define UDR07 7
-
-#define LCDCRA _SFR_MEM8(0xE4)
-#define LCDBL 0
-#define LCDIE 3
-#define LCDIF 4
-#define LCDAB 6
-#define LCDEN 7
-
-#define LCDCRB _SFR_MEM8(0xE5)
-#define LCDPM0 0
-#define LCDPM1 1
-#define LCDPM2 2
-#define LCDPM3 3
-#define LCDMUX0 4
-#define LCDMUX1 5
-#define LCD2B 6
-#define LCDCS 7
-
-#define LCDFRR _SFR_MEM8(0xE6)
-#define LCDCD0 0
-#define LCDCD1 1
-#define LCDCD2 2
-#define LCDPS0 4
-#define LCDPS1 5
-#define LCDPS2 6
-
-#define LCDCCR _SFR_MEM8(0xE7)
-#define LCDCC0 0
-#define LCDCC1 1
-#define LCDCC2 2
-#define LCDCC3 3
-#define LCDDC0 5
-#define LCDDC1 6
-#define LCDDC2 7
-
-#define LCDDR0 _SFR_MEM8(0xEC)
-#define SEG000 0
-#define SEG001 1
-#define SEG002 2
-#define SEG003 3
-#define SEG004 4
-#define SEG005 5
-#define SEG006 6
-#define SEG007 7
-
-#define LCDDR1 _SFR_MEM8(0xED)
-#define SEG008 0
-#define SEG009 1
-#define SEG010 2
-#define SEG011 3
-#define SEG012 4
-#define SEG013 5
-#define SEG014 6
-#define SEG015 7
-
-#define LCDDR2 _SFR_MEM8(0xEE)
-#define SEG016 0
-#define SEG017 1
-#define SEG018 2
-#define SEG019 3
-#define SEG020 4
-#define SEG021 5
-#define SEG022 6
-#define SEG023 7
-
-#define LCDDR3 _SFR_MEM8(0xEF)
-#define SEG024 0
-
-#define LCDDR4 _SFR_MEM8(0xF0)
-
-#define LCDDR5 _SFR_MEM8(0xF1)
-#define SEG100 0
-#define SEG101 1
-#define SEG102 2
-#define SEG103 3
-#define SEG104 4
-#define SEG105 5
-#define SEG106 6
-#define SEG107 7
-
-#define LCDDR6 _SFR_MEM8(0xF2)
-#define SEG108 0
-#define SEG109 1
-#define SEG110 2
-#define SEG111 3
-#define SEG112 4
-#define SEG113 5
-#define SEG114 6
-#define SEG115 7
-
-#define LCDDR7 _SFR_MEM8(0xF3)
-#define SEG116 0
-#define SEG117 1
-#define SEG118 2
-#define SEG119 3
-#define SEG120 4
-#define SEG121 5
-#define SEG122 6
-#define SEG123 7
-
-#define LCDDR8 _SFR_MEM8(0xF4)
-#define SEG124 0
-
-#define LCDDR9 _SFR_MEM8(0xF5)
-
-#define LCDDR10 _SFR_MEM8(0xF6)
-#define SEG200 0
-#define SEG201 1
-#define SEG202 2
-#define SEG203 3
-#define SEG204 4
-#define SEG205 5
-#define SEG206 6
-#define SEG207 7
-
-#define LCDDR11 _SFR_MEM8(0xF7)
-#define SEG208 0
-#define SEG209 1
-#define SEG210 2
-#define SEG211 3
-#define SEG212 4
-#define SEG213 5
-#define SEG214 6
-#define SEG215 7
-
-#define LCDDR12 _SFR_MEM8(0xF8)
-#define SEG216 0
-#define SEG217 1
-#define SEG218 2
-#define SEG219 3
-#define SEG220 4
-#define SEG221 5
-#define SEG222 6
-#define SEG223 7
-
-#define LCDDR13 _SFR_MEM8(0xF9)
-#define SEG224 0
-
-#define LCDDR14 _SFR_MEM8(0xFA)
-
-#define LCDDR15 _SFR_MEM8(0xFB)
-#define SEG300 0
-#define SEG301 1
-#define SEG302 2
-#define SEG303 3
-#define SEG304 4
-#define SEG305 5
-#define SEG306 6
-#define SEG307 7
-
-#define LCDDR16 _SFR_MEM8(0xFC)
-#define SEG308 0
-#define SEG309 1
-#define SEG310 2
-#define SEG311 3
-#define SEG312 4
-#define SEG313 5
-#define SEG314 6
-#define SEG315 7
-
-#define LCDDR17 _SFR_MEM8(0xFD)
-#define SEG316 0
-#define SEG317 1
-#define SEG318 2
-#define SEG319 3
-#define SEG320 4
-#define SEG321 5
-#define SEG322 6
-#define SEG323 7
-
-#define LCDDR18 _SFR_MEM8(0xFE)
-#define SEG324 0
-
-#define LCDDR19 _SFR_MEM8(0xFF)
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  3
-#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
-#define TIMER2_COMP_vect_num  4
-#define TIMER2_COMP_vect      _VECTOR(4)  /* Timer/Counter2 Compare Match */
-#define TIMER2_OVF_vect_num  5
-#define TIMER2_OVF_vect      _VECTOR(5)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  6
-#define TIMER1_CAPT_vect      _VECTOR(6)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  7
-#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  8
-#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer/Counter Compare Match B */
-#define TIMER1_OVF_vect_num  9
-#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMP_vect_num  10
-#define TIMER0_COMP_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match */
-#define TIMER0_OVF_vect_num  11
-#define TIMER0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  12
-#define SPI_STC_vect      _VECTOR(12)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  13
-#define USART0_RX_vect      _VECTOR(13)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  14
-#define USART0_UDRE_vect      _VECTOR(14)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  15
-#define USART0_TX_vect      _VECTOR(15)  /* USART0, Tx Complete */
-#define USI_START_vect_num  16
-#define USI_START_vect      _VECTOR(16)  /* USI Start Condition */
-#define USI_OVERFLOW_vect_num  17
-#define USI_OVERFLOW_vect      _VECTOR(17)  /* USI Overflow */
-#define ANALOG_COMP_vect_num  18
-#define ANALOG_COMP_vect      _VECTOR(18)  /* Analog Comparator */
-#define ADC_vect_num  19
-#define ADC_vect      _VECTOR(19)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  20
-#define EE_READY_vect      _VECTOR(20)  /* EEPROM Ready */
-#define SPM_READY_vect_num  21
-#define SPM_READY_vect      _VECTOR(21)  /* Store Program Memory Read */
-#define LCD_vect_num  22
-#define LCD_vect      _VECTOR(22)  /* LCD Start of Frame */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (23 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (8)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_RESERVED  (unsigned char)~_BV(0)  /* Reserved fuse bit, do not program */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x0B
-
-
-/* Device Pin Definitions */
-#define RXD_DDR   DDRE
-#define RXD_PORT  PORTE
-#define RXD_PIN   PINE
-#define RXD_BIT   0
-
-#define PCINT0_DDR   DDRE
-#define PCINT0_PORT  PORTE
-#define PCINT0_PIN   PINE
-#define PCINT0_BIT   0
-
-#define TXD_DDR   DDRE
-#define TXD_PORT  PORTE
-#define TXD_PIN   PINE
-#define TXD_BIT   1
-
-#define PCINT1_DDR   DDRE
-#define PCINT1_PORT  PORTE
-#define PCINT1_PIN   PINE
-#define PCINT1_BIT   1
-
-#define XCK_DDR   DDRE
-#define XCK_PORT  PORTE
-#define XCK_PIN   PINE
-#define XCK_BIT   2
-
-#define AIN0_DDR   DDRE
-#define AIN0_PORT  PORTE
-#define AIN0_PIN   PINE
-#define AIN0_BIT   2
-
-#define PCINT2_DDR   DDRE
-#define PCINT2_PORT  PORTE
-#define PCINT2_PIN   PINE
-#define PCINT2_BIT   2
-
-#define AIN1_DDR   DDRE
-#define AIN1_PORT  PORTE
-#define AIN1_PIN   PINE
-#define AIN1_BIT   3
-
-#define PCINT3_DDR   DDRE
-#define PCINT3_PORT  PORTE
-#define PCINT3_PIN   PINE
-#define PCINT3_BIT   3
-
-#define USCK_DDR   DDRE
-#define USCK_PORT  PORTE
-#define USCK_PIN   PINE
-#define USCK_BIT   4
-
-#define SCL_DDR   DDRE
-#define SCL_PORT  PORTE
-#define SCL_PIN   PINE
-#define SCL_BIT   4
-
-#define PCINT4_DDR   DDRE
-#define PCINT4_PORT  PORTE
-#define PCINT4_PIN   PINE
-#define PCINT4_BIT   4
-
-#define DI_DDR   DDRE
-#define DI_PORT  PORTE
-#define DI_PIN   PINE
-#define DI_BIT   5
-
-#define SDA_DDR   DDRE
-#define SDA_PORT  PORTE
-#define SDA_PIN   PINE
-#define SDA_BIT   5
-
-#define PCINT5_DDR   DDRE
-#define PCINT5_PORT  PORTE
-#define PCINT5_PIN   PINE
-#define PCINT5_BIT   5
-
-#define DO_DDR   DDRE
-#define DO_PORT  PORTE
-#define DO_PIN   PINE
-#define DO_BIT   6
-
-#define PCINT6_DDR   DDRE
-#define PCINT6_PORT  PORTE
-#define PCINT6_PIN   PINE
-#define PCINT6_BIT   6
-
-#define PCINT7_DDR   DDRE
-#define PCINT7_PORT  PORTE
-#define PCINT7_PIN   PINE
-#define PCINT7_BIT   7
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   1
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   2
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   3
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define OC0_DDR   DDRB
-#define OC0_PORT  PORTB
-#define OC0_PIN   PINB
-#define OC0_BIT   4
-
-#define PCINT12_DDR   DDRB
-#define PCINT12_PORT  PORTB
-#define PCINT12_PIN   PINB
-#define PCINT12_BIT   4
-
-#define OC1A_DDR   DDRB
-#define OC1A_PORT  PORTB
-#define OC1A_PIN   PINB
-#define OC1A_BIT   5
-
-#define PCINT13_DDR   DDRB
-#define PCINT13_PORT  PORTB
-#define PCINT13_PIN   PINB
-#define PCINT13_BIT   5
-
-#define OC1B_DDR   DDRB
-#define OC1B_PORT  PORTB
-#define OC1B_PIN   PINB
-#define OC1B_BIT   6
-
-#define PCINT14_DDR   DDRB
-#define PCINT14_PORT  PORTB
-#define PCINT14_PIN   PINB
-#define PCINT14_BIT   6
-
-#define OC2_DDR   DDRB
-#define OC2_PORT  PORTB
-#define OC2_PIN   PINB
-#define OC2_BIT   7
-
-#define PCINT15_DDR   DDRB
-#define PCINT15_PORT  PORTB
-#define PCINT15_PIN   PINB
-#define PCINT15_BIT   7
-
-#define T1_DDR   DDRG
-#define T1_PORT  PORTG
-#define T1_PIN   PING
-#define T1_BIT   3
-
-#define SEG24_DDR   DDRG
-#define SEG24_PORT  PORTG
-#define SEG24_PIN   PING
-#define SEG24_BIT   3
-
-#define T0_DDR   DDRG
-#define T0_PORT  PORTG
-#define T0_PIN   PING
-#define T0_BIT   4
-
-#define SEG23_DDR   DDRG
-#define SEG23_PORT  PORTG
-#define SEG23_PIN   PING
-#define SEG23_BIT   4
-
-#define ICP/SEG22_DDR   DDRD
-#define ICP/SEG22_PORT  PORTD
-#define ICP/SEG22_PIN   PIND
-#define ICP/SEG22_BIT   0
-
-#define INT0/SEG21_DDR   DDRD
-#define INT0/SEG21_PORT  PORTD
-#define INT0/SEG21_PIN   PIND
-#define INT0/SEG21_BIT   1
-
-#define SEG20_DDR   DDRD
-#define SEG20_PORT  PORTD
-#define SEG20_PIN   PIND
-#define SEG20_BIT   2
-
-#define SEG19_DDR   DDRD
-#define SEG19_PORT  PORTD
-#define SEG19_PIN   PIND
-#define SEG19_BIT   3
-
-#define SEG18_DDR   DDRD
-#define SEG18_PORT  PORTD
-#define SEG18_PIN   PIND
-#define SEG18_BIT   4
-
-#define SEG17_DDR   DDRD
-#define SEG17_PORT  PORTD
-#define SEG17_PIN   PIND
-#define SEG17_BIT   5
-
-#define SEG16_DDR   DDRD
-#define SEG16_PORT  PORTD
-#define SEG16_PIN   PIND
-#define SEG16_BIT   6
-
-#define SEG15_DDR   DDRD
-#define SEG15_PORT  PORTD
-#define SEG15_PIN   PIND
-#define SEG15_BIT   7
-
-#define SEG14_DDR   DDRG
-#define SEG14_PORT  PORTG
-#define SEG14_PIN   PING
-#define SEG14_BIT   0
-
-#define SEG13_DDR   DDRG
-#define SEG13_PORT  PORTG
-#define SEG13_PIN   PING
-#define SEG13_BIT   1
-
-#define SEG12_DDR   DDRC
-#define SEG12_PORT  PORTC
-#define SEG12_PIN   PINC
-#define SEG12_BIT   0
-
-#define SEG11_DDR   DDRC
-#define SEG11_PORT  PORTC
-#define SEG11_PIN   PINC
-#define SEG11_BIT   1
-
-#define SEG10_DDR   DDRC
-#define SEG10_PORT  PORTC
-#define SEG10_PIN   PINC
-#define SEG10_BIT   2
-
-#define SEG9_DDR   DDRC
-#define SEG9_PORT  PORTC
-#define SEG9_PIN   PINC
-#define SEG9_BIT   3
-
-#define SEG8_DDR   DDRC
-#define SEG8_PORT  PORTC
-#define SEG8_PIN   PINC
-#define SEG8_BIT   4
-
-#define SEG7_DDR   DDRC
-#define SEG7_PORT  PORTC
-#define SEG7_PIN   PINC
-#define SEG7_BIT   5
-
-#define SEG6_DDR   DDRC
-#define SEG6_PORT  PORTC
-#define SEG6_PIN   PINC
-#define SEG6_BIT   6
-
-#define SEG5_DDR   DDRC
-#define SEG5_PORT  PORTC
-#define SEG5_PIN   PINC
-#define SEG5_BIT   7
-
-#define SEG4_DDR   DDRG
-#define SEG4_PORT  PORTG
-#define SEG4_PIN   PING
-#define SEG4_BIT   2
-
-#define SEG3_DDR   DDRA
-#define SEG3_PORT  PORTA
-#define SEG3_PIN   PINA
-#define SEG3_BIT   7
-
-#define SEG2_DDR   DDRA
-#define SEG2_PORT  PORTA
-#define SEG2_PIN   PINA
-#define SEG2_BIT   6
-
-#define SEG1_DDR   DDRA
-#define SEG1_PORT  PORTA
-#define SEG1_PIN   PINA
-#define SEG1_BIT   5
-
-#define SEG0_DDR   DDRA
-#define SEG0_PORT  PORTA
-#define SEG0_PIN   PINA
-#define SEG0_BIT   4
-
-#define COM3_DDR   DDRA
-#define COM3_PORT  PORTA
-#define COM3_PIN   PINA
-#define COM3_BIT   3
-
-#define COM2_DDR   DDRA
-#define COM2_PORT  PORTA
-#define COM2_PIN   PINA
-#define COM2_BIT   2
-
-#define COM1_DDR   DDRA
-#define COM1_PORT  PORTA
-#define COM1_PIN   PINA
-#define COM1_BIT   1
-
-#define COM0_DDR   DDRA
-#define COM0_PORT  PORTA
-#define COM0_PIN   PINA
-#define COM0_BIT   0
-
-#define ADC7_DDR   DDRF
-#define ADC7_PORT  PORTF
-#define ADC7_PIN   PINF
-#define ADC7_BIT   7
-
-#define ADC6_DDR   DDRF
-#define ADC6_PORT  PORTF
-#define ADC6_PIN   PINF
-#define ADC6_BIT   6
-
-#define TD0_DDR   DDRF
-#define TD0_PORT  PORTF
-#define TD0_PIN   PINF
-#define TD0_BIT   6
-
-#define ADC5_DDR   DDRF
-#define ADC5_PORT  PORTF
-#define ADC5_PIN   PINF
-#define ADC5_BIT   5
-
-#define ADC4_DDR   DDRF
-#define ADC4_PORT  PORTF
-#define ADC4_PIN   PINF
-#define ADC4_BIT   4
-
-#define ADC3_DDR   DDRF
-#define ADC3_PORT  PORTF
-#define ADC3_PIN   PINF
-#define ADC3_BIT   3
-
-#define ADC2_DDR   DDRF
-#define ADC2_PORT  PORTF
-#define ADC2_PIN   PINF
-#define ADC2_BIT   2
-
-#define ADC1_DDR   DDRF
-#define ADC1_PORT  PORTF
-#define ADC1_PIN   PINF
-#define ADC1_BIT   1
-
-#define ADC0_DDR   DDRF
-#define ADC0_PORT  PORTF
-#define ADC0_PIN   PINF
-#define ADC0_BIT   0
-
-#endif /* _AVR_ATmega649_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom64c1.h b/cpukit/score/cpu/avr/avr/iom64c1.h
deleted file mode 100644
index 5895fe9857..0000000000
--- a/cpukit/score/cpu/avr/avr/iom64c1.h
+++ /dev/null
@@ -1,1313 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega64C1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom64c1.h - definitions for ATmega64C1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom64c1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega64C1_H_
-#define _AVR_ATmega64C1_H_ 1
-
-/**
- * @defgroup AvrDef_iom64c1 ATmega64C1 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 6
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRLIN 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC 5
-#define PRCAN 6
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define PCMSK3 _SFR_MEM8(0x6D)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x75)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0TS2 2
-#define AMPCMP0 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x76)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1TS2 2
-#define AMPCMP1 3
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#define AMP2CSR _SFR_MEM8(0x77)
-#define AMP2TS0 0
-#define AMP2TS1 1
-#define AMP2TS2 2
-#define AMPCMP2 3
-#define AMP2G0 4
-#define AMP2G1 5
-#define AMP2IS 6
-#define AMP2EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define AREFEN 5
-#define ISRCEN 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-#define AMP2PD 6
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define DACON _SFR_MEM8(0x90)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0x91)
-
-#define DACL _SFR_MEM8(0x91)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0x92)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0x94)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define ACCKSEL 3
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0x95)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x96)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x97)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define CANGCON _SFR_MEM8(0xD8)
-#define SWRES 0
-#define ENASTB 1
-#define TEST 2
-#define LISTEN 3
-#define SYNTTC 4
-#define TTC 5
-#define OVRQ 6
-#define ABRQ 7
-
-#define CANGSTA _SFR_MEM8(0xD9)
-#define ERRP 0
-#define BOFF 1
-#define ENFG 2
-#define RXBSY 3
-#define TXBSY 4
-#define OVFG 6
-
-#define CANGIT _SFR_MEM8(0xDA)
-#define AERG 0
-#define FERG 1
-#define CERG 2
-#define SERG 3
-#define BXOK 4
-#define OVRTIM 5
-#define BOFFIT 6
-#define CANIT 7
-
-#define CANGIE _SFR_MEM8(0xDB)
-#define ENOVRT 0
-#define ENERG 1
-#define ENBX 2
-#define ENERR 3
-#define ENTX 4
-#define ENRX 5
-#define ENBOFF 6
-#define ENIT 7
-
-#define CANEN2 _SFR_MEM8(0xDC)
-#define ENMOB0 0
-#define ENMOB1 1
-#define ENMOB2 2
-#define ENMOB3 3
-#define ENMOB4 4
-#define ENMOB5 5
-
-#define CANEN1 _SFR_MEM8(0xDD)
-
-#define CANIE2 _SFR_MEM8(0xDE)
-#define IEMOB0 0
-#define IEMOB1 1
-#define IEMOB2 2
-#define IEMOB3 3
-#define IEMOB4 4
-#define IEMOB5 5
-
-#define CANIE1 _SFR_MEM8(0xDF)
-
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define SIT0 0
-#define SIT1 1
-#define SIT2 2
-#define SIT3 3
-#define SIT4 4
-#define SIT5 5
-
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-#define CANBT1 _SFR_MEM8(0xE2)
-#define BRP0 1
-#define BRP1 2
-#define BRP2 3
-#define BRP3 4
-#define BRP4 5
-#define BRP5 6
-
-#define CANBT2 _SFR_MEM8(0xE3)
-#define PRS0 1
-#define PRS1 2
-#define PRS2 3
-#define SJW0 5
-#define SJW1 6
-
-#define CANBT3 _SFR_MEM8(0xE4)
-#define SMP 0
-#define PHS10 1
-#define PHS11 2
-#define PHS12 3
-#define PHS20 4
-#define PHS21 5
-#define PHS22 6
-
-#define CANTCON _SFR_MEM8(0xE5)
-#define TPRSC0 0
-#define TPRSC1 1
-#define TPRSC2 2
-#define TPRSC3 3
-#define TPRSC4 4
-#define TPRSC5 5
-#define TPRSC6 6
-#define TPRSC7 7
-
-#define CANTIM _SFR_MEM16(0xE6)
-
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIM0 0
-#define CANTIM1 1
-#define CANTIM2 2
-#define CANTIM3 3
-#define CANTIM4 4
-#define CANTIM5 5
-#define CANTIM6 6
-#define CANTIM7 7
-
-#define CANTIMH _SFR_MEM8(0xE7)
-#define CANTIM8 0
-#define CANTIM9 1
-#define CANTIM10 2
-#define CANTIM11 3
-#define CANTIM12 4
-#define CANTIM13 5
-#define CANTIM14 6
-#define CANTIM15 7
-
-#define CANTTC _SFR_MEM16(0xE8)
-
-#define CANTTCL _SFR_MEM8(0xE8)
-#define TIMTCC0 0
-#define TIMTCC1 1
-#define TIMTCC2 2
-#define TIMTCC3 3
-#define TIMTCC4 4
-#define TIMTCC5 5
-#define TIMTCC6 6
-#define TIMTCC7 7
-
-#define CANTTCH _SFR_MEM8(0xE9)
-#define TIMTCC8 0
-#define TIMTCC9 1
-#define TIMTCC10 2
-#define TIMTCC11 3
-#define TIMTCC12 4
-#define TIMTCC13 5
-#define TIMTCC14 6
-#define TIMTCC15 7
-
-#define CANTEC _SFR_MEM8(0xEA)
-#define TEC0 0
-#define TEC1 1
-#define TEC2 2
-#define TEC3 3
-#define TEC4 4
-#define TEC5 5
-#define TEC6 6
-#define TEC7 7
-
-#define CANREC _SFR_MEM8(0xEB)
-#define REC0 0
-#define REC1 1
-#define REC2 2
-#define REC3 3
-#define REC4 4
-#define REC5 5
-#define REC6 6
-#define REC7 7
-
-#define CANHPMOB _SFR_MEM8(0xEC)
-#define CGP0 0
-#define CGP1 1
-#define CGP2 2
-#define CGP3 3
-#define HPMOB0 4
-#define HPMOB1 5
-#define HPMOB2 6
-#define HPMOB3 7
-
-#define CANPAGE _SFR_MEM8(0xED)
-#define INDX0 0
-#define INDX1 1
-#define INDX2 2
-#define AINC 3
-#define MOBNB0 4
-#define MOBNB1 5
-#define MOBNB2 6
-#define MOBNB3 7
-
-#define CANSTMOB _SFR_MEM8(0xEE)
-#define AERR 0
-#define FERR 1
-#define CERR 2
-#define SERR 3
-#define BERR 4
-#define RXOK 5
-#define TXOK 6
-#define DLCW 7
-
-#define CANCDMOB _SFR_MEM8(0xEF)
-#define DLC0 0
-#define DLC1 1
-#define DLC2 2
-#define DLC3 3
-#define IDE 4
-#define RPLV 5
-#define CONMOB0 6
-#define CONMOB1 7
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define RB0TAG 0
-#define RB1TAG 1
-#define RTRTAG 2
-#define IDT0 3
-#define IDT1 4
-#define IDT2 5
-#define IDT3 6
-#define IDT4 7
-
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define IDT5 0
-#define IDT6 1
-#define IDT7 2
-#define IDT8 3
-#define IDT9 4
-#define IDT10 5
-#define IDT11 6
-#define IDT12 7
-
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define IDT13 0
-#define IDT14 1
-#define IDT15 2
-#define IDT16 3
-#define IDT17 4
-#define IDT18 5
-#define IDT19 6
-#define IDT20 7
-
-#define CANIDT1 _SFR_MEM8(0xF3)
-#define IDT21 0
-#define IDT22 1
-#define IDT23 2
-#define IDT24 3
-#define IDT25 4
-#define IDT26 5
-#define IDT27 6
-#define IDT28 7
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define IDEMSK 0
-#define RTRMSK 2
-#define IDMSK0 3
-#define IDMSK1 4
-#define IDMSK2 5
-#define IDMSK3 6
-#define IDMSK4 7
-
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define IDMSK5 0
-#define IDMSK6 1
-#define IDMSK7 2
-#define IDMSK8 3
-#define IDMSK9 4
-#define IDMSK10 5
-#define IDMSK11 6
-#define IDMSK12 7
-
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define IDMSK13 0
-#define IDMSK14 1
-#define IDMSK15 2
-#define IDMSK16 3
-#define IDMSK17 4
-#define IDMSK18 5
-#define IDMSK19 6
-#define IDMSK20 7
-
-#define CANIDM1 _SFR_MEM8(0xF7)
-#define IDMSK21 0
-#define IDMSK22 1
-#define IDMSK23 2
-#define IDMSK24 3
-#define IDMSK25 4
-#define IDMSK26 5
-#define IDMSK27 6
-#define IDMSK28 7
-
-#define CANSTM _SFR_MEM16(0xF8)
-
-#define CANSTML _SFR_MEM8(0xF8)
-#define TIMSTM0 0
-#define TIMSTM1 1
-#define TIMSTM2 2
-#define TIMSTM3 3
-#define TIMSTM4 4
-#define TIMSTM5 5
-#define TIMSTM6 6
-#define TIMSTM7 7
-
-#define CANSTMH _SFR_MEM8(0xF9)
-#define TIMSTM8 0
-#define TIMSTM9 1
-#define TIMSTM10 2
-#define TIMSTM11 3
-#define TIMSTM12 4
-#define TIMSTM13 5
-#define TIMSTM14 6
-#define TIMSTM15 7
-
-#define CANMSG _SFR_MEM8(0xFA)
-#define MSG0 0
-#define MSG1 1
-#define MSG2 2
-#define MSG3 3
-#define MSG4 4
-#define MSG5 5
-#define MSG6 6
-#define MSG7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define ANACOMP0_vect_num  1
-#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
-#define ANACOMP1_vect_num  2
-#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
-#define ANACOMP2_vect_num  3
-#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
-#define ANACOMP3_vect_num  4
-#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
-#define PSC_FAULT_vect_num  5
-#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
-#define PSC_EC_vect_num  6
-#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
-#define INT0_vect_num  7
-#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
-#define INT1_vect_num  8
-#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
-#define INT2_vect_num  9
-#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
-#define INT3_vect_num  10
-#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  12
-#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  13
-#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  14
-#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  15
-#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  16
-#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  17
-#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define CAN_INT_vect_num  18
-#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
-#define CAN_TOVF_vect_num  19
-#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
-#define LIN_TC_vect_num  20
-#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  21
-#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
-#define PCINT0_vect_num  22
-#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  23
-#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  24
-#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  25
-#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
-#define SPI_STC_vect_num  26
-#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  27
-#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
-#define WDT_vect_num  28
-#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
-#define EE_READY_vect_num  29
-#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
-#define SPM_READY_vect_num  30
-#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (8)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
-#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
-#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
-#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x86
-
-/** @} */
-
-#endif /* _AVR_ATmega64C1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom64hve.h b/cpukit/score/cpu/avr/avr/iom64hve.h
deleted file mode 100644
index 913697de98..0000000000
--- a/cpukit/score/cpu/avr/avr/iom64hve.h
+++ /dev/null
@@ -1,1030 +0,0 @@
-/**
- * @file avr/iom64hve.h
- *
- * @brief Definitions for ATmega64HVE
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom64hve.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATmega64HVE_H_
-#define _AVR_ATmega64HVE_H_ 1
-
-/**
- *  @defgroup Avr_iom64hve ATmega64HVE Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-#define ICF0 3
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 3
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define ICS0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-
-#define TCNT0 _SFR_IO16(0x26)
-
-#define TCNT0L _SFR_IO8(0x26)
-#define TCNT0L0 0
-#define TCNT0L1 1
-#define TCNT0L2 2
-#define TCNT0L3 3
-#define TCNT0L4 4
-#define TCNT0L5 5
-#define TCNT0L6 6
-#define TCNT0L7 7
-
-#define TCNT0H _SFR_IO8(0x27)
-#define TCNT0H0 0
-#define TCNT0H1 1
-#define TCNT0H2 2
-#define TCNT0H3 3
-#define TCNT0H4 4
-#define TCNT0H5 5
-#define TCNT0H6 6
-#define TCNT0H7 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR0A0 0
-#define OCR0A1 1
-#define OCR0A2 2
-#define OCR0A3 3
-#define OCR0A4 4
-#define OCR0A5 5
-#define OCR0A6 6
-#define OCR0A7 7
-
-#define OCR0B _SFR_IO8(0x29)
-#define OCR0B0 0
-#define OCR0B1 1
-#define OCR0B2 2
-#define OCR0B3 3
-#define OCR0B4 4
-#define OCR0B5 5
-#define OCR0B6 6
-#define OCR0B7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define TCCR0C _SFR_IO8(0x2F)
-
-#define OCDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BODRF 2
-#define WDRF 3
-#define OCDRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define CKOE 5
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define LBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPCE 7
-
-#define WUTCSR _SFR_MEM8(0x62)
-#define WUTP0 0
-#define WUTP1 1
-#define WUTP2 2
-#define WUTE 3
-#define WUTR 4
-#define WUTIE 6
-#define WUTIF 7
-
-#define WDTCLR _SFR_MEM8(0x63)
-#define WDCLE 0
-#define WDCL0 1
-#define WDCL1 2
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRTIM0 0
-#define PRTIM1 1
-#define PRSPI 2
-#define PRLIN 3
-
-#define SOSCCALA _SFR_MEM8(0x66)
-#define SCALA0 0
-#define SCALA1 1
-#define SCALA2 2
-#define SCALA3 3
-#define SCALA4 4
-#define SCALA5 5
-#define SCALA6 6
-#define SCALA7 7
-
-#define SOSCCALB _SFR_MEM8(0x67)
-#define SCALB0 0
-#define SCALB1 1
-#define SCALB2 2
-#define SCALB3 3
-#define SCALB4 4
-#define SCALB5 5
-#define SCALB6 6
-#define SCALB7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT2 0
-#define PCINT3 1
-#define PCINT4 2
-#define PCINT5 3
-#define PCINT6 4
-#define PCINT7 5
-#define PCINT8 6
-#define PCINT9 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-#define ICIE0 3
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 3
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define PA0DID 0
-#define PA1DID 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define ICS1 3
-#define ICES1 4
-#define ICNC1 5
-#define ICEN1 6
-#define TCW1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-
-#define TCCR1C _SFR_MEM8(0x82)
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR1A _SFR_MEM8(0x88)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define OCR1B _SFR_MEM8(0x89)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define LINCR _SFR_MEM8(0xC0)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC1)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xC2)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xC3)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xC4)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xC5)
-
-#define LINBRRL _SFR_MEM8(0xC5)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xC6)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xC7)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xC8)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xC9)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xCA)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define BGCSRA _SFR_MEM8(0xD1)
-#define BGSC0 0
-#define BGSC1 1
-#define BGSC2 2
-
-#define BGCRB _SFR_MEM8(0xD2)
-#define BGCL0 0
-#define BGCL1 1
-#define BGCL2 2
-#define BGCL3 3
-#define BGCL4 4
-#define BGCL5 5
-#define BGCL6 6
-#define BGCL7 7
-
-#define BGCRA _SFR_MEM8(0xD3)
-#define BGCN0 0
-#define BGCN1 1
-#define BGCN2 2
-#define BGCN3 3
-#define BGCN4 4
-#define BGCN5 5
-#define BGCN6 6
-#define BGCN7 7
-
-#define BGLR _SFR_MEM8(0xD4)
-#define BGPL 0
-#define BGPLE 1
-
-#define PLLCSR _SFR_MEM8(0xD8)
-#define PLLCIE 0
-#define PLLCIF 1
-#define LOCK 4
-#define SWEN 5
-
-#define PBOV _SFR_MEM8(0xDC)
-#define PBOE0 0
-#define PBOE3 3
-#define PBOVCE 7
-
-#define ADSCSRA _SFR_MEM8(0xE0)
-#define SCMD0 0
-#define SCMD1 1
-#define SBSY 2
-
-#define ADSCSRB _SFR_MEM8(0xE1)
-#define CADICRB 0
-#define CADACRB 1
-#define CADICPS 2
-#define VADICRB 4
-#define VADACRB 5
-#define VADICPS 6
-
-#define ADCRA _SFR_MEM8(0xE2)
-#define CKSEL 0
-#define ADCMS0 1
-#define ADCMS1 2
-#define ADPSEL 3
-
-#define ADCRB _SFR_MEM8(0xE3)
-#define ADADES0 0
-#define ADADES1 1
-#define ADADES2 2
-#define ADIDES0 3
-#define ADIDES1 4
-
-#define ADCRC _SFR_MEM8(0xE4)
-#define CADRCT0 0
-#define CADRCT1 1
-#define CADRCT2 2
-#define CADRCT3 3
-#define CADRCM0 4
-#define CADRCM1 5
-#define CADEN 7
-
-#define ADCRD _SFR_MEM8(0xE5)
-#define CADDSEL 0
-#define CADPDM0 1
-#define CADPDM1 2
-#define CADG0 3
-#define CADG1 4
-#define CADG2 5
-
-#define ADCRE _SFR_MEM8(0xE6)
-#define VADMUX0 0
-#define VADMUX1 1
-#define VADMUX2 2
-#define VADPDM0 3
-#define VADPDM1 4
-#define VADREFS 5
-#define VADEN 7
-
-#define ADIFR _SFR_MEM8(0xE7)
-#define CADICIF 0
-#define CADACIF 1
-#define CADRCIF 2
-#define VADICIF 4
-#define VADACIF 5
-
-#define ADIMR _SFR_MEM8(0xE8)
-#define CADICIE 0
-#define CADACIE 1
-#define CADRCIE 2
-#define VADICIE 4
-#define VADACIE 5
-
-#define CADRCL _SFR_MEM16(0xE9)
-
-#define CADRCLL _SFR_MEM8(0xE9)
-#define CADRCL0 0
-#define CADRCL1 1
-#define CADRCL2 2
-#define CADRCL3 3
-#define CADRCL4 4
-#define CADRCL5 5
-#define CADRCL6 6
-#define CADRCL7 7
-
-#define CADRCLH _SFR_MEM8(0xEA)
-#define CADRCL8 0
-#define CADRCL9 1
-#define CADRCL10 2
-#define CADRCL11 3
-#define CADRCL12 4
-#define CADRCL13 5
-#define CADRCL14 6
-#define CADRCL15 7
-
-#define CADIC _SFR_MEM16(0xEB)
-
-#define CADICL _SFR_MEM8(0xEB)
-#define CADIC0 0
-#define CADIC1 1
-#define CADIC2 2
-#define CADIC3 3
-#define CADIC4 4
-#define CADIC5 5
-#define CADIC6 6
-#define CADIC7 7
-
-#define CADICH _SFR_MEM8(0xEC)
-#define CADIC8 0
-#define CADIC9 1
-#define CADIC10 2
-#define CADIC11 3
-#define CADIC12 4
-#define CADIC13 5
-#define CADIC14 6
-#define CADIC15 7
-
-#define CADAC0 _SFR_MEM8(0xED)
-#define CADAC00 0
-#define CADAC01 1
-#define CADAC02 2
-#define CADAC03 3
-#define CADAC04 4
-#define CADAC05 5
-#define CADAC06 6
-#define CADAC07 7
-
-#define CADAC1 _SFR_MEM8(0xEE)
-#define CADAC08 0
-#define CADAC09 1
-#define CADAC10 2
-#define CADAC11 3
-#define CADAC12 4
-#define CADAC13 5
-#define CADAC14 6
-#define CADAC15 7
-
-#define CADAC2 _SFR_MEM8(0xEF)
-#define CADAC16 0
-#define CADAC17 1
-#define CADAC18 2
-#define CADAC19 3
-#define CADAC20 4
-#define CADAC21 5
-#define CADAC22 6
-#define CADAC23 7
-
-#define CADAC3 _SFR_MEM8(0xF0)
-#define CADAC24 0
-#define CADAC25 1
-#define CADAC26 2
-#define CADAC27 3
-#define CADAC28 4
-#define CADAC29 5
-#define CADAC30 6
-#define CADAC31 7
-
-#define VADIC _SFR_MEM16(0xF1)
-
-#define VADICL _SFR_MEM8(0xF1)
-#define VADIC0 0
-#define VADIC1 1
-#define VADIC2 2
-#define VADIC3 3
-#define VADIC4 4
-#define VADIC5 5
-#define VADIC6 6
-#define VADIC7 7
-
-#define VADICH _SFR_MEM8(0xF2)
-#define VADIC8 0
-#define VADIC9 1
-#define VADIC10 2
-#define VADIC11 3
-#define VADIC12 4
-#define VADIC13 5
-#define VADIC14 6
-#define VADIC15 7
-
-#define VADAC0 _SFR_MEM8(0xF3)
-#define VADAC00 0
-#define VADAC01 1
-#define VADAC02 2
-#define VADAC03 3
-#define VADAC04 4
-#define VADAC05 5
-#define VADAC06 6
-#define VADAC07 7
-
-#define VADAC1 _SFR_MEM8(0xF4)
-#define VADAC08 0
-#define VADAC09 1
-#define VADAC10 2
-#define VADAC11 3
-#define VADAC12 4
-#define VADAC13 5
-#define VADAC14 6
-#define VADAC15 7
-
-#define VADAC2 _SFR_MEM8(0xF5)
-#define VADAC16 0
-#define VADAC17 1
-#define VADAC18 2
-#define VADAC19 3
-#define VADAC20 4
-#define VADAC21 5
-#define VADAC22 6
-#define VADAC23 7
-
-#define VADAC3 _SFR_MEM8(0xF6)
-#define VADAC24 0
-#define VADAC25 1
-#define VADAC26 2
-#define VADAC27 3
-#define VADAC28 4
-#define VADAC29 5
-#define VADAC30 6
-#define VADAC31 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt 0 */
-#define PCINT1_vect_num  3
-#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt 1 */
-#define WDT_vect_num  4
-#define WDT_vect      _VECTOR(4)  /* Watchdog Timeout Interrupt */
-#define WAKEUP_vect_num  5
-#define WAKEUP_vect      _VECTOR(5)  /* Wakeup Timer Overflow */
-#define TIMER1_IC_vect_num  6
-#define TIMER1_IC_vect      _VECTOR(6)  /* Timer 1 Input capture */
-#define TIMER1_COMPA_vect_num  7
-#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer 1 Compare Match A */
-#define TIMER1_COMPB_vect_num  8
-#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer 1 Compare Match B */
-#define TIMER1_OVF_vect_num  9
-#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer 1 overflow */
-#define TIMER0_IC_vect_num  10
-#define TIMER0_IC_vect      _VECTOR(10)  /* Timer 0 Input Capture */
-#define TIMER0_COMPA_vect_num  11
-#define TIMER0_COMPA_vect      _VECTOR(11)  /* Timer 0 Comapre Match A */
-#define TIMER0_COMPB_vect_num  12
-#define TIMER0_COMPB_vect      _VECTOR(12)  /* Timer 0 Compare Match B */
-#define TIMER0_OVF_vect_num  13
-#define TIMER0_OVF_vect      _VECTOR(13)  /* Timer 0 Overflow */
-#define LIN_STATUS_vect_num  14
-#define LIN_STATUS_vect      _VECTOR(14)  /* LIN Status Interrupt */
-#define LIN_ERROR_vect_num  15
-#define LIN_ERROR_vect      _VECTOR(15)  /* LIN Error Interrupt */
-#define SPI_STC_vect_num  16
-#define SPI_STC_vect      _VECTOR(16)  /* SPI Serial transfer complete */
-#define VADC_CONV_vect_num  17
-#define VADC_CONV_vect      _VECTOR(17)  /* Voltage ADC Instantaneous Conversion Complete */
-#define VADC_ACC_vect_num  18
-#define VADC_ACC_vect      _VECTOR(18)  /* Voltage ADC Accumulated Conversion Complete */
-#define CADC_CONV_vect_num  19
-#define CADC_CONV_vect      _VECTOR(19)  /* C-ADC Instantaneous Conversion Complete */
-#define CADC_REG_CUR_vect_num  20
-#define CADC_REG_CUR_vect      _VECTOR(20)  /* C-ADC Regular Current */
-#define CADC_ACC_vect_num  21
-#define CADC_ACC_vect      _VECTOR(21)  /* C-ADC Accumulated Conversion Complete */
-#define EE_READY_vect_num  22
-#define EE_READY_vect      _VECTOR(22)  /* EEPROM Ready */
-#define SPM_vect_num  23
-#define SPM_vect      _VECTOR(23)  /* SPM Ready */
-#define PLL_vect_num  24
-#define PLL_vect      _VECTOR(24)  /* PLL Lock Change Interrupt */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (25 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (NA)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x3FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_OSCSEL0  (unsigned char)~_BV(0)  /* Oscillator Select */
-#define FUSE_SUT0  (unsigned char)~_BV(1)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(2)  /* Select start-up time */
-#define FUSE_CKDIV8  (unsigned char)~_BV(3)  /* Divide clock by 8 */
-#define FUSE_BODEN  (unsigned char)~_BV(4)  /* Enable BOD */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_DWEN  (unsigned char)~_BV(3)  /* Enable debugWire */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x10
-
-
-/* Device Pin Definitions */
-#define PV2_DDR   DDRV
-#define PV2_PORT  PORTV
-#define PV2_PIN   PINV
-#define PV2_BIT   2
-
-#define PV1_DDR   DDRV
-#define PV1_PORT  PORTV
-#define PV1_PIN   PINV
-#define PV1_BIT   1
-
-#define NV_DDR   DDRNV
-#define NV_PORT  PORTNV
-#define NV_PIN   PINNV
-#define NV_BIT   NV
-
-#define VFET_DDR   DDRVFET
-#define VFET_PORT  PORTVFET
-#define VFET_PIN   PINVFET
-#define VFET_BIT   VFET
-
-#define CF1P_DDR   DDRCF1P
-#define CF1P_PORT  PORTCF1P
-#define CF1P_PIN   PINCF1P
-#define CF1P_BIT   CF1P
-
-#define CF1N_DDR   DDRCF1N
-#define CF1N_PORT  PORTCF1N
-#define CF1N_PIN   PINCF1N
-#define CF1N_BIT   CF1N
-
-#define CF2P_DDR   DDRCF2P
-#define CF2P_PORT  PORTCF2P
-#define CF2P_PIN   PINCF2P
-#define CF2P_BIT   CF2P
-
-#define CF2N_DDR   DDRCF2N
-#define CF2N_PORT  PORTCF2N
-#define CF2N_PIN   PINCF2N
-#define CF2N_BIT   CF2N
-
-#define VREG_DDR   DDRVREG
-#define VREG_PORT  PORTVREG
-#define VREG_PIN   PINVREG
-#define VREG_BIT   VREG
-
-#define VREF_DDR   DDRVREF
-#define VREF_PORT  PORTVREF
-#define VREF_PIN   PINVREF
-#define VREF_BIT   VREF
-
-#define VREFGND_DDR   DDRVREFGND
-#define VREFGND_PORT  PORTVREFGND
-#define VREFGND_PIN   PINVREFGND
-#define VREFGND_BIT   VREFGND
-
-#define PI_DDR   DDRI
-#define PI_PORT  PORTI
-#define PI_PIN   PINI
-#define PI_BIT
-
-#define NI_DDR   DDRNI
-#define NI_PORT  PORTNI
-#define NI_PIN   PINNI
-#define NI_BIT   NI
-
-#define PA0_DDR   DDRA
-#define PA0_PORT  PORTA
-#define PA0_PIN   PINA
-#define PA0_BIT   0
-
-#define PA1_DDR   DDRA
-#define PA1_PORT  PORTA
-#define PA1_PIN   PINA
-#define PA1_BIT   1
-
-#define PA2_DDR   DDRA
-#define PA2_PORT  PORTA
-#define PA2_PIN   PINA
-#define PA2_BIT   2
-
-#define PB0_DDR   DDRB
-#define PB0_PORT  PORTB
-#define PB0_PIN   PINB
-#define PB0_BIT   0
-
-#define PB1_DDR   DDRB
-#define PB1_PORT  PORTB
-#define PB1_PIN   PINB
-#define PB1_BIT   1
-
-#define PB2_DDR   DDRB
-#define PB2_PORT  PORTB
-#define PB2_PIN   PINB
-#define PB2_BIT   2
-
-#define PB3_DDR   DDRB
-#define PB3_PORT  PORTB
-#define PB3_PIN   PINB
-#define PB3_BIT   3
-
-#define PC0_DDR   DDRC
-#define PC0_PORT  PORTC
-#define PC0_PIN   PINC
-#define PC0_BIT   0
-
-#define BATT_DDR   DDRBATT
-#define BATT_PORT  PORTBATT
-#define BATT_PIN   PINBATT
-#define BATT_BIT   BATT
-
-#define OC_DDR   DDROC
-#define OC_PORT  PORTOC
-#define OC_PIN   PINOC
-#define OC_BIT   OC
-
-/**@}*/
-#endif /* _AVR_ATmega64HVE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom64m1.h b/cpukit/score/cpu/avr/avr/iom64m1.h
deleted file mode 100644
index 492e524185..0000000000
--- a/cpukit/score/cpu/avr/avr/iom64m1.h
+++ /dev/null
@@ -1,1581 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom64m1.h - definitions for ATmega64M1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom64m1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega64M1_H_
-#define _AVR_ATmega64M1_H_ 1
-
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 6
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define DWDR _SFR_IO8(0x31)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRLIN 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC 5
-#define PRCAN 6
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define PCMSK3 _SFR_MEM8(0x6D)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x75)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0TS2 2
-#define AMPCMP0 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x76)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1TS2 2
-#define AMPCMP1 3
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#define AMP2CSR _SFR_MEM8(0x77)
-#define AMP2TS0 0
-#define AMP2TS1 1
-#define AMP2TS2 2
-#define AMPCMP2 3
-#define AMP2G0 4
-#define AMP2G1 5
-#define AMP2IS 6
-#define AMP2EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define AREFEN 5
-#define ISRCEN 6
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-#define AMP2PD 6
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define DACON _SFR_MEM8(0x90)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0x91)
-
-#define DACL _SFR_MEM8(0x91)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0x92)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0x94)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define ACCKSEL 3
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0x95)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x96)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x97)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define POCR0SA _SFR_MEM16(0xA0)
-
-#define POCR0SAL _SFR_MEM8(0xA0)
-#define POCR0SA_0 0
-#define POCR0SA_1 1
-#define POCR0SA_2 2
-#define POCR0SA_3 3
-#define POCR0SA_4 4
-#define POCR0SA_5 5
-#define POCR0SA_6 6
-#define POCR0SA_7 7
-
-#define POCR0SAH _SFR_MEM8(0xA1)
-#define POCR0SA_8 0
-#define POCR0SA_9 1
-#define POCR0SA_10 2
-#define POCR0SA_11 3
-
-#define POCR0RA _SFR_MEM16(0xA2)
-
-#define POCR0RAL _SFR_MEM8(0xA2)
-#define POCR0RA_0 0
-#define POCR0RA_1 1
-#define POCR0RA_2 2
-#define POCR0RA_3 3
-#define POCR0RA_4 4
-#define POCR0RA_5 5
-#define POCR0RA_6 6
-#define POCR0RA_7 7
-
-#define POCR0RAH _SFR_MEM8(0xA3)
-#define POCR0RA_8 0
-#define POCR0RA_9 1
-#define POCR0RA_10 2
-#define POCR0RA_11 3
-
-#define POCR0SB _SFR_MEM16(0xA4)
-
-#define POCR0SBL _SFR_MEM8(0xA4)
-#define POCR0SB_0 0
-#define POCR0SB_1 1
-#define POCR0SB_2 2
-#define POCR0SB_3 3
-#define POCR0SB_4 4
-#define POCR0SB_5 5
-#define POCR0SB_6 6
-#define POCR0SB_7 7
-
-#define POCR0SBH _SFR_MEM8(0xA5)
-#define POCR0SB_8 0
-#define POCR0SB_9 1
-#define POCR0SB_10 2
-#define POCR0SB_11 3
-
-#define POCR1SA _SFR_MEM16(0xA6)
-
-#define POCR1SAL _SFR_MEM8(0xA6)
-#define POCR1SA_0 0
-#define POCR1SA_1 1
-#define POCR1SA_2 2
-#define POCR1SA_3 3
-#define POCR1SA_4 4
-#define POCR1SA_5 5
-#define POCR1SA_6 6
-#define POCR1SA_7 7
-
-#define POCR1SAH _SFR_MEM8(0xA7)
-#define POCR1SA_8 0
-#define POCR1SA_9 1
-#define POCR1SA_10 2
-#define POCR1SA_11 3
-
-#define POCR1RA _SFR_MEM16(0xA8)
-
-#define POCR1RAL _SFR_MEM8(0xA8)
-#define POCR1RA_0 0
-#define POCR1RA_1 1
-#define POCR1RA_2 2
-#define POCR1RA_3 3
-#define POCR1RA_4 4
-#define POCR1RA_5 5
-#define POCR1RA_6 6
-#define POCR1RA_7 7
-
-#define POCR1RAH _SFR_MEM8(0xA9)
-#define POCR1RA_8 0
-#define POCR1RA_9 1
-#define POCR1RA_10 2
-#define POCR1RA_11 3
-
-#define POCR1SB _SFR_MEM16(0xAA)
-
-#define POCR1SBL _SFR_MEM8(0xAA)
-#define POCR1SB_0 0
-#define POCR1SB_1 1
-#define POCR1SB_2 2
-#define POCR1SB_3 3
-#define POCR1SB_4 4
-#define POCR1SB_5 5
-#define POCR1SB_6 6
-#define POCR1SB_7 7
-
-#define POCR1SBH _SFR_MEM8(0xAB)
-#define POCR1SB_8 0
-#define POCR1SB_9 1
-#define POCR1SB_10 2
-#define POCR1SB_11 3
-
-#define POCR2SA _SFR_MEM16(0xAC)
-
-#define POCR2SAL _SFR_MEM8(0xAC)
-#define POCR2SA_0 0
-#define POCR2SA_1 1
-#define POCR2SA_2 2
-#define POCR2SA_3 3
-#define POCR2SA_4 4
-#define POCR2SA_5 5
-#define POCR2SA_6 6
-#define POCR2SA_7 7
-
-#define POCR2SAH _SFR_MEM8(0xAD)
-#define POCR2SA_8 0
-#define POCR2SA_9 1
-#define POCR2SA_10 2
-#define POCR2SA_11 3
-
-#define POCR2RA _SFR_MEM16(0xAE)
-
-#define POCR2RAL _SFR_MEM8(0xAE)
-#define POCR2RA_0 0
-#define POCR2RA_1 1
-#define POCR2RA_2 2
-#define POCR2RA_3 3
-#define POCR2RA_4 4
-#define POCR2RA_5 5
-#define POCR2RA_6 6
-#define POCR2RA_7 7
-
-#define POCR2RAH _SFR_MEM8(0xAF)
-#define POCR2RA_8 0
-#define POCR2RA_9 1
-#define POCR2RA_10 2
-#define POCR2RA_11 3
-
-#define POCR2SB _SFR_MEM16(0xB0)
-
-#define POCR2SBL _SFR_MEM8(0xB0)
-#define POCR2SB_0 0
-#define POCR2SB_1 1
-#define POCR2SB_2 2
-#define POCR2SB_3 3
-#define POCR2SB_4 4
-#define POCR2SB_5 5
-#define POCR2SB_6 6
-#define POCR2SB_7 7
-
-#define POCR2SBH _SFR_MEM8(0xB1)
-#define POCR2SB_8 0
-#define POCR2SB_9 1
-#define POCR2SB_10 2
-#define POCR2SB_11 3
-
-#define POCR_RB _SFR_MEM16(0xB2)
-
-#define POCR_RBL _SFR_MEM8(0xB2)
-#define POCR_RB_0 0
-#define POCR_RB_1 1
-#define POCR_RB_2 2
-#define POCR_RB_3 3
-#define POCR_RB_4 4
-#define POCR_RB_5 5
-#define POCR_RB_6 6
-#define POCR_RB_7 7
-
-#define POCR_RBH _SFR_MEM8(0xB3)
-#define POCR_RB_8 0
-#define POCR_RB_9 1
-#define POCR_RB_10 2
-#define POCR_RB_11 3
-
-#define PSYNC _SFR_MEM8(0xB4)
-#define PSYNC00 0
-#define PSYNC01 1
-#define PSYNC10 2
-#define PSYNC11 3
-#define PSYNC20 4
-#define PSYNC21 5
-
-#define PCNF _SFR_MEM8(0xB5)
-#define POPA 2
-#define POPB 3
-#define PMODE 4
-#define PULOCK 5
-
-#define POC _SFR_MEM8(0xB6)
-#define POEN0A 0
-#define POEN0B 1
-#define POEN1A 2
-#define POEN1B 3
-#define POEN2A 4
-#define POEN2B 5
-
-#define PCTL _SFR_MEM8(0xB7)
-#define PRUN 0
-#define PCCYC 1
-#define PCLKSEL 5
-#define PPRE0 6
-#define PPRE1 7
-
-#define PMIC0 _SFR_MEM8(0xB8)
-#define PRFM00 0
-#define PRFM01 1
-#define PRFM02 2
-#define PAOC0 3
-#define PFLTE0 4
-#define PELEV0 5
-#define PISEL0 6
-#define POVEN0 7
-
-#define PMIC1 _SFR_MEM8(0xB9)
-#define PRFM10 0
-#define PRFM11 1
-#define PRFM12 2
-#define PAOC1 3
-#define PFLTE1 4
-#define PELEV1 5
-#define PISEL1 6
-#define POVEN1 7
-
-#define PMIC2 _SFR_MEM8(0xBA)
-#define PRFM20 0
-#define PRFM21 1
-#define PRFM22 2
-#define PAOC2 3
-#define PFLTE2 4
-#define PELEV2 5
-#define PISEL2 6
-#define POVEN2 7
-
-#define PIM _SFR_MEM8(0xBB)
-#define PEOPE 0
-#define PEVE0 1
-#define PEVE1 2
-#define PEVE2 3
-
-#define PIFR _SFR_MEM8(0xBC)
-#define PEOP 0
-#define PEV0 1
-#define PEV1 2
-#define PEV2 3
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-#define CANGCON _SFR_MEM8(0xD8)
-#define SWRES 0
-#define ENASTB 1
-#define TEST 2
-#define LISTEN 3
-#define SYNTTC 4
-#define TTC 5
-#define OVRQ 6
-#define ABRQ 7
-
-#define CANGSTA _SFR_MEM8(0xD9)
-#define ERRP 0
-#define BOFF 1
-#define ENFG 2
-#define RXBSY 3
-#define TXBSY 4
-#define OVFG 6
-
-#define CANGIT _SFR_MEM8(0xDA)
-#define AERG 0
-#define FERG 1
-#define CERG 2
-#define SERG 3
-#define BXOK 4
-#define OVRTIM 5
-#define BOFFIT 6
-#define CANIT 7
-
-#define CANGIE _SFR_MEM8(0xDB)
-#define ENOVRT 0
-#define ENERG 1
-#define ENBX 2
-#define ENERR 3
-#define ENTX 4
-#define ENRX 5
-#define ENBOFF 6
-#define ENIT 7
-
-#define CANEN2 _SFR_MEM8(0xDC)
-#define ENMOB0 0
-#define ENMOB1 1
-#define ENMOB2 2
-#define ENMOB3 3
-#define ENMOB4 4
-#define ENMOB5 5
-
-#define CANEN1 _SFR_MEM8(0xDD)
-
-#define CANIE2 _SFR_MEM8(0xDE)
-#define IEMOB0 0
-#define IEMOB1 1
-#define IEMOB2 2
-#define IEMOB3 3
-#define IEMOB4 4
-#define IEMOB5 5
-
-#define CANIE1 _SFR_MEM8(0xDF)
-
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define SIT0 0
-#define SIT1 1
-#define SIT2 2
-#define SIT3 3
-#define SIT4 4
-#define SIT5 5
-
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-#define CANBT1 _SFR_MEM8(0xE2)
-#define BRP0 1
-#define BRP1 2
-#define BRP2 3
-#define BRP3 4
-#define BRP4 5
-#define BRP5 6
-
-#define CANBT2 _SFR_MEM8(0xE3)
-#define PRS0 1
-#define PRS1 2
-#define PRS2 3
-#define SJW0 5
-#define SJW1 6
-
-#define CANBT3 _SFR_MEM8(0xE4)
-#define SMP 0
-#define PHS10 1
-#define PHS11 2
-#define PHS12 3
-#define PHS20 4
-#define PHS21 5
-#define PHS22 6
-
-#define CANTCON _SFR_MEM8(0xE5)
-#define TPRSC0 0
-#define TPRSC1 1
-#define TPRSC2 2
-#define TPRSC3 3
-#define TPRSC4 4
-#define TPRSC5 5
-#define TPRSC6 6
-#define TPRSC7 7
-
-#define CANTIM _SFR_MEM16(0xE6)
-
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIM0 0
-#define CANTIM1 1
-#define CANTIM2 2
-#define CANTIM3 3
-#define CANTIM4 4
-#define CANTIM5 5
-#define CANTIM6 6
-#define CANTIM7 7
-
-#define CANTIMH _SFR_MEM8(0xE7)
-#define CANTIM8 0
-#define CANTIM9 1
-#define CANTIM10 2
-#define CANTIM11 3
-#define CANTIM12 4
-#define CANTIM13 5
-#define CANTIM14 6
-#define CANTIM15 7
-
-#define CANTTC _SFR_MEM16(0xE8)
-
-#define CANTTCL _SFR_MEM8(0xE8)
-#define TIMTCC0 0
-#define TIMTCC1 1
-#define TIMTCC2 2
-#define TIMTCC3 3
-#define TIMTCC4 4
-#define TIMTCC5 5
-#define TIMTCC6 6
-#define TIMTCC7 7
-
-#define CANTTCH _SFR_MEM8(0xE9)
-#define TIMTCC8 0
-#define TIMTCC9 1
-#define TIMTCC10 2
-#define TIMTCC11 3
-#define TIMTCC12 4
-#define TIMTCC13 5
-#define TIMTCC14 6
-#define TIMTCC15 7
-
-#define CANTEC _SFR_MEM8(0xEA)
-#define TEC0 0
-#define TEC1 1
-#define TEC2 2
-#define TEC3 3
-#define TEC4 4
-#define TEC5 5
-#define TEC6 6
-#define TEC7 7
-
-#define CANREC _SFR_MEM8(0xEB)
-#define REC0 0
-#define REC1 1
-#define REC2 2
-#define REC3 3
-#define REC4 4
-#define REC5 5
-#define REC6 6
-#define REC7 7
-
-#define CANHPMOB _SFR_MEM8(0xEC)
-#define CGP0 0
-#define CGP1 1
-#define CGP2 2
-#define CGP3 3
-#define HPMOB0 4
-#define HPMOB1 5
-#define HPMOB2 6
-#define HPMOB3 7
-
-#define CANPAGE _SFR_MEM8(0xED)
-#define INDX0 0
-#define INDX1 1
-#define INDX2 2
-#define AINC 3
-#define MOBNB0 4
-#define MOBNB1 5
-#define MOBNB2 6
-#define MOBNB3 7
-
-#define CANSTMOB _SFR_MEM8(0xEE)
-#define AERR 0
-#define FERR 1
-#define CERR 2
-#define SERR 3
-#define BERR 4
-#define RXOK 5
-#define TXOK 6
-#define DLCW 7
-
-#define CANCDMOB _SFR_MEM8(0xEF)
-#define DLC0 0
-#define DLC1 1
-#define DLC2 2
-#define DLC3 3
-#define IDE 4
-#define RPLV 5
-#define CONMOB0 6
-#define CONMOB1 7
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define RB0TAG 0
-#define RB1TAG 1
-#define RTRTAG 2
-#define IDT0 3
-#define IDT1 4
-#define IDT2 5
-#define IDT3 6
-#define IDT4 7
-
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define IDT5 0
-#define IDT6 1
-#define IDT7 2
-#define IDT8 3
-#define IDT9 4
-#define IDT10 5
-#define IDT11 6
-#define IDT12 7
-
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define IDT13 0
-#define IDT14 1
-#define IDT15 2
-#define IDT16 3
-#define IDT17 4
-#define IDT18 5
-#define IDT19 6
-#define IDT20 7
-
-#define CANIDT1 _SFR_MEM8(0xF3)
-#define IDT21 0
-#define IDT22 1
-#define IDT23 2
-#define IDT24 3
-#define IDT25 4
-#define IDT26 5
-#define IDT27 6
-#define IDT28 7
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define IDEMSK 0
-#define RTRMSK 2
-#define IDMSK0 3
-#define IDMSK1 4
-#define IDMSK2 5
-#define IDMSK3 6
-#define IDMSK4 7
-
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define IDMSK5 0
-#define IDMSK6 1
-#define IDMSK7 2
-#define IDMSK8 3
-#define IDMSK9 4
-#define IDMSK10 5
-#define IDMSK11 6
-#define IDMSK12 7
-
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define IDMSK13 0
-#define IDMSK14 1
-#define IDMSK15 2
-#define IDMSK16 3
-#define IDMSK17 4
-#define IDMSK18 5
-#define IDMSK19 6
-#define IDMSK20 7
-
-#define CANIDM1 _SFR_MEM8(0xF7)
-#define IDMSK21 0
-#define IDMSK22 1
-#define IDMSK23 2
-#define IDMSK24 3
-#define IDMSK25 4
-#define IDMSK26 5
-#define IDMSK27 6
-#define IDMSK28 7
-
-#define CANSTM _SFR_MEM16(0xF8)
-
-#define CANSTML _SFR_MEM8(0xF8)
-#define TIMSTM0 0
-#define TIMSTM1 1
-#define TIMSTM2 2
-#define TIMSTM3 3
-#define TIMSTM4 4
-#define TIMSTM5 5
-#define TIMSTM6 6
-#define TIMSTM7 7
-
-#define CANSTMH _SFR_MEM8(0xF9)
-#define TIMSTM8 0
-#define TIMSTM9 1
-#define TIMSTM10 2
-#define TIMSTM11 3
-#define TIMSTM12 4
-#define TIMSTM13 5
-#define TIMSTM14 6
-#define TIMSTM15 7
-
-#define CANMSG _SFR_MEM8(0xFA)
-#define MSG0 0
-#define MSG1 1
-#define MSG2 2
-#define MSG3 3
-#define MSG4 4
-#define MSG5 5
-#define MSG6 6
-#define MSG7 7
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-#define ANACOMP0_vect_num  1
-#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
-#define ANACOMP1_vect_num  2
-#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
-#define ANACOMP2_vect_num  3
-#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
-#define ANACOMP3_vect_num  4
-#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
-#define PSC_FAULT_vect_num  5
-#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
-#define PSC_EC_vect_num  6
-#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
-#define INT0_vect_num  7
-#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
-#define INT1_vect_num  8
-#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
-#define INT2_vect_num  9
-#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
-#define INT3_vect_num  10
-#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  12
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect      _VECTOR(12)  
-#define TIMER1_COMPB_vect_num  13
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect      _VECTOR(13)  
-#define TIMER1_OVF_vect_num  14
-#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  15
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect      _VECTOR(15)  
-#define TIMER0_COMPB_vect_num  16
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect      _VECTOR(16)  
-#define TIMER0_OVF_vect_num  17
-#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define CAN_INT_vect_num  18
-#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
-#define CAN_TOVF_vect_num  19
-#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
-#define LIN_TC_vect_num  20
-#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  21
-#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
-#define PCINT0_vect_num  22
-#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  23
-#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  24
-#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect_num  25
-#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
-#define SPI_STC_vect_num  26
-#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  27
-#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
-#define WDT_vect_num  28
-#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
-#define EE_READY_vect_num  29
-#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
-#define SPM_READY_vect_num  30
-#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (8)
-#define FLASHEND     (0xFFFF)
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & \
-                       FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-/* EEPROM memory is preserved through chip erase */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-/* Enable Serial programming and Data Downloading */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-/* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  
-/* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  
-/* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  
-#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
-#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
-#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x84
-/** @} */
-
-#endif /* _AVR_ATmega64M1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom8.h b/cpukit/score/cpu/avr/avr/iom8.h
deleted file mode 100644
index c918b43dfb..0000000000
--- a/cpukit/score/cpu/avr/avr/iom8.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega8
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom8.h - definitions for ATmega8 */
-
-#ifndef _AVR_IOM8_H_
-#define _AVR_IOM8_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom8.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom8 ATmega8 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-#define TWBR	_SFR_IO8(0x00)
-#define TWSR	_SFR_IO8(0x01)
-#define TWAR	_SFR_IO8(0x02)
-#define TWDR	_SFR_IO8(0x03)
-
-/* ADC */
-#define ADCW	_SFR_IO16(0x04)
-#ifndef __ASSEMBLER__
-#define ADC	_SFR_IO16(0x04)
-#endif
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-#define ADCSR	_SFR_IO8(0x06)
-#define ADCSRA	_SFR_IO8(0x06)  /* Changed in 2486H-AVR-09/02 */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* analog comparator */
-#define ACSR	_SFR_IO8(0x08)
-
-/* USART */
-#define UBRRL	_SFR_IO8(0x09)
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Port C */
-#define PINC	_SFR_IO8(0x13)
-#define DDRC	_SFR_IO8(0x14)
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UCSRC	_SFR_IO8(0x20)
-#define UBRRH	_SFR_IO8(0x20)
-
-#define WDTCR	_SFR_IO8(0x21)
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer 2 */
-#define OCR2	_SFR_IO8(0x23)
-#define TCNT2	_SFR_IO8(0x24)
-#define TCCR2	_SFR_IO8(0x25)
-
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-#define SFIOR	_SFR_IO8(0x30)
-
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer 0 */
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUCSR	_SFR_IO8(0x34)
-#define MCUSR   _SFR_IO8(0x34)  /* Defined as an alias for MCUCSR. */
-
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TWCR	_SFR_IO8(0x36)
-
-#define SPMCR	_SFR_IO8(0x37)
-
-#define TIFR	_SFR_IO8(0x38)
-#define TIMSK	_SFR_IO8(0x39)
-
-#define GIFR	_SFR_IO8(0x3A)
-#define GIMSK	_SFR_IO8(0x3B)
-#define GICR	_SFR_IO8(0x3B)   /* Changed in 2486H-AVR-09/02 */
-
-/* 0x3C reserved (OCR0?) */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* USART, Rx Complete */
-#define USART_RXC_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* USART, Tx Complete */
-#define USART_TXC_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(18)
-#define SIG_SPM_READY			_VECTOR(18)
-
-#define _VECTORS_SIZE 38
-
-/* Bit numbers */
-
-/* GIMSK / GICR */
-#define INT1	7
-#define INT0	6
-#define IVSEL	1
-#define IVCE	0
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-
-/* TIMSK */
-#define OCIE2	7
-#define TOIE2	6
-#define TICIE1	5
-#define OCIE1A	4
-#define OCIE1B	3
-#define TOIE1	2
-/* bit 1 reserved (OCIE0?) */
-#define TOIE0	0
-
-/* TIFR */
-#define OCF2	7
-#define TOV2	6
-#define ICF1	5
-#define OCF1A	4
-#define OCF1B	3
-#define TOV1	2
-/* bit 1 reserved (OCF0?) */
-#define TOV0	0
-
-/* SPMCR */
-#define SPMIE	7
-#define RWWSB	6
-/* bit 5 reserved */
-#define RWWSRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* TWCR */
-#define TWINT	7
-#define TWEA	6
-#define TWSTA	5
-#define TWSTO	4
-#define TWWC	3
-#define TWEN	2
-/* bit 1 reserved (TWI_TST?) */
-#define TWIE	0
-
-/* TWAR */
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE	0
-
-/* TWSR */
-#define TWS7	7
-#define TWS6	6
-#define TWS5	5
-#define TWS4	4
-#define TWS3	3
-/* bit 2 reserved */
-#define TWPS1	1
-#define TWPS0	0
-
-/* MCUCR */
-#define SE	7
-#define SM2	6
-#define SM1	5
-#define SM0	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* MCUCSR */
-/* bits 7-4 reserved */
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-/* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
-   to be fast enough even without feeding it more power.
-*/
-
-/* SFIOR */
-/* bits 7-5 reserved */
-#define ACME	3
-#define PUD	2
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-/* bits 7-3 reserved */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define WGM20	6
-#define COM21	5
-#define COM20	4
-#define WGM21	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-/* bits 7-4 reserved */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define WGM11	1
-#define WGM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bit 5 reserved */
-#define WGM13	4
-#define WGM12	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDCE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* UBRRH */
-#define URSEL	7
-
-/* UCSRC */
-#define URSEL	7
-#define UMSEL	6
-#define UPM1	5
-#define UPM0	4
-#define USBS	3
-#define UCSZ1	2
-#define UCSZ0	1
-#define UCPOL	0
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTC */
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSRA */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-#define PE	2
-#define U2X	1
-#define MPCM	0
-
-/* UCSRB */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define UCSZ2	2
-#define RXB8	1
-#define TXB8	0
-
-/* ACSR */
-#define ACD	7
-#define ACBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* ADCSR / ADCSRA */
-#define ADEN	7
-#define ADSC	6
-#define ADFR	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-/* ADMUX */
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-/* bit 4 reserved */
-#define MUX3	3
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND		 0x45F
-#define XRAMEND		 RAMEND
-#define E2END		 0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND	 0x1FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_WDTON       (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x07
-
-/** @} */
-
-#endif /* _AVR_IOM8_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom8515.h b/cpukit/score/cpu/avr/avr/iom8515.h
deleted file mode 100644
index 7576f8df4e..0000000000
--- a/cpukit/score/cpu/avr/avr/iom8515.h
+++ /dev/null
@@ -1,647 +0,0 @@
-/**
- * @file avr/iom8515.h
- *
- * @brief Definitions for ATmega8515
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Steinar Haugen
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM8515_H_
-#define _AVR_IOM8515_H_ 1
-
-/**
- *  @defgroup Avr_iom8515 ATmega8515 Definitons
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom8515.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Oscillator Calibration Register */
-#define OSCCAL  _SFR_IO8(0x04)
-
-/* Input Pins, Port E */
-#define PINE    _SFR_IO8(0x05)
-
-/* Data Direction Register, Port E */
-#define DDRE    _SFR_IO8(0x06)
-
-/* Data Register, Port E */
-#define PORTE   _SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR    _SFR_IO8(0x08)
-
-/* USART Baud Rate Register */
-#define UBRRL   _SFR_IO8(0x09)
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_IO8(0x0A)
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_IO8(0x0B)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR    _SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND    _SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD    _SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD   _SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC   _SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB    _SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB    _SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB   _SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA    _SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA    _SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA   _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* USART Baud Rate Register HI         */
-/* USART Control and Status Register C */
-#define UBRRH   _SFR_IO8(0x20)
-#define UCSRC   UBRRH
-
-/* Watchdog Timer Control Register */
-#define WDTCR   _SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1    _SFR_IO16(0x24)
-#define ICR1L   _SFR_IO8(0x24)
-#define ICR1H   _SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B   _SFR_IO16(0x28)
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A   _SFR_IO16(0x2A)
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1   _SFR_IO16(0x2C)
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B  _SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A  _SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR   _SFR_IO8(0x30)
-
-/* Timer/Counter 0 Output Compare Register */
-#define OCR0    _SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0   _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0   _SFR_IO8(0x33)
-
-/* MCU Control and Status Register */
-#define MCUCSR  _SFR_IO8(0x34)
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-
-/* Extended MCU Control Register */
-#define EMCUCR  _SFR_IO8(0x36)
-
-/* Store Program Memory Control Register */
-#define SPMCR   _SFR_IO8(0x37)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR    _SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK   _SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR    _SFR_IO8(0x3A)
-
-/* General Interrupt Control Register */
-#define GICR    _SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Compare MatchB */
-#define TIMER1_COMPB_vect		_VECTOR(5)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW1			_VECTOR(6)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(7)
-#define SIG_OVERFLOW0			_VECTOR(7)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(8)
-#define SIG_SPI				_VECTOR(8)
-
-/* UART, Rx Complete */
-#define USART_RX_vect                   _VECTOR(9)
-#define UART_RX_vect                    _VECTOR(9) /* For compatability only */
-#define SIG_UART_RECV                   _VECTOR(9) /* For compatability only */
-
-/* UART Data Register Empty */
-#define USART_UDRE_vect                 _VECTOR(10)
-#define UART_UDRE_vect                  _VECTOR(10) /* For compatability only */
-#define SIG_UART_DATA                   _VECTOR(10) /* For compatability only */
-
-/* UART, Tx Complete */
-#define USART_TX_vect                   _VECTOR(11)
-#define UART_TX_vect                    _VECTOR(11) /* For compatability only */
-#define SIG_UART_TRANS                  _VECTOR(11) /* For compatability only */
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(13)
-#define SIG_INTERRUPT2			_VECTOR(13)
-
-/* Timer 0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(16)
-#define SIG_SPM_READY			_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* General Interrupt Control Register */
-#define    INT1         7
-#define    INT0         6
-#define    INT2         5
-#define    IVSEL        1
-#define    IVCE         0
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-#define    INTF2        5
-
-/* Timer/Counter Interrupt MaSK Register */
-#define    TOIE1        7
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TICIE1       3
-#define    TOIE0        1
-#define    OCIE0        0
-
-/* Timer/Counter Interrupt Flag Register */
-#define    TOV1         7
-#define    OCF1A        6
-#define    OCF1B        5
-#define    ICF1         3
-#define    TOV0         1
-#define    OCF0         0
-
-/* Store Program Memory Control Register */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-
-/* Extended MCU Control Register */
-#define    SM0          7
-#define    SRL2         6
-#define    SRL1         5
-#define    SRL0         4
-#define    SRW01        3
-#define    SRW00        2
-#define    SRW11        1
-#define    ISC2         0
-
-/* MCU Control Register */
-#define    SRE          7
-#define    SRW10        6
-#define    SE           5
-#define    SM1          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* MCU Control and Status Register */
-#define    SM2          5
-#define    WDRF         3
-#define    BORF         2
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter 0 Control Register */
-#define    FOC0         7
-#define    WGM00        6
-#define    COM01        5
-#define    COM00        4
-#define    WGM01        3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Special Function IO Register */
-#define    XMBK         6
-#define    XMM2         5
-#define    XMM1         4
-#define    XMM0         3
-#define    PUD          2
-#define    PSR10        0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    FOC1A        3
-#define    FOC1B        2
-#define    WGM11        1
-#define    WGM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* USART Control and Status Register C */
-#define    URSEL        7
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* USART Control and Status Register A */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    PE           2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART Control and Status Register B */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ2        2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* Data Register, Port E */
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-
-/* Data Direction Register, Port E */
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Input Pins, Port E */
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x25F    /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_WDTON       (unsigned char)~_BV(6)
-#define FUSE_S8515C      (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x06
-
-/**@}*/
-#endif /* _AVR_IOM8515_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom8535.h b/cpukit/score/cpu/avr/avr/iom8535.h
deleted file mode 100644
index 061a0fce6b..0000000000
--- a/cpukit/score/cpu/avr/avr/iom8535.h
+++ /dev/null
@@ -1,737 +0,0 @@
-/* Copyright (c) 2002, Steinar Haugen
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom8535.h - definitions for ATmega8535 */
-
-#ifndef _AVR_IOM8535_H_
-#define _AVR_IOM8535_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom8535.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-#define TWBR    _SFR_IO8(0x00)
-#define TWSR    _SFR_IO8(0x01)
-#define TWAR    _SFR_IO8(0x02)
-#define TWDR    _SFR_IO8(0x03)
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-#define ADCW    _SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSRA  _SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX   _SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR    _SFR_IO8(0x08)
-
-/* USART Baud Rate Register */
-#define UBRRL   _SFR_IO8(0x09)
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_IO8(0x0A)
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_IO8(0x0B)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR    _SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND    _SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD    _SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD   _SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC   _SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB    _SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB    _SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB   _SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA    _SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA    _SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA   _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* USART Baud Rate Register HI         */
-/* USART Control and Status Register C */
-#define UBRRH   _SFR_IO8(0x20)
-#define UCSRC   UBRRH
-
-/* Watchdog Timer Control Register */
-#define WDTCR   _SFR_IO8(0x21)
-
-/* Asynchronous mode Status Register */
-#define ASSR    _SFR_IO8(0x22)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2    _SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2   _SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control Register */
-#define TCCR2   _SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1    _SFR_IO16(0x26)
-#define ICR1L   _SFR_IO8(0x26)
-#define ICR1H   _SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B   _SFR_IO16(0x28)
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A   _SFR_IO16(0x2A)
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1   _SFR_IO16(0x2C)
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B  _SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A  _SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR   _SFR_IO8(0x30)
-
-/* Oscillator Calibration Register */
-#define OSCCAL  _SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0   _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0   _SFR_IO8(0x33)
-
-/* MCU Control and Status Register */
-#define MCUCSR  _SFR_IO8(0x34)
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-
-/* TWI Control Register */
-#define TWCR    _SFR_IO8(0x36)
-
-/* Store Program Memory Control Register */
-#define SPMCR   _SFR_IO8(0x37)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR    _SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK   _SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR    _SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GICR    _SFR_IO8(0x3B)
-
-/* Timer/Counter 0 Output Compare Register */
-#define OCR0    _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* USART, RX Complete */
-#define USART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* USART, TX Complete */
-#define USART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* Two-wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(18)
-#define SIG_INTERRUPT2			_VECTOR(18)
-
-/* TimerCounter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(19)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(19)
-
-/* Store Program Memory Read */
-#define SPM_RDY_vect			_VECTOR(20)
-#define SIG_SPM_READY			_VECTOR(20)
-
-#define _VECTORS_SIZE 42
-/** @} */
-/*
- * The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt Control Register */
-#define    INT1         7
-#define    INT0         6
-#define    INT2         5
-#define    IVSEL        1
-#define    IVCE         0
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-#define    INTF2        5
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* Store Program Memory Control Register */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-
-/* TWI Control Register */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-
-/* MCU Control Register */
-#define    SM2          7
-#define    SE           6
-#define    SM1          5
-#define    SM0          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* MCU Control and Status Register */
-#define    ISC2         6
-#define    WDRF         3
-#define    BORF         2
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter 0 Control Register */
-#define    FOC0         7
-#define    WGM00        6
-#define    COM01        5
-#define    COM00        4
-#define    WGM01        3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* 
- * The ADHSM bit has been removed from all documentation, 
- * as being not needed at all since the comparator has proven 
- * to be fast enough even without feeding it more power.
- */
-
-/* Special Function IO Register */
-#define    ADTS2        7
-#define    ADTS1        6
-#define    ADTS0        5
-#define    ACME         3
-#define    PUD          2
-#define    PSR2         1
-#define    PSR10        0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    FOC1A        3
-#define    FOC1B        2
-#define    WGM11        1
-#define    WGM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control Register */
-#define    FOC2         7
-#define    WGM20        6
-#define    COM21        5
-#define    COM20        4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Asynchronous mode Status Register */
-#define    AS2          3
-#define    TCN2UB       2
-#define    OCR2UB       1
-#define    TCR2UB       0
-
-/* Watchdog Timer Control Register */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* USART Control and Status Register C */
-#define    URSEL        7
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* USART Control and Status Register A */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    PE           2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART Control and Status Register B */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ2        2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Multiplexer Selection Register */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* ADC Control and Status Register */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADATE        5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* TWI (Slave) Address Register */
-#define    TWGCE        0
-
-/* TWI Status Register */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE 64
-#define RAMEND       0x25F    /* Last On-Chip SRAM Location */
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_SUT1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_WDTON       (unsigned char)~_BV(6)
-#define FUSE_S8535C      (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x08
-/** @} */
-
-#endif /* _AVR_IOM8535_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom88.h b/cpukit/score/cpu/avr/avr/iom88.h
deleted file mode 100644
index f3e5e64c45..0000000000
--- a/cpukit/score/cpu/avr/avr/iom88.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega88
- */
-
-/* Copyright (c) 2004, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-#ifndef _AVR_IOM88_H_
-#define _AVR_IOM88_H_ 1
-
-/**
- * @defgroup AvrDef_iom88 ATmega88 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iomx8.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x4FF
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0A
-
-/** @} */
-
-#endif /* _AVR_IOM88_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom88p.h b/cpukit/score/cpu/avr/avr/iom88p.h
deleted file mode 100644
index 0c98183d58..0000000000
--- a/cpukit/score/cpu/avr/avr/iom88p.h
+++ /dev/null
@@ -1,884 +0,0 @@
-/**
- * @file avr/iom88p.h
- *
- * @brief Definitions for ATmega88P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom88p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM88P_H_
-#define _AVR_IOM88P_H_ 1
-
-/**
- *  @defgroup Avr_iom88p ATmega88P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define EEPROM_REG_LOCATIONS 1F2021
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCPHA0 1
-#define UCSZ01 2
-#define UDORD0 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect         _VECTOR(1)   /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)   /* External Interrupt Request 1 */
-#define PCINT0_vect       _VECTOR(3)   /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(4)   /* Pin Change Interrupt Request 0 */
-#define PCINT2_vect       _VECTOR(5)   /* Pin Change Interrupt Request 1 */
-#define WDT_vect          _VECTOR(6)   /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(7)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(8)   /* Timer/Counter2 Compare Match A */
-#define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(16)  /* Timer/Couner0 Overflow */
-#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect     _VECTOR(18)  /* USART Rx Complete */
-#define USART_UDRE_vect   _VECTOR(19)  /* USART, Data Register Empty */
-#define USART_TX_vect     _VECTOR(20)  /* USART Tx Complete */
-#define ADC_vect          _VECTOR(21)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(22)  /* EEPROM Ready */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define TWI_vect          _VECTOR(24)  /* Two-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(25)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE (26 * 2)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x4FF     /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0F
-
-/**@}*/
-#endif  /* _AVR_IOM88P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom88pa.h b/cpukit/score/cpu/avr/avr/iom88pa.h
deleted file mode 100644
index d5c2b21767..0000000000
--- a/cpukit/score/cpu/avr/avr/iom88pa.h
+++ /dev/null
@@ -1,1166 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom88pa.h - definitions for ATmega88PA */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom88pa.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega88PA_H_
-#define _AVR_ATmega88PA_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A_0 0
-#define OCR2A_1 1
-#define OCR2A_2 2
-#define OCR2A_3 3
-#define OCR2A_4 4
-#define OCR2A_5 5
-#define OCR2A_6 6
-#define OCR2A_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B_0 0
-#define OCR2B_1 1
-#define OCR2B_2 2
-#define OCR2B_3 3
-#define OCR2B_4 4
-#define OCR2B_5 5
-#define OCR2B_6 6
-#define OCR2B_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define _UBRR0 0
-#define _UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define PCINT0_vect_num  3
-#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  4
-#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT2_vect_num  5
-#define PCINT2_vect      _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define WDT_vect_num  6
-#define WDT_vect      _VECTOR(6)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  7
-#define TIMER2_COMPA_vect      _VECTOR(7)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  8
-#define TIMER2_COMPB_vect      _VECTOR(8)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_OVF_vect_num  9
-#define TIMER2_OVF_vect      _VECTOR(9)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  10
-#define TIMER1_CAPT_vect      _VECTOR(10)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  11
-#define TIMER1_COMPA_vect      _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  12
-#define TIMER1_COMPB_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  13
-#define TIMER1_OVF_vect      _VECTOR(13)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  14
-#define TIMER0_COMPA_vect      _VECTOR(14)  /* TimerCounter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  15
-#define TIMER0_COMPB_vect      _VECTOR(15)  /* TimerCounter0 Compare Match B */
-#define TIMER0_OVF_vect_num  16
-#define TIMER0_OVF_vect      _VECTOR(16)  /* Timer/Couner0 Overflow */
-#define SPI_STC_vect_num  17
-#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect_num  18
-#define USART_RX_vect      _VECTOR(18)  /* USART Rx Complete */
-#define USART_UDRE_vect_num  19
-#define USART_UDRE_vect      _VECTOR(19)  /* USART, Data Register Empty */
-#define USART_TX_vect_num  20
-#define USART_TX_vect      _VECTOR(20)  /* USART Tx Complete */
-#define ADC_vect_num  21
-#define ADC_vect      _VECTOR(21)  /* ADC Conversion Complete */
-#define EE_READY_vect_num  22
-#define EE_READY_vect      _VECTOR(22)  /* EEPROM Ready */
-#define ANALOG_COMP_vect_num  23
-#define ANALOG_COMP_vect      _VECTOR(23)  /* Analog Comparator */
-#define TWI_vect_num  24
-#define TWI_vect      _VECTOR(24)  /* Two-wire Serial Interface */
-#define SPM_Ready_vect_num  25
-#define SPM_Ready_vect      _VECTOR(25)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (26 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (1024)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select reset vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select boot size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select boot size */
-#define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0F
-
-
-/* Device Pin Definitions */
-#define PCINT19_DDR   DDRD
-#define PCINT19_PORT  PORTD
-#define PCINT19_PIN   PIND
-#define PCINT19_BIT   3
-
-#define OC2B_DDR   DDRD
-#define OC2B_PORT  PORTD
-#define OC2B_PIN   PIND
-#define OC2B_BIT   3
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define XCK_DDR   DDRD
-#define XCK_PORT  PORTD
-#define XCK_PIN   PIND
-#define XCK_BIT   4
-
-#define T0_DDR   DDRD
-#define T0_PORT  PORTD
-#define T0_PIN   PIND
-#define T0_BIT   4
-
-#define PCINT20_DDR   DDRD
-#define PCINT20_PORT  PORTD
-#define PCINT20_PIN   PIND
-#define PCINT20_BIT   4
-
-#define PCINT6_DDR   DDRB
-#define PCINT6_PORT  PORTB
-#define PCINT6_PIN   PINB
-#define PCINT6_BIT   6
-
-#define PCINT7_DDR   DDRB
-#define PCINT7_PORT  PORTB
-#define PCINT7_PIN   PINB
-#define PCINT7_BIT   7
-
-#define T1_DDR   DDRD
-#define T1_PORT  PORTD
-#define T1_PIN   PIND
-#define T1_BIT   5
-
-#define OC0B_DDR   DDRD
-#define OC0B_PORT  PORTD
-#define OC0B_PIN   PIND
-#define OC0B_BIT   5
-
-#define PCINT21_DDR   DDRD
-#define PCINT21_PORT  PORTD
-#define PCINT21_PIN   PIND
-#define PCINT21_BIT   5
-
-#define AIN0_DDR   DDRD
-#define AIN0_PORT  PORTD
-#define AIN0_PIN   PIND
-#define AIN0_BIT   6
-
-#define OC0A_DDR   DDRD
-#define OC0A_PORT  PORTD
-#define OC0A_PIN   PIND
-#define OC0A_BIT   6
-
-#define PCINT22_DDR   DDRD
-#define PCINT22_PORT  PORTD
-#define PCINT22_PIN   PIND
-#define PCINT22_BIT   6
-
-#define AIN1_DDR   DDRD
-#define AIN1_PORT  PORTD
-#define AIN1_PIN   PIND
-#define AIN1_BIT   7
-
-#define PCINT23_DDR   DDRD
-#define PCINT23_PORT  PORTD
-#define PCINT23_PIN   PIND
-#define PCINT23_BIT   7
-
-#define ICP1_DDR   DDRB
-#define ICP1_PORT  PORTB
-#define ICP1_PIN   PINB
-#define ICP1_BIT   0
-
-#define CLKO_DDR   DDRB
-#define CLKO_PORT  PORTB
-#define CLKO_PIN   PINB
-#define CLKO_BIT   0
-
-#define PCINT0_DDR   DDRB
-#define PCINT0_PORT  PORTB
-#define PCINT0_PIN   PINB
-#define PCINT0_BIT   0
-
-#define OC1A_DDR   DDRB
-#define OC1A_PORT  PORTB
-#define OC1A_PIN   PINB
-#define OC1A_BIT   1
-
-#define PCINT1_DDR   DDRB
-#define PCINT1_PORT  PORTB
-#define PCINT1_PIN   PINB
-#define PCINT1_BIT   1
-
-#define SS_DDR   DDRB
-#define SS_PORT  PORTB
-#define SS_PIN   PINB
-#define SS_BIT   2
-
-#define OC1B_DDR   DDRB
-#define OC1B_PORT  PORTB
-#define OC1B_PIN   PINB
-#define OC1B_BIT   2
-
-#define PCINT2_DDR   DDRB
-#define PCINT2_PORT  PORTB
-#define PCINT2_PIN   PINB
-#define PCINT2_BIT   2
-
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   3
-
-#define OC2A_DDR   DDRB
-#define OC2A_PORT  PORTB
-#define OC2A_PIN   PINB
-#define OC2A_BIT   3
-
-#define PCINT3_DDR   DDRB
-#define PCINT3_PORT  PORTB
-#define PCINT3_PIN   PINB
-#define PCINT3_BIT   3
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   4
-
-#define PCINT4_DDR   DDRB
-#define PCINT4_PORT  PORTB
-#define PCINT4_PIN   PINB
-#define PCINT4_BIT   4
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   5
-
-#define PCINT5_DDR   DDRB
-#define PCINT5_PORT  PORTB
-#define PCINT5_PIN   PINB
-#define PCINT5_BIT   5
-
-#define ADC6_DDR   DDRADC
-#define ADC6_PORT  PORTADC
-#define ADC6_PIN   PINADC
-#define ADC6_BIT   ADC6
-
-#define ADC7_DDR   DDRADC
-#define ADC7_PORT  PORTADC
-#define ADC7_PIN   PINADC
-#define ADC7_BIT   ADC7
-
-#define ADC0_DDR   DDRC
-#define ADC0_PORT  PORTC
-#define ADC0_PIN   PINC
-#define ADC0_BIT   0
-
-#define PCINT8_DDR   DDRC
-#define PCINT8_PORT  PORTC
-#define PCINT8_PIN   PINC
-#define PCINT8_BIT   0
-
-#define ADC1_DDR   DDRC
-#define ADC1_PORT  PORTC
-#define ADC1_PIN   PINC
-#define ADC1_BIT   1
-
-#define PCINT9_DDR   DDRC
-#define PCINT9_PORT  PORTC
-#define PCINT9_PIN   PINC
-#define PCINT9_BIT   1
-
-#define ADC2_DDR   DDRC
-#define ADC2_PORT  PORTC
-#define ADC2_PIN   PINC
-#define ADC2_BIT   2
-
-#define PCINT10_DDR   DDRC
-#define PCINT10_PORT  PORTC
-#define PCINT10_PIN   PINC
-#define PCINT10_BIT   2
-
-#define ADC3_DDR   DDRC
-#define ADC3_PORT  PORTC
-#define ADC3_PIN   PINC
-#define ADC3_BIT   3
-
-#define PCINT11_DDR   DDRC
-#define PCINT11_PORT  PORTC
-#define PCINT11_PIN   PINC
-#define PCINT11_BIT   3
-
-#define ADC4_DDR   DDRC
-#define ADC4_PORT  PORTC
-#define ADC4_PIN   PINC
-#define ADC4_BIT   4
-
-#define SDA_DDR   DDRC
-#define SDA_PORT  PORTC
-#define SDA_PIN   PINC
-#define SDA_BIT   4
-
-#define PCINT12_DDR   DDRC
-#define PCINT12_PORT  PORTC
-#define PCINT12_PIN   PINC
-#define PCINT12_BIT   4
-
-#define ADC5_DDR   DDRC
-#define ADC5_PORT  PORTC
-#define ADC5_PIN   PINC
-#define ADC5_BIT   5
-
-#define SCL_DDR   DDRC
-#define SCL_PORT  PORTC
-#define SCL_PIN   PINC
-#define SCL_BIT   5
-
-#define PCINT13_DDR   DDRC
-#define PCINT13_PORT  PORTC
-#define PCINT13_PIN   PINC
-#define PCINT13_BIT   5
-
-#define PCINT14_DDR   DDRC
-#define PCINT14_PORT  PORTC
-#define PCINT14_PIN   PINC
-#define PCINT14_BIT   6
-
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define PCINT16_DDR   DDRD
-#define PCINT16_PORT  PORTD
-#define PCINT16_PIN   PIND
-#define PCINT16_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define PCINT17_DDR   DDRD
-#define PCINT17_PORT  PORTD
-#define PCINT17_PIN   PIND
-#define PCINT17_BIT   1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define PCINT18_DDR   DDRD
-#define PCINT18_PORT  PORTD
-#define PCINT18_PIN   PIND
-#define PCINT18_BIT   2
-
-#endif /* _AVR_ATmega88PA_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom8hva.h b/cpukit/score/cpu/avr/avr/iom8hva.h
deleted file mode 100644
index fc36eabb25..0000000000
--- a/cpukit/score/cpu/avr/avr/iom8hva.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega8HVA
- */
-
-/* Copyright (c) 2007, Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iom8hva.h - definitions for ATmega8HVA.  */
-
-#ifndef _AVR_IOM8HVA_H_
-#define _AVR_IOM8HVA_H_ 1
-
-#include <avr/iomxxhva.h>
-
-/**
- * @defgroup AvrDef_iom8hva ATmega8HVA Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND      0x2FF
-#define XRAMEND     RAMEND
-#define E2END       0xFF
-#define E2PAGESIZE  4
-#define FLASHEND    0x1FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SUT0        (unsigned char)~_BV(0)
-#define FUSE_SUT1        (unsigned char)~_BV(1)
-#define FUSE_SUT2        (unsigned char)~_BV(2)
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(3)
-#define FUSE_DWEN        (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_EESAVE      (unsigned char)~_BV(6)
-#define FUSE_WDTON       (unsigned char)~_BV(7)
-#define FUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-/** @} */
-
-#endif /* _AVR_IOM8HVA_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom8u2.h b/cpukit/score/cpu/avr/avr/iom8u2.h
deleted file mode 100644
index c3ee0ba211..0000000000
--- a/cpukit/score/cpu/avr/avr/iom8u2.h
+++ /dev/null
@@ -1,983 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega8U2
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom8u2.h - definitions for ATmega8U2 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom8u2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATmega8U2_H_
-#define _AVR_ATmega8U2_H_ 1
-
-/**
- * @defgroup AvrDef_iom8u2 ATmega8U2 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define OCF1C 3
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-#define INTF4 4
-#define INTF5 5
-#define INTF6 6
-#define INTF7 7
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-#define INT4 4
-#define INT5 5
-#define INT6 6
-#define INT7 7
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLP0 2
-#define PLLP1 3
-#define PLLP2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define DWDR _SFR_IO8(0x31)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define USBRF 5
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define EIND _SFR_IO8(0x3C)
-#define EIND0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define WDTCKD _SFR_MEM8(0x62)
-#define WCLKD0 0
-#define WCLKD1 1
-#define WDEWIE 2
-#define WDEWIF 3
-
-#define REGCR _SFR_MEM8(0x63)
-#define REGDIS 0
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSART1 0
-#define PRUSB 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define EICRB _SFR_MEM8(0x6A)
-#define ISC40 0
-#define ISC41 1
-#define ISC50 2
-#define ISC51 3
-#define ISC60 4
-#define ISC61 5
-#define ISC70 6
-#define ISC71 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define OCIE1C 3
-#define ICIE1 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1C0 2
-#define COM1C1 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1C _SFR_MEM16(0x8C)
-
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CL0 0
-#define OCR1CL1 1
-#define OCR1CL2 2
-#define OCR1CL3 3
-#define OCR1CL4 4
-#define OCR1CL5 5
-#define OCR1CL6 6
-#define OCR1CL7 7
-
-#define OCR1CH _SFR_MEM8(0x8D)
-#define OCR1CH0 0
-#define OCR1CH1 1
-#define OCR1CH2 2
-#define OCR1CH3 3
-#define OCR1CH4 4
-#define OCR1CH5 5
-#define OCR1CH6 6
-#define OCR1CH7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UCSR1D _SFR_MEM8(0xCB)
-#define RTSEN 0
-#define CTSEN 1
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-#define CLKSEL0 _SFR_MEM8(0xD0)
-#define CLKS 0
-#define EXTE 2
-#define RCE 3
-#define EXSUT0 4
-#define EXSUT1 5
-#define RCSUT0 6
-#define RCSUT1 7
-
-#define CLKSEL1 _SFR_MEM8(0xD1)
-#define EXCKSEL0 0
-#define EXCKSEL1 1
-#define EXCKSEL2 2
-#define EXCKSEL3 3
-#define RCCKSEL0 4
-#define RCCKSEL1 5
-#define RCCKSEL2 6
-#define RCCKSEL3 7
-
-#define CLKSTA _SFR_MEM8(0xD2)
-#define EXTON 0
-#define RCON 1
-
-#define USBCON _SFR_MEM8(0xD8)
-#define FRZCLK 5
-#define USBE 7
-
-#define UDCON _SFR_MEM8(0xE0)
-#define DETACH 0
-#define RMWKUP 1
-#define RSTCPU 2
-
-#define UDINT _SFR_MEM8(0xE1)
-#define SUSPI 0
-#define SOFI 2
-#define EORSTI 3
-#define WAKEUPI 4
-#define EORSMI 5
-#define UPRSMI 6
-
-#define UDIEN _SFR_MEM8(0xE2)
-#define SUSPE 0
-#define SOFE 2
-#define EORSTE 3
-#define WAKEUPE 4
-#define EORSME 5
-#define UPRSME 6
-
-#define UDADDR _SFR_MEM8(0xE3)
-#define UADD0 0
-#define UADD1 1
-#define UADD2 2
-#define UADD3 3
-#define UADD4 4
-#define UADD5 5
-#define UADD6 6
-#define ADDEN 7
-
-#define UDFNUM _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UDFNUMH _SFR_MEM8(0xE5)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UDMFN _SFR_MEM8(0xE6)
-#define FNCERR 4
-
-#define UEINTX _SFR_MEM8(0xE8)
-#define TXINI 0
-#define STALLEDI 1
-#define RXOUTI 2
-#define RXSTPI 3
-#define NAKOUTI 4
-#define RWAL 5
-#define NAKINI 6
-#define FIFOCON 7
-
-#define UENUM _SFR_MEM8(0xE9)
-#define EPNUM0 0
-#define EPNUM1 1
-#define EPNUM2 2
-
-#define UERST _SFR_MEM8(0xEA)
-#define EPRST0 0
-#define EPRST1 1
-#define EPRST2 2
-#define EPRST3 3
-#define EPRST4 4
-
-#define UECONX _SFR_MEM8(0xEB)
-#define EPEN 0
-#define RSTDT 3
-#define STALLRQC 4
-#define STALLRQ 5
-
-#define UECFG0X _SFR_MEM8(0xEC)
-#define EPDIR 0
-#define EPTYPE0 6
-#define EPTYPE1 7
-
-#define UECFG1X _SFR_MEM8(0xED)
-#define ALLOC 1
-#define EPBK0 2
-#define EPBK1 3
-#define EPSIZE0 4
-#define EPSIZE1 5
-#define EPSIZE2 6
-
-#define UESTA0X _SFR_MEM8(0xEE)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UESTA1X _SFR_MEM8(0xEF)
-#define CURRBK0 0
-#define CURRBK1 1
-#define CTRLDIR 2
-
-#define UEIENX _SFR_MEM8(0xF0)
-#define TXINE 0
-#define STALLEDE 1
-#define RXOUTE 2
-#define RXSTPE 3
-#define NAKOUTE 4
-#define NAKINE 6
-#define FLERRE 7
-
-#define UEDATX _SFR_MEM8(0xF1)
-#define DAT0 0
-#define DAT1 1
-#define DAT2 2
-#define DAT3 3
-#define DAT4 4
-#define DAT5 5
-#define DAT6 6
-#define DAT7 7
-
-#define UEBCLX _SFR_MEM8(0xF2)
-#define BYCT0 0
-#define BYCT1 1
-#define BYCT2 2
-#define BYCT3 3
-#define BYCT4 4
-#define BYCT5 5
-#define BYCT6 6
-#define BYCT7 7
-
-#define UEINT _SFR_MEM8(0xF4)
-#define EPINT0 0
-#define EPINT1 1
-#define EPINT2 2
-#define EPINT3 3
-#define EPINT4 4
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define INT4_vect_num  5
-#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
-#define INT5_vect_num  6
-#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
-#define INT6_vect_num  7
-#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
-#define INT7_vect_num  8
-#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
-#define PCINT0_vect_num  9
-#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  10
-#define PCINT1_vect      _VECTOR(10)  /* Pin Change Interrupt Request 1 */
-#define USB_GEN_vect_num  11
-#define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
-#define USB_COM_vect_num  12
-#define USB_COM_vect      _VECTOR(12)  /* USB Endpoint/Pipe Interrupt Communication Request */
-#define WDT_vect_num  13
-#define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
-#define TIMER1_CAPT_vect_num  14
-#define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
-#define TIMER1_COMPA_vect_num  15
-#define TIMER1_COMPA_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match B */
-#define TIMER0_COMPA_vect_num  19
-#define TIMER0_COMPA_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  20
-#define TIMER0_COMPB_vect      _VECTOR(20)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  21
-#define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  22
-#define SPI_STC_vect      _VECTOR(22)  /* SPI Serial Transfer Complete */
-#define USART1_RX_vect_num  23
-#define USART1_RX_vect      _VECTOR(23)  /* USART1, Rx Complete */
-#define USART1_UDRE_vect_num  24
-#define USART1_UDRE_vect      _VECTOR(24)  /* USART1 Data register Empty */
-#define USART1_TX_vect_num  25
-#define USART1_TX_vect      _VECTOR(25)  /* USART1, Tx Complete */
-#define ANALOG_COMP_vect_num  26
-#define ANALOG_COMP_vect      _VECTOR(26)  /* Analog Comparator */
-#define EE_READY_vect_num  27
-#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
-#define SPM_READY_vect_num  28
-#define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
-#define TIMER1_COMPB_vect_num  16
-#define TIMER1_COMPB_vect      _VECTOR(16)  /* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPC_vect_num  17
-#define TIMER1_COMPC_vect      _VECTOR(17)  /* Timer/Counter2 Compare Match C */
-#define TIMER1_OVF_vect_num  18
-#define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
-#define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x89
-
-/* Device Pin Definitions */
-
-/** @} */
-
-#endif /* _AVR_ATmega8U2_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iomx8.h b/cpukit/score/cpu/avr/avr/iomx8.h
deleted file mode 100644
index f145d9d27d..0000000000
--- a/cpukit/score/cpu/avr/avr/iomx8.h
+++ /dev/null
@@ -1,747 +0,0 @@
-/* Copyright (c) 2004,2005, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iomx8.h - definitions for ATmega48, ATmega88 and ATmega168 */
-
-#ifndef _AVR_IOMX8_H_
-#define _AVR_IOMX8_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iomx8.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* Port B */
-
-#define PINB    _SFR_IO8 (0x03)
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8 (0x04)
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8 (0x05)
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Port C */
-
-#define PINC    _SFR_IO8 (0x06)
-/* PINC */
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8 (0x07)
-/* DDRC */
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8 (0x08)
-/* PORTC */
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-/* Port D */
-
-#define PIND    _SFR_IO8 (0x09)
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8 (0x0A)
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8 (0x0B)
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define TIFR0   _SFR_IO8 (0x15)
-/* TIFR0 */
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIFR1   _SFR_IO8 (0x16)
-/* TIFR1 */
-#define ICF1    5
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-#define TIFR2   _SFR_IO8 (0x17)
-/* TIFR2 */
-#define OCF2B   2
-#define OCF2A   1
-#define TOV2    0
-
-#define PCIFR   _SFR_IO8 (0x1B)
-/* PCIFR */
-#define PCIF2   2
-#define PCIF1   1
-#define PCIF0   0
-
-#define EIFR    _SFR_IO8 (0x1C)
-/* EIFR */
-#define INTF1   1
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8 (0x1D)
-/* EIMSK */
-#define INT1    1
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8 (0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-/* EECT - EEPROM Control Register */
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-/* 
- * Even though EEARH is not used by the mega48, the EEAR8 bit in the register
- * must be written to 0, according to the datasheet, hence the EEARH register
- * must be defined for the mega48.
- */
-/*
- * 6-char sequence denoting where to find the EEPROM registers in 
- * memory space.
- * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
- * subroutines.
- * First two letters:  EECR address.
- * Second two letters: EEDR address.
- * Last two letters:   EEAR address.  
- */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-
-#define GTCCR   _SFR_IO8 (0x23)
-/* GTCCR */
-#define TSM     7
-#define PSRASY  1
-#define PSRSYNC 0
-
-#define TCCR0A  _SFR_IO8 (0x24)
-/* TCCR0A */
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define TCCR0B  _SFR_IO8 (0x25)
-/* TCCR0A */
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define TCNT0   _SFR_IO8 (0x26)
-#define OCR0A   _SFR_IO8 (0x27)
-#define OCR0B   _SFR_IO8 (0x28)
-
-#define GPIOR1  _SFR_IO8 (0x2A)
-#define GPIOR2  _SFR_IO8 (0x2B)
-
-#define SPCR    _SFR_IO8 (0x2C)
-/* SPCR */
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-#define SPSR    _SFR_IO8 (0x2D)
-/* SPSR */
-#define SPIF    7
-#define WCOL    6
-#define SPI2X   0
-
-#define SPDR    _SFR_IO8 (0x2E)
-
-#define ACSR    _SFR_IO8 (0x30)
-/* ACSR */
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-#define MONDR   _SFR_IO8 (0x31)
-
-#define SMCR    _SFR_IO8 (0x33)
-/* SMCR */
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-#define MCUSR   _SFR_IO8 (0x34)
-/* MCUSR */
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8 (0x35)
-/* MCUCR */
-#define PUD     4
-#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) 
-#define IVSEL   1
-#define IVCE    0
-#endif
-
-#define SPMCSR  _SFR_IO8 (0x37)
-/* SPMCSR */
-#define SPMIE     7
-#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)
-#  define RWWSB   6
-#  define RWWSRE  4
-#endif
-#define BLBSET    3
-#define PGWRT     2
-#define PGERS     1
-#define SELFPRGEN 0
-#define SPMEN     0
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-#define WDTCSR  _SFR_MEM8 (0x60)
-/* WDTCSR */
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define CLKPR   _SFR_MEM8 (0x61)
-/* CLKPR */
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-#define PRR     _SFR_MEM8 (0x64)
-/* PRR */
-#define PRTWI    7
-#define PRTIM2   6
-#define PRTIM0   5
-#define PRTIM1   3
-#define PRSPI    2
-#define PRUSART0 1
-#define PRADC    0
-
-#define OSCCAL  _SFR_MEM8 (0x66)
-
-#define PCICR   _SFR_MEM8 (0x68)
-/* PCICR */
-#define PCIE2   2
-#define PCIE1   1
-#define PCIE0   0
-
-#define EICRA   _SFR_MEM8 (0x69)
-/* EICRA */
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-#define PCMSK0  _SFR_MEM8 (0x6B)
-/* PCMSK0 */
-#define PCINT7    7
-#define PCINT6    6
-#define PCINT5    5
-#define PCINT4    4
-#define PCINT3    3
-#define PCINT2    2
-#define PCINT1    1
-#define PCINT0    0
-
-#define PCMSK1  _SFR_MEM8 (0x6C)
-/* PCMSK1 */
-#define PCINT14   6
-#define PCINT13   5
-#define PCINT12   4
-#define PCINT11   3
-#define PCINT10   2
-#define PCINT9    1
-#define PCINT8    0
-
-#define PCMSK2  _SFR_MEM8 (0x6D)
-/* PCMSK2 */
-#define PCINT23   7
-#define PCINT22   6
-#define PCINT21   5
-#define PCINT20   4
-#define PCINT19   3
-#define PCINT18   2
-#define PCINT17   1
-#define PCINT16   0
-
-#define TIMSK0  _SFR_MEM8 (0x6E)
-/* TIMSK0 */
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define TIMSK1  _SFR_MEM8 (0x6F)
-/* TIMSK1 */
-#define ICIE1   5
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-#define TIMSK2  _SFR_MEM8 (0x70)
-/* TIMSK2 */
-#define OCIE2B  2
-#define OCIE2A  1
-#define TOIE2   0
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16 (0x78)
-#endif
-#define ADCW    _SFR_MEM16 (0x78)
-#define ADCL    _SFR_MEM8 (0x78)
-#define ADCH    _SFR_MEM8 (0x79)
-
-#define ADCSRA  _SFR_MEM8 (0x7A)
-/* ADCSRA */
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-#define ADCSRB  _SFR_MEM8 (0x7B)
-/* ADCSRB */
-#define ACME    6
-#define ADTS2   2
-#define ADTS1   1
-#define ADTS0   0
-
-#define ADMUX   _SFR_MEM8 (0x7C)
-/* ADMUX */
-#define REFS1   7
-#define REFS0   6
-#define ADLAR   5
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-#define DIDR0   _SFR_MEM8 (0x7E)
-/* DIDR0 */
-#define ADC5D   5
-#define ADC4D   4
-#define ADC3D   3
-#define ADC2D   2
-#define ADC1D   1
-#define ADC0D   0
-
-#define DIDR1   _SFR_MEM8 (0x7F)
-/* DIDR1 */
-#define AIN1D   1
-#define AIN0D   0
-
-#define TCCR1A  _SFR_MEM8 (0x80)
-/* TCCR1A */
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define WGM11   1
-#define WGM10   0
-
-#define TCCR1B  _SFR_MEM8 (0x81)
-/* TCCR1B */
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define TCCR1C  _SFR_MEM8 (0x82)
-/* TCCR1C */
-#define FOC1A   7
-#define FOC1B   6
-
-#define TCNT1   _SFR_MEM16 (0x84)
-#define TCNT1L  _SFR_MEM8 (0x84)
-#define TCNT1H  _SFR_MEM8 (0x85)
-
-#define ICR1    _SFR_MEM16 (0x86)
-#define ICR1L   _SFR_MEM8 (0x86)
-#define ICR1H   _SFR_MEM8 (0x87)
-
-#define OCR1A   _SFR_MEM16 (0x88)
-#define OCR1AL  _SFR_MEM8 (0x88)
-#define OCR1AH  _SFR_MEM8 (0x89)
-
-#define OCR1B   _SFR_MEM16 (0x8A)
-#define OCR1BL  _SFR_MEM8 (0x8A)
-#define OCR1BH  _SFR_MEM8 (0x8B)
-
-#define TCCR2A  _SFR_MEM8 (0xB0)
-/* TCCR2A */
-#define COM2A1  7
-#define COM2A0  6
-#define COM2B1  5
-#define COM2B0  4
-#define WGM21   1
-#define WGM20   0
-
-#define TCCR2B  _SFR_MEM8 (0xB1)
-/* TCCR2B */
-#define FOC2A   7
-#define FOC2B   6
-#define WGM22   3
-#define CS22    2
-#define CS21    1
-#define CS20    0
-
-#define TCNT2   _SFR_MEM8 (0xB2)
-#define OCR2A   _SFR_MEM8 (0xB3)
-#define OCR2B   _SFR_MEM8 (0xB4)
-
-#define ASSR    _SFR_MEM8 (0xB6)
-/* ASSR */
-#define EXCLK    6
-#define AS2      5
-#define TCN2UB   4
-#define OCR2AUB  3
-#define OCR2BUB  2
-#define TCR2AUB  1
-#define TCR2BUB  0
-
-#define TWBR    _SFR_MEM8 (0xB8)
-
-#define TWSR    _SFR_MEM8 (0xB9)
-/* TWSR */
-#define TWS7    7
-#define TWS6    6
-#define TWS5    5
-#define TWS4    4
-#define TWS3    3
-#define TWPS1   1
-#define TWPS0   0
-
-#define TWAR    _SFR_MEM8 (0xBA)
-/* TWAR */
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE   0
-
-#define TWDR    _SFR_MEM8 (0xBB)
-
-#define TWCR    _SFR_MEM8 (0xBC)
-/* TWCR */
-#define TWINT   7
-#define TWEA    6
-#define TWSTA   5
-#define TWSTO   4
-#define TWWC    3
-#define TWEN    2
-#define TWIE    0
-
-#define TWAMR   _SFR_MEM8 (0xBD)
-/* TWAMR */
-#define TWAM6   7
-#define TWAM5   6
-#define TWAM4   5
-#define TWAM3   4
-#define TWAM2   3
-#define TWAM1   2
-#define TWAM0   1
-
-#define UCSR0A  _SFR_MEM8 (0xC0)
-/* UCSR0A */
-#define RXC0    7
-#define TXC0    6
-#define UDRE0   5
-#define FE0     4
-#define DOR0    3
-#define UPE0    2
-#define U2X0    1
-#define MPCM0   0
-
-#define UCSR0B  _SFR_MEM8 (0xC1)
-/* UCSR0B */
-#define RXCIE0  7
-#define TXCIE0  6
-#define UDRIE0  5
-#define RXEN0   4
-#define TXEN0   3
-#define UCSZ02  2
-#define RXB80   1
-#define TXB80   0
-
-#define UCSR0C  _SFR_MEM8 (0xC2)
-/* UCSR0C */
-#define UMSEL01  7
-#define UMSEL00  6
-#define UPM01    5
-#define UPM00    4
-#define USBS0    3
-#define UCSZ01   2
-#define UDORD0   2
-#define UCSZ00   1
-#define UCPHA0   1
-#define UCPOL0   0
-
-#define UBRR0   _SFR_MEM16 (0xC4)
-#define UBRR0L  _SFR_MEM8 (0xC4)
-#define UBRR0H  _SFR_MEM8 (0xC5)
-#define UDR0    _SFR_MEM8 (0xC6)
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE0			_VECTOR(3)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT1_vect			_VECTOR(4)
-#define SIG_PIN_CHANGE1			_VECTOR(4)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT2_vect			_VECTOR(5)
-#define SIG_PIN_CHANGE2			_VECTOR(5)
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect			_VECTOR(6)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(6)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE2A		_VECTOR(7)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE2B		_VECTOR(8)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW2			_VECTOR(9)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(10)
-#define SIG_INPUT_CAPTURE1		_VECTOR(10)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(11)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(13)
-#define SIG_OVERFLOW1			_VECTOR(13)
-
-/* TimerCounter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
-
-/* TimerCounter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
-
-/* Timer/Couner0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* USART Rx Complete */
-#define USART_RX_vect			_VECTOR(18)
-#define SIG_USART_RECV			_VECTOR(18)
-
-/* USART, Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(19)
-#define SIG_USART_DATA			_VECTOR(19)
-
-/* USART Tx Complete */
-#define USART_TX_vect			_VECTOR(20)
-#define SIG_USART_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* Two-wire Serial Interface */
-#define TWI_vect			_VECTOR(24)
-#define SIG_TWI				_VECTOR(24)
-#define SIG_2WIRE_SERIAL		_VECTOR(24)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(25)
-#define SIG_SPM_READY			_VECTOR(25)
-
-/* 
- * The mega48 and mega88 vector tables are single instruction entries (16 bits
- * per entry for an RJMP) while the mega168 table has double instruction
- * entries (32 bits per entry for a JMP). 
- */
-
-#if defined (__AVR_ATmega168__)
-#  define _VECTORS_SIZE 104
-#else
-#  define _VECTORS_SIZE 52
-#endif
-/** @} */
-
-#endif /* _AVR_IOM8_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxx0_1.h b/cpukit/score/cpu/avr/avr/iomxx0_1.h
deleted file mode 100644
index 2e62117ce9..0000000000
--- a/cpukit/score/cpu/avr/avr/iomxx0_1.h
+++ /dev/null
@@ -1,1564 +0,0 @@
-/**
- * @file avr/iomxx0_1.h
- *
- * @brief Definitions for ATmega640/1280/1281/2560/2561
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2005, Anatoly Sokolov
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOMXX0_1_H_
-#define _AVR_IOMXX0_1_H_ 1
-
-/**
- *  @defgroup Avr_iomxx0_1 ATmega640/1280/1281/2560/2561 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iomxx0_1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-# define __ATmegaxx0__
-#elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__)
-# define __ATmegaxx1__
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0X00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0X01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0X02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0X03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG5    5
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG5     5
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIFR1   _SFR_IO8(0x16)
-#define ICF1    5
-#define OCF1C   3
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-#define TIFR2   _SFR_IO8(0x17)
-#define OCF2B   2
-#define OCF2A   1
-#define TOV2    0
-
-#define TIFR3   _SFR_IO8(0x18)
-#define ICF3    5
-#define OCF3C   3
-#define OCF3B   2
-#define OCF3A   1
-#define TOV3    0
-
-#define TIFR4   _SFR_IO8(0x19)
-#define ICF4    5
-#define OCF4C   3
-#define OCF4B   2
-#define OCF4A   1
-#define TOV4    0
-
-#define TIFR5   _SFR_IO8(0x1A)
-#define ICF5    5
-#define OCF5C   3
-#define OCF5B   2
-#define OCF5A   1
-#define TOV5    0
-
-#define PCIFR   _SFR_IO8(0x1B)
-#if defined(__ATmegaxx0__)
-# define PCIF2  2
-#endif /* __ATmegaxx0__ */
-#define PCIF1   1
-#define PCIF0   0
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF7   7
-#define INTF6   6
-#define INTF5   5
-#define INTF4   4
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT7    7
-#define INT6    6
-#define INT5    5
-#define INT4    4
-#define INT3    3
-#define INT2    2
-#define INT1    1
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define TSM     7
-#define PSRASY  1
-#define PSRSYNC 0
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-#define OCR0B   _SFR_IO8(0X28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPIF    7
-#define WCOL    6
-#define SPI2X   0
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-#define MONDR   _SFR_IO8(0x31)
-#define OCDR    _SFR_IO8(0x31)
-#define IDRD    7
-#define OCDR7   7
-#define OCDR6   6
-#define OCDR5   5
-#define OCDR4   4
-#define OCDR3   3
-#define OCDR2   2
-#define OCDR1   1
-#define OCDR0   0
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define JTRF    4
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0X35)
-#define JTD     7
-#define PUD     4
-#define IVSEL   1
-#define IVCE    0
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMIE   7
-#define RWWSB   6
-#define SIGRD   5
-#define RWWSRE  4
-#define BLBSET  3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* Reserved [0x38..0x3A] */
-
-#define RAMPZ   _SFR_IO8(0X3B)
-#define RAMPZ0  0
-
-#define EIND    _SFR_IO8(0X3C)
-#define EIND0   0
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-/* Reserved [0x62..0x63] */
-
-#define PRR0    _SFR_MEM8(0x64)
-#define PRTWI       7
-#define PRTIM2      6
-#define PRTIM0      5
-#define PRTIM1      3
-#define PRSPI       2
-#define PRUSART0    1
-#define PRADC       0
-
-#define PRR1    _SFR_MEM8(0x65)
-#define PRTIM5      5
-#define PRTIM4      4
-#define PRTIM3      3
-#define PRUSART3    2
-#define PRUSART2    1
-#define PRUSART1    0
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#if defined(__ATmegaxx0__)
-# define PCIE2  2
-#endif /* __ATmegaxx0__ */
-#define PCIE1   1
-#define PCIE0   0
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-#define EICRB   _SFR_MEM8(0x6A)
-#define ISC71   7
-#define ISC70   6
-#define ISC61   5
-#define ISC60   4
-#define ISC51   3
-#define ISC50   2
-#define ISC41   1
-#define ISC40   0
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9  1
-#define PCINT8  0
-
-#if defined(__ATmegaxx0__)
-# define PCMSK2 _SFR_MEM8(0x6D)
-# define PCINT23 7
-# define PCINT22 6
-# define PCINT21 5
-# define PCINT20 4
-# define PCINT19 3
-# define PCINT18 2
-# define PCINT17 1
-# define PCINT16 0
-#endif /* __ATmegaxx0__ */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define ICIE1   5
-#define OCIE1C  3
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define OCIE2B  2
-#define OCIE2A  1
-#define TOIE2   0
-
-#define TIMSK3  _SFR_MEM8(0x71)
-#define ICIE3   5
-#define OCIE3C  3
-#define OCIE3B  2
-#define OCIE3A  1
-#define TOIE3   0
-
-#define TIMSK4  _SFR_MEM8(0x72)
-#define ICIE4   5
-#define OCIE4C  3
-#define OCIE4B  2
-#define OCIE4A  1
-#define TOIE4   0
-
-#define TIMSK5  _SFR_MEM8(0x73)
-#define ICIE5   5
-#define OCIE5C  3
-#define OCIE5B  2
-#define OCIE5A  1
-#define TOIE5   0
-
-#define XMCRA   _SFR_MEM8(0x74)
-#define SRE     7
-#define SRL2    6
-#define SRL1    5
-#define SRL0    4
-#define SRW11   3
-#define SRW10   2
-#define SRW01   1
-#define SRW00   0
-
-#define XMCRB   _SFR_MEM8(0x75)
-#define XMBK    7
-#define XMM2    2
-#define XMM1    1
-#define XMM0    0
-
-/* Reserved [0x76..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ACME    6
-#if defined(__ATmegaxx0__)
-# define MUX5    3
-#endif /* __ATmegaxx0__ */
-#define ADTS2   2
-#define ADTS1   1
-#define ADTS0   0
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define REFS1   7
-#define REFS0   6
-#define ADLAR   5
-#define MUX4    4
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-#define DIDR2   _SFR_MEM8(0x7D)
-#define ADC15D  7
-#define ADC14D  6
-#define ADC13D  5
-#define ADC12D  4
-#define ADC11D  3
-#define ADC10D  2
-#define ADC9D   1
-#define ADC8D   0
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC7D   7
-#define ADC6D   6
-#define ADC5D   5
-#define ADC4D   4
-#define ADC3D   3
-#define ADC2D   2
-#define ADC1D   1
-#define ADC0D   0
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN1D   1
-#define AIN0D   0
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define COM1C1  3
-#define COM1C0  2
-#define WGM11   1
-#define WGM10   0
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1A   7
-#define FOC1B   6
-#define FOC1C   5
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Combine OCR1CL and OCR1CH */
-#define OCR1C   _SFR_MEM16(0x8C)
-
-#define OCR1CL  _SFR_MEM8(0x8C)
-#define OCR1CH  _SFR_MEM8(0x8D)
-
-/* Reserved [0x8E..0x8F] */
-
-#define TCCR3A  _SFR_MEM8(0x90)
-#define COM3A1  7
-#define COM3A0  6
-#define COM3B1  5
-#define COM3B0  4
-#define COM3C1  3
-#define COM3C0  2
-#define WGM31   1
-#define WGM30   0
-
-#define TCCR3B  _SFR_MEM8(0x91)
-#define ICNC3   7
-#define ICES3   6
-#define WGM33   4
-#define WGM32   3
-#define CS32    2
-#define CS31    1
-#define CS30    0
-
-#define TCCR3C  _SFR_MEM8(0x92)
-#define FOC3A   7
-#define FOC3B   6
-#define FOC3C   5
-
-/* Reserved [0x93] */
-
-/* Combine TCNT3L and TCNT3H */
-#define TCNT3   _SFR_MEM16(0x94)
-
-#define TCNT3L  _SFR_MEM8(0x94)
-#define TCNT3H  _SFR_MEM8(0x95)
-
-/* Combine ICR3L and ICR3H */
-#define ICR3    _SFR_MEM16(0x96)
-
-#define ICR3L   _SFR_MEM8(0x96)
-#define ICR3H   _SFR_MEM8(0x97)
-
-/* Combine OCR3AL and OCR3AH */
-#define OCR3A   _SFR_MEM16(0x98)
-
-#define OCR3AL  _SFR_MEM8(0x98)
-#define OCR3AH  _SFR_MEM8(0x99)
-
-/* Combine OCR3BL and OCR3BH */
-#define OCR3B   _SFR_MEM16(0x9A)
-
-#define OCR3BL  _SFR_MEM8(0x9A)
-#define OCR3BH  _SFR_MEM8(0x9B)
-
-/* Combine OCR3CL and OCR3CH */
-#define OCR3C   _SFR_MEM16(0x9C)
-
-#define OCR3CL  _SFR_MEM8(0x9C)
-#define OCR3CH  _SFR_MEM8(0x9D)
-
-/* Reserved [0x9E..0x9F] */
-
-#define TCCR4A  _SFR_MEM8(0xA0)
-#define COM4A1  7
-#define COM4A0  6
-#define COM4B1  5
-#define COM4B0  4
-#define COM4C1  3
-#define COM4C0  2
-#define WGM41   1
-#define WGM40   0
-
-#define TCCR4B  _SFR_MEM8(0xA1)
-#define ICNC4   7
-#define ICES4   6
-#define WGM43   4
-#define WGM42   3
-#define CS42    2
-#define CS41    1
-#define CS40    0
-
-#define TCCR4C  _SFR_MEM8(0xA2)
-#define FOC4A   7
-#define FOC4B   6
-#define FOC4C   5
-
-/* Reserved [0xA3] */
-
-/* Combine TCNT4L and TCNT4H */
-#define TCNT4   _SFR_MEM16(0xA4)
-
-#define TCNT4L  _SFR_MEM8(0xA4)
-#define TCNT4H  _SFR_MEM8(0xA5)
-
-/* Combine ICR4L and ICR4H */
-#define ICR4    _SFR_MEM16(0xA6)
-
-#define ICR4L   _SFR_MEM8(0xA6)
-#define ICR4H   _SFR_MEM8(0xA7)
-
-/* Combine OCR4AL and OCR4AH */
-#define OCR4A   _SFR_MEM16(0xA8)
-
-#define OCR4AL  _SFR_MEM8(0xA8)
-#define OCR4AH  _SFR_MEM8(0xA9)
-
-/* Combine OCR4BL and OCR4BH */
-#define OCR4B   _SFR_MEM16(0xAA)
-
-#define OCR4BL  _SFR_MEM8(0xAA)
-#define OCR4BH  _SFR_MEM8(0xAB)
-
-/* Combine OCR4CL and OCR4CH */
-#define OCR4C   _SFR_MEM16(0xAC)
-
-#define OCR4CL  _SFR_MEM8(0xAC)
-#define OCR4CH  _SFR_MEM8(0xAD)
-
-/* Reserved [0xAE..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define COM2A1  7
-#define COM2A0  6
-#define COM2B1  5
-#define COM2B0  4
-#define WGM21   1
-#define WGM20   0
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define FOC2A   7
-#define FOC2B   6
-#define WGM22   3
-#define CS22    2
-#define CS21    1
-#define CS20    0
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define EXCLK   6
-#define AS2     5
-#define TCN2UB  4
-#define OCR2AUB 3
-#define OCR2BUB 2
-#define TCR2AUB 1
-#define TCR2BUB 0
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWS7    7
-#define TWS6    6
-#define TWS5    5
-#define TWS4    4
-#define TWS3    3
-#define TWPS1   1
-#define TWPS0   0
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE   0
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWINT   7
-#define TWEA    6
-#define TWSTA   5
-#define TWSTO   4
-#define TWWC    3
-#define TWEN    2
-#define TWIE    0
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM6   7
-#define TWAM5   6
-#define TWAM4   5
-#define TWAM3   4
-#define TWAM2   3
-#define TWAM1   2
-#define TWAM0   1
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define RXC0    7
-#define TXC0    6
-#define UDRE0   5
-#define FE0     4
-#define DOR0    3
-#define UPE0    2
-#define U2X0    1
-#define MPCM0   0
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define RXCIE0  7
-#define TXCIE0  6
-#define UDRIE0  5
-#define RXEN0   4
-#define TXEN0   3
-#define UCSZ02  2
-#define RXB80   1
-#define TXB80   0
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UMSEL01 7
-#define UMSEL00 6
-#define UPM01   5
-#define UPM00   4
-#define USBS0   3
-#define UCSZ01  2
-#define UCSZ00  1
-#define UCPOL0  0
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7] */
-
-#define UCSR1A  _SFR_MEM8(0xC8)
-#define RXC1    7
-#define TXC1    6
-#define UDRE1   5
-#define FE1     4
-#define DOR1    3
-#define UPE1    2
-#define U2X1    1
-#define MPCM1   0
-
-#define UCSR1B  _SFR_MEM8(0XC9)
-#define RXCIE1  7
-#define TXCIE1  6
-#define UDRIE1  5
-#define RXEN1   4
-#define TXEN1   3
-#define UCSZ12  2
-#define RXB81   1
-#define TXB81   0
-
-#define UCSR1C  _SFR_MEM8(0xCA)
-#define UMSEL11 7
-#define UMSEL10 6
-#define UPM11   5
-#define UPM10   4
-#define USBS1   3
-#define UCSZ11  2
-#define UCSZ10  1
-#define UCPOL1  0
-
-/* Reserved [0xCB] */
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0xCC)
-
-#define UBRR1L  _SFR_MEM8(0xCC)
-#define UBRR1H  _SFR_MEM8(0xCD)
-
-#define UDR1    _SFR_MEM8(0XCE)
-
-/* Reserved [0xCF] */
-
-#if defined(__ATmegaxx0__)
-
-# define UCSR2A _SFR_MEM8(0xD0)
-# define RXC2   7
-# define TXC2   6
-# define UDRE2  5
-# define FE2    4
-# define DOR2   3
-# define UPE2   2
-# define U2X2   1
-# define MPCM2  0
-
-# define UCSR2B _SFR_MEM8(0XD1)
-# define RXCIE2 7
-# define TXCIE2 6
-# define UDRIE2 5
-# define RXEN2  4
-# define TXEN2  3
-# define UCSZ22 2
-# define RXB82  1
-# define TXB82  0
-
-# define UCSR2C _SFR_MEM8(0xD2)
-# define UMSEL21 7
-# define UMSEL20 6
-# define UPM21  5
-# define UPM20  4
-# define USBS2  3
-# define UCSZ21 2
-# define UCSZ20 1
-# define UCPOL2 0
-
-/* Reserved [0xD3] */
-
-/* Combine UBRR2L and UBRR2H */
-# define UBRR2  _SFR_MEM16(0xD4)
-
-# define UBRR2L _SFR_MEM8(0xD4)
-# define UBRR2H _SFR_MEM8(0xD5)
-
-# define UDR2   _SFR_MEM8(0XD6)
-
-#endif /* __ATmegaxx0__ */
-
-/* Reserved [0xD7..0xFF] */
-
-#if defined(__ATmegaxx0__)
-
-# define PINH   _SFR_MEM8(0x100)
-# define PINH7  7
-# define PINH6  6
-# define PINH5  5
-# define PINH4  4
-# define PINH3  3
-# define PINH2  2
-# define PINH1  1
-# define PINH0  0
-
-# define DDRH   _SFR_MEM8(0x101)
-# define DDH7   7
-# define DDH6   6
-# define DDH5   5
-# define DDH4   4
-# define DDH3   3
-# define DDH2   2
-# define DDH1   1
-# define DDH0   0
-
-# define PORTH  _SFR_MEM8(0x102)
-# define PH7    7
-# define PH6    6
-# define PH5    5
-# define PH4    4
-# define PH3    3
-# define PH2    2
-# define PH1    1
-# define PH0    0
-
-# define PINJ   _SFR_MEM8(0x103)
-# define PINJ7  7
-# define PINJ6  6
-# define PINJ5  5
-# define PINJ4  4
-# define PINJ3  3
-# define PINJ2  2
-# define PINJ1  1
-# define PINJ0  0
-
-# define DDRJ   _SFR_MEM8(0x104)
-# define DDJ7   7
-# define DDJ6   6
-# define DDJ5   5
-# define DDJ4   4
-# define DDJ3   3
-# define DDJ2   2
-# define DDJ1   1
-# define DDJ0   0
-
-# define PORTJ  _SFR_MEM8(0x105)
-# define PJ7 7
-# define PJ6 6
-# define PJ5 5
-# define PJ4 4
-# define PJ3 3
-# define PJ2 2
-# define PJ1 1
-# define PJ0 0
-
-# define PINK   _SFR_MEM8(0x106)
-# define PINK7  7
-# define PINK6  6
-# define PINK5  5
-# define PINK4  4
-# define PINK3  3
-# define PINK2  2
-# define PINK1  1
-# define PINK0  0
-
-# define DDRK   _SFR_MEM8(0x107)
-# define DDK7   7
-# define DDK6   6
-# define DDK5   5
-# define DDK4   4
-# define DDK3   3
-# define DDK2   2
-# define DDK1   1
-# define DDK0   0
-
-# define PORTK  _SFR_MEM8(0x108)
-# define PK7 7
-# define PK6 6
-# define PK5 5
-# define PK4 4
-# define PK3 3
-# define PK2 2
-# define PK1 1
-# define PK0 0
-
-# define PINL   _SFR_MEM8(0x109)
-# define PINL7  7
-# define PINL6  6
-# define PINL5  5
-# define PINL4  4
-# define PINL3  3
-# define PINL2  2
-# define PINL1  1
-# define PINL0  0
-
-# define DDRL   _SFR_MEM8(0x10A)
-# define DDL7   7
-# define DDL6   6
-# define DDL5   5
-# define DDL4   4
-# define DDL3   3
-# define DDL2   2
-# define DDL1   1
-# define DDL0   0
-
-# define PORTL  _SFR_MEM8(0x10B)
-# define PL7 7
-# define PL6 6
-# define PL5 5
-# define PL4 4
-# define PL3 3
-# define PL2 2
-# define PL1 1
-# define PL0 0
-
-#endif /* __ATmegaxx0__ */
-
-/* Reserved [0x10C..0x11F] */
-
-#define TCCR5A  _SFR_MEM8(0x120)
-#define COM5A1  7
-#define COM5A0  6
-#define COM5B1  5
-#define COM5B0  4
-#define COM5C1  3
-#define COM5C0  2
-#define WGM51   1
-#define WGM50   0
-
-#define TCCR5B  _SFR_MEM8(0x121)
-#define ICNC5   7
-#define ICES5   6
-#define WGM53   4
-#define WGM52   3
-#define CS52    2
-#define CS51    1
-#define CS50    0
-
-#define TCCR5C  _SFR_MEM8(0x122)
-#define FOC5A   7
-#define FOC5B   6
-#define FOC5C   5
-
-/* Reserved [0x123] */
-
-/* Combine TCNT5L and TCNT5H */
-#define TCNT5   _SFR_MEM16(0x124)
-
-#define TCNT5L  _SFR_MEM8(0x124)
-#define TCNT5H  _SFR_MEM8(0x125)
-
-/* Combine ICR5L and ICR5H */
-#define ICR5    _SFR_MEM16(0x126)
-
-#define ICR5L   _SFR_MEM8(0x126)
-#define ICR5H   _SFR_MEM8(0x127)
-
-/* Combine OCR5AL and OCR5AH */
-#define OCR5A   _SFR_MEM16(0x128)
-
-#define OCR5AL  _SFR_MEM8(0x128)
-#define OCR5AH  _SFR_MEM8(0x129)
-
-/* Combine OCR5BL and OCR5BH */
-#define OCR5B   _SFR_MEM16(0x12A)
-
-#define OCR5BL  _SFR_MEM8(0x12A)
-#define OCR5BH  _SFR_MEM8(0x12B)
-
-/* Combine OCR5CL and OCR5CH */
-#define OCR5C   _SFR_MEM16(0x12C)
-
-#define OCR5CL  _SFR_MEM8(0x12C)
-#define OCR5CH  _SFR_MEM8(0x12D)
-
-/* Reserved [0x12E..0x12F] */
-
-#if defined(__ATmegaxx0__)
-
-# define UCSR3A _SFR_MEM8(0x130)
-# define RXC3   7
-# define TXC3   6
-# define UDRE3  5
-# define FE3    4
-# define DOR3   3
-# define UPE3   2
-# define U2X3   1
-# define MPCM3  0
-
-# define UCSR3B _SFR_MEM8(0X131)
-# define RXCIE3 7
-# define TXCIE3 6
-# define UDRIE3 5
-# define RXEN3  4
-# define TXEN3  3
-# define UCSZ32 2
-# define RXB83  1
-# define TXB83  0
-
-# define UCSR3C _SFR_MEM8(0x132)
-# define UMSEL31 7
-# define UMSEL30 6
-# define UPM31  5
-# define UPM30  4
-# define USBS3  3
-# define UCSZ31 2
-# define UCSZ30 1
-# define UCPOL3 0
-
-/* Reserved [0x133] */
-
-/* Combine UBRR3L and UBRR3H */
-# define UBRR3  _SFR_MEM16(0x134)
-
-# define UBRR3L _SFR_MEM8(0x134)
-# define UBRR3H _SFR_MEM8(0x135)
-
-# define UDR3   _SFR_MEM8(0X136)
-
-#endif /* __ATmegaxx0__ */
-
-/* Reserved [0x137..1FF] */
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(9)
-#define SIG_PIN_CHANGE0			_VECTOR(9)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(10)
-#define SIG_PIN_CHANGE1			_VECTOR(10)
-
-#if defined(__ATmegaxx0__)
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(11)
-#define SIG_PIN_CHANGE2			_VECTOR(11)
-
-#endif /* __ATmegaxx0__ */
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect			_VECTOR(12)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW2			_VECTOR(15)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(16)
-#define SIG_INPUT_CAPTURE1		_VECTOR(16)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(17)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(18)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(19)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(20)
-#define SIG_OVERFLOW1			_VECTOR(20)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(21)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(22)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(23)
-#define SIG_OVERFLOW0			_VECTOR(23)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(24)
-#define SIG_SPI				_VECTOR(24)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(25)
-#define SIG_USART0_RECV			_VECTOR(25)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(26)
-#define SIG_USART0_DATA			_VECTOR(26)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(27)
-#define SIG_USART0_TRANS		_VECTOR(27)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(28)
-#define SIG_COMPARATOR			_VECTOR(28)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(29)
-#define SIG_ADC				_VECTOR(29)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(30)
-#define SIG_EEPROM_READY		_VECTOR(30)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(31)
-#define SIG_INPUT_CAPTURE3		_VECTOR(31)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(32)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(33)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(34)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(35)
-#define SIG_OVERFLOW3			_VECTOR(35)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(36)
-#define SIG_USART1_RECV			_VECTOR(36)
-
-/* USART1 Data register Empty */
-#define USART1_UDRE_vect		_VECTOR(37)
-#define SIG_USART1_DATA			_VECTOR(37)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(38)
-#define SIG_USART1_TRANS		_VECTOR(38)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(39)
-#define SIG_2WIRE_SERIAL		_VECTOR(39)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(40)
-#define SIG_SPM_READY			_VECTOR(40)
-
-#if defined(__ATmegaxx0__)
-/* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect		_VECTOR(41)
-#define SIG_INPUT_CAPTURE4		_VECTOR(41)
-
-#endif /* __ATmegaxx0__ */
-
-/* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect		_VECTOR(42)
-#define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
-
-/* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect		_VECTOR(43)
-#define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
-
-/* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect		_VECTOR(44)
-#define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
-
-/* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect			_VECTOR(45)
-#define SIG_OVERFLOW4			_VECTOR(45)
-
-#if defined(__ATmegaxx0__)
-/* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect		_VECTOR(46)
-#define SIG_INPUT_CAPTURE5		_VECTOR(46)
-
-#endif /* __ATmegaxx0__ */
-
-/* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect		_VECTOR(47)
-#define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
-
-/* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect		_VECTOR(48)
-#define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
-
-/* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect		_VECTOR(49)
-#define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
-
-/* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect			_VECTOR(50)
-#define SIG_OVERFLOW5			_VECTOR(50)
-
-#if defined(__ATmegaxx1__)
-
-# define _VECTORS_SIZE 204
-
-#else
-
-/* USART2, Rx Complete */
-#define USART2_RX_vect			_VECTOR(51)
-#define SIG_USART2_RECV			_VECTOR(51)
-
-/* USART2 Data register Empty */
-#define USART2_UDRE_vect		_VECTOR(52)
-#define SIG_USART2_DATA			_VECTOR(52)
-
-/* USART2, Tx Complete */
-#define USART2_TX_vect			_VECTOR(53)
-#define SIG_USART2_TRANS		_VECTOR(53)
-
-/* USART3, Rx Complete */
-#define USART3_RX_vect			_VECTOR(54)
-#define SIG_USART3_RECV			_VECTOR(54)
-
-/* USART3 Data register Empty */
-#define USART3_UDRE_vect		_VECTOR(55)
-#define SIG_USART3_DATA			_VECTOR(55)
-
-/* USART3, Tx Complete */
-#define USART3_TX_vect			_VECTOR(56)
-#define SIG_USART3_TRANS		_VECTOR(56)
-
-# define _VECTORS_SIZE 228
-
-#endif /* __ATmegaxx1__ */
-
-#if defined(__ATmegaxx0__)
-# undef __ATmegaxx0__
-#endif
-
-#if defined(__ATmegaxx1__)
-# undef __ATmegaxx1__
-#endif
-
-/**@}*/
-#endif /* _AVR_IOMXX0_1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxx4.h b/cpukit/score/cpu/avr/avr/iomxx4.h
deleted file mode 100644
index 9dd64d875d..0000000000
--- a/cpukit/score/cpu/avr/avr/iomxx4.h
+++ /dev/null
@@ -1,882 +0,0 @@
-/**
- * @file avr/iomXX4.h
- *
- * @brief Definitions for ATmega164P/324P/644P and ATmega644
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOMXX4_H_
-#define _AVR_IOMXX4_H_ 1
-
-/**
- * @defgroup AvrDef_iomXX4 ATmega164P/324P/644P , ATmega644 Defintions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom164.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA	_SFR_IO8(0X00)
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-#define DDRA	_SFR_IO8(0X01)
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-#define PORTA	_SFR_IO8(0X02)
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-#define PINB	_SFR_IO8(0X03)
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-#define DDRB	_SFR_IO8(0x04)
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-#define PORTB	_SFR_IO8(0x05)
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-#define PINC	_SFR_IO8(0x06)
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-#define DDRC	_SFR_IO8(0x07)
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-#define PORTC	_SFR_IO8(0x08)
-#define PC7	7
-#define PC6	6
-#define PC5	5
-#define PC4	4
-#define PC3	3
-#define PC2	2
-#define PC1	1
-#define PC0	0
-
-#define PIND	_SFR_IO8(0x09)
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-#define DDRD	_SFR_IO8(0x0A)
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-#define PORTD	_SFR_IO8(0x0B)
-#define PD7	7
-#define PD6	6
-#define PD5	5
-#define PD4	4
-#define PD3	3
-#define PD2	2
-#define PD1	1
-#define PD0	0
-
-/* Reserved [0x0C..0x14] */
-
-#define TIFR0	_SFR_IO8(0x15)
-#define OCF0B	2
-#define OCF0A	1
-#define TOV0	0
-
-#define TIFR1	_SFR_IO8(0x16)
-#define ICF1	5
-#define OCF1B	2
-#define OCF1A	1
-#define TOV1	0
-
-#define TIFR2	_SFR_IO8(0x17)
-#define OCF2B	2
-#define OCF2A	1
-#define TOV2	0
-
-/* Reserved [0x18..0x1A] */
-
-#define PCIFR	_SFR_IO8(0x1B)
-#define PCIF3	3
-#define PCIF2	2
-#define PCIF1	1
-#define PCIF0	0
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF2	2
-#define INTF1	1
-#define INTF0	0
-
-#define EIMSK	_SFR_IO8(0x1D)
-#define INT2	2
-#define INT1	1
-#define INT0	0
-
-#define GPIOR0	_SFR_IO8(0x1E)
-
-#define EECR   _SFR_IO8(0x1F)
-/* EECR - EEPROM Control Register */
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR   _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR	_SFR_IO8(0x23)
-#define TSM	7
-#define PSRASY	1
-#define PSRSYNC 0
-
-#define TCCR0A	_SFR_IO8(0x24)
-#define COM0A1	7
-#define COM0A0	6
-#define COM0B1	5
-#define COM0B0	4
-#define WGM01	1
-#define WGM00	0
-
-#define TCCR0B	_SFR_IO8(0x25)
-#define FOC0A	7
-#define FOC0B	6
-#define WGM02	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-#define TCNT0	_SFR_IO8(0X26)
-
-#define OCR0A	_SFR_IO8(0X27)
-
-#define OCR0B	_SFR_IO8(0X28)
-
-/* Reserved [0x29] */
-
-#define GPIOR1	_SFR_IO8(0x2A)
-
-#define GPIOR2	_SFR_IO8(0x2B)
-
-#define SPCR	_SFR_IO8(0x2C)
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-#define SPSR	_SFR_IO8(0x2D)
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-#define SPDR	_SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR	_SFR_IO8(0x30)
-#define ACD	7
-#define ACBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-#define MONDR	_SFR_IO8(0x31)
-#define OCDR	_SFR_IO8(0x31)
-#define IDRD	7
-#define OCDR7	7
-#define OCDR6	6
-#define OCDR5	5
-#define OCDR4	4
-#define OCDR3	3
-#define OCDR2	2
-#define OCDR1	1
-#define OCDR0	0
-
-/* Reserved [0x32] */
-
-#define SMCR	_SFR_IO8(0x33)
-#define SM2	3
-#define SM1	2
-#define SM0	1
-#define SE	0
-
-#define MCUSR	_SFR_IO8(0x34)
-#define JTRF	4
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-#define MCUCR	_SFR_IO8(0X35)
-#define JTD	7
-#if !defined(__AVR_ATmega644__)
-#define BODS    6
-#define BODSE   5
-#endif
-#define PUD	4
-#define IVSEL	1
-#define IVCE	0
-
-/* Reserved [0x36] */
-
-#define SPMCSR	_SFR_IO8(0x37)
-#define SPMIE	7
-#define RWWSB	6
-#define SIGRD	5
-#define RWWSRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCSR	_SFR_MEM8(0x60)
-#define WDIF	7
-#define WDIE	6
-#define WDP3	5
-#define WDCE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-#define CLKPR	_SFR_MEM8(0x61)
-#define CLKPCE	7
-#define CLKPS3	3
-#define CLKPS2	2
-#define CLKPS1	1
-#define CLKPS0	0
-
-/* Reserved [0x62..0x63] */
-
-#define PRR	_SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D–AVR–02/07
-                                   and ATmega644 2593L–AVR–02/07.  */
-#define PRR0	_SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
-#define PRTWI		7
-#define PRTIM2		6
-#define PRTIM0		5
-#if !defined(__AVR_ATmega644__)
-# define PRUSART1	4
-#endif
-#define PRTIM1		3
-#define PRSPI		2
-#define PRUSART0	1
-#define PRADC		0
-
-/* Reserved [0x65] */
-
-#define OSCCAL	_SFR_MEM8(0x66)
-
-/* Reserved [0x67] */
-
-#define PCICR	_SFR_MEM8(0x68)
-#define PCIE3	3
-#define PCIE2	2
-#define PCIE1	1
-#define PCIE0	0
-
-#define EICRA	_SFR_MEM8(0x69)
-#define ISC21	5
-#define ISC20	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* Reserved [0x6A] */
-
-#define PCMSK0	_SFR_MEM8(0x6B)
-#define PCINT7	7
-#define PCINT6	6
-#define PCINT5	5
-#define PCINT4	4
-#define PCINT3	3
-#define PCINT2	2
-#define PCINT1	1
-#define PCINT0	0
-
-#define PCMSK1	_SFR_MEM8(0x6C)
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9	1
-#define PCINT8	0
-
-#define PCMSK2	_SFR_MEM8(0x6D)
-#define PCINT23 7
-#define PCINT22 6
-#define PCINT21 5
-#define PCINT20 4
-#define PCINT19 3
-#define PCINT18 2
-#define PCINT17 1
-#define PCINT16 0
-
-#define TIMSK0	_SFR_MEM8(0x6E)
-#define OCIE0B	2
-#define OCIE0A	1
-#define TOIE0	0
-
-#define TIMSK1	_SFR_MEM8(0x6F)
-#define ICIE1	5
-#define OCIE1B	2
-#define OCIE1A	1
-#define TOIE1	0
-
-#define TIMSK2	_SFR_MEM8(0x70)
-#define OCIE2B	2
-#define OCIE2A	1
-#define TOIE2	0
-
-/* Reserved [0x71..0x72] */
-
-#define PCMSK3	_SFR_MEM8(0x73)
-#define PCINT31 7
-#define PCINT30 6
-#define PCINT29 5
-#define PCINT28 4
-#define PCINT27 3
-#define PCINT26 2
-#define PCINT25 1
-#define PCINT24 0
-
-/* Reserved [0x74..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC	_SFR_MEM16(0x78)
-#endif
-#define ADCW	_SFR_MEM16(0x78)
-#define ADCL	_SFR_MEM8(0x78)
-#define ADCH	_SFR_MEM8(0x79)
-
-#define ADCSRA	_SFR_MEM8(0x7A)
-#define ADEN	7
-#define ADSC	6
-#define ADATE	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-#define ADCSRB	_SFR_MEM8(0x7B)
-#define ACME	6
-#define ADTS2	2
-#define ADTS1	1
-#define ADTS0	0
-
-#define ADMUX	_SFR_MEM8(0x7C)
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-#define MUX4	4
-#define MUX3	3
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* Reserved [0x7D] */
-
-#define DIDR0	_SFR_MEM8(0x7E)
-#define ADC7D	7
-#define ADC6D	6
-#define ADC5D	5
-#define ADC4D	4
-#define ADC3D	3
-#define ADC2D	2
-#define ADC1D	1
-#define ADC0D	0
-
-#define DIDR1	_SFR_MEM8(0x7F)
-#define AIN1D	1
-#define AIN0D	0
-
-#define TCCR1A	_SFR_MEM8(0x80)
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define WGM11	1
-#define WGM10	0
-
-#define TCCR1B	_SFR_MEM8(0x81)
-#define ICNC1	7
-#define ICES1	6
-#define WGM13	4
-#define WGM12	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-#define TCCR1C	_SFR_MEM8(0x82)
-#define FOC1A	7
-#define FOC1B	6
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1	_SFR_MEM16(0x84)
-
-#define TCNT1L	_SFR_MEM8(0x84)
-#define TCNT1H	_SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1	_SFR_MEM16(0x86)
-
-#define ICR1L	_SFR_MEM8(0x86)
-#define ICR1H	_SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A	_SFR_MEM16(0x88)
-
-#define OCR1AL	_SFR_MEM8(0x88)
-#define OCR1AH	_SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B	_SFR_MEM16(0x8A)
-
-#define OCR1BL	_SFR_MEM8(0x8A)
-#define OCR1BH	_SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A	_SFR_MEM8(0xB0)
-#define COM2A1	7
-#define COM2A0	6
-#define COM2B1	5
-#define COM2B0	4
-#define WGM21	1
-#define WGM20	0
-
-#define TCCR2B	_SFR_MEM8(0xB1)
-#define FOC2A	7
-#define FOC2B	6
-#define WGM22	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-#define TCNT2	_SFR_MEM8(0xB2)
-
-#define OCR2A	_SFR_MEM8(0xB3)
-
-#define OCR2B	_SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR	_SFR_MEM8(0xB6)
-#define EXCLK	6
-#define AS2	5
-#define TCN2UB	4
-#define OCR2AUB 3
-#define OCR2BUB 2
-#define TCR2AUB 1
-#define TCR2BUB 0
-
-/* Reserved [0xB7] */
-
-#define TWBR	_SFR_MEM8(0xB8)
-
-#define TWSR	_SFR_MEM8(0xB9)
-#define TWS7	7
-#define TWS6	6
-#define TWS5	5
-#define TWS4	4
-#define TWS3	3
-#define TWPS1	1
-#define TWPS0	0
-
-#define TWAR	_SFR_MEM8(0xBA)
-#define TWA6	7
-#define TWA5	6
-#define TWA4	5
-#define TWA3	4
-#define TWA2	3
-#define TWA1	2
-#define TWA0	1
-#define TWGCE	0
-
-#define TWDR	_SFR_MEM8(0xBB)
-
-#define TWCR	_SFR_MEM8(0xBC)
-#define TWINT	7
-#define TWEA	6
-#define TWSTA	5
-#define TWSTO	4
-#define TWWC	3
-#define TWEN	2
-#define TWIE	0
-
-#define TWAMR	_SFR_MEM8(0xBD)
-#define TWAM6	7
-#define TWAM5	6
-#define TWAM4	5
-#define TWAM3	4
-#define TWAM2	3
-#define TWAM1	2
-#define TWAM0	1
-
-/* Reserved [0xBE..0xBF] */
-
-#define UCSR0A	_SFR_MEM8(0xC0)
-#define RXC0	7
-#define TXC0	6
-#define UDRE0	5
-#define FE0	4
-#define DOR0	3
-#define UPE0	2
-#define U2X0	1
-#define MPCM0	0
-
-#define UCSR0B	_SFR_MEM8(0XC1)
-#define RXCIE0	7
-#define TXCIE0	6
-#define UDRIE0	5
-#define RXEN0	4
-#define TXEN0	3
-#define UCSZ02	2
-#define RXB80	1
-#define TXB80	0
-
-#define UCSR0C	_SFR_MEM8(0xC2)
-#define UMSEL01 7
-#define UMSEL00 6
-#define UPM01	5
-#define UPM00	4
-#define USBS0	3
-#define UCSZ01	2
-#define UCSZ00	1
-#define UCPHA0  1
-#define UCPOL0	0
-
-/* Reserved [0xC3] */
-
-/* Combine UBRR0L and UBRR0H */
-#define UBRR0	_SFR_MEM16(0xC4)
-
-#define UBRR0L	_SFR_MEM8(0xC4)
-#define UBRR0H	_SFR_MEM8(0xC5)
-
-#define UDR0	_SFR_MEM8(0XC6)
-
-#if !defined(__AVR_ATmega644__)
-/*
- * Only ATmega164P/324P/644P have a second USART.
- */
-/* Reserved [0xC7] */
-
-#define UCSR1A	_SFR_MEM8(0xC8)
-#define RXC1	7
-#define TXC1	6
-#define UDRE1	5
-#define FE1	4
-#define DOR1	3
-#define UPE1	2
-#define U2X1	1
-#define MPCM1	0
-
-#define UCSR1B	_SFR_MEM8(0XC9)
-#define RXCIE1	7
-#define TXCIE1	6
-#define UDRIE1	5
-#define RXEN1	4
-#define TXEN1	3
-#define UCSZ12	2
-#define RXB81	1
-#define TXB81	0
-
-#define UCSR1C	_SFR_MEM8(0xCA)
-#define UMSEL11 7
-#define UMSEL10 6
-#define UPM11	5
-#define UPM10	4
-#define USBS1	3
-#define UCSZ11	2
-#define UCSZ10	1
-#define UCPHA1  1
-#define UCPOL1	0
-
-/* Reserved [0xCB] */
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1	_SFR_MEM16(0xCC)
-
-#define UBRR1L	_SFR_MEM8(0xCC)
-#define UBRR1H	_SFR_MEM8(0xCD)
-
-#define UDR1	_SFR_MEM8(0XCE)
-#endif /* !defined(__AVR_ATmega644) */
-
-/* Reserved [0xCF..0xFF] */
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(4)
-#define SIG_PIN_CHANGE0			_VECTOR(4)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(5)
-#define SIG_PIN_CHANGE1			_VECTOR(5)
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect			_VECTOR(6)
-#define SIG_PIN_CHANGE2			_VECTOR(6)
-
-/* Pin Change Interrupt Request 3 */
-#define PCINT3_vect			_VECTOR(7)
-#define SIG_PIN_CHANGE3			_VECTOR(7)
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect			_VECTOR(8)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(8)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2A		_VECTOR(9)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE2B		_VECTOR(10)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW2			_VECTOR(11)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(12)
-#define SIG_INPUT_CAPTURE1		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(13)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(16)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(17)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(17)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(18)
-#define SIG_OVERFLOW0			_VECTOR(18)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(19)
-#define SIG_SPI				_VECTOR(19)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(20)
-#define SIG_USART_RECV			_VECTOR(20)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(21)
-#define SIG_USART_DATA			_VECTOR(21)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(22)
-#define SIG_USART_TRANS			_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(24)
-#define SIG_ADC				_VECTOR(24)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(25)
-#define SIG_EEPROM_READY		_VECTOR(25)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(26)
-#define SIG_2WIRE_SERIAL		_VECTOR(26)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(27)
-#define SIG_SPM_READY			_VECTOR(27)
-
-#if defined(__AVR_ATmega644__)
-
-# define _VECTORS_SIZE 112
-
-#else /* !defined(__AVR_ATmega644__) */
-
-/* USART1, Rx Complete */
-/* USART1 RX complete */
-#define USART1_RX_vect			_VECTOR(28)
-#define SIG_USART1_RECV			_VECTOR(28)
-
-/* USART1 Data register Empty */
-/* USART1 Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(29)
-#define SIG_USART1_DATA			_VECTOR(29)
-
-/* USART1, Tx Complete */
-/* USART1 TX complete */
-#define USART1_TX_vect			_VECTOR(30)
-#define SIG_USART1_TRANS		_VECTOR(30)
-
-# define _VECTORS_SIZE 124
-
-#endif /* defined(__AVR_ATmega644__) */
-
-
-/** @} */
-#endif /* _AVR_IOMXX4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxxhva.h b/cpukit/score/cpu/avr/avr/iomxxhva.h
deleted file mode 100644
index 2f62e18a0b..0000000000
--- a/cpukit/score/cpu/avr/avr/iomxxhva.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/**
- * @file iomxxhva.h
- *
- * @brief Definitions for ATmega8HVA and ATmega16HVA
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2007 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOMXXHVA_H_
-#define _AVR_IOMXXHVA_H_ 1
-
-/**
- *  @defgroup Avr_iomxxhva ATmega8HVA, ATmega16HVA Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iomxxhva.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0X00)
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0X03)
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC0   0
-
-/* Reserved [0x7] */
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-
-/* Reserved [0x9..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define ICF0    3
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIFR1   _SFR_IO8(0x16)
-#define ICF1    3
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-#define OSICSR  _SFR_IO8(0x17)
-#define OSISEL0 4
-#define OSIST   1
-#define OSIEN   0
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT2    2
-#define INT1    1
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR    _SFR_IO8(0x20)
-
-#define EEAR    _SFR_IO8(0x21)
-#define EEARL   _SFR_IO8(0x21)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* Reserved [0x22] */
-
-#define GTCCR   _SFR_IO8(0x23)
-#define TSM     7
-#define PSRSYNC 0
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define TCW0    7
-#define ICEN0   6
-#define ICNC0   5
-#define ICES0   4
-#define ICS0    3
-#define WGM00   0
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define TCNT0   _SFR_IO16(0X26)
-#define TCNT0L  _SFR_IO8(0X26)
-#define TCNT0H  _SFR_IO8(0X27)
-
-#define OCR0A   _SFR_IO8(0x28)
-
-#define OCR0B   _SFR_IO8(0X29)
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPIF    7
-#define WCOL    6
-#define SPI2X   0
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F..0x30] */
-
-#define DWDR    _SFR_IO8(0x31)
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define OCDRF   4
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0x35)
-#define CKOE    5
-#define PUD     4
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SIGRD   5
-#define CTPB    4
-#define RFLB    3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPCE  7
-#define CLKPS1  1
-#define CLKPS0  0
-
-/* Reserved [0x62..0x63] */
-
-#define PRR0    _SFR_MEM8(0x64)
-#define PRVRM   5
-#define PRSPI   3
-#define PRTIM1  2
-#define PRTIM0  1
-#define PRVADC  0
-
-/* Reserved [0x65] */
-
-#define FOSCCAL _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Reserved [0x6A..0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define ICIE0   3
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define ICIE1   3
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-/* Reserved [0x70..0x77] */
-
-#define VADC	_SFR_MEM16(0x78)
-#define VADCL	_SFR_MEM8(0x78)
-#define VADCH	_SFR_MEM8(0x79)
-
-#define VADCSR	_SFR_MEM8(0x7A)
-#define VADEN   3
-#define VADSC   2
-#define VADCCIF 1
-#define VADCCIE 0
-
-/* Reserved [0x7B] */
-
-#define VADMUX	_SFR_MEM8(0x7C)
-#define VADMUX3 3
-#define VADMUX2 2
-#define VADMUX1 1
-#define VADMUX0 0
-
-/* Reserved [0x7D] */
-
-#define DIDR0	_SFR_MEM8(0x7E)
-#define PA1DID  1
-#define PA0DID  0
-
-/* Reserved [0x7F] */
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define TCW1    7
-#define ICEN1   6
-#define ICNC1   5
-#define ICES1   4
-#define ICS1    3
-#define WGM10   0
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-/* Reserved [0x82..0x83] */
-
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Reserved [0x86..0x87] */
-
-#define OCR1A   _SFR_MEM8(0x88)
-
-#define OCR1B   _SFR_MEM8(0x89)
-
-/* Reserved [0x8A..0xC7] */
-
-#define ROCR    _SFR_MEM8(0xC8)
-#define ROCS    7
-#define ROCWIF  1
-#define ROCWIE  0
-
-/* Reserved [0xC9..0xCF] */
-
-#define BGCCR   _SFR_MEM8(0xD0)
-#define BGD     7
-#define BGCC5   5
-#define BGCC4   4
-#define BGCC3   3
-#define BGCC2   2
-#define BGCC1   1
-#define BGCC0   0
-
-#define BGCRR   _SFR_MEM8(0xD1)
-#define BGCR7   7
-#define BGCR6   6
-#define BGCR5   5
-#define BGCR4   4
-#define BGCR3   3
-#define BGCR2   2
-#define BGCR1   1
-#define BGCR0   0
-
-/* Reserved [0xD2..0xDF] */
-
-/* CC-ADC Accumulate Current */
-/* TODO: Add _SFR_MEM32 */
-/* #define CADAC   _SFR_MEM32(0xE0) */
-#define CADAC0  _SFR_MEM8(0xE0)
-#define CADAC1  _SFR_MEM8(0xE1)
-#define CADAC2  _SFR_MEM8(0xE2)
-#define CADAC3  _SFR_MEM8(0xE3)
-
-#define CADCSRA _SFR_MEM8(0xE4)
-#define CADEN   7
-#define CADPOL  6
-#define CADUB   5
-#define CADAS1  4
-#define CADAS0  3
-#define CADSI1  2
-#define CADSI0  1
-#define CADSE   0
-
-#define CADCSRB _SFR_MEM8(0xE5)
-#define CADACIE 6
-#define CADRCIE 5
-#define CADICIE 4
-#define CADACIF 2
-#define CADRCIF 1
-#define CADICIF 0
-
-#define CADRC   _SFR_MEM8(0xE6)
-
-/* Reserved [0xE7] */
-
-#define CADIC   _SFR_MEM16(0xE8)
-#define CADICL  _SFR_MEM8(0xE8)
-#define CADICH  _SFR_MEM8(0xE9)
-
-/* Reserved [0xEA..0xEF] */
-
-#define FCSR    _SFR_MEM8(0xF0)
-#define DUVRD   3
-#define CPS     2
-#define DFE     1
-#define CFE     0
-
-/* Reserved [0xF1] */
-
-#define BPIMSK  _SFR_MEM8(0xF2)
-#define SCIE    4
-#define DOCIE   3
-#define COCIE   2
-#define DHCIE   1
-#define CHCIE   0
-
-#define BPIFR   _SFR_MEM8(0xF3)
-#define SCIF    4
-#define DOCIF   3
-#define COCIF   2
-#define DHCIF   1
-#define CHCIF   0
-
-/* Reserved [0xF4] */
-
-#define BPSCD   _SFR_MEM8(0xF5)
-
-#define BPDOCD  _SFR_MEM8(0xF6)
-
-#define BPCOCD  _SFR_MEM8(0xF7)
-
-#define BPDHCD  _SFR_MEM8(0xF8)
-
-#define BPCHCD  _SFR_MEM8(0xF9)
-
-#define BPSCTR  _SFR_MEM8(0xFA)
-
-#define BPOCTR  _SFR_MEM8(0xFB)
-
-#define BPHCTR  _SFR_MEM8(0xFC)
-
-#define BPCR    _SFR_MEM8(0xFD)
-#define SCD     4
-#define DOCD    3
-#define COCD    2
-#define DHCD    1
-#define CHCD    0
-
-#define BPPLR   _SFR_MEM8(0xFE)
-#define BPPLE   1
-#define BPPL    0
-
-/* Reserved [0xFF] */
-
-/* Interrupt vectors */
-/* Battery Protection Interrupt */
-#define BPINT_vect			_VECTOR(1)
-
-/* Voltage Regulator Monitor Interrupt */
-#define VREGMON_vect			_VECTOR(2)
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(3)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(4)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(5)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(6)
-
-/* Timer/Counter 1 Input Capture */
-#define TIMER1_IC_vect			_VECTOR(7)
-
-/* Timer/Counter 1 Compare A Match */
-#define TIMER1_COMPA_vect		_VECTOR(8)
-
-/* Timer/Counter 1 Compare B Match */
-#define TIMER1_COMPB_vect		_VECTOR(9)
-
-/* Timer/Counter 1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(10)
-
-/* Timer/Counter 0 Input Capture */
-#define TIMER0_IC_vect			_VECTOR(11)
-
-/* Timer/Counter0 Compare A Match */
-#define TIMER0_COMPA_vect		_VECTOR(12)
-
-/* Timer/Counter0 Compare B Match */
-#define TIMER0_COMPB_vect		_VECTOR(13)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(14)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(15)
-
-/* Voltage ADC Conversion Complete */
-#define VADC_vect			_VECTOR(16)
-
-/* Coulomb Counter ADC Conversion Complete */
-#define CCADC_CONV_vect			_VECTOR(17)
-
-/* Coloumb Counter ADC Regular Current */
-#define CCADC_REG_CUR_vect		_VECTOR(18)
-
-/* Coloumb Counter ADC Accumulator */
-#define CCADC_ACC_vect			_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-
-#if defined (__AVR_ATmega16HVA__)
-#  define _VECTORS_SIZE 84
-#else
-#  define _VECTORS_SIZE 42
-#endif
-
-/**@}*/
-#endif  /* _AVR_IOMXXHVA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn11.h b/cpukit/score/cpu/avr/avr/iotn11.h
deleted file mode 100644
index 8310f560ed..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn11.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/**
- * @file avr/iotn11.h
- *
- * @brief Definitions for ATtiny10/11
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2002, 2005 Marek Michalkiewicz
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN11_H_
-#define _AVR_IOTN11_H_ 1
-
-/**
- *  @defgroup Avr_iotn11 ATtiny10/11 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn11.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/* I/O registers */
-
-/* 0x00..0x07 reserved */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x15 reserved */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* 0x19..0x20 reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22..0x31 reserved */
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 0 */
-#define IO_PINS_vect			_VECTOR(2)
-#define SIG_PIN				_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(3)
-#define SIG_OVERFLOW0			_VECTOR(3)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(4)
-#define SIG_COMPARATOR			_VECTOR(4)
-
-#define _VECTORS_SIZE 10
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT0	6
-#define PCIE	5
-
-/* GIFR */
-#define INTF0	6
-#define PCIF	5
-
-/* TIMSK */
-#define TOIE0	1
-
-/* TIFR */
-#define TOV0	1
-
-/* MCUCR */
-#define SE	5
-#define SM	4
-#define ISC01	1
-#define ISC00	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/*
-   PB5 = RESET#
-   PB4 = XTAL2
-   PB3 = XTAL1
-   PB2 = T0
-   PB1 = INT0 / AIN1
-   PB0 = AIN0
- */
-
-/* PORTB */
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* ACSR */
-#define ACD	7
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x0
-#define E2PAGESIZE  2
-#define FLASHEND	0x3FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(3)
-#define FUSE_FSTRT       (unsigned char)~_BV(4)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x04
-
-
-/**@}*/
-#endif /* _AVR_IOTN11_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn12.h b/cpukit/score/cpu/avr/avr/iotn12.h
deleted file mode 100644
index 5851dee68b..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn12.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/**
- * @file avr/iotn12.h
- *
- * @brief Definitions for ATtiny12
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002,2005 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN12_H_
-#define _AVR_IOTN12_H_ 1
-
-/**
- *  @defgroup Avr_iotn12 ATtiny12 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn12.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/* I/O registers */
-
-/* 0x00..0x07 reserved */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x15 reserved */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* 0x19..0x1B reserved */
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* 0x1F..0x20 reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22..0x30 reserved */
-
-/* Oscillator Calibration Register */
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 0 */
-#define IO_PINS_vect			_VECTOR(2)
-#define SIG_PIN				_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(3)
-#define SIG_OVERFLOW0			_VECTOR(3)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(4)
-#define SIG_EEPROM_READY		_VECTOR(4)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(5)
-#define SIG_COMPARATOR			_VECTOR(5)
-
-#define _VECTORS_SIZE 12
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT0	6
-#define PCIE	5
-
-/* GIFR */
-#define INTF0	6
-#define PCIF	5
-
-/* TIMSK */
-#define TOIE0	1
-
-/* TIFR */
-#define TOV0	1
-
-/* MCUCR */
-#define PUD	6
-#define SE	5
-#define SM	4
-#define ISC01	1
-#define ISC00	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/*
-   PB5 = RESET#
-   PB4 = XTAL2
-   PB3 = XTAL1
-   PB2 = T0 / SCK
-   PB1 = INT0 / AIN1 / MISO
-   PB0 = AIN0 / MOSI
- */
-
-/* PORTB */
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x3F
-#define E2PAGESIZE  2
-#define FLASHEND	0x3FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x05
-
-/**@}*/
-#endif /* _AVR_IOTN12_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn13.h b/cpukit/score/cpu/avr/avr/iotn13.h
deleted file mode 100644
index 3f491fa914..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn13.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/**
- * @file avr/iotn13.h
- *
- * @brief Definitions for ATtiny13
- *
- * Verified 5/20/04 by Bruce Graham
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2004, Theodore A. Roth
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN13_H_
-#define _AVR_IOTN13_H_ 1
-
-/**
- *  @defgroup Avr_iotn13 ATtiny13 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn13.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers and bit names */
-
-/* ADC Control and Status Register B */
-#define ADCSRB               _SFR_IO8(0x03)
-#  define ACME                 6
-#  define ADTS2                2
-#  define ADTS1                1
-#  define ADTS0                0
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC                  _SFR_IO16 (0x04)
-#endif
-#define ADCW                 _SFR_IO16 (0x04)
-#define ADCL                 _SFR_IO8(0x04)
-#define ADCH                 _SFR_IO8(0x05)
-
-/* ADC Control and Status Register A */
-#define ADCSRA               _SFR_IO8(0x06)
-#  define ADEN                 7
-#  define ADSC                 6
-#  define ADATE                5
-#  define ADIF                 4
-#  define ADIE                 3
-#  define ADPS2                2
-#  define ADPS1                1
-#  define ADPS0                0
-
-/* ADC Multiplex Selection Register */
-#define ADMUX                _SFR_IO8(0x07)
-#  define REFS0                6
-#  define ADLAR                5
-#  define MUX1                 1
-#  define MUX0                 0
-
-/* Analog Comparator Control and Status Register */
-#define ACSR                 _SFR_IO8(0x08)
-#  define ACD                  7
-#  define ACBG                 6
-#  define ACO                  5
-#  define ACI                  4
-#  define ACIE                 3
-#  define ACIS1                1
-#  define ACIS0                0
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                _SFR_IO8(0x14)
-#  define ADC0D                5
-#  define ADC2D                4
-#  define ADC3D                3
-#  define ADC1D                2
-#  define AIN1D                1
-#  define AIN0D                0
-
-/* PIN Change Mask Register */
-#define PCMSK                _SFR_IO8(0x15)
-#  define PCINT5               5
-#  define PCINT4               4
-#  define PCINT3               3
-#  define PCINT2               2
-#  define PCINT1               1
-#  define PCINT0               0
-
-/* Port B Pin Utilization [2535D-AVR-04/04]
-   - PORTB5 = PCINT5/RESET#/ADC0/dW
-   - PORTB4 = PCINT4/ADC2
-   - PORTB3 = PCINT3/CLKI/ADC3
-   - PORTB2 = SCK/ADC1/T0/PCINT2
-   - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1
-   - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */
-
-/* Input Pins, Port B */
-#define PINB                 _SFR_IO8(0x16)
-#  define PINB5                5
-#  define PINB4                4
-#  define PINB3                3
-#  define PINB2                2
-#  define PINB1                1
-#  define PINB0                0
-
-/* Data Direction Register, Port B */
-#define DDRB                 _SFR_IO8(0x17)
-#  define DDB5                 5
-#  define DDB4                 4
-#  define DDB3                 3
-#  define DDB2                 2
-#  define DDB1                 1
-#  define DDB0                 0
-
-/* Data Register, Port B */
-#define PORTB                _SFR_IO8(0x18)
-#  define PB5                  5
-#  define PB4                  4
-#  define PB3                  3
-#  define PB2                  2
-#  define PB1                  1
-#  define PB0                  0
-
-/* ATtiny EEPROM Control Register EECR */
-#define EECR	             _SFR_IO8(0x1C)
-#define EEPM1                  5
-#define EEPM0                  4
-#define EERIE                  3
-#define EEMPE                  2
-#define EEPE                   1
-#define EERE                   0
-
-/* EEPROM Data Register */
-#define EEDR	             _SFR_IO8(0x1D)
-
-/* The EEPROM Address Register EEAR[6:0] */
-#define EEAR	             _SFR_IO8(0x1E)
-#define EEARL	             _SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR                _SFR_IO8(0x21)
-#  define WDTIF                7
-#  define WDTIE                6
-#  define WDP3                 5
-#  define WDCE                 4
-#  define WDE                  3
-#  define WDP2                 2
-#  define WDP1                 1
-#  define WDP0                 0
-
-/* Clock Prescale Register */
-#define CLKPR                _SFR_IO8(0x26)
-#  define CLKPCE               7
-#  define CLKPS3               3
-#  define CLKPS2               2
-#  define CLKPS1               1
-#  define CLKPS0               0
-
-/* General Timer/Counter Control Register */
-#define GTCCR                _SFR_IO8(0x28)
-#  define TSM                  7
-#  define PSR10                0
-
-/* Output Compare 0 Register B */
-#define OCR0B                _SFR_IO8(0x29)
-
-/* debugWIRE Data Register */
-#define DWDR                 _SFR_IO8(0x2e)
-
-/* Timer/Counter 0 Control Register A */
-#define TCCR0A               _SFR_IO8(0x2f)
-#  define COM0A1               7
-#  define COM0A0               6
-#  define COM0B1               5
-#  define COM0B0               4
-#  define WGM01                1
-#  define WGM00                0
-
-/* Oscillator Calibration Register */
-#define OSCCAL               _SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0                _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register B */
-#define TCCR0B               _SFR_IO8(0x33)
-#  define FOC0A                7
-#  define FOC0B                6
-#  define WGM02                3
-#  define CS02                 2
-#  define CS01                 1
-#  define CS00                 0
-
-/* MCU General Status Register */
-#define MCUSR                _SFR_IO8(0x34)
-#  define WDRF                 3
-#  define BORF                 2
-#  define EXTRF                1
-#  define PORF                 0
-
-/* MCU General Control Register */
-#define MCUCR                _SFR_IO8(0x35)
-#  define PUD                  6
-#  define SE                   5
-#  define SM1                  4
-#  define SM0                  3
-#  define ISC01                1
-#  define ISC00                0
-
-/* Output Compare 0 REgister A */
-#define OCR0A                _SFR_IO8(0x36)
-
-/* Store Program Memory Control and Status Register */
-#define SPMCSR               _SFR_IO8(0x37)
-#  define CTPB                 4
-#  define RFLB                 3
-#  define PGWRT                2
-#  define PGERS                1
-#  define SPMEN                0
-#  define SELFPRGEN            0
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0                _SFR_IO8(0x38)
-#  define OCF0B                3
-#  define OCF0A                2
-#  define TOV0                 1
-
-/* Timer/Counter 0 Interrupt MaSK Register */
-#define TIMSK0               _SFR_IO8(0x39)
-#  define OCIE0B               3
-#  define OCIE0A               2
-#  define TOIE0                1
-
-/* General Interrupt Flag Register */
-#define GIFR                 _SFR_IO8(0x3a)
-#  define INTF0                6
-#  define PCIF                 5
-
-/* General Interrupt MaSK register */
-#define GIMSK                _SFR_IO8(0x3b)
-#  define INT0                 6
-#  define PCIE                 5
-
-/* SPL and SREG are defined in <avr/io.h> */
-
-/* From the datasheet:
-   1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset
-   2 0x0001 INT0 External Interrupt Request 0
-   3 0x0002 PCINT0 Pin Change Interrupt Request 0
-   4 0x0003 TIM0_OVF Timer/Counter Overflow
-   5 0x0004 EE_RDY EEPROM Ready
-   6 0x0005 ANA_COMP Analog Comparator
-   7 0x0006 TIM0_COMPA Timer/Counter Compare Match A
-   8 0x0007 TIM0_COMPB Timer/Counter Compare Match B
-   9 0x0008 WDT Watchdog Time-out
-   10 0x0009 ADC ADC Conversion Complete */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Timer/Counter0 Overflow */
-#define TIM0_OVF_vect			_VECTOR(3)
-#define SIG_OVERFLOW0			_VECTOR(3)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(4)
-#define SIG_EEPROM_READY		_VECTOR(4)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(5)
-#define SIG_COMPARATOR			_VECTOR(5)
-
-/* Timer/Counter Compare Match A */
-#define TIM0_COMPA_vect			_VECTOR(6)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(6)
-
-/* Timer/Counter Compare Match B */
-#define TIM0_COMPB_vect			_VECTOR(7)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(7)
-
-/* Watchdog Time-out */
-#define WDT_vect			_VECTOR(8)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(8)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(9)
-#define SIG_ADC				_VECTOR(9)
-
-#define _VECTORS_SIZE 20
-
-#define SPM_PAGESIZE 32
-#define RAMEND      0x9F
-#define XRAMEND     RAMEND
-#define E2END       0x3F
-#define E2PAGESIZE  4
-#define FLASHEND    0x3FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_SUT0        (unsigned char)~_BV(2)
-#define FUSE_SUT1        (unsigned char)~_BV(3)
-#define FUSE_CKDIV8      (unsigned char)~_BV(4)
-#define FUSE_WDTON       (unsigned char)~_BV(5)
-#define FUSE_EESAVE      (unsigned char)~_BV(6)
-#define FUSE_SPIEN       (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN)
-
-/* High Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_DWEN        (unsigned char)~_BV(3)
-#define FUSE_SPMEN       (unsigned char)~_BV(4)
-#define HFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x07
-
-
-/**@}*/
-#endif /* _AVR_IOTN13_H_*/
diff --git a/cpukit/score/cpu/avr/avr/iotn13a.h b/cpukit/score/cpu/avr/avr/iotn13a.h
deleted file mode 100644
index 689f4032d6..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn13a.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/* Copyright (c) 2008 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn13a.h - definitions for ATtiny13 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn13a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATTINY13A_H_
-#define _AVR_ATTINY13A_H_ 1
-
-/**
- * @name Registers and Associated Bit Numbers
- * 
- */
-/**@{**/
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define ADLAR 5
-#define REFS0 6
-
-#define ACSR _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define DIDR0 _SFR_IO8(0x14)
-#define AIN0D 0
-#define AIN1D 1
-#define ADC1D 2
-#define ADC3D 3
-#define ADC2D 4
-#define ADC0D 5
-
-#define PCMSK _SFR_IO8(0x15)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEARL _SFR_IO8(0x1E)
-
-#define EEAR _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-
-#define WDTCR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDTIE 6
-#define WDTIF 7
-
-#define PRR _SFR_IO8(0x25)
-#define PRADC 0
-#define PRTIM0 1
-
-#define CLKPR _SFR_IO8(0x26)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define GTCCR _SFR_IO8(0x28)
-#define PSR10 0
-#define TSM 7
-
-#define OCR0B _SFR_IO8(0x29)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define DWDR _SFR_IO8(0x2E)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define TCCR0A _SFR_IO8(0x2F)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define BODCR _SFR_IO8(0x30)
-#define BPDSE 0
-#define BPDS 1
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define TCNT0 _SFR_IO8(0x32)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-
-#define OCR0A _SFR_IO8(0x36)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR0 _SFR_IO8(0x38)
-#define TOV0 1
-#define OCF0A 2
-#define OCF0B 3
-
-#define TIMSK0 _SFR_IO8(0x39)
-#define TOIE0 1
-#define OCIE0A 2
-#define OCIE0B 3
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF 5
-#define INTF0 6
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE 5
-#define INT0 6
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* External Interrupt Request 0 */
-#define TIM0_OVF_vect_num  3
-#define TIM0_OVF_vect      _VECTOR(3)  /* Timer/Counter0 Overflow */
-#define EE_RDY_vect_num  4
-#define EE_RDY_vect      _VECTOR(4)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  5
-#define ANA_COMP_vect      _VECTOR(5)  /* Analog Comparator */
-#define TIM0_COMPA_vect_num  6
-#define TIM0_COMPA_vect      _VECTOR(6)  /* Timer/Counter Compare Match A */
-#define TIM0_COMPB_vect_num  7
-#define TIM0_COMPB_vect      _VECTOR(7)  /* Timer/Counter Compare Match B */
-#define WDT_vect_num  8
-#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out */
-#define ADC_vect_num  9
-#define ADC_vect      _VECTOR(9)  /* ADC Conversion Complete */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE (32)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (64)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      RAMEND
-#define E2END        (64 - 1)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (1024 - 1)
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_SUT0 (unsigned char)~_BV(2)  /* Select start-up time */
-#define FUSE_SUT1 (unsigned char)~_BV(3)  /* Select start-up time */
-/* Start up with system clock divided by 8 */
-#define FUSE_CKDIV8 (unsigned char)~_BV(4)  
-#define FUSE_WDTON (unsigned char)~_BV(5)  /* Watch dog timer always on */
-/* Keep EEprom contents during chip erase */
-#define FUSE_EESAVE (unsigned char)~_BV(6)  
-#define FUSE_SPIEN (unsigned char)~_BV(7)  /* SPI programming enable */
-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_RSTDISBL (unsigned char)~_BV(0)  /* Disable external reset */
-/* Enable BOD and select level */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)  
-/* Enable BOD and select level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)  
-#define FUSE_DWEN (unsigned char)~_BV(3)  /* DebugWire Enable */
-#define FUSE_SELFPRGEN (unsigned char)~_BV(4)  /* Self Programming Enable */
-#define HFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x07
-/** @} */
-
-#endif /* _AVR_ATTINY13A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn15.h b/cpukit/score/cpu/avr/avr/iotn15.h
deleted file mode 100644
index 3e7ac81487..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn15.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/**
- * @file avr/iotn15.h
- *
- * @brief Definitions for ATtiny15
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002,2005 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN15_H_
-#define _AVR_IOTN15_H_ 1
-
-/**
- * @defgroup AvrDef_iotn15 ATtiny15 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn15.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/* I/O registers */
-
-/* 0x00..0x03 reserved */
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16 (0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-#define ADCSR	_SFR_IO8(0x06)
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x15 reserved */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* 0x19..0x1B reserved */
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* 0x1F..0x20 reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22..0x2B reserved */
-#define SFIOR	_SFR_IO8(0x2C)
-
-#define OCR1B	_SFR_IO8(0x2D)
-#define OCR1A	_SFR_IO8(0x2E)
-#define TCNT1	_SFR_IO8(0x2F)
-#define TCCR1	_SFR_IO8(0x30)
-
-/* Oscillator Calibration Register */
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 0 */
-#define IO_PINS_vect			_VECTOR(2)
-#define SIG_PIN				_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(3)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW1			_VECTOR(4)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW0			_VECTOR(5)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(6)
-#define SIG_EEPROM_READY		_VECTOR(6)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(7)
-#define SIG_COMPARATOR			_VECTOR(7)
-
-/* ADC Conversion Ready */
-#define ADC_vect			_VECTOR(8)
-#define SIG_ADC				_VECTOR(8)
-
-#define _VECTORS_SIZE 18
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT0	6
-#define PCIE	5
-
-/* GIFR */
-#define INTF0	6
-#define PCIF	5
-
-/* TIMSK */
-#define OCIE1	6
-#define TOIE1	2
-#define TOIE0	1
-
-/* TIFR */
-#define OCF1	6
-#define TOV1	2
-#define TOV0	1
-
-/* MCUCR */
-#define PUD	6
-#define SE	5
-#define SM1	4
-#define SM0	3
-#define ISC01	1
-#define ISC00	0
-
-/* MCUSR */
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR1 */
-#define CTC1	7
-#define PWM1	6
-#define COM1A1	5
-#define COM1A0	4
-#define CS13	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* SFIOR */
-#define FOC1A	2
-#define PSR1	1
-#define PSR0	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/*
-   PB5 = RESET# / ADC0
-   PB4 = ADC3
-   PB3 = ADC2
-   PB2 = SCK / ADC1 / T0 / INT0
-   PB1 = MISO / AIN1 / OCP
-   PB0 = MOSI / AIN0 / AREF
- */
-
-/* PORTB */
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* ACSR */
-#define ACD	7
-#define GREF	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* ADMUX */
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* ADCSR */
-#define ADEN	7
-#define ADSC	6
-#define ADFR	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x3F
-#define E2PAGESIZE  2
-#define FLASHEND	0x3FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x06
-
-/** @} */
-#endif /* _AVR_IOTN15_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn167.h b/cpukit/score/cpu/avr/avr/iotn167.h
deleted file mode 100644
index 53202b33a2..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn167.h
+++ /dev/null
@@ -1,846 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny167
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2008 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iotn167.h - definitions for ATtiny167. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn167.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IOTN167_H_
-#define _AVR_IOTN167_H_ 1
-
-/**
- * @defgroup AvrDef_iotn167 ATtiny167 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PORTCR _SFR_IO8(0x12)
-#define PUDA 0
-#define PUDB 2
-#define BBMA 4
-#define BBMB 5
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR1 0
-#define PSR0 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x25)
-#define WGM00 0
-#define WGM01 1
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x26)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x27)
-#define TCNT00 0
-#define TCNT01 1
-#define TCNT02 2
-#define TCNT03 3
-#define TCNT04 4
-#define TCNT05 5
-#define TCNT06 6
-#define TCNT07 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR00 0
-#define OCR01 1
-#define OCR02 2
-#define OCR03 3
-#define OCR04 4
-#define OCR05 5
-#define OCR06 6
-#define OCR07 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACIRS 6
-#define ACD 7
-
-#define DWDR _SFR_IO8(0x31)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define BODS 5
-#define BODSE 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-#define SIGRD 5
-#define RWWSB 6
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define CLKCSR _SFR_MEM8(0x62)
-#define CLKC0 0
-#define CLKC1 1
-#define CLKC2 2
-#define CLKC3 3
-#define CLKRDY 4
-#define CLKCCE 7
-
-#define CLKSELR _SFR_MEM8(0x63)
-#define CSEL0 0
-#define CSEL1 1
-#define CSEL2 2
-#define CSEL3 3
-#define CSUT0 4
-#define CSUT1 5
-#define COUT 6
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-#define PRSPI 4
-#define PRLIN 5
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMISCR _SFR_MEM8(0x77)
-#define ISRCEN 0
-#define XREFEN 1
-#define AREFEN 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACIR0 4
-#define ACIR1 5
-#define ACME 6
-#define BIN 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCCR1D _SFR_MEM8(0x83)
-#define OC1AU 0
-#define OC1AV 1
-#define OC1AW 2
-#define OC1AX 3
-#define OC1BU 4
-#define OC1BV 5
-#define OC1BW 6
-#define OC1BX 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM8(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR0BUB 0
-#define TCR0AUB 1
-#define OCR0AUB 3
-#define TCN0UB 4
-#define AS0 5
-#define EXCLK 6
-
-#define USICR _SFR_MEM8(0xB8)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_MEM8(0xBA)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_MEM8(0xBB)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define USIPP _SFR_MEM8(0xBC)
-#define USIPOS 0
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-#define INT0_vect           _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect           _VECTOR(2)  /* External Interrupt Request 1 */
-#define PCINT0_vect         _VECTOR(3)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect         _VECTOR(4)  /* Pin Change Interrupt Request 1 */
-#define WDT_vect            _VECTOR(5)  /* Watchdog Time-Out Interrupt */
-#define TIMER1_CAPT_vect    _VECTOR(6)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(7)  /* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPB_vect   _VECTOR(8)  /* Timer/Counter1 Compare Match 1B */
-#define TIMER1_OVF_vect     _VECTOR(9)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(10)  /* Timer/Counter0 Compare Match 0A */
-#define TIMER0_OVF_vect     _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define LIN_TC_vect         _VECTOR(12)  /* LIN Transfer Complete */
-#define LIN_ERR_vect        _VECTOR(13)  /* LIN Error */
-#define SPI_STC_vect        _VECTOR(14)  /* SPI Serial Transfer Complete */
-#define ADC_vect            _VECTOR(15)  /* ADC Conversion Complete */
-#define EE_RDY_vect         _VECTOR(16)  /* EEPROM Ready */
-#define ANA_COMP_vect       _VECTOR(17)  /* Analog Comparator */
-#define USI_START_vect      _VECTOR(18)  /* USI Start */
-#define USI_OVF_vect        _VECTOR(19)  /* USI Overflow */
-
-#define _VECTORS_SIZE (20 * 4)
-
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (0x1FF)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)  /* Last On-Chip SRAM Location */
-#define XRAMSIZE     (0)
-#define XRAMEND      RAMEND
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4) 
-#define FLASHEND     (0x3FFF)
-
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer always ON */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x87
-
-/** @} */
-
-#endif  /* _AVR_IOTN167_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn22.h b/cpukit/score/cpu/avr/avr/iotn22.h
deleted file mode 100644
index 6eda011fc9..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn22.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn22.h - definitions for ATtiny22 */
-
-#ifndef _AVR_IOTN22_H_
-#define _AVR_IOTN22_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn22.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-#define _VECTORS_SIZE 6
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt MaSK register */
-#define    INT0    6
-#define    INTF0   6
-
-/* General Interrupt Flag Register */
-#define    TOIE0   1
-#define    TOV0    1
-
-/* MCU general Control Register */
-#define    SE      5
-#define    SM      4
-#define    ISC01   1
-#define    ISC00   0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
-
-/*
-   PB2 = SCK/T0
-   PB1 = MISO/INT0
-   PB0 = MOSI
- */
-
-/* Data Register, Port B */
-#define    PB4     4
-#define    PB3     3
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
-
-/* Data Direction Register, Port B */
-#define    DDB4    4
-#define    DDB3    3
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
-
-/* Input Pins, Port B */
-#define    PINB4   4
-#define    PINB3   3
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-
-/* Constants */
-#define RAMEND     0xDF
-#define XRAMEND    RAMEND
-#define E2END      0x7F
-#define E2PAGESIZE 0
-#define FLASHEND   0x07FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_CKSEL       (unsigned char)~_BV(0)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x06
-
-
-#endif /* _AVR_IOTN22_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn2313.h b/cpukit/score/cpu/avr/avr/iotn2313.h
deleted file mode 100644
index 21a00522a3..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn2313.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny2313
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004, 2005, 2006 Bob Paddock
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iotn2313.h derived from io2313.h by Bob Paddock.
-
-   The changes between the AT90S2313 and the ATtiny2313 are extensive.
-
-   Atmel has renamed several registers, and bits.  See Atmel application note
-   AVR091, as well as the errata at the end of the current ATtiny2313 data
-   sheet.  Some of the names have changed more than once during the sampling
-   period of the ATtiny2313.
-
-   Where there is no conflict the new and old names are both supported.
-
-   In the case of a new feature in a register, only the new name is used.
-   This intentionally breaks old code, so that there are no silent bugs.  The
-   source code must be updated to the new name in this case.
-
-   The hardware interrupt vector table has changed from that of the AT90S2313.
-
-   ATtiny2313 programs in page mode rather than the byte mode of the
-   AT90S2313.  Beware of programming the ATtiny2313 as a AT90S2313 device,
-   when programming the Flash.
-
-   ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A.
-
-   Changes and/or additions are noted by "ATtiny" in the comments below. */
-
-/* avr/iotn2313.h - definitions for ATtiny2313 */
-
-#ifndef _AVR_IOTN2313_H_
-#define _AVR_IOTN2313_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn2313.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_iotn2313 ATtiny2313 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/*
- *  The Register Bit names are represented by their bit number (0-7).
- *  Example: PORTB |= _BV(PORTB7); Set MSB of PORTB.
- */
-
-/* 0x00 Reserved */
-
-/* ATtiny Digital Input Disable Register DIDR */
-#define DIDR    _SFR_IO8(0x01)
-
-#define AIN1D   1
-#define AIN0D   0
-
-/* ATtiny USART Baud Rate Register High UBBRH[11:8] */
-#define UBRRH   _SFR_IO8(0x02)
-
-/* ATtiny USART Control and Status Register C UCSRC */
-#define UCSRC   _SFR_IO8(0x03)
-
-#define UMSEL   6
-#define UPM1    5
-#define UPM0    4
-#define USBS    3
-#define UCSZ1   2
-#define UCSZ0   1
-#define UCPOL   0
-
-/* 0x04 -> 0x07 Reserved */
-
-/* ATtiny Analog Comparator Control and Status Register ACSR */
-#define ACSR    _SFR_IO8(0x08)
-
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-/* USART Baud Rate Register Low UBBRL[7:0] */
-#define UBRRL   _SFR_IO8(0x09)
-
-/* ATtiny USART Control Register UCSRB */
-#define UCSRB   _SFR_IO8(0x0A)
-
-#define RXCIE   7
-#define TXCIE   6
-#define UDRIE   5
-#define RXEN    4
-#define TXEN    3
-#define UCSZ2   2
-#define RXB8    1
-#define TXB8    0
-
-/* ATtiny USART Status Register UCSRA */
-#define UCSRA   _SFR_IO8(0x0B)
-
-#define RXC     7
-#define TXC     6
-#define UDRE    5
-#define FE      4
-#define DOR     3
-#define UPE     2
-#define U2X     1
-#define MPCM    0
-
-/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */
-#define UDR     _SFR_IO8(0x0C)
-#define RXB     _SFR_IO8(0x0C)
-#define TXB     _SFR_IO8(0x0C)
-
-/* ATtiny USI Control Register USICR */
-#define USICR   _SFR_IO8(0x0D)
-
-#define USISIE  7
-#define USIOIE  6
-#define USIWM1  5
-#define USIWM0  4
-#define USICS1  3
-#define USICS0  2
-#define USICLK  1
-#define USITC   0
-
-/* ATtiny USI Status Register USISR */
-#define USISR   _SFR_IO8(0x0E)
-
-#define USISIF  7
-#define USIOIF  6
-#define USIPF   5
-#define USIDC   4
-#define USICNT3 3
-#define USICNT2 2
-#define USICNT1 1
-#define USICNT0 0
-
-/* ATtiny USI Data Register USIDR[7:0] */
-#define USIDR   _SFR_IO8(0x0F)
-
-/* Input Pins, Port D PIND[6:0] */
-#define PIND    _SFR_IO8(0x10)
-
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* Data Direction Register, Port D DDRD[6:0] */
-#define DDRD    _SFR_IO8(0x11)
-
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* Data Register, Port D PORTD[6:0] */
-#define PORTD   _SFR_IO8(0x12)
-
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */
-#define GPIOR0  _SFR_IO8(0x13)
-
-/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */
-#define GPIOR1  _SFR_IO8(0x14)
-
-/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */
-#define GPIOR2  _SFR_IO8(0x15)
-
-/* Input Pins, Port B PORTB[7:0] */
-#define PINB    _SFR_IO8(0x16)
-
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/* Data Direction Register, Port B PORTB[7:0] */
-#define DDRB    _SFR_IO8(0x17)
-
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* Data Register, Port B PORTB[7:0] */
-#define PORTB   _SFR_IO8(0x18)
-
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Port A Input Pins Address PINA[2:0] */
-#define PINA    _SFR_IO8(0x19)
-
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-/* Port A Data Direction Register DDRA[2:0] */
-#define DDRA    _SFR_IO8(0x1A)
-
-#define DDRA2   2
-#define DDRA1   1
-#define DDRA0   0
-
-/* Port A Data Register PORTA[2:0] */
-#define PORTA   _SFR_IO8(0x1B)
-
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-/* ATtiny EEPROM Control Register EECR */
-#define EECR	_SFR_IO8(0x1C)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* The EEPROM Address Register EEAR[6:0] */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEAR6   6
-#define EEAR5   5
-#define EEAR4   4
-#define EEAR3   3
-#define EEAR2   2
-#define EEAR1   1
-#define EEAR0   0
-
-/* 0x1F Reserved */
-
-/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */
-#define PCMSK   _SFR_IO8(0x20)
-
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-/* ATtiny Watchdog Timer Control Register WDTCSR */
-#define WDTCSR  _SFR_IO8(0x21)
-
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-/* ATtiny Timer/Counter1 Control Register C TCCR1C */
-#define TCCR1C  _SFR_IO8(0x22)
-
-#define FOC1A   7
-#define FOC1B   6
-
-/* General Timer/Counter Control Register GTCCR */
-#define GTCCR   _SFR_IO8(0x23)
-
-#define PSR10   0
-
-/* T/C 1 Input Capture Register ICR1[15:0] */
-#define ICR1    _SFR_IO16(0x24)
-#define ICR1L   _SFR_IO8(0x24)
-#define ICR1H   _SFR_IO8(0x25)
-
-/* ATtiny Clock Prescale Register */
-#define CLKPR   _SFR_IO8(0x26)
-
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-/* 0x27 Reserved */
-
-/* ATtiny Output Compare Register 1 B OCR1B[15:0] */
-#define OCR1B   _SFR_IO16(0x28)
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Output Compare Register 1 OCR1A[15:0] */
-#define OCR1    _SFR_IO16(0x2A)
-#define OCR1L   _SFR_IO8(0x2A)
-#define OCR1H   _SFR_IO8(0x2B)
-#define OCR1A   _SFR_IO16(0x2A)
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 TCNT1[15:0] */
-#define TCNT1   _SFR_IO16(0x2C)
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */
-#define TCCR1B  _SFR_IO8(0x2E)
-
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3 /* Was CTC1 in AT90S2313 */
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-/* ATtiny Timer/Counter 1 Control Register TCCR1A */
-#define TCCR1A  _SFR_IO8(0x2F)
-
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define WGM11   1 /* Was PWM11 in AT90S2313 */
-#define WGM10   0 /* Was PWM10 in AT90S2313 */
-
-/* ATtiny Timer/Counter Control Register A TCCR0A */
-#define TCCR0A  _SFR_IO8(0x30)
-
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define CAL6    6
-#define CAL5    5
-#define CAL4    4
-#define CAL3    3
-#define CAL2    2
-#define CAL1    1
-#define CAL0    0
-
-/* Timer/Counter 0 TCNT0[7:0] */
-#define TCNT0   _SFR_IO8(0x32)
-
-/* ATtiny Timer/Counter 0 Control Register TCCR0B */
-#define TCCR0B  _SFR_IO8(0x33)
-
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-/* ATtiny MCU Status Register MCUSR */
-#define MCUSR   _SFR_IO8(0x34)
-
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-/* ATtiny MCU general Control Register MCUCR */
-#define MCUCR   _SFR_IO8(0x35)
-
-#define PUD     7
-#define SM1     6
-#define SE      5
-#define SM0     4 /* Some preliminary ATtiny2313 data sheets incorrectly refer
-                     to this bit as SMD; was SM in AT90S2313. */
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* ATtiny Output Compare Register A OCR0A[7:0] */
-#define OCR0A   _SFR_IO8(0x36)
-
-/* ATtiny Store Program Memory Control and Status Register SPMCSR */
-#define SPMCSR  _SFR_IO8(0x37)
-
-#define CTPB    4
-#define RFLB    3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0   /* The name is used in ATtiny2313.xml file. */
-#define SELFPRGEN 0 /* The name is used in datasheet. */
-#define SELFPRGE  0 /* The name is left for compatibility. */
-
-/* ATtiny Timer/Counter Interrupt Flag register TIFR */
-#define TIFR    _SFR_IO8(0x38)
-
-#define TOV1    7
-#define OCF1A   6
-#define OCF1B   5
-#define ICF1    3
-#define OCF0B   2
-#define TOV0    1
-#define OCF0A   0
-
-/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */
-#define TIMSK   _SFR_IO8(0x39)
-
-#define TOIE1   7
-#define OCIE1A  6
-#define OCIE1B  5
-#define ICIE1   3
-#define OCIE0B  2
-#define TOIE0   1
-#define OCIE0A  0
-
-/* ATtiny External Interrupt Flag Register EIFR, was GIFR */
-#define EIFR    _SFR_IO8(0x3A)
-
-#define INTF1   7
-#define INTF0   6
-#define PCIF    5
-
-/* ATtiny General Interrupt MaSK register GIMSK */
-#define GIMSK   _SFR_IO8(0x3B)
-
-#define INT1    7
-#define INT0    6
-#define PCIE    5
-
-/* ATtiny Output Compare Register B OCR0B[7:0] */
-#define OCR0B   _SFR_IO8(0x3C)
-
-/* Interrupt vectors: */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-#define SIG_INT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-#define SIG_INT1			_VECTOR(2)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-#define SIG_TIMER1_CAPT			_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-#define SIG_TIMER1_COMPA		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-#define SIG_TIMER1_OVF			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-#define SIG_TIMER0_OVF			_VECTOR(6)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(7)
-#define SIG_USART0_RECV			_VECTOR(7)
-#define SIG_USART0_RX			_VECTOR(7)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(8)
-#define SIG_USART0_DATA			_VECTOR(8)
-#define SIG_USART0_UDRE			_VECTOR(8)
-
-/* USART, Tx Complete */
-#define USART_TX_vect			_VECTOR(9)
-#define SIG_USART0_TRANS		_VECTOR(9)
-#define SIG_USART0_TX			_VECTOR(9)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(10)
-#define SIG_COMPARATOR			_VECTOR(10)
-#define SIG_ANALOG_COMP			_VECTOR(10)
-#define PCINT_vect			_VECTOR(11)
-#define SIG_PIN_CHANGE			_VECTOR(11)
-#define SIG_PCINT			_VECTOR(11)
-#define TIMER1_COMPB_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)
-#define SIG_TIMER1_COMPB		_VECTOR(12)
-#define TIMER0_COMPA_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(13)
-#define SIG_TIMER0_COMPA		_VECTOR(13)
-#define TIMER0_COMPB_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(14)
-#define SIG_TIMER0_COMPB		_VECTOR(14)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(15)
-#define SIG_USI_START			_VECTOR(15)
-#define SIG_USI_START			_VECTOR(15)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(16)
-#define SIG_USI_OVERFLOW		_VECTOR(16)
-#define SIG_USI_OVERFLOW		_VECTOR(16)
-#define EEPROM_READY_vect		_VECTOR(17)
-#define SIG_EEPROM_READY		_VECTOR(17)
-#define SIG_EE_READY			_VECTOR(17)
-
-/* Watchdog Timer Overflow */
-#define WDT_OVERFLOW_vect		_VECTOR(18)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(18)
-#define SIG_WDT_OVERFLOW		_VECTOR(18)
-
-/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */
-#define _VECTORS_SIZE     38
-
-/* Constants */
-#define SPM_PAGESIZE 32
-#define RAMEND       0xDF
-#define XRAMEND      RAMEND
-#define E2END        0x7F
-#define E2PAGESIZE   4
-#define FLASHEND     0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_EESAVE      (unsigned char)~_BV(6)
-#define FUSE_DWEN        (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0A
-
-/** @} */
-
-#endif  /* _AVR_IOTN2313_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn2313a.h b/cpukit/score/cpu/avr/avr/iotn2313a.h
deleted file mode 100644
index a84e4ee3a3..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn2313a.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/**
- * @file avr/iotn2313a.h
- *
- * @brief Definitions for ATtiny2313A
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn2313a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny2313A_H_
-#define _AVR_ATtiny2313A_H_ 1
-
-/**
- *  @defgroup Avr_io4434 AT90S4434 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define DIDR _SFR_IO8(0x001)
-#define AIN0D 0
-#define AIN1D 1
-
-#define UBRRH _SFR_IO8(0x002)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UCSRC _SFR_IO8(0x003)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL 6
-
-#define PCMSK1 _SFR_IO8(0x004)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-
-#define PCMSK2 _SFR_IO8(0x005)
-#define PCINT11 0
-#define PCINT12 1
-#define PCINT13 2
-#define PCINT14 3
-#define PCINT15 4
-#define PCINT16 5
-#define PCINT17 6
-
-#define PRR _SFR_IO8(0x006)
-#define PRUSART 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define BODCR _SFR_IO8(0x007)
-#define BPDSE 0
-#define BPDS 1
-
-#define ACSR _SFR_IO8(0x008)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define UBRRL _SFR_IO8(0x009)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UCSRB _SFR_IO8(0x00A)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRA _SFR_IO8(0x00B)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UDR _SFR_IO8(0x00C)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define USICR _SFR_IO8(0x00D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x00E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x00F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define PIND _SFR_IO8(0x010)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-
-#define DDRD _SFR_IO8(0x011)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-
-#define PORTD _SFR_IO8(0x012)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-
-#define GPIOR0 _SFR_IO8(0x013)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x014)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x015)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PINB _SFR_IO8(0x016)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x017)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x018)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x019)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-
-#define DDRA _SFR_IO8(0x01A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-
-#define PORTA _SFR_IO8(0x01B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-
-#define EECR _SFR_IO8(0x01C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x01D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO8(0x01E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-
-#define PCMSK _SFR_IO8(0x020)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define WDTCR _SFR_IO8(0x021)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define TCCR1C _SFR_IO8(0x022)
-#define FOC1B 6
-#define FOC1A 7
-
-#define GTCCR _SFR_IO8(0x023)
-#define PSR10 0
-
-#define ICR1 _SFR_IO16(0x024)
-
-#define ICR1L _SFR_IO8(0x024)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_IO8(0x025)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define CLKPR _SFR_IO8(0x026)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define OCR1B _SFR_IO16(0x028)
-
-#define OCR1BL _SFR_IO8(0x028)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_IO8(0x029)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1A _SFR_IO16(0x02A)
-
-#define OCR1AL _SFR_IO8(0x02A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_IO8(0x02B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCNT1 _SFR_IO16(0x02C)
-
-#define TCNT1L _SFR_IO8(0x02C)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x02D)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define TCCR1B _SFR_IO8(0x02E)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1A _SFR_IO8(0x02F)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR0A _SFR_IO8(0x030)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define OSCCAL _SFR_IO8(0x031)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define TCNT0 _SFR_IO8(0x032)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x033)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x034)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x035)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define SM0 4
-#define SE 5
-#define SM1 6
-#define PUD 7
-
-#define OCR0A _SFR_IO8(0x036)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x037)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR _SFR_IO8(0x038)
-#define OCF0A 0
-#define TOV0 1
-#define OCF0B 2
-#define ICF1 3
-#define OCF1B 5
-#define OCF1A 6
-#define TOV1 7
-
-#define TIMSK _SFR_IO8(0x039)
-#define OCIE0A 0
-#define TOIE0 1
-#define OCIE0B 2
-#define ICIE1 3
-#define OCIE1B 5
-#define OCIE1A 6
-#define TOIE1 7
-
-#define EIFR _SFR_IO8(0x03A)
-#define PCIF 5
-#define INTF0 6
-#define INTF1 7
-
-#define GIMSK _SFR_IO8(0x03B)
-#define PCIE 5
-#define INT0 6
-#define INT1 7
-
-#define OCR0B _SFR_IO8(0x03C)
-#define OCR0_0 0
-#define OCR0_1 1
-#define OCR0_2 2
-#define OCR0_3 3
-#define OCR0_4 4
-#define OCR0_5 5
-#define OCR0_6 6
-#define OCR0_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define TIMER1_CAPT_vect_num  3
-#define TIMER1_CAPT_vect      _VECTOR(3)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  4
-#define TIMER1_COMPA_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_OVF_vect_num  5
-#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  6
-#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
-#define USART_RX_vect_num  7
-#define USART_RX_vect      _VECTOR(7)  /* USART, Rx Complete */
-#define USART_UDRE_vect_num  8
-#define USART_UDRE_vect      _VECTOR(8)  /* USART Data Register Empty */
-#define USART_TX_vect_num  9
-#define USART_TX_vect      _VECTOR(9)  /* USART, Tx Complete */
-#define ANA_COMP_vect_num  10
-#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
-#define PCINT_B_vect_num  11
-#define PCINT_B_vect      _VECTOR(11)  /* Pin Change Interrupt Request B */
-#define TIMER1_COMPB_vect_num  12
-#define TIMER1_COMPB_vect      _VECTOR(12)  /*  */
-#define TIMER0_COMPA_vect_num  13
-#define TIMER0_COMPA_vect      _VECTOR(13)  /*  */
-#define TIMER0_COMPB_vect_num  14
-#define TIMER0_COMPB_vect      _VECTOR(14)  /*  */
-#define USI_START_vect_num  15
-#define USI_START_vect      _VECTOR(15)  /* USI Start Condition */
-#define USI_OVERFLOW_vect_num  16
-#define USI_OVERFLOW_vect      _VECTOR(16)  /* USI Overflow */
-#define WDT_OVERFLOW_vect_num  18
-#define WDT_OVERFLOW_vect      _VECTOR(18)  /* Watchdog Timer Overflow */
-#define PCINT_D_vect_num  20
-#define PCINT_D_vect      _VECTOR(20)  /* Pin Change Interrupt Request D */
-#define EEPROM_Ready_vect_num  17
-#define EEPROM_Ready_vect      _VECTOR(17)  /*  */
-#define PCINT_A_vect_num  19
-#define PCINT_A_vect      _VECTOR(19)  /* Pin Change Interrupt Request A */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (32)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (128)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7F)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0A
-
-
-/* Device Pin Definitions */
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define PA1_DDR   DDRXTAL
-#define PA1_PORT  PORTXTAL
-#define PA1_PIN   PINXTAL
-#define PA1_BIT   XTAL2
-
-#define PA0_DDR   DDRXTAL
-#define PA0_PORT  PORTXTAL
-#define PA0_PIN   PINXTAL
-#define PA0_BIT   XTAL1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define XCK_DDR   DDRD
-#define XCK_PORT  PORTD
-#define XCK_PIN   PIND
-#define XCK_BIT   2
-
-#define CKOUT_DDR   DDRD
-#define CKOUT_PORT  PORTD
-#define CKOUT_PIN   PIND
-#define CKOUT_BIT   2
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define T0_DDR   DDRD
-#define T0_PORT  PORTD
-#define T0_PIN   PIND
-#define T0_BIT   4
-
-#define T1_DDR   DDRD
-#define T1_PORT  PORTD
-#define T1_PIN   PIND
-#define T1_BIT   5
-
-#define OC0B_DDR   DDRD
-#define OC0B_PORT  PORTD
-#define OC0B_PIN   PIND
-#define OC0B_BIT   5
-
-#define ICP_DDR   DDRD
-#define ICP_PORT  PORTD
-#define ICP_PIN   PIND
-#define ICP_BIT   6
-
-#define AIN0_DDR   DDRB
-#define AIN0_PORT  PORTB
-#define AIN0_PIN   PINB
-#define AIN0_BIT   0
-
-#define AIN1_DDR   DDRB
-#define AIN1_PORT  PORTB
-#define AIN1_PIN   PINB
-#define AIN1_BIT   1
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   2
-
-#define OC1A_DDR   DDRB
-#define OC1A_PORT  PORTB
-#define OC1A_PIN   PINB
-#define OC1A_BIT   3
-
-#define OC1B_DDR   DDRB
-#define OC1B_PORT  PORTB
-#define OC1B_PIN   PINB
-#define OC1B_BIT   4
-
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   5
-
-#define DI_DDR   DDRB
-#define DI_PORT  PORTB
-#define DI_PIN   PINB
-#define DI_BIT   5
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   6
-
-#define DO_DDR   DDRB
-#define DO_PORT  PORTB
-#define DO_PIN   PINB
-#define DO_BIT   6
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   7
-
-#define SCL_DDR   DDRB
-#define SCL_PORT  PORTB
-#define SCL_PIN   PINB
-#define SCL_BIT   7
-
-/**@}*/
-#endif /* _AVR_ATtiny2313A_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn24.h b/cpukit/score/cpu/avr/avr/iotn24.h
deleted file mode 100644
index 2fc94b10da..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn24.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- * @file avr/iotn24.h
- *
- * @brief Definitions for ATtiny24
- */
-
-/*
- * Copyright (c) 2005 Anatoly Sokolov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN24_H_
-#define _AVR_IOTN24_H_ 1
-
-/**
- *  @defgroup Avr_iotn24 ATtiny24 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iotnx4.h>
-
-#define SPM_PAGESIZE 32
-#define RAMEND       0xDF
-#define XRAMEND      RAMEND
-#define E2END        0x7F
-#define E2PAGESIZE   4
-#define FLASHEND     0x7FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0B
-
-
-/**@}*/
-#endif /* _AVR_IOTN24_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn24a.h b/cpukit/score/cpu/avr/avr/iotn24a.h
deleted file mode 100644
index 266bc94db8..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn24a.h
+++ /dev/null
@@ -1,841 +0,0 @@
-/**
- * @file avr/iotn24a.h
- *
- * @brief Definitions for ATtiny24A
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn24a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny24A_H_
-#define _AVR_ATtiny24A_H_ 1
-
-/**
- *  @defgroup Avr_iotn24a ATtiny24A Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PRR _SFR_IO8(0x00)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADLAR 4
-#define ACME 6
-#define BIN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define MUX5 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSR _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define TIFR1 _SFR_IO8(0x0B)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIMSK1 _SFR_IO8(0x0C)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define PCMSK0 _SFR_IO8(0x12)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define GPIOR0 _SFR_IO8(0x13)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x14)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x15)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define PCMSK1 _SFR_IO8(0x20)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-
-#define WDTCSR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define TCCR1C _SFR_IO8(0x22)
-#define FOC1B 6
-#define FOC1A 7
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define TSM 7
-
-#define ICR1 _SFR_IO16(0x24)
-
-#define ICR1L _SFR_IO8(0x24)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_IO8(0x25)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define CLKPR _SFR_IO8(0x26)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define DWDR _SFR_IO8(0x27)
-
-#define OCR1B _SFR_IO16(0x28)
-
-#define OCR1BL _SFR_IO8(0x28)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_IO8(0x29)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1A _SFR_IO16(0x2A)
-
-#define OCR1AL _SFR_IO8(0x2A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_IO8(0x2B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCNT1 _SFR_IO16(0x2C)
-
-#define TCNT1L _SFR_IO8(0x2C)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x2D)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define TCCR1B _SFR_IO8(0x2E)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1A _SFR_IO8(0x2F)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR0A _SFR_IO8(0x30)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0 _SFR_IO8(0x32)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-
-#define OCR0A _SFR_IO8(0x36)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR0 _SFR_IO8(0x38)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIMSK0 _SFR_IO8(0x39)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF0 4
-#define PCIF1 5
-#define INTF0 6
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0 6
-
-#define OCR0B _SFR_IO8(0x3C)
-#define OCR0_0 0
-#define OCR0_1 1
-#define OCR0_2 2
-#define OCR0_3 3
-#define OCR0_4 4
-#define OCR0_5 5
-#define OCR0_6 6
-#define OCR0_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define EXT_INT0_vect_num  1
-#define EXT_INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  3
-#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
-#define WATCHDOG_vect_num  4
-#define WATCHDOG_vect      _VECTOR(4)  /* Watchdog Time-out */
-#define TIM1_CAPT_vect_num  5
-#define TIM1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
-#define TIM1_COMPA_vect_num  6
-#define TIM1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
-#define TIM1_COMPB_vect_num  7
-#define TIM1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
-#define TIM1_OVF_vect_num  8
-#define TIM1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
-#define TIM0_COMPA_vect_num  9
-#define TIM0_COMPA_vect      _VECTOR(9)  /* Timer/Counter0 Compare Match A */
-#define TIM0_COMPB_vect_num  10
-#define TIM0_COMPB_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match B */
-#define TIM0_OVF_vect_num  11
-#define TIM0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define ANA_COMP_vect_num  12
-#define ANA_COMP_vect      _VECTOR(12)  /* Analog Comparator */
-#define ADC_vect_num  13
-#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
-#define EE_RDY_vect_num  14
-#define EE_RDY_vect      _VECTOR(14)  /* EEPROM Ready */
-#define USI_STR_vect_num  15
-#define USI_STR_vect      _VECTOR(15)  /* USI START */
-#define USI_OVF_vect_num  16
-#define USI_OVF_vect      _VECTOR(16)  /* USI Overflow */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (32)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (128)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7F)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0B
-
-
-/* Device Pin Definitions */
-#define ADC4_DDR   DDRA
-#define ADC4_PORT  PORTA
-#define ADC4_PIN   PINA
-#define ADC4_BIT   4
-
-#define USCK_DDR   DDRA
-#define USCK_PORT  PORTA
-#define USCK_PIN   PINA
-#define USCK_BIT   4
-
-#define SCL_DDR   DDRA
-#define SCL_PORT  PORTA
-#define SCL_PIN   PINA
-#define SCL_BIT   4
-
-#define T1_DDR   DDRA
-#define T1_PORT  PORTA
-#define T1_PIN   PINA
-#define T1_BIT   4
-
-#define PCINT4_DDR   DDRA
-#define PCINT4_PORT  PORTA
-#define PCINT4_PIN   PINA
-#define PCINT4_BIT   4
-
-#define ADC3_DDR   DDRA
-#define ADC3_PORT  PORTA
-#define ADC3_PIN   PINA
-#define ADC3_BIT   3
-
-#define T0_DDR   DDRA
-#define T0_PORT  PORTA
-#define T0_PIN   PINA
-#define T0_BIT   3
-
-#define PCINT3_DDR   DDRA
-#define PCINT3_PORT  PORTA
-#define PCINT3_PIN   PINA
-#define PCINT3_BIT   3
-
-#define ADC2_DDR   DDRA
-#define ADC2_PORT  PORTA
-#define ADC2_PIN   PINA
-#define ADC2_BIT   2
-
-#define AIN1_DDR   DDRA
-#define AIN1_PORT  PORTA
-#define AIN1_PIN   PINA
-#define AIN1_BIT   2
-
-#define PCINT2_DDR   DDRA
-#define PCINT2_PORT  PORTA
-#define PCINT2_PIN   PINA
-#define PCINT2_BIT   2
-
-#define ADC1_DDR   DDRA
-#define ADC1_PORT  PORTA
-#define ADC1_PIN   PINA
-#define ADC1_BIT   1
-
-#define AIN0_DDR   DDRA
-#define AIN0_PORT  PORTA
-#define AIN0_PIN   PINA
-#define AIN0_BIT   1
-
-#define PCINT1_DDR   DDRA
-#define PCINT1_PORT  PORTA
-#define PCINT1_PIN   PINA
-#define PCINT1_BIT   1
-
-#define ADC0_DDR   DDRA
-#define ADC0_PORT  PORTA
-#define ADC0_PIN   PINA
-#define ADC0_BIT   0
-
-#define PCINT0_DDR   DDRA
-#define PCINT0_PORT  PORTA
-#define PCINT0_PIN   PINA
-#define PCINT0_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define dW_DDR   DDRB
-#define dW_PORT  PORTB
-#define dW_PIN   PINB
-#define dW_BIT   3
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define INT0_DDR   DDRB
-#define INT0_PORT  PORTB
-#define INT0_PIN   PINB
-#define INT0_BIT   2
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   2
-
-#define CKOUT_DDR   DDRB
-#define CKOUT_PORT  PORTB
-#define CKOUT_PIN   PINB
-#define CKOUT_BIT   2
-
-#define PCINT7_DDR   DDRA
-#define PCINT7_PORT  PORTA
-#define PCINT7_PIN   PINA
-#define PCINT7_BIT   7
-
-#define ICP1_DDR   DDRA
-#define ICP1_PORT  PORTA
-#define ICP1_PIN   PINA
-#define ICP1_BIT   7
-
-#define OC0B_DDR   DDRA
-#define OC0B_PORT  PORTA
-#define OC0B_PIN   PINA
-#define OC0B_BIT   7
-
-#define ADC7_DDR   DDRA
-#define ADC7_PORT  PORTA
-#define ADC7_PIN   PINA
-#define ADC7_BIT   7
-
-#define PCINT6_DDR   DDRA
-#define PCINT6_PORT  PORTA
-#define PCINT6_PIN   PINA
-#define PCINT6_BIT   6
-
-#define OC1A_DDR   DDRA
-#define OC1A_PORT  PORTA
-#define OC1A_PIN   PINA
-#define OC1A_BIT   6
-
-#define DI_DDR   DDRA
-#define DI_PORT  PORTA
-#define DI_PIN   PINA
-#define DI_BIT   6
-
-#define SDA_DDR   DDRA
-#define SDA_PORT  PORTA
-#define SDA_PIN   PINA
-#define SDA_BIT   6
-
-#define MOSI_DDR   DDRA
-#define MOSI_PORT  PORTA
-#define MOSI_PIN   PINA
-#define MOSI_BIT   6
-
-#define ADC6_DDR   DDRA
-#define ADC6_PORT  PORTA
-#define ADC6_PIN   PINA
-#define ADC6_BIT   6
-
-#define ADC5_DDR   DDRA
-#define ADC5_PORT  PORTA
-#define ADC5_PIN   PINA
-#define ADC5_BIT   5
-
-#define DO_DDR   DDRA
-#define DO_PORT  PORTA
-#define DO_PIN   PINA
-#define DO_BIT   5
-
-#define MISO_DDR   DDRA
-#define MISO_PORT  PORTA
-#define MISO_PIN   PINA
-#define MISO_BIT   5
-
-#define OC1B_DDR   DDRA
-#define OC1B_PORT  PORTA
-#define OC1B_PIN   PINA
-#define OC1B_BIT   5
-
-#define PCINT5_DDR   DDRA
-#define PCINT5_PORT  PORTA
-#define PCINT5_PIN   PINA
-#define PCINT5_BIT   5
-
-/**@}*/
-#endif /* _AVR_ATtiny24A_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn25.h b/cpukit/score/cpu/avr/avr/iotn25.h
deleted file mode 100644
index bd2b5b8f5e..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn25.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright (c) 2005, Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn25.h - definitions for ATtiny25 */
-
-#ifndef _AVR_IOTN25_H_
-#define _AVR_IOTN25_H_ 1
-
-#include <avr/iotnx5.h>
-
-#define SPM_PAGESIZE 32
-#define RAMEND       0xDF
-#define XRAMEND      RAMEND
-#define E2END        0x7F
-#define E2PAGESIZE   4
-#define FLASHEND     0x7FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x08
-
-
-#endif /* _AVR_IOTN25_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn26.h b/cpukit/score/cpu/avr/avr/iotn26.h
deleted file mode 100644
index 7fcf2a3b59..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn26.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny26
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004,2005 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn26.h - definitions for ATtiny26 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn26.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-#ifndef _AVR_IOTN26_H_
-#define _AVR_IOTN26_H_ 1
-
-/**
- * @defgroup AvrDef_iotn26 ATtiny26 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-/* Reserved [0x00..0x03] */
-
-#define ADCW    _SFR_IO16(0x04)
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSR   _SFR_IO8(0x06)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADFR    5
-#define ADSC    6
-#define ADEN    7
-
-#define ADMUX   _SFR_IO8(0x07)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-#define ACSR    _SFR_IO8(0x08)
-#define ACIS0   0
-#define ACIS1   1
-#define ACME    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-/* Reserved [0x09..0x0C] */
-
-#define USICR   _SFR_IO8(0x0D)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_IO8(0x0F)
-
-/* Reserved [0x10..0x15] */
-
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA0   0
-#define PINA1   1
-#define PINA2   2
-#define PINA3   3
-#define PINA4   4
-#define PINA5   5
-#define PINA6   6
-#define PINA7   7
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PA0     0
-#define PA1     1
-#define PA2     2
-#define PA3     3
-#define PA4     4
-#define PA5     5
-#define PA6     6
-#define PA7     7
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Reserved [0x1F..0x20] */
-
-#define WDTCR   _SFR_IO8(0x21)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-/* Reserved [0x22..0x28] */
-
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0
-#define PLLE    1
-#define PCKE    2
-
-/* Reserved [0x2A] */
-
-#define OCR1C   _SFR_IO8(0x2B)
-
-#define OCR1B   _SFR_IO8(0x2C)
-
-#define OCR1A   _SFR_IO8(0x2D)
-
-#define TCNT1   _SFR_IO8(0x2E)
-
-#define TCCR1B  _SFR_IO8(0x2F)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define CS13    3
-#define PSR1    6
-#define CTC1    7
-
-#define TCCR1A  _SFR_IO8(0x30)
-#define PWM1B   0
-#define PWM1A   1
-#define FOC1B   2
-#define FOC1A   3
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0   _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define PSR0    3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define SM0     3
-#define SM1     4
-#define SE      5
-#define PUD     6
-
-/* Reserved [0x36..0x37] */
-
-#define TIFR    _SFR_IO8(0x38)
-#define TOV0    1
-#define TOV1    2
-#define OCF1B   5
-#define OCF1A   6
-
-#define TIMSK   _SFR_IO8(0x39)
-#define TOIE0   1
-#define TOIE1   2
-#define OCIE1B  5
-#define OCIE1A  6
-
-#define GIFR    _SFR_IO8(0x3A)
-#define PCIF    5
-#define INTF0   6
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define PCIE0   4
-#define PCIE1   5
-#define INT0    6
-
-/* Reserved [0x3C] */
-
-/* SP [0x3D] */
-
-/* Reserved [0x3E] */
-
-/* SREG [0x3F] */
-
-
-/* Interrupt vectors */
-/* Interrupt vector 0 is the reset vector. */
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 0 */
-#define IO_PINS_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIMER1_CMPA_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match 1B */
-#define TIMER1_CMPB_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF1_vect		_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* USI Start */
-#define USI_STRT_vect			_VECTOR(7)
-#define SIG_USI_START			_VECTOR(7)
-
-/* USI Overflow */
-#define USI_OVF_vect			_VECTOR(8)
-#define SIG_USI_OVERFLOW		_VECTOR(8)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(9)
-#define SIG_EEPROM_READY		_VECTOR(9)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(10)
-#define SIG_ANA_COMP			_VECTOR(10)
-#define SIG_COMPARATOR			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-#define _VECTORS_SIZE 24
-
-
-/* Constants */
-#define RAMEND      0xDF
-#define XRAMEND     RAMEND
-#define E2END       0x7F
-#define E2PAGESIZE  4
-#define FLASHEND    0x07FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOPT       (unsigned char)~_BV(6)
-#define FUSE_PLLCK       (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BODEN       (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(1)
-#define FUSE_EESAVE      (unsigned char)~_BV(2)
-#define FUSE_SPIEN       (unsigned char)~_BV(3)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x09
-
-/** @} */
-
-#endif  /* _AVR_IOTN26_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn261.h b/cpukit/score/cpu/avr/avr/iotn261.h
deleted file mode 100644
index 129e595a34..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn261.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny261
- */
-
-/* Copyright (c) 2006, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn261.h - definitions for ATtiny261 */
-
-#ifndef _AVR_IOTN261_H_
-#define _AVR_IOTN261_H_ 1
-
-/**
- * @defgroup AvrDef_iotn261 ATtiny261 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iotnx61.h>
-
-#define SPM_PAGESIZE 32
-#define RAMEND       0xDF
-#define XRAMEND      RAMEND
-#define E2END        0x7F
-#define E2PAGESIZE   4
-#define FLASHEND     0x7FF
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0C
-
-/** @} */
-
-#endif /* _AVR_IOTN261_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn261a.h b/cpukit/score/cpu/avr/avr/iotn261a.h
deleted file mode 100644
index 607642fe88..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn261a.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/**
- * @file avr/iotn261a.h
- *
- * @brief Definitions for ATtiny261A
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn261a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny261A_H_
-#define _AVR_ATtiny261A_H_ 1
-
-/**
- *  @defgroup Avr_iotn261a ATtiny261A Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define TCCR1E _SFR_IO8(0x00)
-#define OC1OE0 0
-#define OC1OE1 1
-#define OC1OE2 2
-#define OC1OE3 3
-#define OC1OE4 4
-#define OC1OE5 5
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define AREFD 3
-#define ADC3D 4
-#define ADC4D 5
-#define ADC5D 6
-#define ADC6D 7
-
-#define DIDR1 _SFR_IO8(0x02)
-#define ADC7D 4
-#define ADC8D 5
-#define ADC9D 6
-#define ADC10D 7
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define MUX5 3
-#define REFS2 4
-#define IPR 5
-#define GSEL 6
-#define BIN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSRA _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACME 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define ACSRB _SFR_IO8(0x09)
-#define ACM0 0
-#define ACM1 1
-#define ACM2 2
-#define HLEV 6
-#define HSEL 7
-
-#define GPIOR0 _SFR_IO8(0x0A)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x0B)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x0C)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define USIPP _SFR_IO8(0x11)
-#define USIPOS 0
-
-#define OCR0B _SFR_IO8(0x12)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0A _SFR_IO8(0x13)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define TCNT0H _SFR_IO8(0x14)
-#define TCNT0H_0 0
-#define TCNT0H_1 1
-#define TCNT0H_2 2
-#define TCNT0H_3 3
-#define TCNT0H_4 4
-#define TCNT0H_5 5
-#define TCNT0H_6 6
-#define TCNT0H_7 7
-
-#define TCCR0A _SFR_IO8(0x15)
-#define WGM00 0
-#define ACIC0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define DWDR _SFR_IO8(0x20)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define WDTCR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define PCMSK1 _SFR_IO8(0x22)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK0 _SFR_IO8(0x23)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define DT1 _SFR_IO8(0x24)
-#define DT1L0 0
-#define DT1L1 1
-#define DT1L2 2
-#define DT1L3 3
-#define DT1H0 4
-#define DT1H1 5
-#define DT1H2 6
-#define DT1H3 7
-
-#define TC1H _SFR_IO8(0x25)
-#define TC18 0
-#define TC19 1
-
-#define TCCR1D _SFR_IO8(0x26)
-#define WGM10 0
-#define WGM11 1
-#define FPF1 2
-#define FPAC1 3
-#define FPES1 4
-#define FPNC1 5
-#define FPEN1 6
-#define FPIE1 7
-
-#define TCCR1C _SFR_IO8(0x27)
-#define PWM1D 0
-#define FOC1D 1
-#define COM1D0 2
-#define COM1D1 3
-#define COM1B0S 4
-#define COM1B1S 5
-#define COM1A0S 6
-#define COM1A1S 7
-
-#define CLKPR _SFR_IO8(0x28)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PCKE 2
-#define LSM 7
-
-#define OCR1D _SFR_IO8(0x2A)
-#define OCR1D0 0
-#define OCR1D1 1
-#define OCR1D2 2
-#define OCR1D3 3
-#define OCR1D4 4
-#define OCR1D5 5
-#define OCR1D6 6
-#define OCR1D7 7
-
-#define OCR1C _SFR_IO8(0x2B)
-#define OCR1C0 0
-#define OCR1C1 1
-#define OCR1C2 2
-#define OCR1C3 3
-#define OCR1C4 4
-#define OCR1C5 5
-#define OCR1C6 6
-#define OCR1C7 7
-
-#define OCR1B _SFR_IO8(0x2C)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define OCR1A _SFR_IO8(0x2D)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define TCNT1 _SFR_IO8(0x2E)
-#define TC1H_0 0
-#define TC1H_1 1
-#define TC1H_2 2
-#define TC1H_3 3
-#define TC1H_4 4
-#define TC1H_5 5
-#define TC1H_6 6
-#define TC1H_7 7
-
-#define TCCR1B _SFR_IO8(0x2F)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define CS13 3
-#define DTPS10 4
-#define DTPS11 5
-#define PSR1 6
-
-#define TCCR1A _SFR_IO8(0x30)
-#define PWM1B 0
-#define PWM1A 1
-#define FOC1B 2
-#define FOC1A 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0L _SFR_IO8(0x32)
-#define TCNT0L_0 0
-#define TCNT0L_1 1
-#define TCNT0L_2 2
-#define TCNT0L_3 3
-#define TCNT0L_4 4
-#define TCNT0L_5 5
-#define TCNT0L_6 6
-#define TCNT0L_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define PSR0 3
-#define TSM 4
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define BODSE 2
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-#define BODS 7
-
-#define PRR _SFR_IO8(0x36)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR _SFR_IO8(0x38)
-#define ICF0 0
-#define TOV0 1
-#define TOV1 2
-#define OCF0B 3
-#define OCF0A 4
-#define OCF1B 5
-#define OCF1A 6
-#define OCF1D 7
-
-#define TIMSK _SFR_IO8(0x39)
-#define TICIE0 0
-#define TOIE0 1
-#define TOIE1 2
-#define OCIE0B 3
-#define OCIE0A 4
-#define OCIE1B 5
-#define OCIE1A 6
-#define OCIE1D 7
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF 5
-#define INTF0 6
-#define INTF1 7
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0 6
-#define INT1 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
-#define PCINT_vect_num  2
-#define PCINT_vect      _VECTOR(2)  /* Pin Change Interrupt */
-#define TIMER1_COMPA_vect_num  3
-#define TIMER1_COMPA_vect      _VECTOR(3)  /* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPB_vect_num  4
-#define TIMER1_COMPB_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match 1B */
-#define TIMER1_OVF_vect_num  5
-#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  6
-#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
-#define USI_START_vect_num  7
-#define USI_START_vect      _VECTOR(7)  /* USI Start */
-#define USI_OVF_vect_num  8
-#define USI_OVF_vect      _VECTOR(8)  /* USI Overflow */
-#define EE_RDY_vect_num  9
-#define EE_RDY_vect      _VECTOR(9)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  10
-#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
-#define ADC_vect_num  11
-#define ADC_vect      _VECTOR(11)  /* ADC Conversion Complete */
-#define WDT_vect_num  12
-#define WDT_vect      _VECTOR(12)  /* Watchdog Time-Out */
-#define INT1_vect_num  13
-#define INT1_vect      _VECTOR(13)  /* External Interrupt 1 */
-#define TIMER0_COMPA_vect_num  14
-#define TIMER0_COMPA_vect      _VECTOR(14)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  15
-#define TIMER0_COMPB_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_CAPT_vect_num  16
-#define TIMER0_CAPT_vect      _VECTOR(16)  /* ADC Conversion Complete */
-#define TIMER1_COMPD_vect_num  17
-#define TIMER1_COMPD_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match D */
-#define FAULT_PROTECTION_vect_num  18
-#define FAULT_PROTECTION_vect      _VECTOR(18)  /* Timer/Counter1 Fault Protection */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (32)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (128)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7F)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x7FF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x0C
-
-
-/* Device Pin Definitions */
-#define DI_B_DDR   DDRMOSI
-#define DI_B_PORT  PORTMOSI
-#define DI_B_PIN   PINMOSI
-#define DI_B_BIT   MOSI
-
-#define SDA_B_DDR   DDRMOSI
-#define SDA_B_PORT  PORTMOSI
-#define SDA_B_PIN   PINMOSI
-#define SDA_B_BIT   MOSI
-
-#define _OC1A_DDR   DDRMOSI
-#define _OC1A_PORT  PORTMOSI
-#define _OC1A_PIN   PINMOSI
-#define _OC1A_BIT   MOSI
-
-#define PCINT8_DDR   DDRMOSI
-#define PCINT8_PORT  PORTMOSI
-#define PCINT8_PIN   PINMOSI
-#define PCINT8_BIT   MOSI
-
-#define PB0_DDR   DDRMOSI
-#define PB0_PORT  PORTMOSI
-#define PB0_PIN   PINMOSI
-#define PB0_BIT   MOSI
-
-#define DO_B_DDR   DDRMISO
-#define DO_B_PORT  PORTMISO
-#define DO_B_PIN   PINMISO
-#define DO_B_BIT   MISO
-
-#define OC1A_DDR   DDRMISO
-#define OC1A_PORT  PORTMISO
-#define OC1A_PIN   PINMISO
-#define OC1A_BIT   MISO
-
-#define PCINT9_DDR   DDRMISO
-#define PCINT9_PORT  PORTMISO
-#define PCINT9_PIN   PINMISO
-#define PCINT9_BIT   MISO
-
-#define PB1_DDR   DDRMISO
-#define PB1_PORT  PORTMISO
-#define PB1_PIN   PINMISO
-#define PB1_BIT   MISO
-
-#define USCK_B_DDR   DDRSCK
-#define USCK_B_PORT  PORTSCK
-#define USCK_B_PIN   PINSCK
-#define USCK_B_BIT   SCK
-
-#define SCL_B_DDR   DDRSCK
-#define SCL_B_PORT  PORTSCK
-#define SCL_B_PIN   PINSCK
-#define SCL_B_BIT   SCK
-
-#define OC1B_DDR   DDRSCK
-#define OC1B_PORT  PORTSCK
-#define OC1B_PIN   PINSCK
-#define OC1B_BIT   SCK
-
-#define PCINT10_DDR   DDRSCK
-#define PCINT10_PORT  PORTSCK
-#define PCINT10_PIN   PINSCK
-#define PCINT10_BIT   SCK
-
-#define PB2_DDR   DDRSCK
-#define PB2_PORT  PORTSCK
-#define PB2_PIN   PINSCK
-#define PB2_BIT   SCK
-
-#define PCINT11_DDR   DDROC1B
-#define PCINT11_PORT  PORTOC1B
-#define PCINT11_PIN   PINOC1B
-#define PCINT11_BIT   OC1B
-
-#define PB3_DDR   DDROC1B
-#define PB3_PORT  PORTOC1B
-#define PB3_PIN   PINOC1B
-#define PB3_BIT   OC1B
-
-#define PCINT12_DDR   DDRADC
-#define PCINT12_PORT  PORTADC
-#define PCINT12_PIN   PINADC
-#define PCINT12_BIT   ADC7
-
-#define _OC1D_DDR   DDRADC
-#define _OC1D_PORT  PORTADC
-#define _OC1D_PIN   PINADC
-#define _OC1D_BIT   ADC7
-
-#define CLKI_DDR   DDRADC
-#define CLKI_PORT  PORTADC
-#define CLKI_PIN   PINADC
-#define CLKI_BIT   ADC7
-
-#define PB4_DDR   DDRADC
-#define PB4_PORT  PORTADC
-#define PB4_PIN   PINADC
-#define PB4_BIT   ADC7
-
-#define PCINT13_DDR   DDRADC
-#define PCINT13_PORT  PORTADC
-#define PCINT13_PIN   PINADC
-#define PCINT13_BIT   ADC8
-
-#define OC1D_DDR   DDRADC
-#define OC1D_PORT  PORTADC
-#define OC1D_PIN   PINADC
-#define OC1D_BIT   ADC8
-
-#define CKLO_DDR   DDRADC
-#define CKLO_PORT  PORTADC
-#define CKLO_PIN   PINADC
-#define CKLO_BIT   ADC8
-
-#define PB5_DDR   DDRADC
-#define PB5_PORT  PORTADC
-#define PB5_PIN   PINADC
-#define PB5_BIT   ADC8
-
-#define INT0_DDR   DDRADC
-#define INT0_PORT  PORTADC
-#define INT0_PIN   PINADC
-#define INT0_BIT   ADC9
-
-#define T0_DDR   DDRADC
-#define T0_PORT  PORTADC
-#define T0_PIN   PINADC
-#define T0_BIT   ADC9
-
-#define PCINT14_DDR   DDRADC
-#define PCINT14_PORT  PORTADC
-#define PCINT14_PIN   PINADC
-#define PCINT14_BIT   ADC9
-
-#define PB6_DDR   DDRADC
-#define PB6_PORT  PORTADC
-#define PB6_PIN   PINADC
-#define PB6_BIT   ADC9
-
-#define PCINT15_DDR   DDRADC1
-#define PCINT15_PORT  PORTADC1
-#define PCINT15_PIN   PINADC1
-#define PCINT15_BIT   ADC10
-
-#define PB7_DDR   DDRADC1
-#define PB7_PORT  PORTADC1
-#define PB7_PIN   PINADC1
-#define PB7_BIT   ADC10
-
-#define AIN1_DDR   DDRADC
-#define AIN1_PORT  PORTADC
-#define AIN1_PIN   PINADC
-#define AIN1_BIT   ADC6
-
-#define PCINT7_DDR   DDRADC
-#define PCINT7_PORT  PORTADC
-#define PCINT7_PIN   PINADC
-#define PCINT7_BIT   ADC6
-
-#define PA7_DDR   DDRADC
-#define PA7_PORT  PORTADC
-#define PA7_PIN   PINADC
-#define PA7_BIT   ADC6
-
-#define AIN0_DDR   DDRADC
-#define AIN0_PORT  PORTADC
-#define AIN0_PIN   PINADC
-#define AIN0_BIT   ADC5
-
-#define PCINT6_DDR   DDRADC
-#define PCINT6_PORT  PORTADC
-#define PCINT6_PIN   PINADC
-#define PCINT6_BIT   ADC5
-
-#define PA6_DDR   DDRADC
-#define PA6_PORT  PORTADC
-#define PA6_PIN   PINADC
-#define PA6_BIT   ADC5
-
-#define AIN2_DDR   DDRADC
-#define AIN2_PORT  PORTADC
-#define AIN2_PIN   PINADC
-#define AIN2_BIT   ADC4
-
-#define PCINT5_DDR   DDRADC
-#define PCINT5_PORT  PORTADC
-#define PCINT5_PIN   PINADC
-#define PCINT5_BIT   ADC4
-
-#define PA5_DDR   DDRADC
-#define PA5_PORT  PORTADC
-#define PA5_PIN   PINADC
-#define PA5_BIT   ADC4
-
-#define ICP0_DDR   DDRADC
-#define ICP0_PORT  PORTADC
-#define ICP0_PIN   PINADC
-#define ICP0_BIT   ADC3
-
-#define PCINT4_DDR   DDRADC
-#define PCINT4_PORT  PORTADC
-#define PCINT4_PIN   PINADC
-#define PCINT4_BIT   ADC3
-
-#define PA4_DDR   DDRADC
-#define PA4_PORT  PORTADC
-#define PA4_PIN   PINADC
-#define PA4_BIT   ADC3
-
-#define PCINT3_DDR   DDRAREF
-#define PCINT3_PORT  PORTAREF
-#define PCINT3_PIN   PINAREF
-#define PCINT3_BIT   AREF
-
-#define PA3_DDR   DDRAREF
-#define PA3_PORT  PORTAREF
-#define PA3_PIN   PINAREF
-#define PA3_BIT   AREF
-
-#define INT1_DDR   DDRADC
-#define INT1_PORT  PORTADC
-#define INT1_PIN   PINADC
-#define INT1_BIT   ADC2
-
-#define USCK_A_DDR   DDRADC
-#define USCK_A_PORT  PORTADC
-#define USCK_A_PIN   PINADC
-#define USCK_A_BIT   ADC2
-
-#define SCL_A_DDR   DDRADC
-#define SCL_A_PORT  PORTADC
-#define SCL_A_PIN   PINADC
-#define SCL_A_BIT   ADC2
-
-#define PCINT2_DDR   DDRADC
-#define PCINT2_PORT  PORTADC
-#define PCINT2_PIN   PINADC
-#define PCINT2_BIT   ADC2
-
-#define PA2_DDR   DDRADC
-#define PA2_PORT  PORTADC
-#define PA2_PIN   PINADC
-#define PA2_BIT   ADC2
-
-#define DO_A_DDR   DDRADC
-#define DO_A_PORT  PORTADC
-#define DO_A_PIN   PINADC
-#define DO_A_BIT   ADC1
-
-#define PCINT1_DDR   DDRADC
-#define PCINT1_PORT  PORTADC
-#define PCINT1_PIN   PINADC
-#define PCINT1_BIT   ADC1
-
-#define PA1_DDR   DDRADC
-#define PA1_PORT  PORTADC
-#define PA1_PIN   PINADC
-#define PA1_BIT   ADC1
-
-#define DI_A_DDR   DDRADC
-#define DI_A_PORT  PORTADC
-#define DI_A_PIN   PINADC
-#define DI_A_BIT   ADC0
-
-#define SDA_A_DDR   DDRADC
-#define SDA_A_PORT  PORTADC
-#define SDA_A_PIN   PINADC
-#define SDA_A_BIT   ADC0
-
-#define PCINT0_DDR   DDRADC
-#define PCINT0_PORT  PORTADC
-#define PCINT0_PIN   PINADC
-#define PCINT0_BIT   ADC0
-
-#define PA0_DDR   DDRADC
-#define PA0_PORT  PORTADC
-#define PA0_PIN   PINADC
-#define PA0_BIT   ADC0
-
-/**@}*/
-#endif /* _AVR_ATtiny261A_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn28.h b/cpukit/score/cpu/avr/avr/iotn28.h
deleted file mode 100644
index 28a68e5ca2..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn28.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny28
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn28.h - definitions for ATtiny28 */
-
-#ifndef _AVR_IOTN28_H_
-#define _AVR_IOTN28_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn28.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/**
- * @defgroup AvrDef_iotn28 ATtiny28 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-#define OSCCAL	_SFR_IO8(0x00)
-
-#define WDTCR	_SFR_IO8(0x01)
-
-#define MODCR	_SFR_IO8(0x02)
-
-#define TCNT0	_SFR_IO8(0x03)
-#define TCCR0	_SFR_IO8(0x04)
-
-#define IFR	_SFR_IO8(0x05)
-#define ICR	_SFR_IO8(0x06)
-
-#define MCUCS	_SFR_IO8(0x07)
-
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x0F reserved */
-
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* 0x13..0x15 reserved */
-
-#define PINB	_SFR_IO8(0x16)
-
-/* 0x17..0x18 reserved */
-
-#define PINA	_SFR_IO8(0x19)
-#define PACR	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Low-level Input on Port B */
-#define LOWLEVEL_IO_PINS_vect		_VECTOR(3)
-#define SIG_PIN				_VECTOR(3)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW0			_VECTOR(4)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(5)
-#define SIG_COMPARATOR			_VECTOR(5)
-
-#define _VECTORS_SIZE 12
-
-
-/* Bit numbers */
-
-/* ICR */
-#define INT1	7
-#define INT0	6
-#define LLIE	5
-#define TOIE0	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00
-
-/* IFR */
-#define INTF1	7
-#define INTF0	6
-#define TOV0	4
-
-/* MCUCS */
-#define PLUPB	7
-#define SE	5
-#define SM	4
-#define WDRF	3
-#define EXTRF	1
-#define PORF	0
-
-/* TCCR0 */
-#define FOV0	7
-#define OOM01	4
-#define OOM00	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* MODCR */
-#define ONTIM4	7
-#define ONTIM3	6
-#define ONTIM2	5
-#define ONTIM1	4
-#define ONTIM0	3
-#define MCONF2	2
-#define MCONF1	1
-#define MCONF0	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/*
-   PA2 = IR
- */
-
-/* PORTA */
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* PACR */
-#define DDA3	3
-#define PA2HC	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA3	3
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB4 = INT1
-   PB3 = INT0
-   PB2 = T0
-   PB1 = AIN1
-   PB0 = AIN0
- */
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTD */
-#define PD7	7
-#define PD6	6
-#define PD5	5
-#define PD4	4
-#define PD3	3
-#define PD2	2
-#define PD1	1
-#define PD0	0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* ACSR */
-#define ACD	7
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x0
-#define E2PAGESIZE  0
-#define FLASHEND	0x7FF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_INTCAP      (unsigned char)~_BV(4)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x07
-
-/** @} */
-
-#endif /* _AVR_IOTN28_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn4313.h b/cpukit/score/cpu/avr/avr/iotn4313.h
deleted file mode 100644
index f3744853fd..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn4313.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/**
- * @file avr/iotn4313.h
- *
- * @brief Definitions for ATtiny4313
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn4313.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny4313_H_
-#define _AVR_ATtiny4313_H_ 1
-
-/**
- *  @defgroup Avr_iotn4313 ATtiny4313 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define DIDR _SFR_IO8(0x001)
-#define AIN0D 0
-#define AIN1D 1
-
-#define UBRRH _SFR_IO8(0x002)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UCSRC _SFR_IO8(0x003)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL 6
-
-#define PCMSK1 _SFR_IO8(0x004)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-
-#define PCMSK2 _SFR_IO8(0x005)
-#define PCINT11 0
-#define PCINT12 1
-#define PCINT13 2
-#define PCINT14 3
-#define PCINT15 4
-#define PCINT16 5
-#define PCINT17 6
-
-#define PRR _SFR_IO8(0x006)
-#define PRUSART 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define BODCR _SFR_IO8(0x007)
-#define BPDSE 0
-#define BPDS 1
-
-#define ACSR _SFR_IO8(0x008)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define UBRRL _SFR_IO8(0x009)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UCSRB _SFR_IO8(0x00A)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRA _SFR_IO8(0x00B)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UDR _SFR_IO8(0x00C)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define USICR _SFR_IO8(0x00D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x00E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x00F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define PIND _SFR_IO8(0x010)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-
-#define DDRD _SFR_IO8(0x011)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-
-#define PORTD _SFR_IO8(0x012)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-
-#define GPIOR0 _SFR_IO8(0x013)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x014)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x015)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PINB _SFR_IO8(0x016)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x017)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x018)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x019)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-
-#define DDRA _SFR_IO8(0x01A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-
-#define PORTA _SFR_IO8(0x01B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-
-#define EECR _SFR_IO8(0x01C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x01D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO8(0x01E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-
-#define PCMSK _SFR_IO8(0x020)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define WDTCR _SFR_IO8(0x021)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define TCCR1C _SFR_IO8(0x022)
-#define FOC1B 6
-#define FOC1A 7
-
-#define GTCCR _SFR_IO8(0x023)
-#define PSR10 0
-
-#define ICR1 _SFR_IO16(0x024)
-
-#define ICR1L _SFR_IO8(0x024)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_IO8(0x025)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define CLKPR _SFR_IO8(0x026)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define OCR1B _SFR_IO16(0x028)
-
-#define OCR1BL _SFR_IO8(0x028)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_IO8(0x029)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1A _SFR_IO16(0x02A)
-
-#define OCR1AL _SFR_IO8(0x02A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_IO8(0x02B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCNT1 _SFR_IO16(0x02C)
-
-#define TCNT1L _SFR_IO8(0x02C)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x02D)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define TCCR1B _SFR_IO8(0x02E)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1A _SFR_IO8(0x02F)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR0A _SFR_IO8(0x030)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define OSCCAL _SFR_IO8(0x031)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define TCNT0 _SFR_IO8(0x032)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x033)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x034)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x035)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define SM0 4
-#define SE 5
-#define SM1 6
-#define PUD 7
-
-#define OCR0A _SFR_IO8(0x036)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x037)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR _SFR_IO8(0x038)
-#define OCF0A 0
-#define TOV0 1
-#define OCF0B 2
-#define ICF1 3
-#define OCF1B 5
-#define OCF1A 6
-#define TOV1 7
-
-#define TIMSK _SFR_IO8(0x039)
-#define OCIE0A 0
-#define TOIE0 1
-#define OCIE0B 2
-#define ICIE1 3
-#define OCIE1B 5
-#define OCIE1A 6
-#define TOIE1 7
-
-#define EIFR _SFR_IO8(0x03A)
-#define PCIF 5
-#define INTF0 6
-#define INTF1 7
-
-#define GIMSK _SFR_IO8(0x03B)
-#define PCIE 5
-#define INT0 6
-#define INT1 7
-
-#define OCR0B _SFR_IO8(0x03C)
-#define OCR0_0 0
-#define OCR0_1 1
-#define OCR0_2 2
-#define OCR0_3 3
-#define OCR0_4 4
-#define OCR0_5 5
-#define OCR0_6 6
-#define OCR0_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define TIMER1_CAPT_vect_num  3
-#define TIMER1_CAPT_vect      _VECTOR(3)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  4
-#define TIMER1_COMPA_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_OVF_vect_num  5
-#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  6
-#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
-#define USART_RX_vect_num  7
-#define USART_RX_vect      _VECTOR(7)  /* USART, Rx Complete */
-#define USART_UDRE_vect_num  8
-#define USART_UDRE_vect      _VECTOR(8)  /* USART Data Register Empty */
-#define USART_TX_vect_num  9
-#define USART_TX_vect      _VECTOR(9)  /* USART, Tx Complete */
-#define ANA_COMP_vect_num  10
-#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
-#define PCINT_B_vect_num  11
-#define PCINT_B_vect      _VECTOR(11)  /* Pin Change Interrupt Request B */
-#define TIMER1_COMPB_vect_num  12
-#define TIMER1_COMPB_vect      _VECTOR(12)  /*  */
-#define TIMER0_COMPA_vect_num  13
-#define TIMER0_COMPA_vect      _VECTOR(13)  /*  */
-#define TIMER0_COMPB_vect_num  14
-#define TIMER0_COMPB_vect      _VECTOR(14)  /*  */
-#define USI_START_vect_num  15
-#define USI_START_vect      _VECTOR(15)  /* USI Start Condition */
-#define USI_OVERFLOW_vect_num  16
-#define USI_OVERFLOW_vect      _VECTOR(16)  /* USI Overflow */
-#define WDT_OVERFLOW_vect_num  18
-#define WDT_OVERFLOW_vect      _VECTOR(18)  /* Watchdog Timer Overflow */
-#define PCINT_D_vect_num  20
-#define PCINT_D_vect      _VECTOR(20)  /* Pin Change Interrupt Request D */
-#define EEPROM_Ready_vect_num  17
-#define EEPROM_Ready_vect      _VECTOR(17)  /*  */
-#define PCINT_A_vect_num  19
-#define PCINT_A_vect      _VECTOR(19)  /* Pin Change Interrupt Request A */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (256)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0xFF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x0D
-
-
-/* Device Pin Definitions */
-#define RXD_DDR   DDRD
-#define RXD_PORT  PORTD
-#define RXD_PIN   PIND
-#define RXD_BIT   0
-
-#define TXD_DDR   DDRD
-#define TXD_PORT  PORTD
-#define TXD_PIN   PIND
-#define TXD_BIT   1
-
-#define PA1_DDR   DDRXTAL
-#define PA1_PORT  PORTXTAL
-#define PA1_PIN   PINXTAL
-#define PA1_BIT   XTAL2
-
-#define PA0_DDR   DDRXTAL
-#define PA0_PORT  PORTXTAL
-#define PA0_PIN   PINXTAL
-#define PA0_BIT   XTAL1
-
-#define INT0_DDR   DDRD
-#define INT0_PORT  PORTD
-#define INT0_PIN   PIND
-#define INT0_BIT   2
-
-#define XCK_DDR   DDRD
-#define XCK_PORT  PORTD
-#define XCK_PIN   PIND
-#define XCK_BIT   2
-
-#define CKOUT_DDR   DDRD
-#define CKOUT_PORT  PORTD
-#define CKOUT_PIN   PIND
-#define CKOUT_BIT   2
-
-#define INT1_DDR   DDRD
-#define INT1_PORT  PORTD
-#define INT1_PIN   PIND
-#define INT1_BIT   3
-
-#define T0_DDR   DDRD
-#define T0_PORT  PORTD
-#define T0_PIN   PIND
-#define T0_BIT   4
-
-#define T1_DDR   DDRD
-#define T1_PORT  PORTD
-#define T1_PIN   PIND
-#define T1_BIT   5
-
-#define OC0B_DDR   DDRD
-#define OC0B_PORT  PORTD
-#define OC0B_PIN   PIND
-#define OC0B_BIT   5
-
-#define ICP_DDR   DDRD
-#define ICP_PORT  PORTD
-#define ICP_PIN   PIND
-#define ICP_BIT   6
-
-#define AIN0_DDR   DDRB
-#define AIN0_PORT  PORTB
-#define AIN0_PIN   PINB
-#define AIN0_BIT   0
-
-#define AIN1_DDR   DDRB
-#define AIN1_PORT  PORTB
-#define AIN1_PIN   PINB
-#define AIN1_BIT   1
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   2
-
-#define OC1A_DDR   DDRB
-#define OC1A_PORT  PORTB
-#define OC1A_PIN   PINB
-#define OC1A_BIT   3
-
-#define OC1B_DDR   DDRB
-#define OC1B_PORT  PORTB
-#define OC1B_PIN   PINB
-#define OC1B_BIT   4
-
-#define MOSI_DDR   DDRB
-#define MOSI_PORT  PORTB
-#define MOSI_PIN   PINB
-#define MOSI_BIT   5
-
-#define DI_DDR   DDRB
-#define DI_PORT  PORTB
-#define DI_PIN   PINB
-#define DI_BIT   5
-
-#define MISO_DDR   DDRB
-#define MISO_PORT  PORTB
-#define MISO_PIN   PINB
-#define MISO_BIT   6
-
-#define DO_DDR   DDRB
-#define DO_PORT  PORTB
-#define DO_PIN   PINB
-#define DO_BIT   6
-
-#define SCK_DDR   DDRB
-#define SCK_PORT  PORTB
-#define SCK_PIN   PINB
-#define SCK_BIT   7
-
-#define SCL_DDR   DDRB
-#define SCL_PORT  PORTB
-#define SCL_PIN   PINB
-#define SCL_BIT   7
-
-/**@}*/
-#endif /* _AVR_ATtiny4313_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn43u.h b/cpukit/score/cpu/avr/avr/iotn43u.h
deleted file mode 100644
index 52038673ad..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn43u.h
+++ /dev/null
@@ -1,586 +0,0 @@
-/**
- * @file avr/iotn43u.h
- *
- * @brief Definitions for ATtiny43U
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2007 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn43u.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOTN43U_H_
-#define _AVR_IOTN43U_H_ 1
-
-/**
- *  @defgroup Avr_iotn43u ATtiny43U Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PRR _SFR_IO8(0x00)
-#define PRADC  0
-#define PRUSI  1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D  0
-#define ADC1D  1
-#define ADC2D  2
-#define ADC3D  3
-#define AIN0D  4
-#define AIN1D  5
-
-/* Reserved [0x02] */
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0  0
-#define ADTS1  1
-#define ADTS2  2
-#define ADLAR  4
-#define ACME   6
-
-#define ADC _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0  0
-#define ADCL1  1
-#define ADCL2  2
-#define ADCL3  3
-#define ADCL4  4
-#define ADCL5  5
-#define ADCL6  6
-#define ADCL7  7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0  0
-#define ADCH1  1
-#define ADCH2  2
-#define ADCH3  3
-#define ADCH4  4
-#define ADCH5  5
-#define ADCH6  6
-#define ADCH7  7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0  0
-#define ADPS1  1
-#define ADPS2  2
-#define ADIE   3
-#define ADIF   4
-#define ADATE  5
-#define ADSC   6
-#define ADEN   7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0   0
-#define MUX1   1
-#define MUX2   2
-#define REFS0  6
-
-#define ACSR _SFR_IO8(0x08)
-#define ACIS0  0
-#define ACIS1  1
-#define ACIE   3
-#define ACI    4
-#define ACO    5
-#define ACBG   6
-#define ACD    7
-
-/* Reserved [0x09], [0x0A] */
-
-#define TIFR1 _SFR_IO8(0x0B)
-#define TOV1   0
-#define OCF1A  1
-#define OCF1B  2
-
-#define TIMSK1 _SFR_IO8(0x0C)
-#define TOIE1  0
-#define OCIE1A 1
-#define OCIE1B 2
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC  0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-/* Reserved [0x11] */
-
-#define PCMSK0 _SFR_IO8(0x12)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define GPIOR0 _SFR_IO8(0x13)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x14)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x15)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0  0
-#define DDB1  1
-#define DDB2  2
-#define DDB3  3
-#define DDB4  4
-#define DDB5  5
-#define DDB6  6
-#define DDB7  7
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Reserved [0x1F] */
-
-#define PCMSK1 _SFR_IO8(0x20)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-
-#define WDTCSR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE  3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-/* Reserved [0x22] */
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define TSM   7
-
-/* Reserved [0x24], [0x25] */
-
-#define CLKPR _SFR_IO8(0x26)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-/* Reserved [0x27],[0x28],[0x29],[0x2A] */
-
-#define OCR1B _SFR_IO8(0x2B)
-#define OCR1B_0 0
-#define OCR1B_1 1
-#define OCR1B_2 2
-#define OCR1B_3 3
-#define OCR1B_4 4
-#define OCR1B_5 5
-#define OCR1B_6 6
-#define OCR1B_7 7
-
-#define OCR1A _SFR_IO8(0x2C)
-#define OCR1A_0 0
-#define OCR1A_1 1
-#define OCRA1_2 2
-#define OCRA1_3 3
-#define OCRA1_4 4
-#define OCRA1_5 5
-#define OCRA1_6 6
-#define OCRA1_7 7
-
-#define TCNT1 _SFR_IO8(0x2D)
-#define TCNT1_0 0
-#define TCNT1_1 1
-#define TCNT1_2 2
-#define TCNT1_3 3
-#define TCNT1_4 4
-#define TCNT1_5 5
-#define TCNT1_6 6
-#define TCNT1_7 7
-
-#define TCCR1B _SFR_IO8(0x2E)
-#define CS10  0
-#define CS11  1
-#define CS12  2
-#define WGM12 3
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCCR1A _SFR_IO8(0x2F)
-#define WGM10  0
-#define WGM11  1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR0A _SFR_IO8(0x30)
-#define WGM00  0
-#define WGM01  1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0 _SFR_IO8(0x32)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00  0
-#define CS01  1
-#define CS02  2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF  0
-#define EXTRF 1
-#define BORF  2
-#define WDRF  3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define BODSE 2
-#define SM0   3
-#define SM1   4
-#define SE    5
-#define PUD   6
-#define BODS  7
-
-#define OCR0A _SFR_IO8(0x36)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB  3
-#define CTPB  4
-
-#define TIFR0 _SFR_IO8(0x38)
-#define TOV0  0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIMSK0 _SFR_IO8(0x39)
-#define TOIE0  0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF0 4
-#define PCIF1 5
-#define INTF0 6
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0  6
-
-#define OCR0B _SFR_IO8(0x3C)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-
-/* External Interrupt Request 0 */
-#define INT0_vect           _VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect         _VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect         _VECTOR(3)
-
-/* Watchdog Time-out */
-#define WDT_vect            _VECTOR(4)
-
-/* Timer/Counter1 Compare Match A */
-#define TIM1_COMPA_vect     _VECTOR(5)
-
-/* Timer/Counter1 Compare Match B */
-#define TIM1_COMPB_vect     _VECTOR(6)
-
-/* Timer/Counter1 Overflow */
-#define TIM1_OVF_vect       _VECTOR(7)
-
-/* Timer/Counter0 Compare Match A */
-#define TIM0_COMPA_vect     _VECTOR(8)
-
-/* Timer/Counter0 Compare Match B */
-#define TIM0_COMPB_vect     _VECTOR(9)
-
-/* Timer/Counter0 Overflow */
-#define TIM0_OVF_vect       _VECTOR(10)
-
-/* Analog Comparator */
-#define ANA_COMP_vect       _VECTOR(11)
-
-/* ADC Conversion Complete */
-#define ADC_vect            _VECTOR(12)
-
-/* EEPROM Ready */
-#define EE_RDY_vect         _VECTOR(13)
-
-/* USI START */
-#define USI_START_vect      _VECTOR(14)
-
-/* USI Overflow */
-#define USI_OVF_vect        _VECTOR(15)
-
-#define _VECTORS_SIZE 32
-
-
-/* Constants */
-#define SPM_PAGESIZE   64
-#define RAMEND         0x15F
-#define XRAMEND        RAMEND
-#define E2END          0x3F
-#define E2PAGESIZE     4
-#define FLASHEND       0xFFF
-
-
-/* Fuse Information */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)
-#define FUSE_SUT0    (unsigned char)~_BV(4)
-#define FUSE_SUT1    (unsigned char)~_BV(5)
-#define FUSE_CKOUT   (unsigned char)~_BV(6)
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x0C
-
-
-/**@}*/
-#endif /* _AVR_IOTN43U_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn44.h b/cpukit/score/cpu/avr/avr/iotn44.h
deleted file mode 100644
index 5c41ef5484..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn44.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- * @file avr/iotn44.h
- *
- * @brief Definitions for ATtiny44
- */
-
-/*
- *  Copyright (c) 2005, Anatoly Sokolov
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_IOTN44_H_
-#define _AVR_IOTN44_H_ 1
-
-/**
- *  @defgroup Avr_iotn44 ATtiny44 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iotnx4.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x15F
-#define XRAMEND      RAMEND
-#define E2END        0xFF
-#define E2PAGESIZE   4
-#define FLASHEND     0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x07
-
-/**@}*/
-#endif /* _AVR_IOTN44_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn44a.h b/cpukit/score/cpu/avr/avr/iotn44a.h
deleted file mode 100644
index c41dfe9c19..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn44a.h
+++ /dev/null
@@ -1,830 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn44a.h - definitions for ATtiny44A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn44a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATtiny44A_H_
-#define _AVR_ATtiny44A_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define PRR _SFR_IO8(0x00)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADLAR 4
-#define ACME 6
-#define BIN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define MUX5 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSR _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define TIFR1 _SFR_IO8(0x0B)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIMSK1 _SFR_IO8(0x0C)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define PCMSK0 _SFR_IO8(0x12)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define GPIOR0 _SFR_IO8(0x13)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x14)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x15)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define PCMSK1 _SFR_IO8(0x20)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-
-#define WDTCSR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define TCCR1C _SFR_IO8(0x22)
-#define FOC1B 6
-#define FOC1A 7
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define TSM 7
-
-#define ICR1 _SFR_IO16(0x24)
-
-#define ICR1L _SFR_IO8(0x24)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_IO8(0x25)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define CLKPR _SFR_IO8(0x26)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define DWDR _SFR_IO8(0x27)
-
-#define OCR1B _SFR_IO16(0x28)
-
-#define OCR1BL _SFR_IO8(0x28)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_IO8(0x29)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define OCR1A _SFR_IO16(0x2A)
-
-#define OCR1AL _SFR_IO8(0x2A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_IO8(0x2B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCNT1 _SFR_IO16(0x2C)
-
-#define TCNT1L _SFR_IO8(0x2C)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x2D)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define TCCR1B _SFR_IO8(0x2E)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1A _SFR_IO8(0x2F)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR0A _SFR_IO8(0x30)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0 _SFR_IO8(0x32)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-
-#define OCR0A _SFR_IO8(0x36)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR0 _SFR_IO8(0x38)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIMSK0 _SFR_IO8(0x39)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF0 4
-#define PCIF1 5
-#define INTF0 6
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0 6
-
-#define OCR0B _SFR_IO8(0x3C)
-#define OCR0_0 0
-#define OCR0_1 1
-#define OCR0_2 2
-#define OCR0_3 3
-#define OCR0_4 4
-#define OCR0_5 5
-#define OCR0_6 6
-#define OCR0_7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define EXT_INT0_vect_num  1
-#define EXT_INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define PCINT0_vect_num  2
-#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  3
-#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
-#define WATCHDOG_vect_num  4
-#define WATCHDOG_vect      _VECTOR(4)  /* Watchdog Time-out */
-#define TIM1_CAPT_vect_num  5
-#define TIM1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
-#define TIM1_COMPA_vect_num  6
-#define TIM1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
-#define TIM1_COMPB_vect_num  7
-#define TIM1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
-#define TIM1_OVF_vect_num  8
-#define TIM1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
-#define TIM0_COMPA_vect_num  9
-#define TIM0_COMPA_vect      _VECTOR(9)  /* Timer/Counter0 Compare Match A */
-#define TIM0_COMPB_vect_num  10
-#define TIM0_COMPB_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match B */
-#define TIM0_OVF_vect_num  11
-#define TIM0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define ANA_COMP_vect_num  12
-#define ANA_COMP_vect      _VECTOR(12)  /* Analog Comparator */
-#define ADC_vect_num  13
-#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
-#define EE_RDY_vect_num  14
-#define EE_RDY_vect      _VECTOR(14)  /* EEPROM Ready */
-#define USI_STR_vect_num  15
-#define USI_STR_vect      _VECTOR(15)  /* USI START */
-#define USI_OVF_vect_num  16
-#define USI_OVF_vect      _VECTOR(16)  /* USI Overflow */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (256)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0xFF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x07
-
-
-/* Device Pin Definitions */
-#define ADC4_DDR   DDRA
-#define ADC4_PORT  PORTA
-#define ADC4_PIN   PINA
-#define ADC4_BIT   4
-
-#define USCK_DDR   DDRA
-#define USCK_PORT  PORTA
-#define USCK_PIN   PINA
-#define USCK_BIT   4
-
-#define SCL_DDR   DDRA
-#define SCL_PORT  PORTA
-#define SCL_PIN   PINA
-#define SCL_BIT   4
-
-#define T1_DDR   DDRA
-#define T1_PORT  PORTA
-#define T1_PIN   PINA
-#define T1_BIT   4
-
-#define PCINT4_DDR   DDRA
-#define PCINT4_PORT  PORTA
-#define PCINT4_PIN   PINA
-#define PCINT4_BIT   4
-
-#define ADC3_DDR   DDRA
-#define ADC3_PORT  PORTA
-#define ADC3_PIN   PINA
-#define ADC3_BIT   3
-
-#define T0_DDR   DDRA
-#define T0_PORT  PORTA
-#define T0_PIN   PINA
-#define T0_BIT   3
-
-#define PCINT3_DDR   DDRA
-#define PCINT3_PORT  PORTA
-#define PCINT3_PIN   PINA
-#define PCINT3_BIT   3
-
-#define ADC2_DDR   DDRA
-#define ADC2_PORT  PORTA
-#define ADC2_PIN   PINA
-#define ADC2_BIT   2
-
-#define AIN1_DDR   DDRA
-#define AIN1_PORT  PORTA
-#define AIN1_PIN   PINA
-#define AIN1_BIT   2
-
-#define PCINT2_DDR   DDRA
-#define PCINT2_PORT  PORTA
-#define PCINT2_PIN   PINA
-#define PCINT2_BIT   2
-
-#define ADC1_DDR   DDRA
-#define ADC1_PORT  PORTA
-#define ADC1_PIN   PINA
-#define ADC1_BIT   1
-
-#define AIN0_DDR   DDRA
-#define AIN0_PORT  PORTA
-#define AIN0_PIN   PINA
-#define AIN0_BIT   1
-
-#define PCINT1_DDR   DDRA
-#define PCINT1_PORT  PORTA
-#define PCINT1_PIN   PINA
-#define PCINT1_BIT   1
-
-#define ADC0_DDR   DDRA
-#define ADC0_PORT  PORTA
-#define ADC0_PIN   PINA
-#define ADC0_BIT   0
-
-#define PCINT0_DDR   DDRA
-#define PCINT0_PORT  PORTA
-#define PCINT0_PIN   PINA
-#define PCINT0_BIT   0
-
-#define PCINT8_DDR   DDRB
-#define PCINT8_PORT  PORTB
-#define PCINT8_PIN   PINB
-#define PCINT8_BIT   0
-
-#define PCINT9_DDR   DDRB
-#define PCINT9_PORT  PORTB
-#define PCINT9_PIN   PINB
-#define PCINT9_BIT   1
-
-#define PCINT11_DDR   DDRB
-#define PCINT11_PORT  PORTB
-#define PCINT11_PIN   PINB
-#define PCINT11_BIT   3
-
-#define dW_DDR   DDRB
-#define dW_PORT  PORTB
-#define dW_PIN   PINB
-#define dW_BIT   3
-
-#define PCINT10_DDR   DDRB
-#define PCINT10_PORT  PORTB
-#define PCINT10_PIN   PINB
-#define PCINT10_BIT   2
-
-#define INT0_DDR   DDRB
-#define INT0_PORT  PORTB
-#define INT0_PIN   PINB
-#define INT0_BIT   2
-
-#define OC0A_DDR   DDRB
-#define OC0A_PORT  PORTB
-#define OC0A_PIN   PINB
-#define OC0A_BIT   2
-
-#define CKOUT_DDR   DDRB
-#define CKOUT_PORT  PORTB
-#define CKOUT_PIN   PINB
-#define CKOUT_BIT   2
-
-#define PCINT7_DDR   DDRA
-#define PCINT7_PORT  PORTA
-#define PCINT7_PIN   PINA
-#define PCINT7_BIT   7
-
-#define ICP1_DDR   DDRA
-#define ICP1_PORT  PORTA
-#define ICP1_PIN   PINA
-#define ICP1_BIT   7
-
-#define OC0B_DDR   DDRA
-#define OC0B_PORT  PORTA
-#define OC0B_PIN   PINA
-#define OC0B_BIT   7
-
-#define ADC7_DDR   DDRA
-#define ADC7_PORT  PORTA
-#define ADC7_PIN   PINA
-#define ADC7_BIT   7
-
-#define PCINT6_DDR   DDRA
-#define PCINT6_PORT  PORTA
-#define PCINT6_PIN   PINA
-#define PCINT6_BIT   6
-
-#define OC1A_DDR   DDRA
-#define OC1A_PORT  PORTA
-#define OC1A_PIN   PINA
-#define OC1A_BIT   6
-
-#define DI_DDR   DDRA
-#define DI_PORT  PORTA
-#define DI_PIN   PINA
-#define DI_BIT   6
-
-#define SDA_DDR   DDRA
-#define SDA_PORT  PORTA
-#define SDA_PIN   PINA
-#define SDA_BIT   6
-
-#define MOSI_DDR   DDRA
-#define MOSI_PORT  PORTA
-#define MOSI_PIN   PINA
-#define MOSI_BIT   6
-
-#define ADC6_DDR   DDRA
-#define ADC6_PORT  PORTA
-#define ADC6_PIN   PINA
-#define ADC6_BIT   6
-
-#define ADC5_DDR   DDRA
-#define ADC5_PORT  PORTA
-#define ADC5_PIN   PINA
-#define ADC5_BIT   5
-
-#define DO_DDR   DDRA
-#define DO_PORT  PORTA
-#define DO_PIN   PINA
-#define DO_BIT   5
-
-#define MISO_DDR   DDRA
-#define MISO_PORT  PORTA
-#define MISO_PIN   PINA
-#define MISO_BIT   5
-
-#define OC1B_DDR   DDRA
-#define OC1B_PORT  PORTA
-#define OC1B_PIN   PINA
-#define OC1B_BIT   5
-
-#define PCINT5_DDR   DDRA
-#define PCINT5_PORT  PORTA
-#define PCINT5_PIN   PINA
-#define PCINT5_BIT   5
-
-#endif /* _AVR_ATtiny44A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn45.h b/cpukit/score/cpu/avr/avr/iotn45.h
deleted file mode 100644
index b8351210b0..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn45.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- * @file avr/iotn45.h
- *
- * @brief Definitions for ATtiny45
- */
-
-/*
- *   Copyright (c) 2005, Joerg Wunsch
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN45_H_
-#define _AVR_IOTN45_H_ 1
-
-/**
- *  @defgroup Avr_iotn45 ATtiny45 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iotnx5.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x15F
-#define XRAMEND      RAMEND
-#define E2END        0xFF
-#define E2PAGESIZE   4
-#define FLASHEND     0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x06
-
-
-/**@}*/
-#endif /* _AVR_IOTN45_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn461.h b/cpukit/score/cpu/avr/avr/iotn461.h
deleted file mode 100644
index 0b14646486..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn461.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny461
- */
-
-/* Copyright (c) 2006, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn461.h - definitions for ATtiny461 */
-
-#ifndef _AVR_IOTN461_H_
-#define _AVR_IOTN461_H_ 1
-
-#include <avr/iotnx61.h>
-
-/**
- * @defgroup AvrDef_iotn461 ATtiny461 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x15F
-#define XRAMEND      RAMEND
-#define E2END        0xFF
-#define E2PAGESIZE   4
-#define FLASHEND     0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x08
-
-/** @} */
-
-#endif /* _AVR_IOTN461_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn461a.h b/cpukit/score/cpu/avr/avr/iotn461a.h
deleted file mode 100644
index 8aac4fbba9..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn461a.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/**
- * @file avr/iotn461a.h
- *
- * @brief Definitions for ATtiny461A
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn461a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny461A_H_
-#define _AVR_ATtiny461A_H_ 1
-
-/**
- *  @defgroup Avr_iotn461a ATtiny461A Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define TCCR1E _SFR_IO8(0x00)
-#define OC1OE0 0
-#define OC1OE1 1
-#define OC1OE2 2
-#define OC1OE3 3
-#define OC1OE4 4
-#define OC1OE5 5
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define AREFD 3
-#define ADC3D 4
-#define ADC4D 5
-#define ADC5D 6
-#define ADC6D 7
-
-#define DIDR1 _SFR_IO8(0x02)
-#define ADC7D 4
-#define ADC8D 5
-#define ADC9D 6
-#define ADC10D 7
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define MUX5 3
-#define REFS2 4
-#define IPR 5
-#define GSEL 6
-#define BIN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSRA _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACME 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define ACSRB _SFR_IO8(0x09)
-#define ACM0 0
-#define ACM1 1
-#define ACM2 2
-#define HLEV 6
-#define HSEL 7
-
-#define GPIOR0 _SFR_IO8(0x0A)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x0B)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x0C)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define USIPP _SFR_IO8(0x11)
-#define USIPOS 0
-
-#define OCR0B _SFR_IO8(0x12)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0A _SFR_IO8(0x13)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define TCNT0H _SFR_IO8(0x14)
-#define TCNT0H_0 0
-#define TCNT0H_1 1
-#define TCNT0H_2 2
-#define TCNT0H_3 3
-#define TCNT0H_4 4
-#define TCNT0H_5 5
-#define TCNT0H_6 6
-#define TCNT0H_7 7
-
-#define TCCR0A _SFR_IO8(0x15)
-#define WGM00 0
-#define ACIC0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define DWDR _SFR_IO8(0x20)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define WDTCR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define PCMSK1 _SFR_IO8(0x22)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK0 _SFR_IO8(0x23)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define DT1 _SFR_IO8(0x24)
-#define DT1L0 0
-#define DT1L1 1
-#define DT1L2 2
-#define DT1L3 3
-#define DT1H0 4
-#define DT1H1 5
-#define DT1H2 6
-#define DT1H3 7
-
-#define TC1H _SFR_IO8(0x25)
-#define TC18 0
-#define TC19 1
-
-#define TCCR1D _SFR_IO8(0x26)
-#define WGM10 0
-#define WGM11 1
-#define FPF1 2
-#define FPAC1 3
-#define FPES1 4
-#define FPNC1 5
-#define FPEN1 6
-#define FPIE1 7
-
-#define TCCR1C _SFR_IO8(0x27)
-#define PWM1D 0
-#define FOC1D 1
-#define COM1D0 2
-#define COM1D1 3
-#define COM1B0S 4
-#define COM1B1S 5
-#define COM1A0S 6
-#define COM1A1S 7
-
-#define CLKPR _SFR_IO8(0x28)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PCKE 2
-#define LSM 7
-
-#define OCR1D _SFR_IO8(0x2A)
-#define OCR1D0 0
-#define OCR1D1 1
-#define OCR1D2 2
-#define OCR1D3 3
-#define OCR1D4 4
-#define OCR1D5 5
-#define OCR1D6 6
-#define OCR1D7 7
-
-#define OCR1C _SFR_IO8(0x2B)
-#define OCR1C0 0
-#define OCR1C1 1
-#define OCR1C2 2
-#define OCR1C3 3
-#define OCR1C4 4
-#define OCR1C5 5
-#define OCR1C6 6
-#define OCR1C7 7
-
-#define OCR1B _SFR_IO8(0x2C)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define OCR1A _SFR_IO8(0x2D)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define TCNT1 _SFR_IO8(0x2E)
-#define TC1H_0 0
-#define TC1H_1 1
-#define TC1H_2 2
-#define TC1H_3 3
-#define TC1H_4 4
-#define TC1H_5 5
-#define TC1H_6 6
-#define TC1H_7 7
-
-#define TCCR1B _SFR_IO8(0x2F)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define CS13 3
-#define DTPS10 4
-#define DTPS11 5
-#define PSR1 6
-
-#define TCCR1A _SFR_IO8(0x30)
-#define PWM1B 0
-#define PWM1A 1
-#define FOC1B 2
-#define FOC1A 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0L _SFR_IO8(0x32)
-#define TCNT0L_0 0
-#define TCNT0L_1 1
-#define TCNT0L_2 2
-#define TCNT0L_3 3
-#define TCNT0L_4 4
-#define TCNT0L_5 5
-#define TCNT0L_6 6
-#define TCNT0L_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define PSR0 3
-#define TSM 4
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define BODSE 2
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-#define BODS 7
-
-#define PRR _SFR_IO8(0x36)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR _SFR_IO8(0x38)
-#define ICF0 0
-#define TOV0 1
-#define TOV1 2
-#define OCF0B 3
-#define OCF0A 4
-#define OCF1B 5
-#define OCF1A 6
-#define OCF1D 7
-
-#define TIMSK _SFR_IO8(0x39)
-#define TICIE0 0
-#define TOIE0 1
-#define TOIE1 2
-#define OCIE0B 3
-#define OCIE0A 4
-#define OCIE1B 5
-#define OCIE1A 6
-#define OCIE1D 7
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF 5
-#define INTF0 6
-#define INTF1 7
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0 6
-#define INT1 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
-#define PCINT_vect_num  2
-#define PCINT_vect      _VECTOR(2)  /* Pin Change Interrupt */
-#define TIMER1_COMPA_vect_num  3
-#define TIMER1_COMPA_vect      _VECTOR(3)  /* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPB_vect_num  4
-#define TIMER1_COMPB_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match 1B */
-#define TIMER1_OVF_vect_num  5
-#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  6
-#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
-#define USI_START_vect_num  7
-#define USI_START_vect      _VECTOR(7)  /* USI Start */
-#define USI_OVF_vect_num  8
-#define USI_OVF_vect      _VECTOR(8)  /* USI Overflow */
-#define EE_RDY_vect_num  9
-#define EE_RDY_vect      _VECTOR(9)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  10
-#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
-#define ADC_vect_num  11
-#define ADC_vect      _VECTOR(11)  /* ADC Conversion Complete */
-#define WDT_vect_num  12
-#define WDT_vect      _VECTOR(12)  /* Watchdog Time-Out */
-#define INT1_vect_num  13
-#define INT1_vect      _VECTOR(13)  /* External Interrupt 1 */
-#define TIMER0_COMPA_vect_num  14
-#define TIMER0_COMPA_vect      _VECTOR(14)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  15
-#define TIMER0_COMPB_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_CAPT_vect_num  16
-#define TIMER0_CAPT_vect      _VECTOR(16)  /* ADC Conversion Complete */
-#define TIMER1_COMPD_vect_num  17
-#define TIMER1_COMPD_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match D */
-#define FAULT_PROTECTION_vect_num  18
-#define FAULT_PROTECTION_vect      _VECTOR(18)  /* Timer/Counter1 Fault Protection */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (256)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0xFF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x08
-
-
-/* Device Pin Definitions */
-#define DI_B_DDR   DDRMOSI
-#define DI_B_PORT  PORTMOSI
-#define DI_B_PIN   PINMOSI
-#define DI_B_BIT   MOSI
-
-#define SDA_B_DDR   DDRMOSI
-#define SDA_B_PORT  PORTMOSI
-#define SDA_B_PIN   PINMOSI
-#define SDA_B_BIT   MOSI
-
-#define _OC1A_DDR   DDRMOSI
-#define _OC1A_PORT  PORTMOSI
-#define _OC1A_PIN   PINMOSI
-#define _OC1A_BIT   MOSI
-
-#define PCINT8_DDR   DDRMOSI
-#define PCINT8_PORT  PORTMOSI
-#define PCINT8_PIN   PINMOSI
-#define PCINT8_BIT   MOSI
-
-#define PB0_DDR   DDRMOSI
-#define PB0_PORT  PORTMOSI
-#define PB0_PIN   PINMOSI
-#define PB0_BIT   MOSI
-
-#define DO_B_DDR   DDRMISO
-#define DO_B_PORT  PORTMISO
-#define DO_B_PIN   PINMISO
-#define DO_B_BIT   MISO
-
-#define OC1A_DDR   DDRMISO
-#define OC1A_PORT  PORTMISO
-#define OC1A_PIN   PINMISO
-#define OC1A_BIT   MISO
-
-#define PCINT9_DDR   DDRMISO
-#define PCINT9_PORT  PORTMISO
-#define PCINT9_PIN   PINMISO
-#define PCINT9_BIT   MISO
-
-#define PB1_DDR   DDRMISO
-#define PB1_PORT  PORTMISO
-#define PB1_PIN   PINMISO
-#define PB1_BIT   MISO
-
-#define USCK_B_DDR   DDRSCK
-#define USCK_B_PORT  PORTSCK
-#define USCK_B_PIN   PINSCK
-#define USCK_B_BIT   SCK
-
-#define SCL_B_DDR   DDRSCK
-#define SCL_B_PORT  PORTSCK
-#define SCL_B_PIN   PINSCK
-#define SCL_B_BIT   SCK
-
-#define OC1B_DDR   DDRSCK
-#define OC1B_PORT  PORTSCK
-#define OC1B_PIN   PINSCK
-#define OC1B_BIT   SCK
-
-#define PCINT10_DDR   DDRSCK
-#define PCINT10_PORT  PORTSCK
-#define PCINT10_PIN   PINSCK
-#define PCINT10_BIT   SCK
-
-#define PB2_DDR   DDRSCK
-#define PB2_PORT  PORTSCK
-#define PB2_PIN   PINSCK
-#define PB2_BIT   SCK
-
-#define PCINT11_DDR   DDROC1B
-#define PCINT11_PORT  PORTOC1B
-#define PCINT11_PIN   PINOC1B
-#define PCINT11_BIT   OC1B
-
-#define PB3_DDR   DDROC1B
-#define PB3_PORT  PORTOC1B
-#define PB3_PIN   PINOC1B
-#define PB3_BIT   OC1B
-
-#define PCINT12_DDR   DDRADC
-#define PCINT12_PORT  PORTADC
-#define PCINT12_PIN   PINADC
-#define PCINT12_BIT   ADC7
-
-#define _OC1D_DDR   DDRADC
-#define _OC1D_PORT  PORTADC
-#define _OC1D_PIN   PINADC
-#define _OC1D_BIT   ADC7
-
-#define CLKI_DDR   DDRADC
-#define CLKI_PORT  PORTADC
-#define CLKI_PIN   PINADC
-#define CLKI_BIT   ADC7
-
-#define PB4_DDR   DDRADC
-#define PB4_PORT  PORTADC
-#define PB4_PIN   PINADC
-#define PB4_BIT   ADC7
-
-#define PCINT13_DDR   DDRADC
-#define PCINT13_PORT  PORTADC
-#define PCINT13_PIN   PINADC
-#define PCINT13_BIT   ADC8
-
-#define OC1D_DDR   DDRADC
-#define OC1D_PORT  PORTADC
-#define OC1D_PIN   PINADC
-#define OC1D_BIT   ADC8
-
-#define CKLO_DDR   DDRADC
-#define CKLO_PORT  PORTADC
-#define CKLO_PIN   PINADC
-#define CKLO_BIT   ADC8
-
-#define PB5_DDR   DDRADC
-#define PB5_PORT  PORTADC
-#define PB5_PIN   PINADC
-#define PB5_BIT   ADC8
-
-#define INT0_DDR   DDRADC
-#define INT0_PORT  PORTADC
-#define INT0_PIN   PINADC
-#define INT0_BIT   ADC9
-
-#define T0_DDR   DDRADC
-#define T0_PORT  PORTADC
-#define T0_PIN   PINADC
-#define T0_BIT   ADC9
-
-#define PCINT14_DDR   DDRADC
-#define PCINT14_PORT  PORTADC
-#define PCINT14_PIN   PINADC
-#define PCINT14_BIT   ADC9
-
-#define PB6_DDR   DDRADC
-#define PB6_PORT  PORTADC
-#define PB6_PIN   PINADC
-#define PB6_BIT   ADC9
-
-#define PCINT15_DDR   DDRADC1
-#define PCINT15_PORT  PORTADC1
-#define PCINT15_PIN   PINADC1
-#define PCINT15_BIT   ADC10
-
-#define PB7_DDR   DDRADC1
-#define PB7_PORT  PORTADC1
-#define PB7_PIN   PINADC1
-#define PB7_BIT   ADC10
-
-#define AIN1_DDR   DDRADC
-#define AIN1_PORT  PORTADC
-#define AIN1_PIN   PINADC
-#define AIN1_BIT   ADC6
-
-#define PCINT7_DDR   DDRADC
-#define PCINT7_PORT  PORTADC
-#define PCINT7_PIN   PINADC
-#define PCINT7_BIT   ADC6
-
-#define PA7_DDR   DDRADC
-#define PA7_PORT  PORTADC
-#define PA7_PIN   PINADC
-#define PA7_BIT   ADC6
-
-#define AIN0_DDR   DDRADC
-#define AIN0_PORT  PORTADC
-#define AIN0_PIN   PINADC
-#define AIN0_BIT   ADC5
-
-#define PCINT6_DDR   DDRADC
-#define PCINT6_PORT  PORTADC
-#define PCINT6_PIN   PINADC
-#define PCINT6_BIT   ADC5
-
-#define PA6_DDR   DDRADC
-#define PA6_PORT  PORTADC
-#define PA6_PIN   PINADC
-#define PA6_BIT   ADC5
-
-#define AIN2_DDR   DDRADC
-#define AIN2_PORT  PORTADC
-#define AIN2_PIN   PINADC
-#define AIN2_BIT   ADC4
-
-#define PCINT5_DDR   DDRADC
-#define PCINT5_PORT  PORTADC
-#define PCINT5_PIN   PINADC
-#define PCINT5_BIT   ADC4
-
-#define PA5_DDR   DDRADC
-#define PA5_PORT  PORTADC
-#define PA5_PIN   PINADC
-#define PA5_BIT   ADC4
-
-#define ICP0_DDR   DDRADC
-#define ICP0_PORT  PORTADC
-#define ICP0_PIN   PINADC
-#define ICP0_BIT   ADC3
-
-#define PCINT4_DDR   DDRADC
-#define PCINT4_PORT  PORTADC
-#define PCINT4_PIN   PINADC
-#define PCINT4_BIT   ADC3
-
-#define PA4_DDR   DDRADC
-#define PA4_PORT  PORTADC
-#define PA4_PIN   PINADC
-#define PA4_BIT   ADC3
-
-#define PCINT3_DDR   DDRAREF
-#define PCINT3_PORT  PORTAREF
-#define PCINT3_PIN   PINAREF
-#define PCINT3_BIT   AREF
-
-#define PA3_DDR   DDRAREF
-#define PA3_PORT  PORTAREF
-#define PA3_PIN   PINAREF
-#define PA3_BIT   AREF
-
-#define INT1_DDR   DDRADC
-#define INT1_PORT  PORTADC
-#define INT1_PIN   PINADC
-#define INT1_BIT   ADC2
-
-#define USCK_A_DDR   DDRADC
-#define USCK_A_PORT  PORTADC
-#define USCK_A_PIN   PINADC
-#define USCK_A_BIT   ADC2
-
-#define SCL_A_DDR   DDRADC
-#define SCL_A_PORT  PORTADC
-#define SCL_A_PIN   PINADC
-#define SCL_A_BIT   ADC2
-
-#define PCINT2_DDR   DDRADC
-#define PCINT2_PORT  PORTADC
-#define PCINT2_PIN   PINADC
-#define PCINT2_BIT   ADC2
-
-#define PA2_DDR   DDRADC
-#define PA2_PORT  PORTADC
-#define PA2_PIN   PINADC
-#define PA2_BIT   ADC2
-
-#define DO_A_DDR   DDRADC
-#define DO_A_PORT  PORTADC
-#define DO_A_PIN   PINADC
-#define DO_A_BIT   ADC1
-
-#define PCINT1_DDR   DDRADC
-#define PCINT1_PORT  PORTADC
-#define PCINT1_PIN   PINADC
-#define PCINT1_BIT   ADC1
-
-#define PA1_DDR   DDRADC
-#define PA1_PORT  PORTADC
-#define PA1_PIN   PINADC
-#define PA1_BIT   ADC1
-
-#define DI_A_DDR   DDRADC
-#define DI_A_PORT  PORTADC
-#define DI_A_PIN   PINADC
-#define DI_A_BIT   ADC0
-
-#define SDA_A_DDR   DDRADC
-#define SDA_A_PORT  PORTADC
-#define SDA_A_PIN   PINADC
-#define SDA_A_BIT   ADC0
-
-#define PCINT0_DDR   DDRADC
-#define PCINT0_PORT  PORTADC
-#define PCINT0_PIN   PINADC
-#define PCINT0_BIT   ADC0
-
-#define PA0_DDR   DDRADC
-#define PA0_PORT  PORTADC
-#define PA0_PIN   PINADC
-#define PA0_BIT   ADC0
-
-/**@}*/
-#endif /* _AVR_ATtiny461A_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn48.h b/cpukit/score/cpu/avr/avr/iotn48.h
deleted file mode 100644
index d878e98305..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn48.h
+++ /dev/null
@@ -1,767 +0,0 @@
-/**
- * @file avr/iotn48.h
- *
- * @brief Definitions for ATtiny48
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn48.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOTN48_H_
-#define _AVR_IOTN48_H_ 1
-
-/**
- *  @defgroup Avr_iotn48 ATtiny48 Definitons
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINA _SFR_IO8(0x0C)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-
-#define DDRA _SFR_IO8(0x0D)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-
-#define PORTA _SFR_IO8(0x0E)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-
-#define PORTCR _SFR_IO8(0x12)
-#define PUDA 0
-#define PUDB 1
-#define PUDC 2
-#define PUDD 3
-#define BBMA 4
-#define BBMB 5
-#define BBMC 6
-#define BBMD 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define CTC0 3
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-#define RWWSB 6
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK3 _SFR_MEM8(0x6A)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 2
-#define TWS4 3
-#define TWS5 4
-#define TWS6 5
-#define TWS7 6
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define TWIHSR _SFR_MEM8(0xBE)  /* Deprecated */
-#define TWHSR _SFR_MEM8(0xBE)
-#define TWIHS 0
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-
-#define INT0_vect         _VECTOR(1)
-#define INT1_vect         _VECTOR(2)
-#define PCINT0_vect       _VECTOR(3)
-#define PCINT1_vect       _VECTOR(4)
-#define PCINT2_vect       _VECTOR(5)
-#define PCINT3_vect       _VECTOR(6)
-#define WDT_vect          _VECTOR(7)
-#define TIMER1_CAPT_vect  _VECTOR(8)
-#define TIMER1_COMPA_vect _VECTOR(9)
-#define TIMER1_COMPB_vect _VECTOR(10)
-#define TIMER1_OVF_vect   _VECTOR(11)
-#define TIMER0_COMPA_vect _VECTOR(12)
-#define TIMER0_COMPB_vect _VECTOR(13)
-#define TIMER0_OVF_vect   _VECTOR(14)
-#define SPI_STC_vect      _VECTOR(15)
-#define ADC_vect          _VECTOR(16)
-#define EE_READY_vect     _VECTOR(17)
-#define ANALOG_COMP_vect  _VECTOR(18)
-#define TWI_vect          _VECTOR(19)
-
-#define _VECTORS_SIZE 40
-
-
-/* Constants */
-#define SPM_PAGESIZE 32
-#define RAMEND       0x1FF
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x3F
-#define E2PAGESIZE   4
-#define FLASHEND     0xFFF
-
-
-/* Fuse Information */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define FUSE_CKOUT  (unsigned char)~_BV(6) /* Clock output */
-#define FUSE_SUT1   (unsigned char)~_BV(5) /* Select start-up time */
-#define FUSE_SUT0   (unsigned char)~_BV(4) /* Select start-up time */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
-#define FUSE_EESAVE      (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON       (unsigned char)~_BV(4) /* Watchdog Timer Always On */
-#define FUSE_SPIEN       (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN        (unsigned char)~_BV(6) /* debugWIRE Enable */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7) /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0) /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x09
-
-/**@}*/
-#endif /* _AVR_IOTN48_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn84.h b/cpukit/score/cpu/avr/avr/iotn84.h
deleted file mode 100644
index 13ba31c309..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn84.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright (c) 2005, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn84.h - definitions for ATtiny84 */
-
-#ifndef _AVR_IOTN84_H_
-#define _AVR_IOTN84_H_ 1
-
-#include <avr/iotnx4.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x25F
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define FUSE_HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0C
-
-
-#endif /* _AVR_IOTN84_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn85.h b/cpukit/score/cpu/avr/avr/iotn85.h
deleted file mode 100644
index 2fa4d3f0b1..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn85.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- * @file avr/iotn85.h
- *
- * @brief Definitions for ATtiny85
- */
-
-/*
- * Copyright (c) 2005, Joerg Wunsch
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTN85_H_
-#define _AVR_IOTN85_H_ 1
-
-/**
- * @defgroup Avr_iotn85 ATtiny85 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iotnx5.h>
-
-/* Constants */
-#define SPM_PAGESIZE 64
-#define RAMEND       0x25F
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0B
-
-/** @} */
-#endif /* _AVR_IOTN85_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn861.h b/cpukit/score/cpu/avr/avr/iotn861.h
deleted file mode 100644
index 54c86570c0..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn861.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright (c) 2006, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn861.h - definitions for ATtiny861 */
-
-#ifndef _AVR_IOTN861_H_
-#define _AVR_IOTN861_H_ 1
-
-#include <avr/iotnx61.h>
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE 64
-#define RAMEND       0x25F
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
-                       FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_DWEN        (unsigned char)~_BV(6)
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
-#define EFUSE_DEFAULT (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits 
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0D
-/** @} */
-
-#endif /* _AVR_IOTN861_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn861a.h b/cpukit/score/cpu/avr/avr/iotn861a.h
deleted file mode 100644
index 654f0959fd..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn861a.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/**
- * @file avr/iotn861a.h
- *
- * @brief Definitions for ATtiny861A
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn861a.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny861A_H_
-#define _AVR_ATtiny861A_H_ 1
-
-/**
- *  @defgroup Avr_iotn861a ATtiny861A Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define TCCR1E _SFR_IO8(0x00)
-#define OC1OE0 0
-#define OC1OE1 1
-#define OC1OE2 2
-#define OC1OE3 3
-#define OC1OE4 4
-#define OC1OE5 5
-
-#define DIDR0 _SFR_IO8(0x01)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define AREFD 3
-#define ADC3D 4
-#define ADC4D 5
-#define ADC5D 6
-#define ADC6D 7
-
-#define DIDR1 _SFR_IO8(0x02)
-#define ADC7D 4
-#define ADC8D 5
-#define ADC9D 6
-#define ADC10D 7
-
-#define ADCSRB _SFR_IO8(0x03)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define MUX5 3
-#define REFS2 4
-#define IPR 5
-#define GSEL 6
-#define BIN 7
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x04)
-#endif
-#define ADCW _SFR_IO16(0x04)
-
-#define ADCL _SFR_IO8(0x04)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x05)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADMUX _SFR_IO8(0x07)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define ACSRA _SFR_IO8(0x08)
-#define ACIS0 0
-#define ACIS1 1
-#define ACME 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define ACSRB _SFR_IO8(0x09)
-#define ACM0 0
-#define ACM1 1
-#define ACM2 2
-#define HLEV 6
-#define HSEL 7
-
-#define GPIOR0 _SFR_IO8(0x0A)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x0B)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x0C)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define USICR _SFR_IO8(0x0D)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_IO8(0x0F)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_IO8(0x10)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define USIPP _SFR_IO8(0x11)
-#define USIPOS 0
-
-#define OCR0B _SFR_IO8(0x12)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0A _SFR_IO8(0x13)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define TCNT0H _SFR_IO8(0x14)
-#define TCNT0H_0 0
-#define TCNT0H_1 1
-#define TCNT0H_2 2
-#define TCNT0H_3 3
-#define TCNT0H_4 4
-#define TCNT0H_5 5
-#define TCNT0H_6 6
-#define TCNT0H_7 7
-
-#define TCCR0A _SFR_IO8(0x15)
-#define WGM00 0
-#define ACIC0 3
-#define ICES0 4
-#define ICNC0 5
-#define ICEN0 6
-#define TCW0 7
-
-#define PINB _SFR_IO8(0x16)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x17)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x18)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINA _SFR_IO8(0x19)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x1A)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x1B)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define DWDR _SFR_IO8(0x20)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define WDTCR _SFR_IO8(0x21)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define PCMSK1 _SFR_IO8(0x22)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK0 _SFR_IO8(0x23)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define DT1 _SFR_IO8(0x24)
-#define DT1L0 0
-#define DT1L1 1
-#define DT1L2 2
-#define DT1L3 3
-#define DT1H0 4
-#define DT1H1 5
-#define DT1H2 6
-#define DT1H3 7
-
-#define TC1H _SFR_IO8(0x25)
-#define TC18 0
-#define TC19 1
-
-#define TCCR1D _SFR_IO8(0x26)
-#define WGM10 0
-#define WGM11 1
-#define FPF1 2
-#define FPAC1 3
-#define FPES1 4
-#define FPNC1 5
-#define FPEN1 6
-#define FPIE1 7
-
-#define TCCR1C _SFR_IO8(0x27)
-#define PWM1D 0
-#define FOC1D 1
-#define COM1D0 2
-#define COM1D1 3
-#define COM1B0S 4
-#define COM1B1S 5
-#define COM1A0S 6
-#define COM1A1S 7
-
-#define CLKPR _SFR_IO8(0x28)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PCKE 2
-#define LSM 7
-
-#define OCR1D _SFR_IO8(0x2A)
-#define OCR1D0 0
-#define OCR1D1 1
-#define OCR1D2 2
-#define OCR1D3 3
-#define OCR1D4 4
-#define OCR1D5 5
-#define OCR1D6 6
-#define OCR1D7 7
-
-#define OCR1C _SFR_IO8(0x2B)
-#define OCR1C0 0
-#define OCR1C1 1
-#define OCR1C2 2
-#define OCR1C3 3
-#define OCR1C4 4
-#define OCR1C5 5
-#define OCR1C6 6
-#define OCR1C7 7
-
-#define OCR1B _SFR_IO8(0x2C)
-#define OCR1B0 0
-#define OCR1B1 1
-#define OCR1B2 2
-#define OCR1B3 3
-#define OCR1B4 4
-#define OCR1B5 5
-#define OCR1B6 6
-#define OCR1B7 7
-
-#define OCR1A _SFR_IO8(0x2D)
-#define OCR1A0 0
-#define OCR1A1 1
-#define OCR1A2 2
-#define OCR1A3 3
-#define OCR1A4 4
-#define OCR1A5 5
-#define OCR1A6 6
-#define OCR1A7 7
-
-#define TCNT1 _SFR_IO8(0x2E)
-#define TC1H_0 0
-#define TC1H_1 1
-#define TC1H_2 2
-#define TC1H_3 3
-#define TC1H_4 4
-#define TC1H_5 5
-#define TC1H_6 6
-#define TC1H_7 7
-
-#define TCCR1B _SFR_IO8(0x2F)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define CS13 3
-#define DTPS10 4
-#define DTPS11 5
-#define PSR1 6
-
-#define TCCR1A _SFR_IO8(0x30)
-#define PWM1B 0
-#define PWM1A 1
-#define FOC1B 2
-#define FOC1A 3
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define OSCCAL _SFR_IO8(0x31)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define TCNT0L _SFR_IO8(0x32)
-#define TCNT0L_0 0
-#define TCNT0L_1 1
-#define TCNT0L_2 2
-#define TCNT0L_3 3
-#define TCNT0L_4 4
-#define TCNT0L_5 5
-#define TCNT0L_6 6
-#define TCNT0L_7 7
-
-#define TCCR0B _SFR_IO8(0x33)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define PSR0 3
-#define TSM 4
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define ISC00 0
-#define ISC01 1
-#define BODSE 2
-#define SM0 3
-#define SM1 4
-#define SE 5
-#define PUD 6
-#define BODS 7
-
-#define PRR _SFR_IO8(0x36)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR _SFR_IO8(0x38)
-#define ICF0 0
-#define TOV0 1
-#define TOV1 2
-#define OCF0B 3
-#define OCF0A 4
-#define OCF1B 5
-#define OCF1A 6
-#define OCF1D 7
-
-#define TIMSK _SFR_IO8(0x39)
-#define TICIE0 0
-#define TOIE0 1
-#define TOIE1 2
-#define OCIE0B 3
-#define OCIE0A 4
-#define OCIE1B 5
-#define OCIE1A 6
-#define OCIE1D 7
-
-#define GIFR _SFR_IO8(0x3A)
-#define PCIF 5
-#define INTF0 6
-#define INTF1 7
-
-#define GIMSK _SFR_IO8(0x3B)
-#define PCIE0 4
-#define PCIE1 5
-#define INT0 6
-#define INT1 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
-#define PCINT_vect_num  2
-#define PCINT_vect      _VECTOR(2)  /* Pin Change Interrupt */
-#define TIMER1_COMPA_vect_num  3
-#define TIMER1_COMPA_vect      _VECTOR(3)  /* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPB_vect_num  4
-#define TIMER1_COMPB_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match 1B */
-#define TIMER1_OVF_vect_num  5
-#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
-#define TIMER0_OVF_vect_num  6
-#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
-#define USI_START_vect_num  7
-#define USI_START_vect      _VECTOR(7)  /* USI Start */
-#define USI_OVF_vect_num  8
-#define USI_OVF_vect      _VECTOR(8)  /* USI Overflow */
-#define EE_RDY_vect_num  9
-#define EE_RDY_vect      _VECTOR(9)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  10
-#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
-#define ADC_vect_num  11
-#define ADC_vect      _VECTOR(11)  /* ADC Conversion Complete */
-#define WDT_vect_num  12
-#define WDT_vect      _VECTOR(12)  /* Watchdog Time-Out */
-#define INT1_vect_num  13
-#define INT1_vect      _VECTOR(13)  /* External Interrupt 1 */
-#define TIMER0_COMPA_vect_num  14
-#define TIMER0_COMPA_vect      _VECTOR(14)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  15
-#define TIMER0_COMPB_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_CAPT_vect_num  16
-#define TIMER0_CAPT_vect      _VECTOR(16)  /* ADC Conversion Complete */
-#define TIMER1_COMPD_vect_num  17
-#define TIMER1_COMPD_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match D */
-#define FAULT_PROTECTION_vect_num  18
-#define FAULT_PROTECTION_vect      _VECTOR(18)  /* Timer/Counter1 Fault Protection */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x60)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x0D
-
-
-/* Device Pin Definitions */
-#define DI_B_DDR   DDRMOSI
-#define DI_B_PORT  PORTMOSI
-#define DI_B_PIN   PINMOSI
-#define DI_B_BIT   MOSI
-
-#define SDA_B_DDR   DDRMOSI
-#define SDA_B_PORT  PORTMOSI
-#define SDA_B_PIN   PINMOSI
-#define SDA_B_BIT   MOSI
-
-#define _OC1A_DDR   DDRMOSI
-#define _OC1A_PORT  PORTMOSI
-#define _OC1A_PIN   PINMOSI
-#define _OC1A_BIT   MOSI
-
-#define PCINT8_DDR   DDRMOSI
-#define PCINT8_PORT  PORTMOSI
-#define PCINT8_PIN   PINMOSI
-#define PCINT8_BIT   MOSI
-
-#define PB0_DDR   DDRMOSI
-#define PB0_PORT  PORTMOSI
-#define PB0_PIN   PINMOSI
-#define PB0_BIT   MOSI
-
-#define DO_B_DDR   DDRMISO
-#define DO_B_PORT  PORTMISO
-#define DO_B_PIN   PINMISO
-#define DO_B_BIT   MISO
-
-#define OC1A_DDR   DDRMISO
-#define OC1A_PORT  PORTMISO
-#define OC1A_PIN   PINMISO
-#define OC1A_BIT   MISO
-
-#define PCINT9_DDR   DDRMISO
-#define PCINT9_PORT  PORTMISO
-#define PCINT9_PIN   PINMISO
-#define PCINT9_BIT   MISO
-
-#define PB1_DDR   DDRMISO
-#define PB1_PORT  PORTMISO
-#define PB1_PIN   PINMISO
-#define PB1_BIT   MISO
-
-#define USCK_B_DDR   DDRSCK
-#define USCK_B_PORT  PORTSCK
-#define USCK_B_PIN   PINSCK
-#define USCK_B_BIT   SCK
-
-#define SCL_B_DDR   DDRSCK
-#define SCL_B_PORT  PORTSCK
-#define SCL_B_PIN   PINSCK
-#define SCL_B_BIT   SCK
-
-#define OC1B_DDR   DDRSCK
-#define OC1B_PORT  PORTSCK
-#define OC1B_PIN   PINSCK
-#define OC1B_BIT   SCK
-
-#define PCINT10_DDR   DDRSCK
-#define PCINT10_PORT  PORTSCK
-#define PCINT10_PIN   PINSCK
-#define PCINT10_BIT   SCK
-
-#define PB2_DDR   DDRSCK
-#define PB2_PORT  PORTSCK
-#define PB2_PIN   PINSCK
-#define PB2_BIT   SCK
-
-#define PCINT11_DDR   DDROC1B
-#define PCINT11_PORT  PORTOC1B
-#define PCINT11_PIN   PINOC1B
-#define PCINT11_BIT   OC1B
-
-#define PB3_DDR   DDROC1B
-#define PB3_PORT  PORTOC1B
-#define PB3_PIN   PINOC1B
-#define PB3_BIT   OC1B
-
-#define PCINT12_DDR   DDRADC
-#define PCINT12_PORT  PORTADC
-#define PCINT12_PIN   PINADC
-#define PCINT12_BIT   ADC7
-
-#define _OC1D_DDR   DDRADC
-#define _OC1D_PORT  PORTADC
-#define _OC1D_PIN   PINADC
-#define _OC1D_BIT   ADC7
-
-#define CLKI_DDR   DDRADC
-#define CLKI_PORT  PORTADC
-#define CLKI_PIN   PINADC
-#define CLKI_BIT   ADC7
-
-#define PB4_DDR   DDRADC
-#define PB4_PORT  PORTADC
-#define PB4_PIN   PINADC
-#define PB4_BIT   ADC7
-
-#define PCINT13_DDR   DDRADC
-#define PCINT13_PORT  PORTADC
-#define PCINT13_PIN   PINADC
-#define PCINT13_BIT   ADC8
-
-#define OC1D_DDR   DDRADC
-#define OC1D_PORT  PORTADC
-#define OC1D_PIN   PINADC
-#define OC1D_BIT   ADC8
-
-#define CKLO_DDR   DDRADC
-#define CKLO_PORT  PORTADC
-#define CKLO_PIN   PINADC
-#define CKLO_BIT   ADC8
-
-#define PB5_DDR   DDRADC
-#define PB5_PORT  PORTADC
-#define PB5_PIN   PINADC
-#define PB5_BIT   ADC8
-
-#define INT0_DDR   DDRADC
-#define INT0_PORT  PORTADC
-#define INT0_PIN   PINADC
-#define INT0_BIT   ADC9
-
-#define T0_DDR   DDRADC
-#define T0_PORT  PORTADC
-#define T0_PIN   PINADC
-#define T0_BIT   ADC9
-
-#define PCINT14_DDR   DDRADC
-#define PCINT14_PORT  PORTADC
-#define PCINT14_PIN   PINADC
-#define PCINT14_BIT   ADC9
-
-#define PB6_DDR   DDRADC
-#define PB6_PORT  PORTADC
-#define PB6_PIN   PINADC
-#define PB6_BIT   ADC9
-
-#define PCINT15_DDR   DDRADC1
-#define PCINT15_PORT  PORTADC1
-#define PCINT15_PIN   PINADC1
-#define PCINT15_BIT   ADC10
-
-#define PB7_DDR   DDRADC1
-#define PB7_PORT  PORTADC1
-#define PB7_PIN   PINADC1
-#define PB7_BIT   ADC10
-
-#define AIN1_DDR   DDRADC
-#define AIN1_PORT  PORTADC
-#define AIN1_PIN   PINADC
-#define AIN1_BIT   ADC6
-
-#define PCINT7_DDR   DDRADC
-#define PCINT7_PORT  PORTADC
-#define PCINT7_PIN   PINADC
-#define PCINT7_BIT   ADC6
-
-#define PA7_DDR   DDRADC
-#define PA7_PORT  PORTADC
-#define PA7_PIN   PINADC
-#define PA7_BIT   ADC6
-
-#define AIN0_DDR   DDRADC
-#define AIN0_PORT  PORTADC
-#define AIN0_PIN   PINADC
-#define AIN0_BIT   ADC5
-
-#define PCINT6_DDR   DDRADC
-#define PCINT6_PORT  PORTADC
-#define PCINT6_PIN   PINADC
-#define PCINT6_BIT   ADC5
-
-#define PA6_DDR   DDRADC
-#define PA6_PORT  PORTADC
-#define PA6_PIN   PINADC
-#define PA6_BIT   ADC5
-
-#define AIN2_DDR   DDRADC
-#define AIN2_PORT  PORTADC
-#define AIN2_PIN   PINADC
-#define AIN2_BIT   ADC4
-
-#define PCINT5_DDR   DDRADC
-#define PCINT5_PORT  PORTADC
-#define PCINT5_PIN   PINADC
-#define PCINT5_BIT   ADC4
-
-#define PA5_DDR   DDRADC
-#define PA5_PORT  PORTADC
-#define PA5_PIN   PINADC
-#define PA5_BIT   ADC4
-
-#define ICP0_DDR   DDRADC
-#define ICP0_PORT  PORTADC
-#define ICP0_PIN   PINADC
-#define ICP0_BIT   ADC3
-
-#define PCINT4_DDR   DDRADC
-#define PCINT4_PORT  PORTADC
-#define PCINT4_PIN   PINADC
-#define PCINT4_BIT   ADC3
-
-#define PA4_DDR   DDRADC
-#define PA4_PORT  PORTADC
-#define PA4_PIN   PINADC
-#define PA4_BIT   ADC3
-
-#define PCINT3_DDR   DDRAREF
-#define PCINT3_PORT  PORTAREF
-#define PCINT3_PIN   PINAREF
-#define PCINT3_BIT   AREF
-
-#define PA3_DDR   DDRAREF
-#define PA3_PORT  PORTAREF
-#define PA3_PIN   PINAREF
-#define PA3_BIT   AREF
-
-#define INT1_DDR   DDRADC
-#define INT1_PORT  PORTADC
-#define INT1_PIN   PINADC
-#define INT1_BIT   ADC2
-
-#define USCK_A_DDR   DDRADC
-#define USCK_A_PORT  PORTADC
-#define USCK_A_PIN   PINADC
-#define USCK_A_BIT   ADC2
-
-#define SCL_A_DDR   DDRADC
-#define SCL_A_PORT  PORTADC
-#define SCL_A_PIN   PINADC
-#define SCL_A_BIT   ADC2
-
-#define PCINT2_DDR   DDRADC
-#define PCINT2_PORT  PORTADC
-#define PCINT2_PIN   PINADC
-#define PCINT2_BIT   ADC2
-
-#define PA2_DDR   DDRADC
-#define PA2_PORT  PORTADC
-#define PA2_PIN   PINADC
-#define PA2_BIT   ADC2
-
-#define DO_A_DDR   DDRADC
-#define DO_A_PORT  PORTADC
-#define DO_A_PIN   PINADC
-#define DO_A_BIT   ADC1
-
-#define PCINT1_DDR   DDRADC
-#define PCINT1_PORT  PORTADC
-#define PCINT1_PIN   PINADC
-#define PCINT1_BIT   ADC1
-
-#define PA1_DDR   DDRADC
-#define PA1_PORT  PORTADC
-#define PA1_PIN   PINADC
-#define PA1_BIT   ADC1
-
-#define DI_A_DDR   DDRADC
-#define DI_A_PORT  PORTADC
-#define DI_A_PIN   PINADC
-#define DI_A_BIT   ADC0
-
-#define SDA_A_DDR   DDRADC
-#define SDA_A_PORT  PORTADC
-#define SDA_A_PIN   PINADC
-#define SDA_A_BIT   ADC0
-
-#define PCINT0_DDR   DDRADC
-#define PCINT0_PORT  PORTADC
-#define PCINT0_PIN   PINADC
-#define PCINT0_BIT   ADC0
-
-#define PA0_DDR   DDRADC
-#define PA0_PORT  PORTADC
-#define PA0_PIN   PINADC
-#define PA0_BIT   ADC0
-
-/**@}*/
-#endif /* _AVR_ATtiny861A_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn87.h b/cpukit/score/cpu/avr/avr/iotn87.h
deleted file mode 100644
index 099d81c05f..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn87.h
+++ /dev/null
@@ -1,856 +0,0 @@
-/**
- * @file avr/iotn87.h
- *
- * @brief Definitions for ATtiny87
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn87.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATtiny87_H_
-#define _AVR_ATtiny87_H_ 1
-
-/**
- *  @defgroup Avr_iotn87 ATtiny87 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PORTCR _SFR_IO8(0x12)
-#define PUDA 0
-#define PUDB 2
-#define BBMA 4
-#define BBMB 5
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR1 0
-#define PSR0 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x25)
-#define WGM00 0
-#define WGM01 1
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x26)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x27)
-#define TCNT00 0
-#define TCNT01 1
-#define TCNT02 2
-#define TCNT03 3
-#define TCNT04 4
-#define TCNT05 5
-#define TCNT06 6
-#define TCNT07 7
-
-#define OCR0A _SFR_IO8(0x28)
-#define OCR00 0
-#define OCR01 1
-#define OCR02 2
-#define OCR03 3
-#define OCR04 4
-#define OCR05 5
-#define OCR06 6
-#define OCR07 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACIRS 6
-#define ACD 7
-
-#define DWDR _SFR_IO8(0x31)
-#define DWDR0 0
-#define DWDR1 1
-#define DWDR2 2
-#define DWDR3 3
-#define DWDR4 4
-#define DWDR5 5
-#define DWDR6 6
-#define DWDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define BODS 5
-#define BODSE 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-#define SIGRD 5
-#define RWWSB 6
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define CLKCSR _SFR_MEM8(0x62)
-#define CLKC0 0
-#define CLKC1 1
-#define CLKC2 2
-#define CLKC3 3
-#define CLKRDY 4
-#define CLKCCE 7
-
-#define CLKSELR _SFR_MEM8(0x63)
-#define CSEL0 0
-#define CSEL1 1
-#define CSEL2 2
-#define CSEL3 3
-#define CSUT0 4
-#define CSUT1 5
-#define COUT 6
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSI 1
-#define PRTIM0 2
-#define PRTIM1 3
-#define PRSPI 4
-#define PRLIN 5
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMISCR _SFR_MEM8(0x77)
-#define ISRCEN 0
-#define XREFEN 1
-#define AREFEN 2
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_MEM16(0x78)
-#endif
-#define ADCW _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACIR0 4
-#define ACIR1 5
-#define ACME 6
-#define BIN 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCCR1D _SFR_MEM8(0x83)
-#define OC1AU 0
-#define OC1AV 1
-#define OC1AW 2
-#define OC1AX 3
-#define OC1BU 4
-#define OC1BV 5
-#define OC1BW 6
-#define OC1BX 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR0BUB 0
-#define TCR0AUB 1
-#define OCR0AUB 3
-#define TCN0UB 4
-#define AS0 5
-#define EXCLK 6
-
-#define USICR _SFR_MEM8(0xB8)
-#define USITC 0
-#define USICLK 1
-#define USICS0 2
-#define USICS1 3
-#define USIWM0 4
-#define USIWM1 5
-#define USIOIE 6
-#define USISIE 7
-
-#define USISR _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC 4
-#define USIPF 5
-#define USIOIF 6
-#define USISIF 7
-
-#define USIDR _SFR_MEM8(0xBA)
-#define USIDR0 0
-#define USIDR1 1
-#define USIDR2 2
-#define USIDR3 3
-#define USIDR4 4
-#define USIDR5 5
-#define USIDR6 6
-#define USIDR7 7
-
-#define USIBR _SFR_MEM8(0xBB)
-#define USIBR0 0
-#define USIBR1 1
-#define USIBR2 2
-#define USIBR3 3
-#define USIBR4 4
-#define USIBR5 5
-#define USIBR6 6
-#define USIBR7 7
-
-#define USIPP _SFR_MEM8(0xBC)
-#define USIPOS 0
-
-#define LINCR _SFR_MEM8(0xC8)
-#define LCMD0 0
-#define LCMD1 1
-#define LCMD2 2
-#define LENA 3
-#define LCONF0 4
-#define LCONF1 5
-#define LIN13 6
-#define LSWRES 7
-
-#define LINSIR _SFR_MEM8(0xC9)
-#define LRXOK 0
-#define LTXOK 1
-#define LIDOK 2
-#define LERR 3
-#define LBUSY 4
-#define LIDST0 5
-#define LIDST1 6
-#define LIDST2 7
-
-#define LINENIR _SFR_MEM8(0xCA)
-#define LENRXOK 0
-#define LENTXOK 1
-#define LENIDOK 2
-#define LENERR 3
-
-#define LINERR _SFR_MEM8(0xCB)
-#define LBERR 0
-#define LCERR 1
-#define LPERR 2
-#define LSERR 3
-#define LFERR 4
-#define LOVERR 5
-#define LTOERR 6
-#define LABORT 7
-
-#define LINBTR _SFR_MEM8(0xCC)
-#define LBT0 0
-#define LBT1 1
-#define LBT2 2
-#define LBT3 3
-#define LBT4 4
-#define LBT5 5
-#define LDISR 7
-
-#define LINBRR _SFR_MEM16(0xCD)
-
-#define LINBRRL _SFR_MEM8(0xCD)
-#define LDIV0 0
-#define LDIV1 1
-#define LDIV2 2
-#define LDIV3 3
-#define LDIV4 4
-#define LDIV5 5
-#define LDIV6 6
-#define LDIV7 7
-
-#define LINBRRH _SFR_MEM8(0xCE)
-#define LDIV8 0
-#define LDIV9 1
-#define LDIV10 2
-#define LDIV11 3
-
-#define LINDLR _SFR_MEM8(0xCF)
-#define LRXDL0 0
-#define LRXDL1 1
-#define LRXDL2 2
-#define LRXDL3 3
-#define LTXDL0 4
-#define LTXDL1 5
-#define LTXDL2 6
-#define LTXDL3 7
-
-#define LINIDR _SFR_MEM8(0xD0)
-#define LID0 0
-#define LID1 1
-#define LID2 2
-#define LID3 3
-#define LID4 4
-#define LID5 5
-#define LP0 6
-#define LP1 7
-
-#define LINSEL _SFR_MEM8(0xD1)
-#define LINDX0 0
-#define LINDX1 1
-#define LINDX2 2
-#define LAINC 3
-
-#define LINDAT _SFR_MEM8(0xD2)
-#define LDATA0 0
-#define LDATA1 1
-#define LDATA2 2
-#define LDATA3 3
-#define LDATA4 4
-#define LDATA5 5
-#define LDATA6 6
-#define LDATA7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define USI_OVF_vect_num  19
-#define USI_OVF_vect      _VECTOR(19)  /* USI Overflow */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define PCINT0_vect_num  3
-#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  4
-#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 1 */
-#define WDT_vect_num  5
-#define WDT_vect      _VECTOR(5)  /* Watchdog Time-Out Interrupt */
-#define TIMER1_CAPT_vect_num  6
-#define TIMER1_CAPT_vect      _VECTOR(6)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  7
-#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPB_vect_num  8
-#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer/Counter1 Compare Match 1B */
-#define TIMER1_OVF_vect_num  9
-#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  10
-#define TIMER0_COMPA_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match 0A */
-#define TIMER0_OVF_vect_num  11
-#define TIMER0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
-#define LIN_TC_vect_num  12
-#define LIN_TC_vect      _VECTOR(12)  /* LIN Transfer Complete */
-#define LIN_ERR_vect_num  13
-#define LIN_ERR_vect      _VECTOR(13)  /* LIN Error */
-#define SPI_STC_vect_num  14
-#define SPI_STC_vect      _VECTOR(14)  /* SPI Serial Transfer Complete */
-#define ADC_vect_num  15
-#define ADC_vect      _VECTOR(15)  /* ADC Conversion Complete */
-#define EE_RDY_vect_num  16
-#define EE_RDY_vect      _VECTOR(16)  /* EEPROM Ready */
-#define ANA_COMP_vect_num  17
-#define ANA_COMP_vect      _VECTOR(17)  /* Analog Comparator */
-#define USI_START_vect_num  18
-#define USI_START_vect      _VECTOR(18)  /* USI Start */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (20 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (128)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always ON */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x87
-
-/**@}*/
-#endif /* _AVR_ATtiny87_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn88.h b/cpukit/score/cpu/avr/avr/iotn88.h
deleted file mode 100644
index 829d13f283..0000000000
--- a/cpukit/score/cpu/avr/avr/iotn88.h
+++ /dev/null
@@ -1,772 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATtiny88
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iotn88.h - definitions for ATtiny88 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotn88.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iotn88 ATtiny88 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_IOTN88_H_
-#define _AVR_IOTN88_H_ 1
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINA _SFR_IO8(0x0C)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-
-#define DDRA _SFR_IO8(0x0D)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-
-#define PORTA _SFR_IO8(0x0E)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-
-#define PORTCR _SFR_IO8(0x12)
-#define PUDA 0
-#define PUDB 1
-#define PUDC 2
-#define PUDD 3
-#define BBMA 4
-#define BBMB 5
-#define BBMC 6
-#define BBMD 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define CTC0 3
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-#define RWWSB 6
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK3 _SFR_MEM8(0x6A)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define TWHSR _SFR_MEM8(0xBE)
-#define TWIHS 0
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-
-#define INT0_vect         _VECTOR(1)
-#define INT1_vect         _VECTOR(2)
-#define PCINT0_vect       _VECTOR(3)
-#define PCINT1_vect       _VECTOR(4)
-#define PCINT2_vect       _VECTOR(5)
-#define PCINT3_vect       _VECTOR(6)
-#define WDT_vect          _VECTOR(7)
-#define TIMER1_CAPT_vect  _VECTOR(8)
-#define TIMER1_COMPA_vect _VECTOR(9)
-#define TIMER1_COMPB_vect _VECTOR(10)
-#define TIMER1_OVF_vect   _VECTOR(11)
-#define TIMER0_COMPA_vect _VECTOR(12)
-#define TIMER0_COMPB_vect _VECTOR(13)
-#define TIMER0_OVF_vect   _VECTOR(14)
-#define SPI_STC_vect      _VECTOR(15)
-#define ADC_vect          _VECTOR(16)
-#define EE_READY_vect     _VECTOR(17)
-#define ANALOG_COMP_vect  _VECTOR(18)
-#define TWI_vect          _VECTOR(19)
-
-#define _VECTORS_SIZE 40
-
-
-/* Constants */
-#define RAMEND       0x1FF
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0x3F
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-#define SPM_PAGESIZE 32
-
-
-/* Fuse Information */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4) /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6) /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
-#define FUSE_EESAVE      (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON       (unsigned char)~_BV(4) /* Watchdog Timer Always On */
-#define FUSE_SPIEN       (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN        (unsigned char)~_BV(6) /* debugWIRE Enable */
-#define FUSE_RSTDISBL    (unsigned char)~_BV(7) /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
-
-/* Extended Fuse Byte */
-#define FUSE_SELFPRGEN   ~_BV(0) /* Self Programming Enable */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x11
-
-/** @} */
-
-#endif /* _AVR_IOTN88_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx4.h b/cpukit/score/cpu/avr/avr/iotnx4.h
deleted file mode 100644
index 8bb310ba13..0000000000
--- a/cpukit/score/cpu/avr/avr/iotnx4.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/* Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */
-
-#ifndef _AVR_IOTNX4_H_
-#define _AVR_IOTNX4_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotnx4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-#define PRR     _SFR_IO8 (0x00)
-#define PRTIM1  3
-#define PRTIM0  2
-#define PRUSI   1
-#define PRADC   0
-
-#define DIDR0    _SFR_IO8(0x01)
-#define ADC7D   7
-#define ADC6D   6
-#define ADC5D   5
-#define ADC4D   4
-#define ADC3D   3
-#define ADC2D   2
-#define ADC1D   1 
-#define ADC0D   0
-
-/* Reserved [0x02] */
-
-#define ADCSRB  _SFR_IO8 (0x03)
-#define BIN     7
-#define ACME    6
-#define ADLAR   4
-#define ADTS2   2
-#define ADTS1   1
-#define ADTS0   0
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-#define ADCW    _SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSRA  _SFR_IO8 (0x06)
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-#define ADMUX   _SFR_IO8(0x07)
-#define REFS1   7
-#define REFS0   6
-#define MUX5    5
-#define MUX4    4
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-#define ACSR    _SFR_IO8(0x08)
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-/* Reserved [0x09..0x0A] */
-
-#define TIFR1   _SFR_IO8(0x0B)
-#define ICF1    5
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-#define TIMSK1   _SFR_IO8(0x0C)
-#define ICIE1   5
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-#define USICR   _SFR_IO8(0x0D)
-#define USISIE  7
-#define USIOIE  6
-#define USIWM1  5
-#define USIWM0  4
-#define USICS1  3
-#define USICS0  2
-#define USICLK  1
-#define USITC   0
-
-#define USISR   _SFR_IO8(0x0E)
-#define USISIF  7 
-#define USIOIF  6
-#define USIPF   5
-#define USIDC   4
-#define USICNT3 3
-#define USICNT2 2
-#define USICNT1 1
-#define USICNT0 0
-
-#define USIDR   _SFR_IO8(0x0F)
-
-#define USIBR   _SFR_IO8(0x10)
-
-/* Reserved [0x11] */
-
-#define PCMSK0  _SFR_IO8(0x12)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-#define GPIOR0  _SFR_IO8(0x13)
-
-#define GPIOR1  _SFR_IO8(0x14)
-
-#define GPIOR2  _SFR_IO8(0x15)
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-/* EEPROM Control Register EECR */
-#define EECR	_SFR_IO8(0x1C)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define PCMSK1  _SFR_IO8(0x20)
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9  1
-#define PCINT8  0
-
-#define WDTCSR _SFR_IO8(0x21)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define TCCR1C  _SFR_IO8(0x22)
-#define FOC1A   7
-#define FOC1B   6
-
-#define GTCCR   _SFR_IO8(0x23)
-#define TSM     7
-#define PSR10   0
-
-#define ICR1    _SFR_IO16(0x24)
-#define ICR1L   _SFR_IO8(0x24)
-#define ICR1H   _SFR_IO8(0x25)
-
-#define CLKPR   _SFR_IO8(0x26)
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-#define DWDR    _SFR_IO8(0x27)
-
-#define OCR1B   _SFR_IO16(0x28)
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-#define OCR1A   _SFR_IO16(0x2A)
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
-#define OCRB1   _SFR_IO16(0x28)
-#define OCRB1L  _SFR_IO8(0x28)
-#define OCRB1H  _SFR_IO8(0x29)
-
-#define OCRA1   _SFR_IO16(0x2A)
-#define OCRA1L  _SFR_IO8(0x2A)
-#define OCRA1H  _SFR_IO8(0x2B)
-
-#define TCNT1   _SFR_IO16(0x2C)
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-#define TCCR1B  _SFR_IO8(0x2E)
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define TCCR1A  _SFR_IO8(0x2F)
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define WGM11   1
-#define WGM10   0
-
-#define TCCR0A  _SFR_IO8(0x30)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0B  _SFR_IO8(0x33)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0x35)
-#define BODS    7
-#define PUD     6
-#define SE      5
-#define SM1     4
-#define SM0     3
-#define BODSE   2
-#define ISC01   1
-#define ISC00   0
-
-#define OCR0A   _SFR_IO8(0x36)
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define RSIG    5
-#define CTPB    4
-#define RFLB    3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-#define TIFR0   _SFR_IO8(0x38)
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIMSK0  _SFR_IO8(0x39)
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define GIFR    _SFR_IO8(0x3A)
-#define INTF0   6
-#define PCIF1   5
-#define PCIF0   4
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define INT0    6
-#define PCIE1   5
-#define PCIE0   4
-
-#define OCR0B   _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* Interrupt vector 0 is the reset vector. */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define EXT_INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Watchdog Time-out */
-#define WDT_vect			_VECTOR(4)
-#define WATCHDOG_vect			_VECTOR(4)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define TIM1_CAPT_vect			_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIM1_COMPA_vect			_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIM1_COMPB_vect			_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIM1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Compare Match A */
-#define TIM0_COMPA_vect			_VECTOR(9)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(9)
-
-/* Timer/Counter0 Compare Match B */
-#define TIM0_COMPB_vect			_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIM0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(13)
-#define SIG_ADC				_VECTOR(13)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(14)
-#define SIG_EEPROM_READY		_VECTOR(14)
-
-/* USI START */
-#define USI_START_vect			_VECTOR(15)
-#define USI_STR_vect			_VECTOR(15)
-#define SIG_USI_START			_VECTOR(15)
-
-/* USI Overflow */
-#define USI_OVF_vect			_VECTOR(16)
-#define SIG_USI_OVERFLOW		_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/** @} */
-
-#endif /* _AVR_IOTNX4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx5.h b/cpukit/score/cpu/avr/avr/iotnx5.h
deleted file mode 100644
index 34edf06e8b..0000000000
--- a/cpukit/score/cpu/avr/avr/iotnx5.h
+++ /dev/null
@@ -1,428 +0,0 @@
-/**
- * @file avr/iotnx5.h
- *
- * @brief Definitions for ATtiny25, ATtiny45 and ATtiny85
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOTNX5_H_
-#define _AVR_IOTNX5_H_ 1
-
-/**
- *  @defgroup Avr_iotnx5 ATtiny25, ATtiny45, ATtiny85 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotnx5.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Reserved [0x00..0x02] */
-
-#define ADCSRB  _SFR_IO8 (0x03)
-#define BIN     7
-#define ACME    6
-#define IPR     5
-#define ADTS2   2
-#define ADTS1   1
-#define ADTS0   0
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-#define ADCW    _SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSRA  _SFR_IO8 (0x06)
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-#define ADMUX   _SFR_IO8(0x07)
-#define REFS1   7
-#define REFS0   6
-#define ADLAR   5
-#define REFS2   4
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-#define ACSR    _SFR_IO8(0x08)
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIS1   1
-#define ACIS0   0
-
-/* Reserved [0x09..0x0C] */
-
-#define USICR   _SFR_IO8(0x0D)
-#define USISIE  7
-#define USIOIE  6
-#define USIWM1  5
-#define USIWM0  4
-#define USICS1  3
-#define USICS0  2
-#define USICLK  1
-#define USITC   0
-
-#define USISR   _SFR_IO8(0x0E)
-#define USISIF  7
-#define USIOIF  6
-#define USIPF   5
-#define USIDC   4
-#define USICNT3 3
-#define USICNT2 2
-#define USICNT1 1
-#define USICNT0 0
-
-#define USIDR   _SFR_IO8(0x0F)
-#define USIBR   _SFR_IO8(0x10)
-
-#define GPIOR0  _SFR_IO8(0x11)
-#define GPIOR1  _SFR_IO8(0x12)
-#define GPIOR2  _SFR_IO8(0x13)
-
-#define DIDR0    _SFR_IO8(0x14)
-#define ADC0D   5
-#define ADC2D   4
-#define ADC3D   3
-#define ADC1D   2
-#define AIN1D   1
-#define AIN0D   0
-
-#define PCMSK   _SFR_IO8(0x15)
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Reserved [0x19..0x1B] */
-
-/* EEPROM Control Register EECR */
-#define EECR	_SFR_IO8(0x1C)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define PRR     _SFR_IO8(0x20)
-#define PRTIM1  3
-#define PRTIM0  2
-#define PRUSI   1
-#define PRADC   0
-
-#define WDTCR   _SFR_IO8(0x21)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define DWDR    _SFR_IO8(0x22)
-
-#define DTPS1   _SFR_IO8(0x23)
-#define DTPS11   1
-#define DTPS10   0
-
-#define DT1B    _SFR_IO8(0x24)
-#define DT1BH3  7
-#define DT1BH2  6
-#define DT1BH1  5
-#define DT1BH0  4
-#define DT1BL3  3
-#define DT1BL2  2
-#define DT1BL1  1
-#define DT1BL0  0
-
-#define DT1A    _SFR_IO8(0x25)
-#define DT1AH3  7
-#define DT1AH2  6
-#define DT1AH1  5
-#define DT1AH0  4
-#define DT1AL3  3
-#define DT1AL2  2
-#define DT1AL1  1
-#define DT1AL0  0
-
-#define CLKPR   _SFR_IO8(0x26)
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-#define PLLCSR  _SFR_IO8(0x27)
-#define LSM     7
-#define PCKE    2
-#define PLLE    1
-#define PLOCK   0
-
-#define OCR0B   _SFR_IO8(0x28)
-
-#define OCR0A   _SFR_IO8(0x29)
-
-#define TCCR0A  _SFR_IO8(0x2A)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define OCR1B   _SFR_IO8(0x2B)
-
-#define GTCCR   _SFR_IO8(0x2C)
-#define TSM     7
-#define PWM1B   6
-#define COM1B1  5
-#define COM1B0  4
-#define FOC1B   3
-#define FOC1A   2
-#define PSR1    1
-#define PSR0    0
-
-#define OCR1C   _SFR_IO8(0x2D)
-
-#define OCR1A   _SFR_IO8(0x2E)
-
-#define TCNT1   _SFR_IO8(0x2F)
-
-#define TCCR1   _SFR_IO8(0x30)
-#define CTC1    7
-#define PWM1A   6
-#define COM1A1  5
-#define COM1A0  4
-#define CS13    3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0B  _SFR_IO8(0x33)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0x35)
-#define BODS    7
-#define PUD     6
-#define SE      5
-#define SM1     4
-#define SM0     3
-#define BODSE   2
-#define ISC01   1
-#define ISC00   0
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define RSIG    5
-#define CTPB    4
-#define RFLB    3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-#define TIFR    _SFR_IO8(0x38)
-#define OCF1A   6
-#define OCF1B   5
-#define OCF0A   4
-#define OCF0B   3
-#define TOV1    2
-#define TOV0    1
-
-#define TIMSK   _SFR_IO8(0x39)
-#define OCIE1A  6
-#define OCIE1B  5
-#define OCIE0A  4
-#define OCIE0B  3
-#define TOIE1   2
-#define TOIE0   1
-
-#define GIFR    _SFR_IO8(0x3A)
-#define INTF0   6
-#define PCIF    5
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define INT0    6
-#define PCIE    5
-
-/* Reserved [0x3C] */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-///---
-
-/* Interrupt vectors */
-/* Interrupt vector 0 is the reset vector. */
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIM1_COMPA_vect			_VECTOR(3)
-#define TIMER1_COMPA_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(3)
-
-/* Timer/Counter1 Overflow */
-#define TIM1_OVF_vect			_VECTOR(4)
-#define TIMER1_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW1			_VECTOR(4)
-
-/* Timer/Counter0 Overflow */
-#define TIM0_OVF_vect			_VECTOR(5)
-#define TIMER0_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW0			_VECTOR(5)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(6)
-#define SIG_EEPROM_READY		_VECTOR(6)
-
-/* Analog comparator */
-#define ANA_COMP_vect			_VECTOR(7)
-#define SIG_COMPARATOR			_VECTOR(7)
-
-/* ADC Conversion ready */
-#define ADC_vect			_VECTOR(8)
-#define SIG_ADC				_VECTOR(8)
-
-/* Timer/Counter1 Compare Match B */
-#define TIM1_COMPB_vect			_VECTOR(9)
-#define TIMER1_COMPB_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(9)
-
-/* Timer/Counter0 Compare Match A */
-#define TIM0_COMPA_vect			_VECTOR(10)
-#define TIMER0_COMPA_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(10)
-
-/* Timer/Counter0 Compare Match B */
-#define TIM0_COMPB_vect			_VECTOR(11)
-#define TIMER0_COMPB_vect		_VECTOR(11)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(11)
-
-/* Watchdog Time-out */
-#define WDT_vect			_VECTOR(12)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
-
-/* USI START */
-#define USI_START_vect			_VECTOR(13)
-#define SIG_USI_START			_VECTOR(13)
-
-/* USI Overflow */
-#define USI_OVF_vect			_VECTOR(14)
-#define SIG_USI_OVERFLOW		_VECTOR(14)
-
-#define _VECTORS_SIZE 30
-
-/**@}*/
-#endif /* _AVR_IOTNX5_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx61.h b/cpukit/score/cpu/avr/avr/iotnx61.h
deleted file mode 100644
index 58cba5c493..0000000000
--- a/cpukit/score/cpu/avr/avr/iotnx61.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/**
- * @file avr/iotnx61.h
- *
- * @brief Definitions for ATtiny261, ATtiny461 and ATtiny861
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2006, 2007 Anatoly Sokolov
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iotnx61.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef _AVR_IOTNx61_H_
-#define _AVR_IOTNx61_H_ 1
-
-/**
- * @defgroup AvrDef_iotnx61 ATtiny261, ATtiny461, ATtiny861 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define TCCR1E  _SFR_IO8(0x00)
-#define OC1OE0  0
-#define OC1OE1  1
-#define OC1OE2  2
-#define OC1OE3  3
-#define OC1OE4  4
-#define OC1OE5  5
-
-#define DIDR0   _SFR_IO8(0x01)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define AREFD   3
-#define ADC3D   4
-#define ADC4D   5
-#define ADC5D   6
-#define ADC6D   7
-
-#define DIDR1   _SFR_IO8(0x02)
-#define ADC7D   4
-#define ADC8D   5
-#define ADC9D   6
-#define ADC10D  7
-
-#define ADCSRB  _SFR_IO8(0x03)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define MUX5    3
-#define REFS2   4
-#define IRP     5
-#define GSEL    6
-#define BIN     7
-
-#define ADCW    _SFR_IO16(0x04)
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_IO16(0x04)
-#endif
-
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSRA  _SFR_IO8(0x06)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADMUX   _SFR_IO8(0x07)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-#define ACSRA   _SFR_IO8(0x08)
-#define ACIS0   0
-#define ACIS1   1
-#define ACME    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define ACSRB   _SFR_IO8(0x09)
-#define ACM0    0
-#define ACM1    1
-#define ACM2    2
-#define HLEV    6
-#define HSEL    7
-
-#define GPIOR0  _SFR_IO8(0x0A)
-
-#define GPIOR1  _SFR_IO8(0x0B)
-
-#define GPIOR2  _SFR_IO8(0x0C)
-
-#define USICR   _SFR_IO8(0x0D)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_IO8(0x0E)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_IO8(0x0F)
-
-#define USIBR   _SFR_IO8(0x10)
-
-#define USIPP   _SFR_IO8(0x11)
-#define USIPOS  0
-
-#define OCR0B   _SFR_IO8(0x12)
-
-#define OCR0A   _SFR_IO8(0x13)
-
-#define TCNT0H  _SFR_IO8(0x14)
-
-#define TCCR0A  _SFR_IO8(0x15)
-#define WGM00   0
-#define ACIC0   3
-#define ICES0   4
-#define ICNC0   5
-#define ICEN0   6
-#define TCW0    7
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA0   0
-#define PINA1   1
-#define PINA2   2
-#define PINA3   3
-#define PINA4   4
-#define PINA5   5
-#define PINA6   6
-#define PINA7   7
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PA0     0
-#define PA1     1
-#define PA2     2
-#define PA3     3
-#define PA4     4
-#define PA5     5
-#define PA6     6
-#define PA7     7
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-#define EERE    0
-#define EEPE    1
-#define EEMPE   2
-#define EERIE   3
-#define EEPM0   4
-#define EEPM1   5
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define DWDR    _SFR_IO8(0x20)
-
-#define WDTCR   _SFR_IO8(0x21)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-#define WDP3    5
-#define WDIE    6
-#define WDIF    7
-
-#define PCMSK1  _SFR_IO8(0x22)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK0  _SFR_IO8(0x23)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define DT1     _SFR_IO8(0x24)
-#define DT1L0   0
-#define DT1L1   1
-#define DT1L2   2
-#define DT1L3   3
-#define DT1H0   4
-#define DT1H1   5
-#define DT1H2   6
-#define DT1H3   7
-
-#define TC1H    _SFR_IO8(0x25)
-#define TC18    0
-#define TC19    1
-
-#define TCCR1D  _SFR_IO8(0x26)
-#define WGM10   0
-#define WGM11   1
-#define FPF1    2
-#define FPAC1   3
-#define FPES1   4
-#define FPNC1   5
-#define FPEN1   6
-#define FPIE1   7
-
-#define TCCR1C  _SFR_IO8(0x27)
-#define PWM1D   0
-#define FOC1D   1
-#define COM1D0  2
-#define COM1D1  3
-#define COM1B0S 4
-#define COM1B1S 5
-#define COM1A0S 6
-#define COM1A1S 7
-
-#define CLKPR   _SFR_IO8(0x28)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0
-#define PLLE    1
-#define PCKE    2
-#define LSM     7
-
-#define OCR1D   _SFR_IO8(0x2A)
-
-#define OCR1C   _SFR_IO8(0x2B)
-
-#define OCR1B   _SFR_IO8(0x2C)
-
-#define OCR1A   _SFR_IO8(0x2D)
-
-#define TCNT1   _SFR_IO8(0x2E)
-
-#define TCCR1B  _SFR_IO8(0x2F)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define CS13    3
-#define DTPS10  4
-#define DTPS11  5
-#define PSR1    6
-#define PWM1X   7
-
-#define TCCR1A  _SFR_IO8(0x30)
-#define PWM1B   0
-#define PWM1A   1
-#define FOC1B   2
-#define FOC1A   3
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define TCNT0L  _SFR_IO8(0x32)
-
-#define TCCR0B  _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define PSR0    3
-#define TSM     4
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define SM0     3
-#define SM1     4
-#define SE      5
-#define PUD     6
-
-#define PRR     _SFR_IO8(0x36)
-#define PRADC   0
-#define PRUSI   1
-#define PRTIM0  2
-#define PRTIM1  3
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT 2
-#define RFLB 3
-#define CTPB 4
-
-#define TIFR    _SFR_IO8(0x38)
-#define ICF0    0
-#define TOV0    1
-#define TOV1    2
-#define OCF0B   3
-#define OCF0A   4
-#define OCF1B   5
-#define OCF1A   6
-#define OCF1D   7
-
-#define TIMSK   _SFR_IO8(0x39)
-#define TICIE0  0
-#define TOIE0   1
-#define TOIE1   2
-#define OCIE0B  3
-#define OCIE0A  4
-#define OCIE1B  5
-#define OCIE1A  6
-#define OCIE1D  7
-
-#define GIFR    _SFR_IO8(0x3A)
-#define PCIF    5
-#define INTF0   6
-#define INTF1   7
-
-#define GIMSK   _SFR_IO8(0x3B)
-#define PCIE0   4
-#define PCIE1   5
-#define INT0    6
-#define INT1    7
-
-/* Reserved [0x3C] */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-
-/* Interrupt vectors */
-/* Interrupt vector 0 is the reset vector. */
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt */
-#define PCINT_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE			_VECTOR(2)
-
-/* Timer/Counter1 Compare Match 1A */
-#define TIMER1_COMPA_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match 1B */
-#define TIMER1_COMPB_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* USI Start */
-#define USI_START_vect			_VECTOR(7)
-#define SIG_USI_START			_VECTOR(7)
-
-/* USI Overflow */
-#define USI_OVF_vect			_VECTOR(8)
-#define SIG_USI_OVERFLOW		_VECTOR(8)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(9)
-#define SIG_EEPROM_READY		_VECTOR(9)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(10)
-#define SIG_ANA_COMP			_VECTOR(10)
-#define SIG_COMPARATOR			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-/* Watchdog Time-Out */
-#define WDT_vect			_VECTOR(12)
-#define SIG_WDT				_VECTOR(12)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(13)
-#define SIG_INTERRUPT1			_VECTOR(13)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
-
-/* ADC Conversion Complete */
-#define TIMER0_CAPT_vect		_VECTOR(16)
-#define SIG_INPUT_CAPTURE0		_VECTOR(16)
-
-/* Timer/Counter1 Compare Match D */
-#define TIMER1_COMPD_vect		_VECTOR(17)
-#define SIG_OUTPUT_COMPARE0D		_VECTOR(17)
-
-/* Timer/Counter1 Fault Protection */
-#define FAULT_PROTECTION_vect		_VECTOR(18)
-
-#define _VECTORS_SIZE 38
-
-/** @} */
-#endif  /* _AVR_IOTNx61_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb1286.h b/cpukit/score/cpu/avr/avr/iousb1286.h
deleted file mode 100644
index 5f9411daff..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb1286.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * @file avr/iousb1286.h
- *
- * @brief Definitions for AT90USB1286
- */
-
-/*
- *  Copyright (c) 2006 Anatoly Sokolov
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_AT90USB1286_H_
-#define _AVR_AT90USB1286_H_ 1
-
-/**
- *  @defgroup Avr_iousb1286 AT90USB1286 Definitons
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iousbxx6_7.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x20FF
-#define XRAMEND      0xFFFF
-#define E2END        0xFFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x82
-
-/**@}*/
-#endif /* _AVR_AT90USB1286_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb1287.h b/cpukit/score/cpu/avr/avr/iousb1287.h
deleted file mode 100644
index f75894bdbc..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb1287.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file avr/iousb1287.h
- *
- * @brief Definitions for AT90USB1287
- */
-
-/*
- * Copyright (c) 2006 Anatoly Sokolov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_AT90USB1287_H_
-#define _AVR_AT90USB1287_H_ 1
-
-/**
- *  @defgroup Avr_iousb1287 AT90USB1287 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iousbxx6_7.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x20FF
-#define XRAMEND      0xFFFF
-#define E2END        0xFFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x82
-
-
-/**@}*/
-#endif /* _AVR_AT90USB1287_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb162.h b/cpukit/score/cpu/avr/avr/iousb162.h
deleted file mode 100644
index 89709a7279..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb162.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright (c) 2007 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb162.h - definitions for AT90USB162 */
-
-#ifndef _AVR_AT90USB162_H_
-#define _AVR_AT90USB162_H_ 1
-
-#include <avr/iousbxx2.h>
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define SPM_PAGESIZE 128
-#define RAMEND       0x2FF
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x3FFF
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (CKSEL0 & SUT1 & CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_RSTDSBL     (unsigned char)~_BV(6)
-#define FUSE_DWEN        (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1 & SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (BODLEVEL0 & BODLEVEL1 & HWBE)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x82
-/** @} */
-
-#endif /* _AVR_AT90USB162_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb646.h b/cpukit/score/cpu/avr/avr/iousb646.h
deleted file mode 100644
index 035cbcd2bc..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb646.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file avr/iousb646.h
- *
- * @brief Definitions for AT90USB646
- */
-
-/*
- * Copyright (c) 2006 Anatoly Sokolov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_AT90USB646_H_
-#define _AVR_AT90USB646_H_ 1
-
-/**
- *  @defgroup Avr_iousb646 AT90USB646 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iousbxx6_7.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      0xFFFF
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (CKSEL0 & CKSEL2 & CKSEL3 & SUT0 & CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1 & SPIEN & JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (BODLEVEL2 & HWBE)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x82
-
-
-/**@}*/
-#endif /* _AVR_AT90USB646_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb647.h b/cpukit/score/cpu/avr/avr/iousb647.h
deleted file mode 100644
index 2e1288accb..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb647.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90USB647
- */
-
-/* Copyright (c) 2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb647.h - definitions for AT90USB647 */
-
-#ifndef _AVR_AT90USB647_H_
-#define _AVR_AT90USB647_H_ 1
-
-#include <avr/iousbxx6_7.h>
-
-/**
- * @defgroup AvrDef_iousb647 AT90USB647 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF
-#define XRAMEND      0xFFFF
-#define E2END        0x7FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (CKSEL0 & CKSEL2 & CKSEL3 & SUT0 & CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1 & SPIEN & JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (BODLEVEL2 & HWBE)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x82
-
-/** @} */
-
-#endif /* _AVR_AT90USB647_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb82.h b/cpukit/score/cpu/avr/avr/iousb82.h
deleted file mode 100644
index 2d66bd5d70..0000000000
--- a/cpukit/score/cpu/avr/avr/iousb82.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/**
- * @file
- *
- * @brief Ddefinitions for AT90USB82
- */
-
-/* Copyright (c) 2007 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb82.h - definitions for AT90USB82 */
-
-#ifndef _AVR_AT90USB82_H_
-#define _AVR_AT90USB82_H_ 1
-
-#include <avr/iousbxx2.h>
-
-/**
- * @defgroup AvrDef_iousb82 AT90USB82 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND       0x2FF
-#define XRAMEND      RAMEND
-#define E2END        0x1FF
-#define E2PAGESIZE   4
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (CKSEL0 & SUT1 & CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_RSTDSBL     (unsigned char)~_BV(6)
-#define FUSE_DWEN        (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1 & SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define FUSE_HWBE        (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (BODLEVEL0 & BODLEVEL1 & HWBE)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-/** @} */
-
-#endif /* _AVR_AT90USB82_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousbxx2.h b/cpukit/score/cpu/avr/avr/iousbxx2.h
deleted file mode 100644
index 3dcbc76262..0000000000
--- a/cpukit/score/cpu/avr/avr/iousbxx2.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/**
- * @file iousbxx2.h
- *
- * @brief Definitions for AT90USB82 and AT90USB162
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2007 Anatoly Sokolov
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOUSBXX2_H_
-#define _AVR_IOUSBXX2_H_ 1
-
-/**
- * @defgroup AvrDef_iousbxx2 AT90USB82, AT90USB162 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iousbxx2.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-/* Reserved [0x00..0x02] */
-
-#define PINB    _SFR_IO8(0X03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* Reserved [0xC..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIFR1   _SFR_IO8(0x16)
-#define ICF1    5
-#define OCF1C   3
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-/* Reserved [0x17..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF1   1
-#define PCIF0   0
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF7   7
-#define INTF6   6
-#define INTF5   5
-#define INTF4   4
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT7    7
-#define INT6    6
-#define INT5    5
-#define INT4    4
-#define INT3    3
-#define INT2    2
-#define INT1    1
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR    _SFR_IO8(0x20)
-
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define TSM     7
-#define PSRASY  1
-#define PSRSYNC 0
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0X28)
-
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLLP2   4
-#define PLLP1   3
-#define PLLP0   2
-#define PLLE    1
-#define PLOCK   0
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPIF    7
-#define WCOL    6
-#define SPI2X   0
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-#define DWDR    _SFR_IO8(0x31)
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define USBRF   5
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0x35)
-#define IVSEL   1
-#define IVCE    0
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMIE   7
-#define RWWSB   6
-#define SIGRD   5
-#define RWWSRE  4
-#define BLBSET  3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-#define WDTCKD  _SFR_MEM8(0x62)
-#define WDEWIF  3
-#define WDEWIE  2
-#define WCLKD1  1
-#define WCLKD0  0
-
-#define REGCR   _SFR_MEM8(0x63)
-#define REGDIS  0
-
-#define PRR0    _SFR_MEM8(0x64)
-#define PRTIM0  5
-#define PRTIM1  3
-#define PRSPI   2
-
-#define PRR1    _SFR_MEM8(0x65)
-#define PRUSB   7
-#define PRUSART1 0
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE1   1
-#define PCIE0   0
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-#define EICRB   _SFR_MEM8(0x6A)
-#define ISC71   7
-#define ISC70   6
-#define ISC61   5
-#define ISC60   4
-#define ISC51   3
-#define ISC50   2
-#define ISC41   1
-#define ISC40   0
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9  1
-#define PCINT8  0
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define ICIE1   5
-#define OCIE1C  3
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-/* Reserved [0x70..0x7F] */
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define COM1C1  3
-#define COM1C0  2
-#define WGM11   1
-#define WGM10   0
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1A   7
-#define FOC1B   6
-#define FOC1C   5
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Combine OCR1CL and OCR1CH */
-#define OCR1C   _SFR_MEM16(0x8C)
-
-#define OCR1CL  _SFR_MEM8(0x8C)
-#define OCR1CH  _SFR_MEM8(0x8D)
-
-/* Reserved [0x8E..0xC7] */
-
-#define UCSR1A  _SFR_MEM8(0xC8)
-#define RXC1    7
-#define TXC1    6
-#define UDRE1   5
-#define FE1     4
-#define DOR1    3
-#define UPE1    2
-#define U2X1    1
-#define MPCM1   0
-
-#define UCSR1B  _SFR_MEM8(0XC9)
-#define RXCIE1  7
-#define TXCIE1  6
-#define UDRIE1  5
-#define RXEN1   4
-#define TXEN1   3
-#define UCSZ12  2
-#define RXB81   1
-#define TXB81   0
-
-#define UCSR1C  _SFR_MEM8(0xCA)
-#define UMSEL11 7
-#define UMSEL10 6
-#define UPM11   5
-#define UPM10   4
-#define USBS1   3
-#define UCSZ11  2
-#define UCSZ10  1
-#define UCPOL1  0
-
-#define UCSR1D  _SFR_MEM8(0xCB)
-#define CTSEN   1
-#define RTSEN   0
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0xCC)
-
-#define UBRR1L  _SFR_MEM8(0xCC)
-#define UBRR1H  _SFR_MEM8(0xCD)
-
-#define UDR1    _SFR_MEM8(0XCE)
-
-/* Reserved [0xCF] */
-
-#define CKSEL0  _SFR_MEM8(0XD0)
-#define RCSUT1  7
-#define RCSUT0  6
-#define EXSUT1  5
-#define EXSUT0  4
-#define RCE     3
-#define EXTE    2
-#define CLKS    0
-
-#define CKSEL1  _SFR_MEM8(0XD1)
-#define RCCKSEL3 7
-#define RCCKSEL2 6
-#define RCCKSEL1 5
-#define RCCKSEL0 4
-#define EXCKSEL3 3
-#define EXCKSEL2 2
-#define EXCKSEL1 1
-#define EXCKSEL0 0
-
-#define CKSTA   _SFR_MEM8(0XD2)
-#define RCON    1
-#define EXTON   0
-
-/* Reserved [0xD3..0xD7] */
-
-#define USBCON  _SFR_MEM8(0XD8)
-#define USBE    7
-#define FRZCLK  5
-
-/* Reserved [0xD9..0xDA] */
-
-/* Combine UDPADDL and UDPADDH */
-#define UDPADD  _SFR_MEM16(0xDB)
-
-#define UDPADDL _SFR_MEM8(0xDB)
-#define UDPADDH _SFR_MEM8(0xDC)
-#define DPACC   7
-
-/* Reserved [0xDD..0xDF] */
-
-#define UDCON   _SFR_MEM8(0XE0)
-#define RSTCPU  2
-#define RMWKUP  1
-#define DETACH  0
-
-#define UDINT   _SFR_MEM8(0XE1)
-#define UPRSMI  6
-#define EORSMI  5
-#define WAKEUPI 4
-#define EORSTI  3
-#define SOFI    2
-#define SUSPI   0
-
-#define UDIEN   _SFR_MEM8(0XE2)
-#define UPRSME  6
-#define EORSME  5
-#define WAKEUPE 4
-#define EORSTE  3
-#define SOFE    2
-#define SUSPE   0
-
-#define UDADDR  _SFR_MEM8(0XE3)
-#define ADDEN   7
-
-/* Combine UDFNUML and UDFNUMH */
-#define UDFNUM  _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define UDFNUMH _SFR_MEM8(0xE5)
-
-#define UDMFN   _SFR_MEM8(0XE6)
-#define FNCERR  4
-
-/* Reserved [0xE7] */
-
-#define UEINTX  _SFR_MEM8(0XE8)
-#define FIFOCON 7
-#define NAKINI  6
-#define RWAL    5
-#define NAKOUTI 4
-#define RXSTPI  3
-#define RXOUTI  2
-#define STALLEDI 1
-#define TXINI   0
-
-#define UENUM   _SFR_MEM8(0XE9)
-#define EPNUM2  2
-#define EPNUM1  1
-#define EPNUM0  0
-
-#define UERST   _SFR_MEM8(0XEA)
-#define EPRST4  4
-#define EPRST3  3
-#define EPRST2  2
-#define EPRST1  1
-#define EPRST0  0
-
-#define UECONX  _SFR_MEM8(0XEB)
-#define STALLRQ 5
-#define STALLRQC 4
-#define RSTDT   3
-#define EPEN    0
-
-#define UECFG0X _SFR_MEM8(0XEC)
-#define EPTYPE1 7
-#define EPTYPE0 6
-#define EPDIR   0
-
-#define UECFG1X  _SFR_MEM8(0XED)
-#define EPSIZE2 6
-#define EPSIZE1 5
-#define EPSIZE0 4
-#define EPBK1   3
-#define EPBK0   2
-#define ALLOC   1
-
-#define UESTA0X _SFR_MEM8(0XEE)
-#define CFGOK   7
-#define OVERFI  6
-#define UNDERFI 5
-#define DTSEQ1  3
-#define DTSEQ0  2
-#define NBUSYBK1 1
-#define NBUSYBK0 0
-
-#define UESTA1X _SFR_MEM8(0XEF)
-#define CTRLDIR 2
-#define CURRBK1 1
-#define CURRBK0 0
-
-#define UEIENX  _SFR_MEM8(0XF0)
-#define FLERRE  7
-#define NAKINE  6
-#define NAKOUTE 4
-#define RXSTPE  3
-#define RXOUTE  2
-#define STALLEDE 1
-#define TXINE   0
-
-#define UEDATX  _SFR_MEM8(0XF1)
-
-#define UEBCLX  _SFR_MEM8(0xF2)
-
-/* Reserved [0xF3] */
-
-#define UEINT   _SFR_MEM8(0XF4)
-#define EPINT4  4
-#define EPINT3  3
-#define EPINT2  2
-#define EPINT1  1
-#define EPINT0  0
-
-/* Reserved [0xF5..0xF9] */
-
-#define PS2CON  _SFR_MEM8(0XFA)
-#define PS2EN   0
-
-#define UPOE    _SFR_MEM8(0XFB)
-#define UPWE1   7
-#define UPWE0   6
-#define UPDRV1  5
-#define UPDRV0  4
-#define SCKI    3
-#define DATAI   2
-#define DPI     1
-#define DMI     0
-
-/* Reserved [0xFC..0xFF] */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(9)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(10)
-
-/* USB General Interrupt Request */
-#define USB_GEN_vect			_VECTOR(11)
-
-/* USB Endpoint/Pipe Interrupt Communication Request */
-#define USB_COM_vect			_VECTOR(12)
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect			_VECTOR(13)
-
-/* Timer/Counter2 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(14)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPA_vect		_VECTOR(15)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(16)
-
-/* Timer/Counter2 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(17)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(18)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(19)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(20)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(21)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(22)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(23)
-
-/* USART1 Data register Empty */
-#define USART1_UDRE_vect		_VECTOR(24)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(25)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(26)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(27)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(28)
-
-#define _VECTORS_SIZE 116
-
-/** @} */
-#endif  /* _AVR_IOUSBXX2_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousbxx6_7.h b/cpukit/score/cpu/avr/avr/iousbxx6_7.h
deleted file mode 100644
index c923c22c82..0000000000
--- a/cpukit/score/cpu/avr/avr/iousbxx6_7.h
+++ /dev/null
@@ -1,1296 +0,0 @@
-/**
- * @file iousbxx6_7.h
- *
- * @brief Definitions for AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2006, Anatoly Sokolov
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOUSBXX6_7_H_
-#define _AVR_IOUSBXX6_7_H_ 1
-
-/**
- *  @defgroup Avr_iomxx0_1 AT90USB-646/647/1286/1287 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
-#  define __AT90USBxx6__ 1
-#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__)
-#  define __AT90USBxx7__ 1
-#endif
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0X00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0X01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0X02)
-#define PA7  7
-#define PA6  6
-#define PA5  5
-#define PA4  4
-#define PA3  3
-#define PA2  2
-#define PA1  1
-#define PA0  0
-
-#define PINB    _SFR_IO8(0X03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7  7
-#define PB6  6
-#define PB5  5
-#define PB4  4
-#define PB3  3
-#define PB2  2
-#define PB1  1
-#define PB0  0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7  7
-#define PC6  6
-#define PC5  5
-#define PC4  4
-#define PC3  3
-#define PC2  2
-#define PC1  1
-#define PC0  0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7  7
-#define PD6  6
-#define PD5  5
-#define PD4  4
-#define PD3  3
-#define PD2  2
-#define PD1  1
-#define PD0  0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7  7
-#define PE6  6
-#define PE5  5
-#define PE4  4
-#define PE3  3
-#define PE2  2
-#define PE1  1
-#define PE0  0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7  7
-#define PF6  6
-#define PF5  5
-#define PF4  4
-#define PF3  3
-#define PF2  2
-#define PF1  1
-#define PF0  0
-
-/* Reserved [0x12..0x14] */
-
-#define TIFR0   _SFR_IO8(0x15)
-#define OCF0B   2
-#define OCF0A   1
-#define TOV0    0
-
-#define TIFR1   _SFR_IO8(0x16)
-#define ICF1    5
-#define OCF1C   3
-#define OCF1B   2
-#define OCF1A   1
-#define TOV1    0
-
-#define TIFR2   _SFR_IO8(0x17)
-#define OCF2B   2
-#define OCF2A   1
-#define TOV2    0
-
-#define TIFR3   _SFR_IO8(0x18)
-#define ICF3    5
-#define OCF3C   3
-#define OCF3B   2
-#define OCF3A   1
-#define TOV3    0
-
-/* Reserved [0x19..0x1A] */
-
-#define PCIFR   _SFR_IO8(0x1B)
-#define PCIF0   0
-
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF7   7
-#define INTF6   6
-#define INTF5   5
-#define INTF4   4
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT7    7
-#define INT6    6
-#define INT5    5
-#define INT4    4
-#define INT3    3
-#define INT2    2
-#define INT1    1
-#define INT0    0
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EEPM1   5
-#define EEPM0   4
-#define EERIE   3
-#define EEMPE   2
-#define EEPE    1
-#define EERE    0
-
-#define EEDR    _SFR_IO8(0x20)
-
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define TSM     7
-#define PSRASY  1
-#define PSRSYNC 0
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define COM0A1  7
-#define COM0A0  6
-#define COM0B1  5
-#define COM0B0  4
-#define WGM01   1
-#define WGM00   0
-
-#define TCCR0B  _SFR_IO8(0x25)
-#define FOC0A   7
-#define FOC0B   6
-#define WGM02   3
-#define CS02    2
-#define CS01    1
-#define CS00    0
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0x27)
-
-#define OCR0B   _SFR_IO8(0X28)
-
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLLP2   4
-#define PLLP1   3
-#define PLLP0   2
-#define PLLE    1
-#define PLOCK   0
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPIE    7
-#define SPE     6
-#define DORD    5
-#define MSTR    4
-#define CPOL    3
-#define CPHA    2
-#define SPR1    1
-#define SPR0    0
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPIF    7
-#define WCOL    6
-#define SPI2X   0
-
-#define SPDR    _SFR_IO8(0x2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACD     7
-#define ACBG    6
-#define ACO     5
-#define ACI     4
-#define ACIE    3
-#define ACIC    2
-#define ACIS1   1
-#define ACIS0   0
-
-#define MONDR   _SFR_IO8(0x31)
-#define OCDR    _SFR_IO8(0x31)
-#define IDRD    7
-#define OCDR7   7
-#define OCDR6   6
-#define OCDR5   5
-#define OCDR4   4
-#define OCDR3   3
-#define OCDR2   2
-#define OCDR1   1
-#define OCDR0   0
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SM2     3
-#define SM1     2
-#define SM0     1
-#define SE      0
-
-#define MCUSR   _SFR_IO8(0x34)
-#define JTRF    4
-#define WDRF    3
-#define BORF    2
-#define EXTRF   1
-#define PORF    0
-
-#define MCUCR   _SFR_IO8(0x35)
-#define JTD     7
-#define PUD     4
-#define IVSEL   1
-#define IVCE    0
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMIE   7
-#define RWWSB   6
-#define SIGRD   5
-#define RWWSRE  4
-#define BLBSET  3
-#define PGWRT   2
-#define PGERS   1
-#define SPMEN   0
-
-/* Reserved [0x38..0x3A] */
-
-#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
-#define RAMPZ   _SFR_IO8(0x3B)
-#endif
-
-/* Reserved [0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDIF    7
-#define WDIE    6
-#define WDP3    5
-#define WDCE    4
-#define WDE     3
-#define WDP2    2
-#define WDP1    1
-#define WDP0    0
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPCE  7
-#define CLKPS3  3
-#define CLKPS2  2
-#define CLKPS1  1
-#define CLKPS0  0
-
-/* Reserved [0x62..0x63] */
-
-#define PRR0    _SFR_MEM8(0x64)
-#define PRTWI   7
-#define PRTIM2  6
-#define PRTIM0  5
-#define PRTIM1  3
-#define PRSPI   2
-#define PRADC   0
-
-#define PRR1    _SFR_MEM8(0x65)
-#define PRUSB   7
-#define PRTIM3  3
-#define PRUSART1 0
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67] */
-
-#define PCICR   _SFR_MEM8(0x68)
-#define PCIE0   0
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-#define EICRB   _SFR_MEM8(0x6A)
-#define ISC71   7
-#define ISC70   6
-#define ISC61   5
-#define ISC60   4
-#define ISC51   3
-#define ISC50   2
-#define ISC41   1
-#define ISC40   0
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT7  7
-#define PCINT6  6
-#define PCINT5  5
-#define PCINT4  4
-#define PCINT3  3
-#define PCINT2  2
-#define PCINT1  1
-#define PCINT0  0
-
-/* Reserved [0x6C..0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define OCIE0B  2
-#define OCIE0A  1
-#define TOIE0   0
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define ICIE1   5
-#define OCIE1C  3
-#define OCIE1B  2
-#define OCIE1A  1
-#define TOIE1   0
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define OCIE2B  2
-#define OCIE2A  1
-#define TOIE2   0
-
-#define TIMSK3  _SFR_MEM8(0x71)
-#define ICIE3   5
-#define OCIE3C  3
-#define OCIE3B  2
-#define OCIE3A  1
-#define TOIE3   0
-
-/* Reserved [0x72..0x73] */
-
-#define XMCRA   _SFR_MEM8(0x74)
-#define SRE     7
-#define SRL2    6
-#define SRL1    5
-#define SRL0    4
-#define SRW11   3
-#define SRW10   2
-#define SRW01   1
-#define SRW00   0
-
-#define XMCRB   _SFR_MEM8(0x75)
-#define XMBK    7
-#define XMM2    2
-#define XMM1    1
-#define XMM0    0
-
-/* Reserved [0x76..0x77] */
-
-/* RegDef:  ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC    _SFR_MEM16(0x78)
-#endif
-#define ADCW   _SFR_MEM16(0x78)
-#define ADCL   _SFR_MEM8(0x78)
-#define ADCH   _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADEN    7
-#define ADSC    6
-#define ADATE   5
-#define ADIF    4
-#define ADIE    3
-#define ADPS2   2
-#define ADPS1   1
-#define ADPS0   0
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ACME    6
-#define ADTS2   2
-#define ADTS1   1
-#define ADTS0   0
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define REFS1   7
-#define REFS0   6
-#define ADLAR   5
-#define MUX4    4
-#define MUX3    3
-#define MUX2    2
-#define MUX1    1
-#define MUX0    0
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC7D   7
-#define ADC6D   6
-#define ADC5D   5
-#define ADC4D   4
-#define ADC3D   3
-#define ADC2D   2
-#define ADC1D   1
-#define ADC0D   0
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN1D   1
-#define AIN0D   0
-
-#define TCCR1A  _SFR_MEM8(0x80)
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define COM1C1  3
-#define COM1C0  2
-#define WGM11   1
-#define WGM10   0
-
-#define TCCR1B  _SFR_MEM8(0x81)
-#define ICNC1   7
-#define ICES1   6
-#define WGM13   4
-#define WGM12   3
-#define CS12    2
-#define CS11    1
-#define CS10    0
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1A   7
-#define FOC1B   6
-#define FOC1C   5
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Combine OCR1CL and OCR1CH */
-#define OCR1C   _SFR_MEM16(0x8C)
-
-#define OCR1CL  _SFR_MEM8(0x8C)
-#define OCR1CH  _SFR_MEM8(0x8D)
-
-/* Reserved [0x8E..0x8F] */
-
-#define TCCR3A  _SFR_MEM8(0x90)
-#define COM3A1  7
-#define COM3A0  6
-#define COM3B1  5
-#define COM3B0  4
-#define COM3C1  3
-#define COM3C0  2
-#define WGM31   1
-#define WGM30   0
-
-#define TCCR3B  _SFR_MEM8(0x91)
-#define ICNC3   7
-#define ICES3   6
-#define WGM33   4
-#define WGM32   3
-#define CS32    2
-#define CS31    1
-#define CS30    0
-
-#define TCCR3C  _SFR_MEM8(0x92)
-#define FOC3A   7
-#define FOC3B   6
-#define FOC3C   5
-
-/* Reserved [0x93] */
-
-/* Combine TCNT3L and TCNT3H */
-#define TCNT3   _SFR_MEM16(0x94)
-
-#define TCNT3L  _SFR_MEM8(0x94)
-#define TCNT3H  _SFR_MEM8(0x95)
-
-/* Combine ICR3L and ICR3H */
-#define ICR3    _SFR_MEM16(0x96)
-
-#define ICR3L   _SFR_MEM8(0x96)
-#define ICR3H   _SFR_MEM8(0x97)
-
-/* Combine OCR3AL and OCR3AH */
-#define OCR3A   _SFR_MEM16(0x98)
-
-#define OCR3AL  _SFR_MEM8(0x98)
-#define OCR3AH  _SFR_MEM8(0x99)
-
-/* Combine OCR3BL and OCR3BH */
-#define OCR3B   _SFR_MEM16(0x9A)
-
-#define OCR3BL  _SFR_MEM8(0x9A)
-#define OCR3BH  _SFR_MEM8(0x9B)
-
-/* Combine OCR3CL and OCR3CH */
-#define OCR3C   _SFR_MEM16(0x9C)
-
-#define OCR3CL  _SFR_MEM8(0x9C)
-#define OCR3CH  _SFR_MEM8(0x9D)
-
-#if defined(__AT90USBxx7__)
-
-#define UHCON   _SFR_MEM8(0x9E)
-#define RESUME  2
-#define RESET   1
-#define SOFEN   0
-
-#define UHINT   _SFR_MEM8(0x9F)
-#define HWUPI   6
-#define HSOFI   5
-#define RXRSMI  4
-#define RSMEDI  3
-#define RSTI    2
-#define DDISCI  1
-#define DCONNI  0
-
-#define UHIEN   _SFR_MEM8(0xA0)
-#define HWUPE   6
-#define HSOFE   5
-#define RXRSME  4
-#define RSMEDE  3
-#define RSTE    2
-#define DDISCE  1
-#define DCONNE  0
-
-#define UHADDR  _SFR_MEM8(0xA1)
-
-/* Combine UHFNUML and UHFNUMH */
-#define UHFNUM  _SFR_MEM16(0xA2)
-
-#define UHFNUML _SFR_MEM8(0xA2)
-#define UHFNUMH _SFR_MEM8(0xA3)
-
-#define UHFLEN  _SFR_MEM8(0xA4)
-
-#define UPINRQX _SFR_MEM8(0xA5)
-
-#define UPINTX  _SFR_MEM8(0xA6)
-#define FIFOCON 7
-#define NAKEDI  6
-#define RWAL    5
-#define PERRI   4
-#define TXSTPI  3
-#define TXOUTI  2
-#define RXSTALLI 1
-#define RXINI   0
-
-#define UPNUM   _SFR_MEM8(0xA7)
-
-#define UPRST   _SFR_MEM8(0xA8)
-#define PRST6   6
-#define PRST5   5
-#define PRST4   4
-#define PRST3   3
-#define PRST2   2
-#define PRST1   1
-#define PRST0   0
-
-#define UPCONX  _SFR_MEM8(0xA9)
-#define PFREEZE 6
-#define INMODE  5
-/* #define AUTOSW  4 */ /* Reserved */
-#define RSTDT   3
-#define PEN     0
-
-#define UPCFG0X _SFR_MEM8(0XAA)
-#define PTYPE1  7
-#define PTYPE0  6
-#define PTOKEN1 5
-#define PTOKEN0 4
-#define PEPNUM3 3
-#define PEPNUM2 2
-#define PEPNUM1 1
-#define PEPNUM0 0
-
-#define UPCFG1X _SFR_MEM8(0XAB)
-#define PSIZE2  6
-#define PSIZE1  5
-#define PSIZE0  4
-#define PBK1    3
-#define PBK0    2
-#define ALLOC   1
-
-#define UPSTAX  _SFR_MEM8(0XAC)
-#define CFGOK   7
-#define OVERFI  6
-#define UNDERFI 5
-#define DTSEQ1  3
-#define DTSEQ0  2
-#define NBUSYBK1 1
-#define NBUSYBK0 0
-
-#define UPCFG2X _SFR_MEM8(0XAD)
-
-#define UPIENX  _SFR_MEM8(0XAE)
-#define FLERRE  7
-#define NAKEDE  6
-#define PERRE   4
-#define TXSTPE  3
-#define TXOUTE  2
-#define RXSTALLE 1
-#define RXINE   0
-
-#define UPDATX  _SFR_MEM8(0XAF)
-
-#endif /* __AT90USBxx7__ */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define COM2A1  7
-#define COM2A0  6
-#define COM2B1  5
-#define COM2B0  4
-#define WGM21   1
-#define WGM20   0
-
-#define TCCR2B  _SFR_MEM8(0xB1)
-#define FOC2A   7
-#define FOC2B   6
-#define WGM22   3
-#define CS22    2
-#define CS21    1
-#define CS20    0
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-#define OCR2B   _SFR_MEM8(0xB4)
-
-/* Reserved [0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define EXCLK   6
-#define AS2     5
-#define TCN2UB  4
-#define OCR2AUB 3
-#define OCR2BUB 2
-#define TCR2AUB 1
-#define TCR2BUB 0
-
-/* Reserved [0xB7] */
-
-#define TWBR    _SFR_MEM8(0xB8)
-
-#define TWSR    _SFR_MEM8(0xB9)
-#define TWS7    7
-#define TWS6    6
-#define TWS5    5
-#define TWS4    4
-#define TWS3    3
-#define TWPS1   1
-#define TWPS0   0
-
-#define TWAR    _SFR_MEM8(0xBA)
-#define TWA6    7
-#define TWA5    6
-#define TWA4    5
-#define TWA3    4
-#define TWA2    3
-#define TWA1    2
-#define TWA0    1
-#define TWGCE   0
-
-#define TWDR    _SFR_MEM8(0xBB)
-
-#define TWCR    _SFR_MEM8(0xBC)
-#define TWINT   7
-#define TWEA    6
-#define TWSTA   5
-#define TWSTO   4
-#define TWWC    3
-#define TWEN    2
-#define TWIE    0
-
-#define TWAMR   _SFR_MEM8(0xBD)
-#define TWAM6   7
-#define TWAM5   6
-#define TWAM4   5
-#define TWAM3   4
-#define TWAM2   3
-#define TWAM1   2
-#define TWAM0   1
-
-/* Reserved [0xBE..0xC7] */
-
-#define UCSR1A  _SFR_MEM8(0xC8)
-#define RXC1    7
-#define TXC1    6
-#define UDRE1   5
-#define FE1     4
-#define DOR1    3
-#define UPE1    2
-#define U2X1    1
-#define MPCM1   0
-
-#define UCSR1B  _SFR_MEM8(0XC9)
-#define RXCIE1  7
-#define TXCIE1  6
-#define UDRIE1  5
-#define RXEN1   4
-#define TXEN1   3
-#define UCSZ12  2
-#define RXB81   1
-#define TXB81   0
-
-#define UCSR1C  _SFR_MEM8(0xCA)
-#define UMSEL11 7
-#define UMSEL10 6
-#define UPM11   5
-#define UPM10   4
-#define USBS1   3
-#define UCSZ11  2
-#define UCSZ10  1
-#define UCPOL1  0
-
-/* Reserved [0xCB] */
-
-/* Combine UBRR1L and UBRR1H */
-#define UBRR1   _SFR_MEM16(0xCC)
-
-#define UBRR1L  _SFR_MEM8(0xCC)
-#define UBRR1H  _SFR_MEM8(0xCD)
-
-#define UDR1    _SFR_MEM8(0XCE)
-
-/* Reserved [0xCF..0xD6] */
-
-#define UHWCON  _SFR_MEM8(0XD7)
-#define UIMOD   7
-#define UIDE    6
-#define UVCONE  4
-#define UVREGE  0
-
-#define USBCON  _SFR_MEM8(0XD8)
-#define USBE    7
-#define HOST    6
-#define FRZCLK  5
-#define OTGPADE 4
-#define IDTE    1
-#define VBUSTE  0
-
-#define USBSTA  _SFR_MEM8(0XD9)
-#define SPEED   3
-#define ID      1
-#define VBUS    0
-
-#define USBINT  _SFR_MEM8(0XDA)
-#define IDTI    1
-#define VBUSTI  0
-
-/* Combine UDPADDL and UDPADDH */
-#define UDPADD  _SFR_MEM16(0xDB)
-
-#define UDPADDL _SFR_MEM8(0xDB)
-#define UDPADDH _SFR_MEM8(0xDC)
-#define DPACC   7
-
-#if defined(__AT90USBxx7__)
-
-#define OTGCON  _SFR_MEM8(0XDD)
-#define HNPREQ  5
-#define SRPREQ  4
-#define SRPSEL  3
-#define VBUSHWC 2
-#define VBUSREQ 1
-#define VBUSRQC 0
-
-#define OTGIEN  _SFR_MEM8(0XDE)
-#define STOE    5
-#define HNPERRE 4
-#define ROLEEXE 3
-#define BCERRE  2
-#define VBERRE  1
-#define SRPE    0
-
-#define OTGINT  _SFR_MEM8(0XDF)
-#define STOI    5
-#define HNPERRI 4
-#define ROLEEXI 3
-#define BCERRI  2
-#define VBERRI  1
-#define SRPI    0
-
-#endif /* __AT90USBxx7__ */
-
-#define UDCON   _SFR_MEM8(0XE0)
-#define LSM     2
-#define RMWKUP  1
-#define DETACH  0
-
-#define UDINT   _SFR_MEM8(0XE1)
-#define UPRSMI  6
-#define EORSMI  5
-#define WAKEUPI 4
-#define EORSTI  3
-#define SOFI    2
-/* #define MSOFI   1 */ /* Reserved */
-#define SUSPI   0
-
-#define UDIEN   _SFR_MEM8(0XE2)
-#define UPRSME  6
-#define EORSME  5
-#define WAKEUPE 4
-#define EORSTE  3
-#define SOFE    2
-/* #define MSOFE   1 */ /* Reserved */
-#define SUSPE   0
-
-#define UDADDR  _SFR_MEM8(0XE3)
-#define ADDEN   7
-
-/* Combine UDFNUML and UDFNUMH */
-#define UDFNUM  _SFR_MEM16(0xE4)
-
-#define UDFNUML _SFR_MEM8(0xE4)
-#define UDFNUMH _SFR_MEM8(0xE5)
-
-#define UDMFN   _SFR_MEM8(0XE6)
-#define FNCERR  4
-
-#define UDTST   _SFR_MEM8(0XE7)
-#define OPMODE2 5
-#define TSTPCKT 4
-#define TSTK    3
-#define TSTJ    2
-
-#define UEINTX  _SFR_MEM8(0XE8)
-#define FIFOCON 7
-#define NAKINI  6
-#define RWAL    5
-#define NAKOUTI 4
-#define RXSTPI  3
-#define RXOUTI  2
-#define STALLEDI 1
-#define TXINI   0
-
-#define UENUM   _SFR_MEM8(0XE9)
-
-#define UERST   _SFR_MEM8(0XEA)
-#define EPRST6  6
-#define EPRST5  5
-#define EPRST4  4
-#define EPRST3  3
-#define EPRST2  2
-#define EPRST1  1
-#define EPRST0  0
-
-#define UECONX  _SFR_MEM8(0XEB)
-#define STALLRQ 5
-#define STALLRQC 4
-#define RSTDT   3
-#define EPEN    0
-
-#define UECFG0X _SFR_MEM8(0XEC)
-#define EPTYPE1 7
-#define EPTYPE0 6
-/* #define ISOSW   3 */ /* Reserved */
-/* #define AUTOSW  2 */ /* Reserved */
-/* #define NYETSDIS 1 */ /* Reserved */
-#define EPDIR   0
-
-#define UECFG1X  _SFR_MEM8(0XED)
-#define EPSIZE2 6
-#define EPSIZE1 5
-#define EPSIZE0 4
-#define EPBK1   3
-#define EPBK0   2
-#define ALLOC   1
-
-#define UESTA0X _SFR_MEM8(0XEE)
-#define CFGOK   7
-#define OVERFI  6
-#define UNDERFI 5
-#define ZLPSEEN 4
-#define DTSEQ1  3
-#define DTSEQ0  2
-#define NBUSYBK1 1
-#define NBUSYBK0 0
-
-#define UESTA1X _SFR_MEM8(0XEF)
-#define CTRLDIR 2
-#define CURRBK1 1
-#define CURRBK0 0
-
-#define UEIENX  _SFR_MEM8(0XF0)
-#define FLERRE  7
-#define NAKINE  6
-#define NAKOUTE 4
-#define RXSTPE  3
-#define RXOUTE  2
-#define STALLEDE 1
-#define TXINE   0
-
-#define UEDATX  _SFR_MEM8(0XF1)
-
-/* Combine UEBCLX and UEBCHX */
-#define UEBCX   _SFR_MEM16(0xF2)
-
-#define UEBCLX  _SFR_MEM8(0xF2)
-#define UEBCHX  _SFR_MEM8(0xF3)
-
-#define UEINT   _SFR_MEM8(0XF4)
-#define EPINT6  6
-#define EPINT5  5
-#define EPINT4  4
-#define EPINT3  3
-#define EPINT2  2
-#define EPINT1  1
-#define EPINT0  0
-
-#if defined(__AT90USBxx7__)
-
-#define UPERRX  _SFR_MEM8(0XF5)
-#define COUNTER1 6
-#define COUNTER0 5
-#define CRC16    4
-#define TIMEOUT  3
-#define PID      2
-#define DATAPID  1
-#define DATATGL  0
-
-/* Combine UPBCLX and UPBCHX */
-#define UPBCX   _SFR_MEM16(0xF6)
-
-#define UPBCLX  _SFR_MEM8(0xF6)
-#define UPBCHX  _SFR_MEM8(0xF7)
-
-#define UPINT   _SFR_MEM8(0XF8)
-#define PINT6   6
-#define PINT5   5
-#define PINT4   4
-#define PINT3   3
-#define PINT2   2
-#define PINT1   1
-#define PINT0   0
-
-#define OTGTCON _SFR_MEM8(0XF9)
-#define PAGE1   6
-#define PAGE0   5
-#define VALUE1  1
-#define VALUE0  0
-
-#endif /* __AT90USBxx7__ */
-
-/* Reserved [0xFA..0xFF] */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(9)
-
-/* USB General Interrupt Request */
-#define USB_GEN_vect			_VECTOR(10)
-
-/* USB Endpoint/Pipe Interrupt Communication Request */
-#define USB_COM_vect			_VECTOR(11)
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect			_VECTOR(12)
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect		_VECTOR(13)
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect		_VECTOR(14)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(15)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(16)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(17)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(18)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(19)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(20)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect		_VECTOR(21)
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(22)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(23)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(24)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(25)
-
-/* USART1 Data register Empty */
-#define USART1_UDRE_vect		_VECTOR(26)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(27)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(28)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(29)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(30)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(31)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(32)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(33)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(34)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(35)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(36)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(37)
-
-#define _VECTORS_SIZE 152
-
-#if defined(__AT90USBxx6__)
-# undef __AT90USBxx6__
-#endif /* __AT90USBxx6__ */
-
-#if defined(__AT90USBxx7__)
-# undef __AT90USBxx7__
-#endif /* __AT90USBxx7__ */
-
-/**@}*/
-#endif  /* _AVR_IOUSBXX6_7_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox128a1.h b/cpukit/score/cpu/avr/avr/iox128a1.h
deleted file mode 100644
index 4ce4c47e64..0000000000
--- a/cpukit/score/cpu/avr/avr/iox128a1.h
+++ /dev/null
@@ -1,7583 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox128a1.h - definitions for ATxmega128A1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128a1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATxmega128A1_H_
-#define _AVR_ATxmega128A1_H_ 1
-
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-/**
- * @name IO Module Structures
- * 
- */
-/**@{**/
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  
-    /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  
-    /* 32kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    /* External Oscillator Failure Detection Register */
-    register8_t XOSCFAIL;  
-    /* 32kHz Internal Oscillator Calibration Register */
-    register8_t RC32KCAL;  
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    /* Reload at end of transaction */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    /* Reload at end of transaction */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), 
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-     /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), 
-    /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  
-    /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  
-    /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  
-    /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  
-    /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  
-    /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  
-    /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  
-    /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  
-    /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  
-    /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  
-    /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  
-    /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  
-    /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  
-    /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  
-    /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  
-    /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  
-    /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), 
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  
-    /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), 
-    /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  
-    /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  
-    /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  
-    /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  
-    /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  
-    /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  
-    /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  
-    /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  
-    /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  
-    /* USART F1 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  
-    /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  
-    /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  
-    /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  
-    /* Channel 0 > channel 1 > channel 2 > channel 3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  
-    /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  
-    /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  
-    /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  
-    /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  
-    /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  
-    /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  
-    /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  
-    /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  
-    /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  
-    /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  
-    /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  
-    /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  
-    /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  
-    /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  
-    /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  
-    /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  
-    /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  
-    /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  
-    /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  
-    /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  
-    /* Timer/Counter F1 Compare or Capture B */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    /* Erase Application Section page */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    /* Write Application Section page */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  
-    /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  
-    /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  
-    /* Erase/flush EEPROM page buffer */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<2),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<2),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<2),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    /* Differential input, with gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    /* 12-bit left-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    /* First event triggers synchronized sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  
-    /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  
-    /* Interrupt on result above compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), 
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    /* Single channel operation (Channel A only) */
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  
-    /* Dual channel operation (S/H on both channels) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  
-    /* External reference on AREF on PORTB */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  
-    /* Used in Response to Address/Data Interrupt */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), 
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  
-    /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  
-    /* Event Channel 7 Output on Port E pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC0_gc = (0x01<<0),  
-    /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  
-    /* Enable High Resolution both Timer/Counters */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    /* IrDA Transmitter Pulse Length Control Register */
-    register8_t TXPLCTRL;  
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-/** @} */
-
-/**
- * @name IO Module Instances. Mapped to Memory
- * 
- */
-/**@{**/
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACA    (*(DAC_t *) 0x0300)  /* Digital to Analog Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define EBI    (*(EBI_t *) 0x0440)  /* External Bus Interface */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWID    (*(TWI_t *) 0x0490)  /* Two-Wire Interface D */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define TWIF    (*(TWI_t *) 0x04B0)  /* Two-Wire Interface F */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTH    (*(PORT_t *) 0x06E0)  /* Port H */
-#define PORTJ    (*(PORT_t *) 0x0700)  /* Port J */
-#define PORTK    (*(PORT_t *) 0x0720)  /* Port K */
-#define PORTQ    (*(PORT_t *) 0x07C0)  /* Port Q */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-/* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0    (*(USART_t *) 0x08A0)  
-/* Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1    (*(USART_t *) 0x08B0)  
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-/* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  
-/* Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1    (*(USART_t *) 0x09B0)  
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-/* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0    (*(USART_t *) 0x0AA0)  
-/* Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define TCF1    (*(TC1_t *) 0x0B40)  /* Timer/Counter F1 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-/* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0    (*(USART_t *) 0x0BA0)  
-/* Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-/** @} */
-
-/**
- * @name Flattened Fully Qualified IO Register Names
- * 
- */
-/**@{**/
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACA - Digital to Analog Converter A */
-#define DACA_CTRLA  _SFR_MEM8(0x0300)
-#define DACA_CTRLB  _SFR_MEM8(0x0301)
-#define DACA_CTRLC  _SFR_MEM8(0x0302)
-#define DACA_EVCTRL  _SFR_MEM8(0x0303)
-#define DACA_TIMCTRL  _SFR_MEM8(0x0304)
-#define DACA_STATUS  _SFR_MEM8(0x0305)
-#define DACA_GAINCAL  _SFR_MEM8(0x0308)
-#define DACA_OFFSETCAL  _SFR_MEM8(0x0309)
-#define DACA_CH0DATA  _SFR_MEM16(0x0318)
-#define DACA_CH1DATA  _SFR_MEM16(0x031A)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* EBI - External Bus Interface */
-#define EBI_CTRL  _SFR_MEM8(0x0440)
-#define EBI_SDRAMCTRLA  _SFR_MEM8(0x0441)
-#define EBI_REFRESH  _SFR_MEM16(0x0444)
-#define EBI_INITDLY  _SFR_MEM16(0x0446)
-#define EBI_SDRAMCTRLB  _SFR_MEM8(0x0448)
-#define EBI_SDRAMCTRLC  _SFR_MEM8(0x0449)
-#define EBI_CS0_CTRLA  _SFR_MEM8(0x0450)
-#define EBI_CS0_CTRLB  _SFR_MEM8(0x0451)
-#define EBI_CS0_BASEADDR  _SFR_MEM16(0x0452)
-#define EBI_CS1_CTRLA  _SFR_MEM8(0x0454)
-#define EBI_CS1_CTRLB  _SFR_MEM8(0x0455)
-#define EBI_CS1_BASEADDR  _SFR_MEM16(0x0456)
-#define EBI_CS2_CTRLA  _SFR_MEM8(0x0458)
-#define EBI_CS2_CTRLB  _SFR_MEM8(0x0459)
-#define EBI_CS2_BASEADDR  _SFR_MEM16(0x045A)
-#define EBI_CS3_CTRLA  _SFR_MEM8(0x045C)
-#define EBI_CS3_CTRLB  _SFR_MEM8(0x045D)
-#define EBI_CS3_BASEADDR  _SFR_MEM16(0x045E)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWID - Two-Wire Interface D */
-#define TWID_CTRL  _SFR_MEM8(0x0490)
-#define TWID_MASTER_CTRLA  _SFR_MEM8(0x0491)
-#define TWID_MASTER_CTRLB  _SFR_MEM8(0x0492)
-#define TWID_MASTER_CTRLC  _SFR_MEM8(0x0493)
-#define TWID_MASTER_STATUS  _SFR_MEM8(0x0494)
-#define TWID_MASTER_BAUD  _SFR_MEM8(0x0495)
-#define TWID_MASTER_ADDR  _SFR_MEM8(0x0496)
-#define TWID_MASTER_DATA  _SFR_MEM8(0x0497)
-#define TWID_SLAVE_CTRLA  _SFR_MEM8(0x0498)
-#define TWID_SLAVE_CTRLB  _SFR_MEM8(0x0499)
-#define TWID_SLAVE_STATUS  _SFR_MEM8(0x049A)
-#define TWID_SLAVE_ADDR  _SFR_MEM8(0x049B)
-#define TWID_SLAVE_DATA  _SFR_MEM8(0x049C)
-#define TWID_SLAVE_ADDRMASK  _SFR_MEM8(0x049D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* TWIF - Two-Wire Interface F */
-#define TWIF_CTRL  _SFR_MEM8(0x04B0)
-#define TWIF_MASTER_CTRLA  _SFR_MEM8(0x04B1)
-#define TWIF_MASTER_CTRLB  _SFR_MEM8(0x04B2)
-#define TWIF_MASTER_CTRLC  _SFR_MEM8(0x04B3)
-#define TWIF_MASTER_STATUS  _SFR_MEM8(0x04B4)
-#define TWIF_MASTER_BAUD  _SFR_MEM8(0x04B5)
-#define TWIF_MASTER_ADDR  _SFR_MEM8(0x04B6)
-#define TWIF_MASTER_DATA  _SFR_MEM8(0x04B7)
-#define TWIF_SLAVE_CTRLA  _SFR_MEM8(0x04B8)
-#define TWIF_SLAVE_CTRLB  _SFR_MEM8(0x04B9)
-#define TWIF_SLAVE_STATUS  _SFR_MEM8(0x04BA)
-#define TWIF_SLAVE_ADDR  _SFR_MEM8(0x04BB)
-#define TWIF_SLAVE_DATA  _SFR_MEM8(0x04BC)
-#define TWIF_SLAVE_ADDRMASK  _SFR_MEM8(0x04BD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTH - Port H */
-#define PORTH_DIR  _SFR_MEM8(0x06E0)
-#define PORTH_DIRSET  _SFR_MEM8(0x06E1)
-#define PORTH_DIRCLR  _SFR_MEM8(0x06E2)
-#define PORTH_DIRTGL  _SFR_MEM8(0x06E3)
-#define PORTH_OUT  _SFR_MEM8(0x06E4)
-#define PORTH_OUTSET  _SFR_MEM8(0x06E5)
-#define PORTH_OUTCLR  _SFR_MEM8(0x06E6)
-#define PORTH_OUTTGL  _SFR_MEM8(0x06E7)
-#define PORTH_IN  _SFR_MEM8(0x06E8)
-#define PORTH_INTCTRL  _SFR_MEM8(0x06E9)
-#define PORTH_INT0MASK  _SFR_MEM8(0x06EA)
-#define PORTH_INT1MASK  _SFR_MEM8(0x06EB)
-#define PORTH_INTFLAGS  _SFR_MEM8(0x06EC)
-#define PORTH_PIN0CTRL  _SFR_MEM8(0x06F0)
-#define PORTH_PIN1CTRL  _SFR_MEM8(0x06F1)
-#define PORTH_PIN2CTRL  _SFR_MEM8(0x06F2)
-#define PORTH_PIN3CTRL  _SFR_MEM8(0x06F3)
-#define PORTH_PIN4CTRL  _SFR_MEM8(0x06F4)
-#define PORTH_PIN5CTRL  _SFR_MEM8(0x06F5)
-#define PORTH_PIN6CTRL  _SFR_MEM8(0x06F6)
-#define PORTH_PIN7CTRL  _SFR_MEM8(0x06F7)
-
-/* PORTJ - Port J */
-#define PORTJ_DIR  _SFR_MEM8(0x0700)
-#define PORTJ_DIRSET  _SFR_MEM8(0x0701)
-#define PORTJ_DIRCLR  _SFR_MEM8(0x0702)
-#define PORTJ_DIRTGL  _SFR_MEM8(0x0703)
-#define PORTJ_OUT  _SFR_MEM8(0x0704)
-#define PORTJ_OUTSET  _SFR_MEM8(0x0705)
-#define PORTJ_OUTCLR  _SFR_MEM8(0x0706)
-#define PORTJ_OUTTGL  _SFR_MEM8(0x0707)
-#define PORTJ_IN  _SFR_MEM8(0x0708)
-#define PORTJ_INTCTRL  _SFR_MEM8(0x0709)
-#define PORTJ_INT0MASK  _SFR_MEM8(0x070A)
-#define PORTJ_INT1MASK  _SFR_MEM8(0x070B)
-#define PORTJ_INTFLAGS  _SFR_MEM8(0x070C)
-#define PORTJ_PIN0CTRL  _SFR_MEM8(0x0710)
-#define PORTJ_PIN1CTRL  _SFR_MEM8(0x0711)
-#define PORTJ_PIN2CTRL  _SFR_MEM8(0x0712)
-#define PORTJ_PIN3CTRL  _SFR_MEM8(0x0713)
-#define PORTJ_PIN4CTRL  _SFR_MEM8(0x0714)
-#define PORTJ_PIN5CTRL  _SFR_MEM8(0x0715)
-#define PORTJ_PIN6CTRL  _SFR_MEM8(0x0716)
-#define PORTJ_PIN7CTRL  _SFR_MEM8(0x0717)
-
-/* PORTK - Port K */
-#define PORTK_DIR  _SFR_MEM8(0x0720)
-#define PORTK_DIRSET  _SFR_MEM8(0x0721)
-#define PORTK_DIRCLR  _SFR_MEM8(0x0722)
-#define PORTK_DIRTGL  _SFR_MEM8(0x0723)
-#define PORTK_OUT  _SFR_MEM8(0x0724)
-#define PORTK_OUTSET  _SFR_MEM8(0x0725)
-#define PORTK_OUTCLR  _SFR_MEM8(0x0726)
-#define PORTK_OUTTGL  _SFR_MEM8(0x0727)
-#define PORTK_IN  _SFR_MEM8(0x0728)
-#define PORTK_INTCTRL  _SFR_MEM8(0x0729)
-#define PORTK_INT0MASK  _SFR_MEM8(0x072A)
-#define PORTK_INT1MASK  _SFR_MEM8(0x072B)
-#define PORTK_INTFLAGS  _SFR_MEM8(0x072C)
-#define PORTK_PIN0CTRL  _SFR_MEM8(0x0730)
-#define PORTK_PIN1CTRL  _SFR_MEM8(0x0731)
-#define PORTK_PIN2CTRL  _SFR_MEM8(0x0732)
-#define PORTK_PIN3CTRL  _SFR_MEM8(0x0733)
-#define PORTK_PIN4CTRL  _SFR_MEM8(0x0734)
-#define PORTK_PIN5CTRL  _SFR_MEM8(0x0735)
-#define PORTK_PIN6CTRL  _SFR_MEM8(0x0736)
-#define PORTK_PIN7CTRL  _SFR_MEM8(0x0737)
-
-/* PORTQ - Port Q */
-#define PORTQ_DIR  _SFR_MEM8(0x07C0)
-#define PORTQ_DIRSET  _SFR_MEM8(0x07C1)
-#define PORTQ_DIRCLR  _SFR_MEM8(0x07C2)
-#define PORTQ_DIRTGL  _SFR_MEM8(0x07C3)
-#define PORTQ_OUT  _SFR_MEM8(0x07C4)
-#define PORTQ_OUTSET  _SFR_MEM8(0x07C5)
-#define PORTQ_OUTCLR  _SFR_MEM8(0x07C6)
-#define PORTQ_OUTTGL  _SFR_MEM8(0x07C7)
-#define PORTQ_IN  _SFR_MEM8(0x07C8)
-#define PORTQ_INTCTRL  _SFR_MEM8(0x07C9)
-#define PORTQ_INT0MASK  _SFR_MEM8(0x07CA)
-#define PORTQ_INT1MASK  _SFR_MEM8(0x07CB)
-#define PORTQ_INTFLAGS  _SFR_MEM8(0x07CC)
-#define PORTQ_PIN0CTRL  _SFR_MEM8(0x07D0)
-#define PORTQ_PIN1CTRL  _SFR_MEM8(0x07D1)
-#define PORTQ_PIN2CTRL  _SFR_MEM8(0x07D2)
-#define PORTQ_PIN3CTRL  _SFR_MEM8(0x07D3)
-#define PORTQ_PIN4CTRL  _SFR_MEM8(0x07D4)
-#define PORTQ_PIN5CTRL  _SFR_MEM8(0x07D5)
-#define PORTQ_PIN6CTRL  _SFR_MEM8(0x07D6)
-#define PORTQ_PIN7CTRL  _SFR_MEM8(0x07D7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* TCF1 - Timer/Counter F1 */
-#define TCF1_CTRLA  _SFR_MEM8(0x0B40)
-#define TCF1_CTRLB  _SFR_MEM8(0x0B41)
-#define TCF1_CTRLC  _SFR_MEM8(0x0B42)
-#define TCF1_CTRLD  _SFR_MEM8(0x0B43)
-#define TCF1_CTRLE  _SFR_MEM8(0x0B44)
-#define TCF1_INTCTRLA  _SFR_MEM8(0x0B46)
-#define TCF1_INTCTRLB  _SFR_MEM8(0x0B47)
-#define TCF1_CTRLFCLR  _SFR_MEM8(0x0B48)
-#define TCF1_CTRLFSET  _SFR_MEM8(0x0B49)
-#define TCF1_CTRLGCLR  _SFR_MEM8(0x0B4A)
-#define TCF1_CTRLGSET  _SFR_MEM8(0x0B4B)
-#define TCF1_INTFLAGS  _SFR_MEM8(0x0B4C)
-#define TCF1_TEMP  _SFR_MEM8(0x0B4F)
-#define TCF1_CNT  _SFR_MEM16(0x0B60)
-#define TCF1_PER  _SFR_MEM16(0x0B66)
-#define TCF1_CCA  _SFR_MEM16(0x0B68)
-#define TCF1_CCB  _SFR_MEM16(0x0B6A)
-#define TCF1_PERBUF  _SFR_MEM16(0x0B76)
-#define TCF1_CCABUF  _SFR_MEM16(0x0B78)
-#define TCF1_CCBBUF  _SFR_MEM16(0x0B7A)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-/** @} */
-
-/**
- * @name Bitfield Definitions
- * 
- */
-/**@{**/
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-/* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gm  0x03  
-/* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV_gp  0  
-/* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bm  (1<<0)  
-/* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV0_bp  0  
-/* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bm  (1<<1) 
-/* Prescaler B and C Division factor bit 1 position. */
-#define CLK_PSBCDIV1_bp  1  
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-/* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bm  0x04 
-/* Internal 32kHz RC Oscillator Enable bit position. */
-#define OSC_RC32KEN_bp  2  
-
-/* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bm  0x02  
-/* Internal 32MHz RC Oscillator Enable bit position. */
-#define OSC_RC32MEN_bp  1  
-
-/* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bm  0x01  
-/* Internal 2MHz RC Oscillator Enable bit position. */
-#define OSC_RC2MEN_bp  0  
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-/* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bm  0x04 
-/* Internal 32kHz RC Oscillator Ready bit position. */
-#define OSC_RC32KRDY_bp  2  
-
-/* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bm  0x02 
-/* Internal 32MHz RC Oscillator Ready bit position. */
-#define OSC_RC32MRDY_bp  1  
-
-/* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bm  0x01  
-/* Internal 2MHz RC Oscillator Ready bit position. */
-#define OSC_RC2MRDY_bp  0  
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-/* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gm  0x0F  
-/* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL_gp  0
-/* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bm  (1<<0) 
-/* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL0_bp  0  
-/* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bm  (1<<1)  
-/* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL1_bp  1 
-/* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bm  (1<<2)  
-/* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL2_bp  2  
-/* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bm  (1<<3)  
-/* External Oscillator Selection and Startup Time bit 3 position. */
-#define OSC_XOSCSEL3_bp  3  
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-/* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bm  0x02  
-/* Failure Detection Interrupt Flag bit position. */
-#define OSC_XOSCFDIF_bp  1  
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-/* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bm  0x10  
-/* Programming and Debug Interface Interface Reset Flag bit position. */
-#define RST_PDIRF_bp  4  
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-/* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bm  0x02  
-/* Medium Level Interrupt Executing bit position. */
-#define PMIC_MEDLVLEX_bp  1
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-/* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bm  0x04  
-/* Channel Single Shot Data Transfer bit position. */
-#define DMA_CH_SINGLE_bp  2  
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-/* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bm  0x20  
-/* Block Transfer Error Interrupt Flag bit position. */
-#define DMA_CH_ERRIF_bp  5  
-
-/* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bm  0x10  
-/* Transaction Complete Interrup Flag bit position. */
-#define DMA_CH_TRNIF_bp  4  
-
-/* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gm  0x0C  
-/* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL_gp  2  
-/* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  
-/* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL0_bp  2  
-/* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  
- /* Transfer Error Interrupt Level bit 1 position. */
-#define DMA_CH_ERRINTLVL1_bp  3 
-
-/* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gm  0x03  
-/* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL_gp  0  
-/* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  
-/* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL0_bp  0  
-/* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  
-/* Transaction Complete Interrupt Level bit 1 position. */
-#define DMA_CH_TRNINTLVL1_bp  1  
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-/* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gm  0xC0  
-/* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD_gp  6  
-/* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  
-/* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD0_bp  6  
-/* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  
-/* Channel Source Address Reload bit 1 position. */
-#define DMA_CH_SRCRELOAD1_bp  7  
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-/* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  
-/* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR0_bp  4  
-/* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  
-/* Channel Source Address Mode bit 1 position. */
-#define DMA_CH_SRCDIR1_bp  5  
-
-/* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gm  0x0C  
-/* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD_gp  2  
-/* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  
-/* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD0_bp  2  
-/* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  
-/* Channel Destination Address Reload bit 1 position. */
-#define DMA_CH_DESTRELOAD1_bp  3  
-
-/* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gm  0x03  
-/* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR_gp  0  
-/* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  
-/* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR0_bp  0  
-/* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  
-/* Channel Destination Address Mode bit 1 position. */
-#define DMA_CH_DESTDIR1_bp  1  
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-/* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bm  0x80  
-/* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-#define DMA_CH3ERRIF_bp  7  
-
-/* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bm  0x40  
-/* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-#define DMA_CH2ERRIF_bp  6  
-
-/* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bm  0x20  
-/* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-#define DMA_CH1ERRIF_bp  5  
-
-/* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bm  0x10  
-/* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-#define DMA_CH0ERRIF_bp  4  
-
-/* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bm  0x08  
-/* Channel 3 Transaction Complete Interrupt Flag bit position. */
-#define DMA_CH3TRNIF_bp  3  
-
-/* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bm  0x04  
-/* Channel 2 Transaction Complete Interrupt Flag bit position. */
-#define DMA_CH2TRNIF_bp  2  
-
-/* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bm  0x02  
-/* Channel 1 Transaction Complete Interrupt Flag bit position. */
-#define DMA_CH1TRNIF_bp  1 
-
-/* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bm  0x01  
-/* Channel 0 Transaction Complete Interrupt Flag bit position. */
-#define DMA_CH0TRNIF_bp  0  
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-/* Channel 3 Block Transfer Pending bit position. */
-#define DMA_CH3PEND_bp  3  
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-/* Channel 2 Block Transfer Pending bit position. */
-#define DMA_CH2PEND_bp  2  
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-/* Channel 1 Block Transfer Pending bit position. */
-#define DMA_CH1PEND_bp  1  
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-/* Channel 0 Block Transfer Pending bit position. */
-#define DMA_CH0PEND_bp  0  
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-/* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gm  0x60  
-/* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM_gp  5  
-/* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bm  (1<<5)  
-/* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM0_bp  5  
-/* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bm  (1<<6)  
-/* Quadrature Decoder Index Recognition Mode bit 1 position. */
-#define EVSYS_QDIRM1_bp  6  
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-/* EEPROM Page Buffer Active Loading bit position. */
-#define NVM_EELOAD_bp  1  
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-/* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gm  0x30  
-/* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA_gp  4  
- /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bm  (1<<4) 
-/* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA0_bp  4  
-/* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bm  (1<<5)  
-/* Boot Lock Bits - Application Section bit 1 position. */
-#define NVM_BLBA1_bp  5  
-
-/* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gm  0x0C  
-/* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT_gp  2  
-/* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bm  (1<<2)  
-/* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT0_bp  2  
-/* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bm  (1<<3)  
-/* Boot Lock Bits - Application Table bit 1 position. */
-#define NVM_BLBAT1_bp  3  
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-/* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  
-/* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB_gp  6  
-/* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  
- /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB0_bp  6 
-/* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  
-/* Boot Lock Bits - Boot Section bit 1 position. */
-#define NVM_LOCKBITS_BLBB1_bp  7  
-
-/* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gm  0x30  
-/* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA_gp  4  
-/* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  
-/* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA0_bp  4  
-/* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  
-/* Boot Lock Bits - Application Section bit 1 position. */
-#define NVM_LOCKBITS_BLBA1_bp  5  
-
-/* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  
-/* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT_gp  2  
-/* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  
-/* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  
-/* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  
-/* Boot Lock Bits - Application Table bit 1 position. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-/* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gm  0xF0  
-/* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP_gp  4  
-/* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  
-/* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP0_bp  4  
-/* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  
-/* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP1_bp  5  
-/* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  
-/* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP2_bp  6  
-/* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  
-/* Watchdog Window Timeout Period bit 3 position. */
-#define NVM_FUSES_WDWP3_bp  7  
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-/* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bm  0x40  
-/* Boot Loader Section Reset Vector bit position. */
-#define NVM_FUSES_BOOTRST_bp  6  
-
-/* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gm  0x0C  
-/* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT_gp  2 
-/* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bm  (1<<2)  
-/* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT0_bp  2  
-/* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bm  (1<<3)  
-/* BOD Operation in Active Mode bit 1 position. */
-#define NVM_FUSES_BODACT1_bp  3  
-
-/* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gm  0x03  
-/* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD_gp  0  
-/* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  
-/* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD0_bp  0  
-/* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  
-/* BOD Operation in Power-Down Mode bit 1 position. */
-#define NVM_FUSES_BODPD1_bp  1  
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-/* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bm  0x08  
-/* Preserve EEPROM Through Chip Erase bit position. */
-#define NVM_FUSES_EESAVE_bp  3  
-
-/* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gm  0x07  
-/* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL_gp  0  
-/* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  
-/* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL0_bp  0  
-/* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  
-/* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL1_bp  1  
-/* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  
-/* Brown Out Detection Voltage Level bit 2 position. */
-#define NVM_FUSES_BODLVL2_bp  2  
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-/* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gm  0x0C  
-/* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL_gp  2  
- /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bm  (1<<2) 
-/* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL0_bp  2  
-/* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  
-/* Compare Match Interrupt Level bit 1 position. */
-#define RTC_COMPINTLVL1_bp  3  
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-/* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gm  0x38  
-/* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY_gp  3  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bm  (1<<3)  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY0_bp  3  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bm  (1<<4)  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY1_bp  4  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bm  (1<<5)  
-/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-#define EBI_ESRDLY2_bp  5  
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-/* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bm  0x10  
-/* Address/Stop Interrupt Enable bit position. */
-#define TWI_SLAVE_APIEN_bp  4  
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-/* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gm  0xC0  
-/* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL_gp  6  
-/* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  
-/* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL0_bp  6  
-/* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  
-/* Compare or Capture D Interrupt Level bit 1 position. */
-#define TC0_CCDINTLVL1_bp  7  
-
-/* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gm  0x30  
- /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL_gp  4 
-/* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  
-/* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL0_bp  4  
- /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bm  (1<<5) 
-/* Compare or Capture C Interrupt Level bit 1 position. */
-#define TC0_CCCINTLVL1_bp  5  
-
-/* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gm  0x0C  
-/* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL_gp  2  
-/* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  
- /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL0_bp  2 
-/* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  
-/* Compare or Capture B Interrupt Level bit 1 position. */
-#define TC0_CCBINTLVL1_bp  3  
-
-/* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gm  0x03  
-/* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL_gp  0  
-/* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  
-/* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL0_bp  0  
-/* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  
-/* Compare or Capture A Interrupt Level bit 1 position. */
-#define TC0_CCAINTLVL1_bp  1  
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-/* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bm  0x80  
-/* Compare or Capture D Interrupt Flag bit position. */
-#define TC0_CCDIF_bp  7  
-
-/* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bm  0x40  
-/* Compare or Capture C Interrupt Flag bit position. */
-#define TC0_CCCIF_bp  6  
-
-/* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bm  0x20  
-/* Compare or Capture B Interrupt Flag bit position. */
-#define TC0_CCBIF_bp  5  
-
-/* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bm  0x10  
-/* Compare or Capture A Interrupt Flag bit position. */
-#define TC0_CCAIF_bp  4  
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-/* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gm  0x0C  
-/* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL_gp  2  
-/* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  
- /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL0_bp  2 
-/* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  
-/* Compare or Capture B Interrupt Level bit 1 position. */
-#define TC1_CCBINTLVL1_bp  3  
-
-/* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gm  0x03  
-/* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL_gp  0  
-/* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  
-/* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL0_bp  0  
-/* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  
-/* Compare or Capture A Interrupt Level bit 1 position. */
-#define TC1_CCAINTLVL1_bp  1  
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-
-/* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bm  0x20  
-/* Compare or Capture B Interrupt Flag bit position. */
-#define TC1_CCBIF_bp  5  
-
-/* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bm  0x10  
-/* Compare or Capture A Interrupt Flag bit position. */
-#define TC1_CCAIF_bp  4  
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-/* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bm  0x08  
-/* Dead Time Insertion Compare Channel D Enable bit position. */
-#define AWEX_DTICCDEN_bp  3  
-
-/* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bm  0x04  
-/* Dead Time Insertion Compare Channel C Enable bit position. */
-#define AWEX_DTICCCEN_bp  2  
-
-/* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bm  0x02  
-/* Dead Time Insertion Compare Channel B Enable bit position. */
-#define AWEX_DTICCBEN_bp  1  
-
-/* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bm  0x01  
-/* Dead Time Insertion Compare Channel A Enable bit position. */
-#define AWEX_DTICCAEN_bp  0  
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-/* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bm  0x10  
-/* Fault Detect on Disable Break Disable bit position. */
-#define AWEX_FDDBD_bp  4  
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-/* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bm  0x02  
-/* Dead Time High Side Buffer Valid bit position. */
-#define AWEX_DTHSBUFV_bp  1  
-
-/* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bm  0x01  
-/* Dead Time Low Side Buffer Valid bit position. */
-#define AWEX_DTLSBUFV_bp  0  
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-/* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bm  (1<<2)  
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-/* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bm  (1<<3)  
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-/* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gm  0x03  
-/* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL_gp  0  
-/* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bm  (1<<0) 
-/* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL0_bp  0  
-/* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bm  (1<<1)  
-/* Data Register Empty Interrupt Level bit 1 position. */
-#define USART_DREINTLVL1_bp  1  
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-/* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bm  0x02  
-/* Multi-processor Communication Mode bit position. */
-#define USART_MPCM_bp  1  
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-/* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bm  (1<<0)  
-/* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL0_bp  0  
-/* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bm  (1<<1)  
-/* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL1_bp  1  
-/* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bm  (1<<2)  
-/* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL2_bp  2  
-/* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bm  (1<<3)  
-/* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL3_bp  3  
-/* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bm  (1<<4)  
-/* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL4_bp  4  
-/* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bm  (1<<5)  
-/* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL5_bp  5  
-/* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bm  (1<<6)  
-/* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL6_bp  6  
-/* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bm  (1<<7)  
-/* Baud Rate Selection Bits [7:0] bit 7 position. */
-#define USART_BSEL7_bp  7
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01 
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04 
-#define PIN2_bp 2
-#define PIN3_bm 0x08 
-#define PIN3_bp 3
-#define PIN4_bm 0x10 
-#define PIN4_bp 4
-#define PIN5_bm 0x20 
-#define PIN5_bp 5
-#define PIN6_bm 0x40 
-#define PIN6_bp 6
-#define PIN7_bm 0x80 
-#define PIN7_bp 7
-/** @} */
-
-/**
- * @name Interrupt Vector Definitions
- * 
- */
-/**@{**/
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-/* External Oscillator Failure Interrupt (NMI) */
-#define OSC_XOSCF_vect      _VECTOR(1)
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-/* Transmission Complete Interrupt */
-#define USARTC0_TXC_vect      _VECTOR(27)
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
- /* Transmission Complete Interrupt */
-#define USARTC1_TXC_vect      _VECTOR(30)
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-/* Transmission Complete Interrupt */
-#define USARTE0_TXC_vect      _VECTOR(60)
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-/* Transmission Complete Interrupt */
-#define USARTE1_TXC_vect      _VECTOR(63)
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TWID interrupt vectors */
-#define TWID_TWIS_vect_num  75
-#define TWID_TWIS_vect      _VECTOR(75)  /* TWI Slave Interrupt */
-#define TWID_TWIM_vect_num  76
-#define TWID_TWIM_vect      _VECTOR(76)  /* TWI Master Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-/* Transmission Complete Interrupt */
-#define USARTD0_TXC_vect      _VECTOR(90)
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-/* Transmission Complete Interrupt */
-#define USARTD1_TXC_vect      _VECTOR(93)
-
-/* PORTQ interrupt vectors */
-#define PORTQ_INT0_vect_num  94
-#define PORTQ_INT0_vect      _VECTOR(94)  /* External Interrupt 0 */
-#define PORTQ_INT1_vect_num  95
-#define PORTQ_INT1_vect      _VECTOR(95)  /* External Interrupt 1 */
-
-/* PORTH interrupt vectors */
-#define PORTH_INT0_vect_num  96
-#define PORTH_INT0_vect      _VECTOR(96)  /* External Interrupt 0 */
-#define PORTH_INT1_vect_num  97
-#define PORTH_INT1_vect      _VECTOR(97)  /* External Interrupt 1 */
-
-/* PORTJ interrupt vectors */
-#define PORTJ_INT0_vect_num  98
-#define PORTJ_INT0_vect      _VECTOR(98)  /* External Interrupt 0 */
-#define PORTJ_INT1_vect_num  99
-#define PORTJ_INT1_vect      _VECTOR(99)  /* External Interrupt 1 */
-
-/* PORTK interrupt vectors */
-#define PORTK_INT0_vect_num  100
-#define PORTK_INT0_vect      _VECTOR(100)  /* External Interrupt 0 */
-#define PORTK_INT1_vect_num  101
-#define PORTK_INT1_vect      _VECTOR(101)  /* External Interrupt 1 */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TWIF interrupt vectors */
-#define TWIF_TWIS_vect_num  106
-#define TWIF_TWIS_vect      _VECTOR(106)  /* TWI Slave Interrupt */
-#define TWIF_TWIM_vect_num  107
-#define TWIF_TWIM_vect      _VECTOR(107)  /* TWI Master Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* TCF1 interrupt vectors */
-#define TCF1_OVF_vect_num  114
-#define TCF1_OVF_vect      _VECTOR(114)  /* Overflow Interrupt */
-#define TCF1_ERR_vect_num  115
-#define TCF1_ERR_vect      _VECTOR(115)  /* Error Interrupt */
-#define TCF1_CCA_vect_num  116
-#define TCF1_CCA_vect      _VECTOR(116)  /* Compare or Capture A Interrupt */
-#define TCF1_CCB_vect_num  117
-#define TCF1_CCB_vect      _VECTOR(117)  /* Compare or Capture B Interrupt */
-
-/* SPIF interrupt vectors */
-#define SPIF_INT_vect_num  118
-#define SPIF_INT_vect      _VECTOR(118)  /* SPI Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-/* Data Register Empty Interrupt */
-#define USARTF0_DRE_vect      _VECTOR(120)  
-#define USARTF0_TXC_vect_num  121
-/* Transmission Complete Interrupt */
-#define USARTF0_TXC_vect      _VECTOR(121)
-
-/* USARTF1 interrupt vectors */
-#define USARTF1_RXC_vect_num  122
-#define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
-#define USARTF1_DRE_vect_num  123
-/* Data Register Empty Interrupt */
-#define USARTF1_DRE_vect      _VECTOR(123)
-#define USARTF1_TXC_vect_num  124
-/* Transmission Complete Interrupt */
-#define USARTF1_TXC_vect      _VECTOR(124) 
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (125 * _VECTOR_SIZE)
-/** @} */
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (139264)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (131072)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x1E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + \
-                                    APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x20000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16777216)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (8192)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EXTERNAL_SRAM_START     (0x4000)
-#define EXTERNAL_SRAM_SIZE      (16760832)
-#define EXTERNAL_SRAM_PAGE_SIZE (0)
-#define EXTERNAL_SRAM_END       (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + \
-                                   USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + \
-                                   PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      EXTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-/** @} */
-
-/**
- * @name Fuses
- * 
- */
-/**@{**/
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-/* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)
-/* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)
-/* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)
-/* Watchdog Window Timeout Period Bit 3 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-/* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)
-/* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)
-/* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT0  (unsigned char)~_BV(2)
-/* BOD Operation in Active Mode Bit 1 */
-#define FUSE_BODACT1  (unsigned char)~_BV(3)
-/* Boot Loader Section Reset Vector */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-/* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)
-/* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)
-/* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)
-/* Preserve EEPROM Through Chip Erase */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)
-#define FUSE5_DEFAULT  (0xFF)
-/** @} */
-
-/**
- * @name Lock Bits
- * 
- */
-/**@{**/
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-/** @} */
-
-/**
- * @name Signature
- * 
- */
-/**@{**/
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x4C
-/** @} */
-
-#endif /* _AVR_ATxmega128A1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox128a3.h b/cpukit/score/cpu/avr/avr/iox128a3.h
deleted file mode 100644
index e5edf62944..0000000000
--- a/cpukit/score/cpu/avr/avr/iox128a3.h
+++ /dev/null
@@ -1,6900 +0,0 @@
-/**
- * @file avr/iox128a3.h
- *
- * @brief Definitions for ATxmega128A3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128a3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega128A3_H_
-#define _AVR_ATxmega128A3_H_ 1
-
-/**
- *  @defgroup Avr_iox128a3 ATxmega128A3 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (139264)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (131072)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x1E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x20000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16384)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (8192)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x42
-
-
-/**@}*/
-#endif /* _AVR_ATxmega128A3_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox128d3.h b/cpukit/score/cpu/avr/avr/iox128d3.h
deleted file mode 100644
index d020bfa25f..0000000000
--- a/cpukit/score/cpu/avr/avr/iox128d3.h
+++ /dev/null
@@ -1,5645 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox128d3.h - definitions for ATxmega128D3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox128d3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATxmega128D3_H_
-#define _AVR_ATxmega128D3_H_ 1
-
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-    register8_t CTRL;  /* Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0487)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_CTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01 
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04 
-#define PIN2_bp 2
-#define PIN3_bm 0x08 
-#define PIN3_bp 3
-#define PIN4_bm 0x10 
-#define PIN4_bp 4
-#define PIN5_bm 0x20 
-#define PIN5_bp 5
-#define PIN6_bm 0x40 
-#define PIN6_bp 6
-#define PIN7_bm 0x80 
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (139264)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (131072)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x1E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x20000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16384)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (8192)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x48
-
-
-#endif /* _AVR_ATxmega128D3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox16a4.h b/cpukit/score/cpu/avr/avr/iox16a4.h
deleted file mode 100644
index cff1d53360..0000000000
--- a/cpukit/score/cpu/avr/avr/iox16a4.h
+++ /dev/null
@@ -1,6655 +0,0 @@
-/**
- * @file avr/iox16a4.h
- *
- * @brief Definitions for ATxmega16A4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox16a4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- *  @defgroup Avr_iox16a4 ATxmega16A4 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_ATxmega16A4_H_
-#define _AVR_ATxmega16A4_H_ 1
-
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (94 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (20480)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (16384)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x3000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x4000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (10240)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (1024)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (2048)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (1024)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x41
-
-
-/**@}*/
-#endif /* _AVR_ATxmega16A4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox16d4.h b/cpukit/score/cpu/avr/avr/iox16d4.h
deleted file mode 100644
index 0bb088759c..0000000000
--- a/cpukit/score/cpu/avr/avr/iox16d4.h
+++ /dev/null
@@ -1,5552 +0,0 @@
-/**
- * @file avr/iox16d4.h
- *
- * @brief Definitions for ATxmega16D4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox16d4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega16D4_H_
-#define _AVR_ATxmega16D4_H_ 1
-
-/**
- *  @defgroup Avr_iox16d4 ATxmega16D4 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (20480)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (16384)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x3000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x4000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (10240)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (1024)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (2048)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (1024)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x42
-
-
-/**@}*/
-#endif /* _AVR_ATxmega16D4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox192a3.h b/cpukit/score/cpu/avr/avr/iox192a3.h
deleted file mode 100644
index e0f7c26ab2..0000000000
--- a/cpukit/score/cpu/avr/avr/iox192a3.h
+++ /dev/null
@@ -1,6900 +0,0 @@
-/**
- * @file avr/iox192a3.h
- *
- * @brief Definitions for ATxmega192A3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox192a3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega192A3_H_
-#define _AVR_ATxmega192A3_H_ 1
-
-/**
- *  @defgroup Avr_iox192a3 ATxmega192A3 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (204800)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (196608)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x2E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x30000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16777216)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (4096)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (16384)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (4096)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x44
-
-
-/**@}*/
-#endif /* _AVR_ATxmega192A3_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox192d3.h b/cpukit/score/cpu/avr/avr/iox192d3.h
deleted file mode 100644
index e29356e3cf..0000000000
--- a/cpukit/score/cpu/avr/avr/iox192d3.h
+++ /dev/null
@@ -1,5655 +0,0 @@
-/**
- * @file avr/iox192d3.h
- *
- * @brief Definitions for ATxmega192D3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox192d3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega192D3_H_
-#define _AVR_ATxmega192D3_H_ 1
-
-/**
- *  @defgroup Avr_iox192d3 ATxmega192D3 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-   __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.9 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.1 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.4 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.6 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.9 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 3.2 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0487)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (204800)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (196608)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x2E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x30000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (24576)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (16384)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x49
-
-/**@}*/
-#endif /* _AVR_ATxmega192D3_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox256a3.h b/cpukit/score/cpu/avr/avr/iox256a3.h
deleted file mode 100644
index 7d7aca4890..0000000000
--- a/cpukit/score/cpu/avr/avr/iox256a3.h
+++ /dev/null
@@ -1,6889 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox256a3.h - definitions for ATxmega256A3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox256a3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATxmega256A3_H_
-#define _AVR_ATxmega256A3_H_ 1
-
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-  __extension__  union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__   union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01 
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04 
-#define PIN2_bp 2
-#define PIN3_bm 0x08 
-#define PIN3_bp 3
-#define PIN4_bm 0x10 
-#define PIN4_bp 4
-#define PIN5_bm 0x20 
-#define PIN5_bp 5
-#define PIN6_bm 0x40 
-#define PIN6_bp 6
-#define PIN7_bm 0x80 
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (270336)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (262144)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x3E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x40000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (24576)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (4096)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (16384)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (4096)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x98
-#define SIGNATURE_2 0x42
-
-
-#endif /* _AVR_ATxmega256A3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox256a3b.h b/cpukit/score/cpu/avr/avr/iox256a3b.h
deleted file mode 100644
index deee492cca..0000000000
--- a/cpukit/score/cpu/avr/avr/iox256a3b.h
+++ /dev/null
@@ -1,6902 +0,0 @@
-/**
- * @file avr/iox256a3b.h
- *
- * @brief Definitions for ATxmega256A3B
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox256a3b.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega256A3B_H_
-#define _AVR_ATxmega256A3B_H_ 1
-
-/**
- *  @defgroup Avr_iox256a3b ATxmega256A3B Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-   __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC32 - 32-bit Real-Time Counter
---------------------------------------------------------------------------
-*/
-
-/* 32-bit Real-Time Clounter */
-typedef struct RTC32_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t SYNCCTRL;  /* Synchronization Control/Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-} RTC32_t;
-
-/* Compare Interrupt level */
-typedef enum RTC32_COMPINTLVL_enum
-{
-    RTC32_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC32_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC32_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC32_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC32_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC32_OVFINTLVL_enum
-{
-    RTC32_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC32_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC32_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC32_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC32_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-VBAT - VBAT Battery Backup Module
---------------------------------------------------------------------------
-*/
-
-/* VBAT Battery Backup Module */
-typedef struct VBAT_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t BACKUP0;  /* Battery Bacup Register 0 */
-    register8_t BACKUP1;  /* Battery Backup Register 1 */
-} VBAT_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define VBAT    (*(VBAT_t *) 0x00F0)  /* VBAT Battery Backup Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC32    (*(RTC32_t *) 0x0420)  /* 32-bit Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* VBAT - VBAT Battery Backup Module */
-#define VBAT_CTRL  _SFR_MEM8(0x00F0)
-#define VBAT_STATUS  _SFR_MEM8(0x00F1)
-#define VBAT_BACKUP0  _SFR_MEM8(0x00F2)
-#define VBAT_BACKUP1  _SFR_MEM8(0x00F3)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC32 - 32-bit Real-Time Counter */
-#define RTC32_CTRL  _SFR_MEM8(0x0420)
-#define RTC32_SYNCCTRL  _SFR_MEM8(0x0421)
-#define RTC32_INTCTRL  _SFR_MEM8(0x0422)
-#define RTC32_INTFLAGS  _SFR_MEM8(0x0423)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC32 - 32-bit Real-Time Counter */
-/* RTC32.CTRL  bit masks and bit positions */
-#define RTC32_ENABLE_bm  0x01  /* RTC enable bit mask. */
-#define RTC32_ENABLE_bp  0  /* RTC enable bit position. */
-
-
-/* RTC32.SYNCCTRL  bit masks and bit positions */
-#define RTC32_SYNCCNT_bm  0x10  /* Synchronization Busy Flag bit mask. */
-#define RTC32_SYNCCNT_bp  4  /* Synchronization Busy Flag bit position. */
-
-#define RTC32_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC32_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC32.INTCTRL  bit masks and bit positions */
-#define RTC32_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC32_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC32_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC32_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC32_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC32_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC32_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC32_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC32_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC32_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC32_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC32_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC32.INTFLAGS  bit masks and bit positions */
-#define RTC32_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC32_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC32_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC32_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* VBAT - VBAT Battery Backup Module */
-/* VBAT.CTRL  bit masks and bit positions */
-#define VBAT_XOSCSEL_bm  0x10  /* 32-kHz Crystal Oscillator Output Selection bit mask. */
-#define VBAT_XOSCSEL_bp  4  /* 32-kHz Crystal Oscillator Output Selection bit position. */
-
-#define VBAT_XOSCEN_bm  0x08  /* Crystal Oscillator Enable bit mask. */
-#define VBAT_XOSCEN_bp  3  /* Crystal Oscillator Enable bit position. */
-
-#define VBAT_XOSCFDEN_bm  0x04  /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */
-#define VBAT_XOSCFDEN_bp  2  /* Crystal Oscillator Failure Detection Monitor Enable bit position. */
-
-#define VBAT_ACCEN_bm  0x02  /* Battery Backup Access Enable bit mask. */
-#define VBAT_ACCEN_bp  1  /* Battery Backup Access Enable bit position. */
-
-#define VBAT_RESET_bm  0x01  /* Battery Backup Reset bit mask. */
-#define VBAT_RESET_bp  0  /* Battery Backup Reset bit position. */
-
-
-/* VBAT.STATUS  bit masks and bit positions */
-#define VBAT_BBPWR_bm  0x80  /* Battery backup Power bit mask. */
-#define VBAT_BBPWR_bp  7  /* Battery backup Power bit position. */
-
-#define VBAT_XOSCRDY_bm  0x08  /* Crystal Oscillator Ready bit mask. */
-#define VBAT_XOSCRDY_bp  3  /* Crystal Oscillator Ready bit position. */
-
-#define VBAT_XOSCFAIL_bm  0x04  /* Crystal Oscillator Failure bit mask. */
-#define VBAT_XOSCFAIL_bp  2  /* Crystal Oscillator Failure bit position. */
-
-#define VBAT_BBBORF_bm  0x02  /* Battery Backup Brown-Out Reset Flag bit mask. */
-#define VBAT_BBBORF_bp  1  /* Battery Backup Brown-Out Reset Flag bit position. */
-
-#define VBAT_BBPORF_bm  0x01  /* Battery Backup Power-On Reset Flag bit mask. */
-#define VBAT_BBPORF_bp  0  /* Battery Backup Power-On Reset Flag bit position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC32 interrupt vectors */
-#define RTC32_OVF_vect_num  10
-#define RTC32_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC32_COMP_vect_num  11
-#define RTC32_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (270336)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (262144)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x3E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x40000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (24576)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (4096)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (16384)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (4096)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x98
-#define SIGNATURE_2 0x43
-
-
-/**@}*/
-#endif /* _AVR_ATxmega256A3B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox256d3.h b/cpukit/score/cpu/avr/avr/iox256d3.h
deleted file mode 100644
index a49879811d..0000000000
--- a/cpukit/score/cpu/avr/avr/iox256d3.h
+++ /dev/null
@@ -1,5468 +0,0 @@
-/**
- * @file avr/iox256d3.h
- *
- * @brief Definitions for ATxmega256D3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox256d3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega256D3_H_
-#define _AVR_ATxmega256D3_H_ 1
-
-/**
- * @defgroup AvrDef_iox256d3 ATxmega256D3 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-    __extension__ union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.9 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.1 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.4 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.6 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.9 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 3.2 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t reserved_0x05;
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* ACD Temporary Register */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_TEMP  _SFR_MEM8(0x0207)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
-#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
-
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
-#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
-#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_bm  0x01  /* Event Action Select bit mask. */
-#define ADC_EVACT_bp  0  /* Event Action Select bit position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (270336)
-#define PROGMEM_PAGE_SIZE (512)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (262144)
-#define APP_SECTION_PAGE_SIZE (512)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x3E000)
-#define APPTABLE_SECTION_SIZE      (8192)
-#define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x40000)
-#define BOOT_SECTION_SIZE      (8192)
-#define BOOT_SECTION_PAGE_SIZE (512)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (24576)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (4096)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (16384)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (4096)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (512)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x98
-#define SIGNATURE_2 0x44
-
-
-/** @} */
-#endif /* _AVR_ATxmega256D3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox32a4.h b/cpukit/score/cpu/avr/avr/iox32a4.h
deleted file mode 100644
index f0eba4ecc0..0000000000
--- a/cpukit/score/cpu/avr/avr/iox32a4.h
+++ /dev/null
@@ -1,6655 +0,0 @@
-/**
- * @file avr/iox32a4.h
- *
- * @brief Definitions for ATxmega32A4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2009 Atmel Corporation
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox32a4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega32A4_H_
-#define _AVR_ATxmega32A4_H_ 1
-
-/**
- *  @defgroup Avr_iox32a4 ATxmega32A4 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (94 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (36864)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (32768)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x07000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x8000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (12288)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (1024)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (4096)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (1024)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x41
-
-
-/**@}*/
-#endif /* _AVR_ATxmega32A4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox32d4.h b/cpukit/score/cpu/avr/avr/iox32d4.h
deleted file mode 100644
index 248e32cadf..0000000000
--- a/cpukit/score/cpu/avr/avr/iox32d4.h
+++ /dev/null
@@ -1,5560 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATxmega32D4
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox32d4.h - definitions for ATxmega32D4 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox32d4.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_ATxmega32D4_H_
-#define _AVR_ATxmega32D4_H_ 1
-
-/**
- * @defgroup AvrDef_iox32d4 ATxmega32D4 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* DACB - Digital to Analog Converter B */
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01 
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04 
-#define PIN2_bp 2
-#define PIN3_bm 0x08 
-#define PIN3_bp 3
-#define PIN4_bm 0x10 
-#define PIN4_bp 4
-#define PIN5_bm 0x20 
-#define PIN5_bp 5
-#define PIN6_bm 0x40 
-#define PIN6_bp 6
-#define PIN7_bm 0x80 
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (36864)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (32768)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x7000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x8000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (12288)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (1024)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (4096)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (1024)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x42
-
-/** @} */
-
-#endif /* _AVR_ATxmega32D4_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox64a1.h b/cpukit/score/cpu/avr/avr/iox64a1.h
deleted file mode 100644
index 73acf1afdc..0000000000
--- a/cpukit/score/cpu/avr/avr/iox64a1.h
+++ /dev/null
@@ -1,7150 +0,0 @@
-/**
- * @file avr/iox64a1.h
- *
- * @brief Definitions for ATxmega64A1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox64a1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega64A1_H_
-#define _AVR_ATxmega64A1_H_ 1
-
-/**
- *  @defgroup Avr_iox64a1 ATxmega64A1 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<2),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<2),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<2),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator  */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACA    (*(DAC_t *) 0x0300)  /* Digitalto Analog Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define EBI    (*(EBI_t *) 0x0440)  /* External Bus Interface */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWID    (*(TWI_t *) 0x0490)  /* Two-Wire Interface D */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define TWIF    (*(TWI_t *) 0x04B0)  /* Two-Wire Interface F */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTH    (*(PORT_t *) 0x06E0)  /* Port H */
-#define PORTJ    (*(PORT_t *) 0x0700)  /* Port J */
-#define PORTK    (*(PORT_t *) 0x0720)  /* Port K */
-#define PORTQ    (*(PORT_t *) 0x07C0)  /* Port Q */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define TCF1    (*(TC1_t *) 0x0B40)  /* Timer/Counter F1 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator  */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACA - Digitalto Analog Converter A */
-#define DACA_CTRLA  _SFR_MEM8(0x0300)
-#define DACA_CTRLB  _SFR_MEM8(0x0301)
-#define DACA_CTRLC  _SFR_MEM8(0x0302)
-#define DACA_EVCTRL  _SFR_MEM8(0x0303)
-#define DACA_TIMCTRL  _SFR_MEM8(0x0304)
-#define DACA_STATUS  _SFR_MEM8(0x0305)
-#define DACA_GAINCAL  _SFR_MEM8(0x0308)
-#define DACA_OFFSETCAL  _SFR_MEM8(0x0309)
-#define DACA_CH0DATA  _SFR_MEM16(0x0318)
-#define DACA_CH1DATA  _SFR_MEM16(0x031A)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* EBI - External Bus Interface */
-#define EBI_CTRL  _SFR_MEM8(0x0440)
-#define EBI_SDRAMCTRLA  _SFR_MEM8(0x0441)
-#define EBI_REFRESH  _SFR_MEM16(0x0444)
-#define EBI_INITDLY  _SFR_MEM16(0x0446)
-#define EBI_SDRAMCTRLB  _SFR_MEM8(0x0448)
-#define EBI_SDRAMCTRLC  _SFR_MEM8(0x0449)
-#define EBI_CS0_CTRLA  _SFR_MEM8(0x0450)
-#define EBI_CS0_CTRLB  _SFR_MEM8(0x0451)
-#define EBI_CS0_BASEADDR  _SFR_MEM16(0x0452)
-#define EBI_CS1_CTRLA  _SFR_MEM8(0x0454)
-#define EBI_CS1_CTRLB  _SFR_MEM8(0x0455)
-#define EBI_CS1_BASEADDR  _SFR_MEM16(0x0456)
-#define EBI_CS2_CTRLA  _SFR_MEM8(0x0458)
-#define EBI_CS2_CTRLB  _SFR_MEM8(0x0459)
-#define EBI_CS2_BASEADDR  _SFR_MEM16(0x045A)
-#define EBI_CS3_CTRLA  _SFR_MEM8(0x045C)
-#define EBI_CS3_CTRLB  _SFR_MEM8(0x045D)
-#define EBI_CS3_BASEADDR  _SFR_MEM16(0x045E)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWID - Two-Wire Interface D */
-#define TWID_CTRL  _SFR_MEM8(0x0490)
-#define TWID_MASTER_CTRLA  _SFR_MEM8(0x0491)
-#define TWID_MASTER_CTRLB  _SFR_MEM8(0x0492)
-#define TWID_MASTER_CTRLC  _SFR_MEM8(0x0493)
-#define TWID_MASTER_STATUS  _SFR_MEM8(0x0494)
-#define TWID_MASTER_BAUD  _SFR_MEM8(0x0495)
-#define TWID_MASTER_ADDR  _SFR_MEM8(0x0496)
-#define TWID_MASTER_DATA  _SFR_MEM8(0x0497)
-#define TWID_SLAVE_CTRLA  _SFR_MEM8(0x0498)
-#define TWID_SLAVE_CTRLB  _SFR_MEM8(0x0499)
-#define TWID_SLAVE_STATUS  _SFR_MEM8(0x049A)
-#define TWID_SLAVE_ADDR  _SFR_MEM8(0x049B)
-#define TWID_SLAVE_DATA  _SFR_MEM8(0x049C)
-#define TWID_SLAVE_ADDRMASK  _SFR_MEM8(0x049D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* TWIF - Two-Wire Interface F */
-#define TWIF_CTRL  _SFR_MEM8(0x04B0)
-#define TWIF_MASTER_CTRLA  _SFR_MEM8(0x04B1)
-#define TWIF_MASTER_CTRLB  _SFR_MEM8(0x04B2)
-#define TWIF_MASTER_CTRLC  _SFR_MEM8(0x04B3)
-#define TWIF_MASTER_STATUS  _SFR_MEM8(0x04B4)
-#define TWIF_MASTER_BAUD  _SFR_MEM8(0x04B5)
-#define TWIF_MASTER_ADDR  _SFR_MEM8(0x04B6)
-#define TWIF_MASTER_DATA  _SFR_MEM8(0x04B7)
-#define TWIF_SLAVE_CTRLA  _SFR_MEM8(0x04B8)
-#define TWIF_SLAVE_CTRLB  _SFR_MEM8(0x04B9)
-#define TWIF_SLAVE_STATUS  _SFR_MEM8(0x04BA)
-#define TWIF_SLAVE_ADDR  _SFR_MEM8(0x04BB)
-#define TWIF_SLAVE_DATA  _SFR_MEM8(0x04BC)
-#define TWIF_SLAVE_ADDRMASK  _SFR_MEM8(0x04BD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTH - Port H */
-#define PORTH_DIR  _SFR_MEM8(0x06E0)
-#define PORTH_DIRSET  _SFR_MEM8(0x06E1)
-#define PORTH_DIRCLR  _SFR_MEM8(0x06E2)
-#define PORTH_DIRTGL  _SFR_MEM8(0x06E3)
-#define PORTH_OUT  _SFR_MEM8(0x06E4)
-#define PORTH_OUTSET  _SFR_MEM8(0x06E5)
-#define PORTH_OUTCLR  _SFR_MEM8(0x06E6)
-#define PORTH_OUTTGL  _SFR_MEM8(0x06E7)
-#define PORTH_IN  _SFR_MEM8(0x06E8)
-#define PORTH_INTCTRL  _SFR_MEM8(0x06E9)
-#define PORTH_INT0MASK  _SFR_MEM8(0x06EA)
-#define PORTH_INT1MASK  _SFR_MEM8(0x06EB)
-#define PORTH_INTFLAGS  _SFR_MEM8(0x06EC)
-#define PORTH_PIN0CTRL  _SFR_MEM8(0x06F0)
-#define PORTH_PIN1CTRL  _SFR_MEM8(0x06F1)
-#define PORTH_PIN2CTRL  _SFR_MEM8(0x06F2)
-#define PORTH_PIN3CTRL  _SFR_MEM8(0x06F3)
-#define PORTH_PIN4CTRL  _SFR_MEM8(0x06F4)
-#define PORTH_PIN5CTRL  _SFR_MEM8(0x06F5)
-#define PORTH_PIN6CTRL  _SFR_MEM8(0x06F6)
-#define PORTH_PIN7CTRL  _SFR_MEM8(0x06F7)
-
-/* PORTJ - Port J */
-#define PORTJ_DIR  _SFR_MEM8(0x0700)
-#define PORTJ_DIRSET  _SFR_MEM8(0x0701)
-#define PORTJ_DIRCLR  _SFR_MEM8(0x0702)
-#define PORTJ_DIRTGL  _SFR_MEM8(0x0703)
-#define PORTJ_OUT  _SFR_MEM8(0x0704)
-#define PORTJ_OUTSET  _SFR_MEM8(0x0705)
-#define PORTJ_OUTCLR  _SFR_MEM8(0x0706)
-#define PORTJ_OUTTGL  _SFR_MEM8(0x0707)
-#define PORTJ_IN  _SFR_MEM8(0x0708)
-#define PORTJ_INTCTRL  _SFR_MEM8(0x0709)
-#define PORTJ_INT0MASK  _SFR_MEM8(0x070A)
-#define PORTJ_INT1MASK  _SFR_MEM8(0x070B)
-#define PORTJ_INTFLAGS  _SFR_MEM8(0x070C)
-#define PORTJ_PIN0CTRL  _SFR_MEM8(0x0710)
-#define PORTJ_PIN1CTRL  _SFR_MEM8(0x0711)
-#define PORTJ_PIN2CTRL  _SFR_MEM8(0x0712)
-#define PORTJ_PIN3CTRL  _SFR_MEM8(0x0713)
-#define PORTJ_PIN4CTRL  _SFR_MEM8(0x0714)
-#define PORTJ_PIN5CTRL  _SFR_MEM8(0x0715)
-#define PORTJ_PIN6CTRL  _SFR_MEM8(0x0716)
-#define PORTJ_PIN7CTRL  _SFR_MEM8(0x0717)
-
-/* PORTK - Port K */
-#define PORTK_DIR  _SFR_MEM8(0x0720)
-#define PORTK_DIRSET  _SFR_MEM8(0x0721)
-#define PORTK_DIRCLR  _SFR_MEM8(0x0722)
-#define PORTK_DIRTGL  _SFR_MEM8(0x0723)
-#define PORTK_OUT  _SFR_MEM8(0x0724)
-#define PORTK_OUTSET  _SFR_MEM8(0x0725)
-#define PORTK_OUTCLR  _SFR_MEM8(0x0726)
-#define PORTK_OUTTGL  _SFR_MEM8(0x0727)
-#define PORTK_IN  _SFR_MEM8(0x0728)
-#define PORTK_INTCTRL  _SFR_MEM8(0x0729)
-#define PORTK_INT0MASK  _SFR_MEM8(0x072A)
-#define PORTK_INT1MASK  _SFR_MEM8(0x072B)
-#define PORTK_INTFLAGS  _SFR_MEM8(0x072C)
-#define PORTK_PIN0CTRL  _SFR_MEM8(0x0730)
-#define PORTK_PIN1CTRL  _SFR_MEM8(0x0731)
-#define PORTK_PIN2CTRL  _SFR_MEM8(0x0732)
-#define PORTK_PIN3CTRL  _SFR_MEM8(0x0733)
-#define PORTK_PIN4CTRL  _SFR_MEM8(0x0734)
-#define PORTK_PIN5CTRL  _SFR_MEM8(0x0735)
-#define PORTK_PIN6CTRL  _SFR_MEM8(0x0736)
-#define PORTK_PIN7CTRL  _SFR_MEM8(0x0737)
-
-/* PORTQ - Port Q */
-#define PORTQ_DIR  _SFR_MEM8(0x07C0)
-#define PORTQ_DIRSET  _SFR_MEM8(0x07C1)
-#define PORTQ_DIRCLR  _SFR_MEM8(0x07C2)
-#define PORTQ_DIRTGL  _SFR_MEM8(0x07C3)
-#define PORTQ_OUT  _SFR_MEM8(0x07C4)
-#define PORTQ_OUTSET  _SFR_MEM8(0x07C5)
-#define PORTQ_OUTCLR  _SFR_MEM8(0x07C6)
-#define PORTQ_OUTTGL  _SFR_MEM8(0x07C7)
-#define PORTQ_IN  _SFR_MEM8(0x07C8)
-#define PORTQ_INTCTRL  _SFR_MEM8(0x07C9)
-#define PORTQ_INT0MASK  _SFR_MEM8(0x07CA)
-#define PORTQ_INT1MASK  _SFR_MEM8(0x07CB)
-#define PORTQ_INTFLAGS  _SFR_MEM8(0x07CC)
-#define PORTQ_PIN0CTRL  _SFR_MEM8(0x07D0)
-#define PORTQ_PIN1CTRL  _SFR_MEM8(0x07D1)
-#define PORTQ_PIN2CTRL  _SFR_MEM8(0x07D2)
-#define PORTQ_PIN3CTRL  _SFR_MEM8(0x07D3)
-#define PORTQ_PIN4CTRL  _SFR_MEM8(0x07D4)
-#define PORTQ_PIN5CTRL  _SFR_MEM8(0x07D5)
-#define PORTQ_PIN6CTRL  _SFR_MEM8(0x07D6)
-#define PORTQ_PIN7CTRL  _SFR_MEM8(0x07D7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* TCF1 - Timer/Counter F1 */
-#define TCF1_CTRLA  _SFR_MEM8(0x0B40)
-#define TCF1_CTRLB  _SFR_MEM8(0x0B41)
-#define TCF1_CTRLC  _SFR_MEM8(0x0B42)
-#define TCF1_CTRLD  _SFR_MEM8(0x0B43)
-#define TCF1_CTRLE  _SFR_MEM8(0x0B44)
-#define TCF1_INTCTRLA  _SFR_MEM8(0x0B46)
-#define TCF1_INTCTRLB  _SFR_MEM8(0x0B47)
-#define TCF1_CTRLFCLR  _SFR_MEM8(0x0B48)
-#define TCF1_CTRLFSET  _SFR_MEM8(0x0B49)
-#define TCF1_CTRLGCLR  _SFR_MEM8(0x0B4A)
-#define TCF1_CTRLGSET  _SFR_MEM8(0x0B4B)
-#define TCF1_INTFLAGS  _SFR_MEM8(0x0B4C)
-#define TCF1_TEMP  _SFR_MEM8(0x0B4F)
-#define TCF1_CNT  _SFR_MEM16(0x0B60)
-#define TCF1_PER  _SFR_MEM16(0x0B66)
-#define TCF1_CCA  _SFR_MEM16(0x0B68)
-#define TCF1_CCB  _SFR_MEM16(0x0B6A)
-#define TCF1_PERBUF  _SFR_MEM16(0x0B76)
-#define TCF1_CCABUF  _SFR_MEM16(0x0B78)
-#define TCF1_CCBBUF  _SFR_MEM16(0x0B7A)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODACT_gm  0x0C  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  2  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<2)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  2  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<3)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  3  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TWID interrupt vectors */
-#define TWID_TWIS_vect_num  75
-#define TWID_TWIS_vect      _VECTOR(75)  /* TWI Slave Interrupt */
-#define TWID_TWIM_vect_num  76
-#define TWID_TWIM_vect      _VECTOR(76)  /* TWI Master Interrupt */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTQ interrupt vectors */
-#define PORTQ_INT0_vect_num  94
-#define PORTQ_INT0_vect      _VECTOR(94)  /* External Interrupt 0 */
-#define PORTQ_INT1_vect_num  95
-#define PORTQ_INT1_vect      _VECTOR(95)  /* External Interrupt 1 */
-
-/* PORTH interrupt vectors */
-#define PORTH_INT0_vect_num  96
-#define PORTH_INT0_vect      _VECTOR(96)  /* External Interrupt 0 */
-#define PORTH_INT1_vect_num  97
-#define PORTH_INT1_vect      _VECTOR(97)  /* External Interrupt 1 */
-
-/* PORTJ interrupt vectors */
-#define PORTJ_INT0_vect_num  98
-#define PORTJ_INT0_vect      _VECTOR(98)  /* External Interrupt 0 */
-#define PORTJ_INT1_vect_num  99
-#define PORTJ_INT1_vect      _VECTOR(99)  /* External Interrupt 1 */
-
-/* PORTK interrupt vectors */
-#define PORTK_INT0_vect_num  100
-#define PORTK_INT0_vect      _VECTOR(100)  /* External Interrupt 0 */
-#define PORTK_INT1_vect_num  101
-#define PORTK_INT1_vect      _VECTOR(101)  /* External Interrupt 1 */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TWIF interrupt vectors */
-#define TWIF_TWIS_vect_num  106
-#define TWIF_TWIS_vect      _VECTOR(106)  /* TWI Slave Interrupt */
-#define TWIF_TWIM_vect_num  107
-#define TWIF_TWIM_vect      _VECTOR(107)  /* TWI Master Interrupt */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* TCF1 interrupt vectors */
-#define TCF1_OVF_vect_num  114
-#define TCF1_OVF_vect      _VECTOR(114)  /* Overflow Interrupt */
-#define TCF1_ERR_vect_num  115
-#define TCF1_ERR_vect      _VECTOR(115)  /* Error Interrupt */
-#define TCF1_CCA_vect_num  116
-#define TCF1_CCA_vect      _VECTOR(116)  /* Compare or Capture A Interrupt */
-#define TCF1_CCB_vect_num  117
-#define TCF1_CCB_vect      _VECTOR(117)  /* Compare or Capture B Interrupt */
-
-/* SPIF interrupt vectors */
-#define SPIF_INT_vect_num  118
-#define SPIF_INT_vect      _VECTOR(118)  /* SPI Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-/* USARTF1 interrupt vectors */
-#define USARTF1_RXC_vect_num  122
-#define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
-#define USARTF1_DRE_vect_num  123
-#define USARTF1_DRE_vect      _VECTOR(123)  /* Data Register Empty Interrupt */
-#define USARTF1_TXC_vect_num  124
-#define USARTF1_TXC_vect      _VECTOR(124)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (125 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (69632)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (65536)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x0F000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x10000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (16777216)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (4096)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EXTERNAL_SRAM_START     (0x3000)
-#define EXTERNAL_SRAM_SIZE      (16764928)
-#define EXTERNAL_SRAM_PAGE_SIZE (0)
-#define EXTERNAL_SRAM_END       (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      EXTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BODACT0  (unsigned char)~_BV(2)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(3)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x4E
-
-
-/**@}*/
-#endif /* _AVR_ATxmega64A1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox64a3.h b/cpukit/score/cpu/avr/avr/iox64a3.h
deleted file mode 100644
index a3a73a44e9..0000000000
--- a/cpukit/score/cpu/avr/avr/iox64a3.h
+++ /dev/null
@@ -1,6899 +0,0 @@
-/**
- * @file avr/iox64a3.h
- *
- * @brief Definitions for ATxmega64A3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox64a3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega64A3_H_
-#define _AVR_ATxmega64A3_H_ 1
-
-/**
- *  @defgroup Avr_iox64a3 ATxmega64A3 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-   __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
-    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
-    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Channel */
-typedef struct DMA_CH_struct
-{
-    register8_t CTRLA;  /* Channel Control */
-    register8_t CTRLB;  /* Channel Control */
-    register8_t ADDRCTRL;  /* Address Control */
-    register8_t TRIGSRC;  /* Channel Trigger Source */
-    _WORDREGISTER(TRFCNT);  /* Channel Block Transfer Count */
-    register8_t REPCNT;  /* Channel Repeat Count */
-    register8_t reserved_0x07;
-    register8_t SRCADDR0;  /* Channel Source Address 0 */
-    register8_t SRCADDR1;  /* Channel Source Address 1 */
-    register8_t SRCADDR2;  /* Channel Source Address 2 */
-    register8_t reserved_0x0B;
-    register8_t DESTADDR0;  /* Channel Destination Address 0 */
-    register8_t DESTADDR1;  /* Channel Destination Address 1 */
-    register8_t DESTADDR2;  /* Channel Destination Address 2 */
-    register8_t reserved_0x0F;
-} DMA_CH_t;
-
-/*
---------------------------------------------------------------------------
-DMA - DMA Controller
---------------------------------------------------------------------------
-*/
-
-/* DMA Controller */
-typedef struct DMA_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t reserved_0x01;
-    register8_t reserved_0x02;
-    register8_t INTFLAGS;  /* Transfer Interrupt Status */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x05;
-    _WORDREGISTER(TEMP);  /* Temporary Register For 16/24-bit Access */
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    DMA_CH_t CH0;  /* DMA Channel 0 */
-    DMA_CH_t CH1;  /* DMA Channel 1 */
-    DMA_CH_t CH2;  /* DMA Channel 2 */
-    DMA_CH_t CH3;  /* DMA Channel 3 */
-} DMA_t;
-
-/* Burst mode */
-typedef enum DMA_CH_BURSTLEN_enum
-{
-    DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),  /* 1-byte burst mode */
-    DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),  /* 2-byte burst mode */
-    DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),  /* 4-byte burst mode */
-    DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),  /* 8-byte burst mode */
-} DMA_CH_BURSTLEN_t;
-
-/* Source address reload mode */
-typedef enum DMA_CH_SRCRELOAD_enum
-{
-    DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
-    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
-    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
-} DMA_CH_SRCRELOAD_t;
-
-/* Source addressing mode */
-typedef enum DMA_CH_SRCDIR_enum
-{
-    DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),  /* Fixed */
-    DMA_CH_SRCDIR_INC_gc = (0x01<<4),  /* Increment */
-    DMA_CH_SRCDIR_DEC_gc = (0x02<<4),  /* Decrement */
-} DMA_CH_SRCDIR_t;
-
-/* Destination adress reload mode */
-typedef enum DMA_CH_DESTRELOAD_enum
-{
-    DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
-    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
-    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
-} DMA_CH_DESTRELOAD_t;
-
-/* Destination adressing mode */
-typedef enum DMA_CH_DESTDIR_enum
-{
-    DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),  /* Fixed */
-    DMA_CH_DESTDIR_INC_gc = (0x01<<0),  /* Increment */
-    DMA_CH_DESTDIR_DEC_gc = (0x02<<0),  /* Decrement */
-} DMA_CH_DESTDIR_t;
-
-/* Transfer trigger source */
-typedef enum DMA_CH_TRIGSRC_enum
-{
-    DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),  /* Off software triggers only */
-    DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),  /* Event System Channel 0 */
-    DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),  /* Event System Channel 1 */
-    DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),  /* Event System Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),  /* ADCA Channel 0 */
-    DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
-    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
-    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
-    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
-    DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
-    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
-    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
-    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
-    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
-    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
-    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
-    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
-    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
-    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
-    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
-    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
-    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
-    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
-    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
-    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
-    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
-} DMA_CH_TRIGSRC_t;
-
-/* Double buffering mode */
-typedef enum DMA_DBUFMODE_enum
-{
-    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
-} DMA_DBUFMODE_t;
-
-/* Priority mode */
-typedef enum DMA_PRIMODE_enum
-{
-    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
-} DMA_PRIMODE_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_ERRINTLVL_enum
-{
-    DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),  /* Low level */
-    DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium level */
-    DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),  /* High level */
-} DMA_CH_ERRINTLVL_t;
-
-/* Interrupt level */
-typedef enum DMA_CH_TRNINTLVL_enum
-{
-    DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),  /* Low level */
-    DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),  /* High level */
-} DMA_CH_TRNINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH4MUX;  /* Event Channel 4 Multiplexer */
-    register8_t CH5MUX;  /* Event Channel 5 Multiplexer */
-    register8_t CH6MUX;  /* Event Channel 6 Multiplexer */
-    register8_t CH7MUX;  /* Event Channel 7 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t CH4CTRL;  /* Channel 4 Control Register */
-    register8_t CH5CTRL;  /* Channel 5 Control Register */
-    register8_t CH6CTRL;  /* Channel 6 Control Register */
-    register8_t CH7CTRL;  /* Channel 7 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),  /* Analog Comparator B Channel 0 */
-    EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),  /* Analog Comparator B Channel 1 */
-    EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),  /* Analog Comparator B Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),  /* ADC A Channel 1 */
-    EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),  /* ADC A Channel 2 */
-    EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),  /* ADC A Channel 3 */
-    EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),  /* ADC B Channel 0 */
-    EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),  /* ADC B Channel 1 */
-    EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),  /* ADC B Channel 2 */
-    EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),  /* ADC B Channel 3 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* JTAG User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CH1RES);  /* Channel 1 Result */
-    _WORDREGISTER(CH2RES);  /* Channel 2 Result */
-    _WORDREGISTER(CH3RES);  /* Channel 3 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-    ADC_CH_t CH1;  /* ADC Channel 1 */
-    ADC_CH_t CH2;  /* ADC Channel 2 */
-    ADC_CH_t CH3;  /* ADC Channel 3 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC / 1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-    ADC_SWEEP_01_gc = (0x01<<6),  /* ADC Channel 0,1 */
-    ADC_SWEEP_012_gc = (0x02<<6),  /* ADC Channel 0,1,2 */
-    ADC_SWEEP_0123_gc = (0x03<<6),  /* ADC Channel 0,1,2,3 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
-    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
-    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* DMA request selection */
-typedef enum ADC_DMASEL_enum
-{
-    ADC_DMASEL_OFF_gc = (0x00<<6),  /* Combined DMA request OFF */
-    ADC_DMASEL_CH01_gc = (0x01<<6),  /* ADC Channel 0 or 1 */
-    ADC_DMASEL_CH012_gc = (0x02<<6),  /* ADC Channel 0 or 1 or 2 */
-    ADC_DMASEL_CH0123_gc = (0x03<<6),  /* ADC Channel 0 or 1 or 2 or 3 */
-} ADC_DMASEL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-DAC - Digital/Analog Converter
---------------------------------------------------------------------------
-*/
-
-/* Digital-to-Analog Converter */
-typedef struct DAC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t EVCTRL;  /* Event Input Control */
-    register8_t TIMCTRL;  /* Timing Control */
-    register8_t STATUS;  /* Status */
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t GAINCAL;  /* Gain Calibration */
-    register8_t OFFSETCAL;  /* Offset Calibration */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    _WORDREGISTER(CH0DATA);  /* Channel 0 Data */
-    _WORDREGISTER(CH1DATA);  /* Channel 1 Data */
-} DAC_t;
-
-/* Output channel selection */
-typedef enum DAC_CHSEL_enum
-{
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
-} DAC_CHSEL_t;
-
-/* Reference voltage selection */
-typedef enum DAC_REFSEL_enum
-{
-    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
-    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
-} DAC_REFSEL_t;
-
-/* Event channel selection */
-typedef enum DAC_EVSEL_enum
-{
-    DAC_EVSEL_0_gc = (0x00<<0),  /* Event Channel 0 */
-    DAC_EVSEL_1_gc = (0x01<<0),  /* Event Channel 1 */
-    DAC_EVSEL_2_gc = (0x02<<0),  /* Event Channel 2 */
-    DAC_EVSEL_3_gc = (0x03<<0),  /* Event Channel 3 */
-    DAC_EVSEL_4_gc = (0x04<<0),  /* Event Channel 4 */
-    DAC_EVSEL_5_gc = (0x05<<0),  /* Event Channel 5 */
-    DAC_EVSEL_6_gc = (0x06<<0),  /* Event Channel 6 */
-    DAC_EVSEL_7_gc = (0x07<<0),  /* Event Channel 7 */
-} DAC_EVSEL_t;
-
-/* Conversion interval */
-typedef enum DAC_CONINTVAL_enum
-{
-    DAC_CONINTVAL_1CLK_gc = (0x00<<4),  /* 1 CLK / 2 CLK in S/H mode */
-    DAC_CONINTVAL_2CLK_gc = (0x01<<4),  /* 2 CLK / 3 CLK in S/H mode */
-    DAC_CONINTVAL_4CLK_gc = (0x02<<4),  /* 4 CLK / 6 CLK in S/H mode */
-    DAC_CONINTVAL_8CLK_gc = (0x03<<4),  /* 8 CLK / 12 CLK in S/H mode */
-    DAC_CONINTVAL_16CLK_gc = (0x04<<4),  /* 16 CLK / 24 CLK in S/H mode */
-    DAC_CONINTVAL_32CLK_gc = (0x05<<4),  /* 32 CLK / 48 CLK in S/H mode */
-    DAC_CONINTVAL_64CLK_gc = (0x06<<4),  /* 64 CLK / 96 CLK in S/H mode */
-    DAC_CONINTVAL_128CLK_gc = (0x07<<4),  /* 128 CLK / 192 CLK in S/H mode */
-} DAC_CONINTVAL_t;
-
-/* Refresh rate */
-typedef enum DAC_REFRESH_enum
-{
-    DAC_REFRESH_16CLK_gc = (0x00<<0),  /* 16 CLK */
-    DAC_REFRESH_32CLK_gc = (0x01<<0),  /* 32 CLK */
-    DAC_REFRESH_64CLK_gc = (0x02<<0),  /* 64 CLK */
-    DAC_REFRESH_128CLK_gc = (0x03<<0),  /* 128 CLK */
-    DAC_REFRESH_256CLK_gc = (0x04<<0),  /* 256 CLK */
-    DAC_REFRESH_512CLK_gc = (0x05<<0),  /* 512 CLK */
-    DAC_REFRESH_1024CLK_gc = (0x06<<0),  /* 1024 CLK */
-    DAC_REFRESH_2048CLK_gc = (0x07<<0),  /* 2048 CLK */
-    DAC_REFRESH_4086CLK_gc = (0x08<<0),  /* 4096 CLK */
-    DAC_REFRESH_8192CLK_gc = (0x09<<0),  /* 8192 CLK */
-    DAC_REFRESH_16384CLK_gc = (0x0A<<0),  /* 16384 CLK */
-    DAC_REFRESH_32768CLK_gc = (0x0B<<0),  /* 32768 CLK */
-    DAC_REFRESH_65536CLK_gc = (0x0C<<0),  /* 65536 CLK */
-    DAC_REFRESH_OFF_gc = (0x0F<<0),  /* Auto refresh OFF */
-} DAC_REFRESH_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEVMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRL;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-/*
---------------------------------------------------------------------------
-AES - AES Module
---------------------------------------------------------------------------
-*/
-
-/* AES Module */
-typedef struct AES_struct
-{
-    register8_t CTRL;  /* AES Control Register */
-    register8_t STATUS;  /* AES Status Register */
-    register8_t STATE;  /* AES State Register */
-    register8_t KEY;  /* AES Key Register */
-    register8_t INTCTRL;  /* AES Interrupt Control Register */
-} AES_t;
-
-/* Interrupt level */
-typedef enum AES_INTLVL_enum
-{
-    AES_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    AES_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} AES_INTLVL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define AES    (*(AES_t *) 0x00C0)  /* AES Crypto Module */
-#define DMA    (*(DMA_t *) 0x0100)  /* DMA Controller */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define ADCB    (*(ADC_t *) 0x0240)  /* Analog to Digital Converter B */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
-#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
-#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIO0  _SFR_MEM8(0x0000)
-#define GPIO_GPIO1  _SFR_MEM8(0x0001)
-#define GPIO_GPIO2  _SFR_MEM8(0x0002)
-#define GPIO_GPIO3  _SFR_MEM8(0x0003)
-#define GPIO_GPIO4  _SFR_MEM8(0x0004)
-#define GPIO_GPIO5  _SFR_MEM8(0x0005)
-#define GPIO_GPIO6  _SFR_MEM8(0x0006)
-#define GPIO_GPIO7  _SFR_MEM8(0x0007)
-#define GPIO_GPIO8  _SFR_MEM8(0x0008)
-#define GPIO_GPIO9  _SFR_MEM8(0x0009)
-#define GPIO_GPIOA  _SFR_MEM8(0x000A)
-#define GPIO_GPIOB  _SFR_MEM8(0x000B)
-#define GPIO_GPIOC  _SFR_MEM8(0x000C)
-#define GPIO_GPIOD  _SFR_MEM8(0x000D)
-#define GPIO_GPIOE  _SFR_MEM8(0x000E)
-#define GPIO_GPIOF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* AES - AES Crypto Module */
-#define AES_CTRL  _SFR_MEM8(0x00C0)
-#define AES_STATUS  _SFR_MEM8(0x00C1)
-#define AES_STATE  _SFR_MEM8(0x00C2)
-#define AES_KEY  _SFR_MEM8(0x00C3)
-#define AES_INTCTRL  _SFR_MEM8(0x00C4)
-
-/* DMA - DMA Controller */
-#define DMA_CTRL  _SFR_MEM8(0x0100)
-#define DMA_INTFLAGS  _SFR_MEM8(0x0103)
-#define DMA_STATUS  _SFR_MEM8(0x0104)
-#define DMA_TEMP  _SFR_MEM16(0x0106)
-#define DMA_CH0_CTRLA  _SFR_MEM8(0x0110)
-#define DMA_CH0_CTRLB  _SFR_MEM8(0x0111)
-#define DMA_CH0_ADDRCTRL  _SFR_MEM8(0x0112)
-#define DMA_CH0_TRIGSRC  _SFR_MEM8(0x0113)
-#define DMA_CH0_TRFCNT  _SFR_MEM16(0x0114)
-#define DMA_CH0_REPCNT  _SFR_MEM8(0x0116)
-#define DMA_CH0_SRCADDR0  _SFR_MEM8(0x0118)
-#define DMA_CH0_SRCADDR1  _SFR_MEM8(0x0119)
-#define DMA_CH0_SRCADDR2  _SFR_MEM8(0x011A)
-#define DMA_CH0_DESTADDR0  _SFR_MEM8(0x011C)
-#define DMA_CH0_DESTADDR1  _SFR_MEM8(0x011D)
-#define DMA_CH0_DESTADDR2  _SFR_MEM8(0x011E)
-#define DMA_CH1_CTRLA  _SFR_MEM8(0x0120)
-#define DMA_CH1_CTRLB  _SFR_MEM8(0x0121)
-#define DMA_CH1_ADDRCTRL  _SFR_MEM8(0x0122)
-#define DMA_CH1_TRIGSRC  _SFR_MEM8(0x0123)
-#define DMA_CH1_TRFCNT  _SFR_MEM16(0x0124)
-#define DMA_CH1_REPCNT  _SFR_MEM8(0x0126)
-#define DMA_CH1_SRCADDR0  _SFR_MEM8(0x0128)
-#define DMA_CH1_SRCADDR1  _SFR_MEM8(0x0129)
-#define DMA_CH1_SRCADDR2  _SFR_MEM8(0x012A)
-#define DMA_CH1_DESTADDR0  _SFR_MEM8(0x012C)
-#define DMA_CH1_DESTADDR1  _SFR_MEM8(0x012D)
-#define DMA_CH1_DESTADDR2  _SFR_MEM8(0x012E)
-#define DMA_CH2_CTRLA  _SFR_MEM8(0x0130)
-#define DMA_CH2_CTRLB  _SFR_MEM8(0x0131)
-#define DMA_CH2_ADDRCTRL  _SFR_MEM8(0x0132)
-#define DMA_CH2_TRIGSRC  _SFR_MEM8(0x0133)
-#define DMA_CH2_TRFCNT  _SFR_MEM16(0x0134)
-#define DMA_CH2_REPCNT  _SFR_MEM8(0x0136)
-#define DMA_CH2_SRCADDR0  _SFR_MEM8(0x0138)
-#define DMA_CH2_SRCADDR1  _SFR_MEM8(0x0139)
-#define DMA_CH2_SRCADDR2  _SFR_MEM8(0x013A)
-#define DMA_CH2_DESTADDR0  _SFR_MEM8(0x013C)
-#define DMA_CH2_DESTADDR1  _SFR_MEM8(0x013D)
-#define DMA_CH2_DESTADDR2  _SFR_MEM8(0x013E)
-#define DMA_CH3_CTRLA  _SFR_MEM8(0x0140)
-#define DMA_CH3_CTRLB  _SFR_MEM8(0x0141)
-#define DMA_CH3_ADDRCTRL  _SFR_MEM8(0x0142)
-#define DMA_CH3_TRIGSRC  _SFR_MEM8(0x0143)
-#define DMA_CH3_TRFCNT  _SFR_MEM16(0x0144)
-#define DMA_CH3_REPCNT  _SFR_MEM8(0x0146)
-#define DMA_CH3_SRCADDR0  _SFR_MEM8(0x0148)
-#define DMA_CH3_SRCADDR1  _SFR_MEM8(0x0149)
-#define DMA_CH3_SRCADDR2  _SFR_MEM8(0x014A)
-#define DMA_CH3_DESTADDR0  _SFR_MEM8(0x014C)
-#define DMA_CH3_DESTADDR1  _SFR_MEM8(0x014D)
-#define DMA_CH3_DESTADDR2  _SFR_MEM8(0x014E)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH4MUX  _SFR_MEM8(0x0184)
-#define EVSYS_CH5MUX  _SFR_MEM8(0x0185)
-#define EVSYS_CH6MUX  _SFR_MEM8(0x0186)
-#define EVSYS_CH7MUX  _SFR_MEM8(0x0187)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_CH4CTRL  _SFR_MEM8(0x018C)
-#define EVSYS_CH5CTRL  _SFR_MEM8(0x018D)
-#define EVSYS_CH6CTRL  _SFR_MEM8(0x018E)
-#define EVSYS_CH7CTRL  _SFR_MEM8(0x018F)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CH1RES  _SFR_MEM16(0x0212)
-#define ADCA_CH2RES  _SFR_MEM16(0x0214)
-#define ADCA_CH3RES  _SFR_MEM16(0x0216)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-#define ADCA_CH1_CTRL  _SFR_MEM8(0x0228)
-#define ADCA_CH1_MUXCTRL  _SFR_MEM8(0x0229)
-#define ADCA_CH1_INTCTRL  _SFR_MEM8(0x022A)
-#define ADCA_CH1_INTFLAGS  _SFR_MEM8(0x022B)
-#define ADCA_CH1_RES  _SFR_MEM16(0x022C)
-#define ADCA_CH2_CTRL  _SFR_MEM8(0x0230)
-#define ADCA_CH2_MUXCTRL  _SFR_MEM8(0x0231)
-#define ADCA_CH2_INTCTRL  _SFR_MEM8(0x0232)
-#define ADCA_CH2_INTFLAGS  _SFR_MEM8(0x0233)
-#define ADCA_CH2_RES  _SFR_MEM16(0x0234)
-#define ADCA_CH3_CTRL  _SFR_MEM8(0x0238)
-#define ADCA_CH3_MUXCTRL  _SFR_MEM8(0x0239)
-#define ADCA_CH3_INTCTRL  _SFR_MEM8(0x023A)
-#define ADCA_CH3_INTFLAGS  _SFR_MEM8(0x023B)
-#define ADCA_CH3_RES  _SFR_MEM16(0x023C)
-
-/* ADCB - Analog to Digital Converter B */
-#define ADCB_CTRLA  _SFR_MEM8(0x0240)
-#define ADCB_CTRLB  _SFR_MEM8(0x0241)
-#define ADCB_REFCTRL  _SFR_MEM8(0x0242)
-#define ADCB_EVCTRL  _SFR_MEM8(0x0243)
-#define ADCB_PRESCALER  _SFR_MEM8(0x0244)
-#define ADCB_CALCTRL  _SFR_MEM8(0x0245)
-#define ADCB_INTFLAGS  _SFR_MEM8(0x0246)
-#define ADCB_CAL  _SFR_MEM16(0x024C)
-#define ADCB_CH0RES  _SFR_MEM16(0x0250)
-#define ADCB_CH1RES  _SFR_MEM16(0x0252)
-#define ADCB_CH2RES  _SFR_MEM16(0x0254)
-#define ADCB_CH3RES  _SFR_MEM16(0x0256)
-#define ADCB_CMP  _SFR_MEM16(0x0258)
-#define ADCB_CH0_CTRL  _SFR_MEM8(0x0260)
-#define ADCB_CH0_MUXCTRL  _SFR_MEM8(0x0261)
-#define ADCB_CH0_INTCTRL  _SFR_MEM8(0x0262)
-#define ADCB_CH0_INTFLAGS  _SFR_MEM8(0x0263)
-#define ADCB_CH0_RES  _SFR_MEM16(0x0264)
-#define ADCB_CH1_CTRL  _SFR_MEM8(0x0268)
-#define ADCB_CH1_MUXCTRL  _SFR_MEM8(0x0269)
-#define ADCB_CH1_INTCTRL  _SFR_MEM8(0x026A)
-#define ADCB_CH1_INTFLAGS  _SFR_MEM8(0x026B)
-#define ADCB_CH1_RES  _SFR_MEM16(0x026C)
-#define ADCB_CH2_CTRL  _SFR_MEM8(0x0270)
-#define ADCB_CH2_MUXCTRL  _SFR_MEM8(0x0271)
-#define ADCB_CH2_INTCTRL  _SFR_MEM8(0x0272)
-#define ADCB_CH2_INTFLAGS  _SFR_MEM8(0x0273)
-#define ADCB_CH2_RES  _SFR_MEM16(0x0274)
-#define ADCB_CH3_CTRL  _SFR_MEM8(0x0278)
-#define ADCB_CH3_MUXCTRL  _SFR_MEM8(0x0279)
-#define ADCB_CH3_INTCTRL  _SFR_MEM8(0x027A)
-#define ADCB_CH3_INTFLAGS  _SFR_MEM8(0x027B)
-#define ADCB_CH3_RES  _SFR_MEM16(0x027C)
-
-/* DACB - Digital to Analog Converter B */
-#define DACB_CTRLA  _SFR_MEM8(0x0320)
-#define DACB_CTRLB  _SFR_MEM8(0x0321)
-#define DACB_CTRLC  _SFR_MEM8(0x0322)
-#define DACB_EVCTRL  _SFR_MEM8(0x0323)
-#define DACB_TIMCTRL  _SFR_MEM8(0x0324)
-#define DACB_STATUS  _SFR_MEM8(0x0325)
-#define DACB_GAINCAL  _SFR_MEM8(0x0328)
-#define DACB_OFFSETCAL  _SFR_MEM8(0x0329)
-#define DACB_CH0DATA  _SFR_MEM16(0x0338)
-#define DACB_CH1DATA  _SFR_MEM16(0x033A)
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* TWIE - Two-Wire Interface E */
-#define TWIE_CTRL  _SFR_MEM8(0x04A0)
-#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
-#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
-#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
-#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
-#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
-#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
-#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
-#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
-#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
-#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
-#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
-#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
-#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEVMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRL  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
-#define USARTC1_DATA  _SFR_MEM8(0x08B0)
-#define USARTC1_STATUS  _SFR_MEM8(0x08B1)
-#define USARTC1_CTRLA  _SFR_MEM8(0x08B3)
-#define USARTC1_CTRLB  _SFR_MEM8(0x08B4)
-#define USARTC1_CTRLC  _SFR_MEM8(0x08B5)
-#define USARTC1_BAUDCTRLA  _SFR_MEM8(0x08B6)
-#define USARTC1_BAUDCTRLB  _SFR_MEM8(0x08B7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* TCD1 - Timer/Counter D1 */
-#define TCD1_CTRLA  _SFR_MEM8(0x0940)
-#define TCD1_CTRLB  _SFR_MEM8(0x0941)
-#define TCD1_CTRLC  _SFR_MEM8(0x0942)
-#define TCD1_CTRLD  _SFR_MEM8(0x0943)
-#define TCD1_CTRLE  _SFR_MEM8(0x0944)
-#define TCD1_INTCTRLA  _SFR_MEM8(0x0946)
-#define TCD1_INTCTRLB  _SFR_MEM8(0x0947)
-#define TCD1_CTRLFCLR  _SFR_MEM8(0x0948)
-#define TCD1_CTRLFSET  _SFR_MEM8(0x0949)
-#define TCD1_CTRLGCLR  _SFR_MEM8(0x094A)
-#define TCD1_CTRLGSET  _SFR_MEM8(0x094B)
-#define TCD1_INTFLAGS  _SFR_MEM8(0x094C)
-#define TCD1_TEMP  _SFR_MEM8(0x094F)
-#define TCD1_CNT  _SFR_MEM16(0x0960)
-#define TCD1_PER  _SFR_MEM16(0x0966)
-#define TCD1_CCA  _SFR_MEM16(0x0968)
-#define TCD1_CCB  _SFR_MEM16(0x096A)
-#define TCD1_PERBUF  _SFR_MEM16(0x0976)
-#define TCD1_CCABUF  _SFR_MEM16(0x0978)
-#define TCD1_CCBBUF  _SFR_MEM16(0x097A)
-
-/* HIRESD - High-Resolution Extension D */
-#define HIRESD_CTRL  _SFR_MEM8(0x0990)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
-#define USARTD1_DATA  _SFR_MEM8(0x09B0)
-#define USARTD1_STATUS  _SFR_MEM8(0x09B1)
-#define USARTD1_CTRLA  _SFR_MEM8(0x09B3)
-#define USARTD1_CTRLB  _SFR_MEM8(0x09B4)
-#define USARTD1_CTRLC  _SFR_MEM8(0x09B5)
-#define USARTD1_BAUDCTRLA  _SFR_MEM8(0x09B6)
-#define USARTD1_BAUDCTRLB  _SFR_MEM8(0x09B7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* TCE1 - Timer/Counter E1 */
-#define TCE1_CTRLA  _SFR_MEM8(0x0A40)
-#define TCE1_CTRLB  _SFR_MEM8(0x0A41)
-#define TCE1_CTRLC  _SFR_MEM8(0x0A42)
-#define TCE1_CTRLD  _SFR_MEM8(0x0A43)
-#define TCE1_CTRLE  _SFR_MEM8(0x0A44)
-#define TCE1_INTCTRLA  _SFR_MEM8(0x0A46)
-#define TCE1_INTCTRLB  _SFR_MEM8(0x0A47)
-#define TCE1_CTRLFCLR  _SFR_MEM8(0x0A48)
-#define TCE1_CTRLFSET  _SFR_MEM8(0x0A49)
-#define TCE1_CTRLGCLR  _SFR_MEM8(0x0A4A)
-#define TCE1_CTRLGSET  _SFR_MEM8(0x0A4B)
-#define TCE1_INTFLAGS  _SFR_MEM8(0x0A4C)
-#define TCE1_TEMP  _SFR_MEM8(0x0A4F)
-#define TCE1_CNT  _SFR_MEM16(0x0A60)
-#define TCE1_PER  _SFR_MEM16(0x0A66)
-#define TCE1_CCA  _SFR_MEM16(0x0A68)
-#define TCE1_CCB  _SFR_MEM16(0x0A6A)
-#define TCE1_PERBUF  _SFR_MEM16(0x0A76)
-#define TCE1_CCABUF  _SFR_MEM16(0x0A78)
-#define TCE1_CCBBUF  _SFR_MEM16(0x0A7A)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEVMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* HIRESE - High-Resolution Extension E */
-#define HIRESE_CTRL  _SFR_MEM8(0x0A90)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
-#define USARTE1_DATA  _SFR_MEM8(0x0AB0)
-#define USARTE1_STATUS  _SFR_MEM8(0x0AB1)
-#define USARTE1_CTRLA  _SFR_MEM8(0x0AB3)
-#define USARTE1_CTRLB  _SFR_MEM8(0x0AB4)
-#define USARTE1_CTRLC  _SFR_MEM8(0x0AB5)
-#define USARTE1_BAUDCTRLA  _SFR_MEM8(0x0AB6)
-#define USARTE1_BAUDCTRLB  _SFR_MEM8(0x0AB7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-/* HIRESF - High-Resolution Extension F */
-#define HIRESF_CTRL  _SFR_MEM8(0x0B90)
-
-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF0_DATA  _SFR_MEM8(0x0BA0)
-#define USARTF0_STATUS  _SFR_MEM8(0x0BA1)
-#define USARTF0_CTRLA  _SFR_MEM8(0x0BA3)
-#define USARTF0_CTRLB  _SFR_MEM8(0x0BA4)
-#define USARTF0_CTRLC  _SFR_MEM8(0x0BA5)
-#define USARTF0_BAUDCTRLA  _SFR_MEM8(0x0BA6)
-#define USARTF0_BAUDCTRLB  _SFR_MEM8(0x0BA7)
-
-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
-#define USARTF1_DATA  _SFR_MEM8(0x0BB0)
-#define USARTF1_STATUS  _SFR_MEM8(0x0BB1)
-#define USARTF1_CTRLA  _SFR_MEM8(0x0BB3)
-#define USARTF1_CTRLB  _SFR_MEM8(0x0BB4)
-#define USARTF1_CTRLC  _SFR_MEM8(0x0BB5)
-#define USARTF1_BAUDCTRLA  _SFR_MEM8(0x0BB6)
-#define USARTF1_BAUDCTRLB  _SFR_MEM8(0x0BB7)
-
-/* SPIF - Serial Peripheral Interface F */
-#define SPIF_CTRL  _SFR_MEM8(0x0BC0)
-#define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
-#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
-#define SPIF_DATA  _SFR_MEM8(0x0BC3)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* DMA - DMA Controller */
-/* DMA_CH.CTRLA  bit masks and bit positions */
-#define DMA_CH_ENABLE_bm  0x80  /* Channel Enable bit mask. */
-#define DMA_CH_ENABLE_bp  7  /* Channel Enable bit position. */
-
-#define DMA_CH_RESET_bm  0x40  /* Channel Software Reset bit mask. */
-#define DMA_CH_RESET_bp  6  /* Channel Software Reset bit position. */
-
-#define DMA_CH_REPEAT_bm  0x20  /* Channel Repeat Mode bit mask. */
-#define DMA_CH_REPEAT_bp  5  /* Channel Repeat Mode bit position. */
-
-#define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
-#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
-
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
-
-#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
-#define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
-#define DMA_CH_BURSTLEN0_bm  (1<<0)  /* Channel Transfer Mode bit 0 mask. */
-#define DMA_CH_BURSTLEN0_bp  0  /* Channel Transfer Mode bit 0 position. */
-#define DMA_CH_BURSTLEN1_bm  (1<<1)  /* Channel Transfer Mode bit 1 mask. */
-#define DMA_CH_BURSTLEN1_bp  1  /* Channel Transfer Mode bit 1 position. */
-
-
-/* DMA_CH.CTRLB  bit masks and bit positions */
-#define DMA_CH_CHBUSY_bm  0x80  /* Block Transfer Busy bit mask. */
-#define DMA_CH_CHBUSY_bp  7  /* Block Transfer Busy bit position. */
-
-#define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
-#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
-
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
-
-
-/* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
-
-#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
-#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
-
-
-/* DMA_CH.TRIGSRC  bit masks and bit positions */
-#define DMA_CH_TRIGSRC_gm  0xFF  /* Channel Trigger Source group mask. */
-#define DMA_CH_TRIGSRC_gp  0  /* Channel Trigger Source group position. */
-#define DMA_CH_TRIGSRC0_bm  (1<<0)  /* Channel Trigger Source bit 0 mask. */
-#define DMA_CH_TRIGSRC0_bp  0  /* Channel Trigger Source bit 0 position. */
-#define DMA_CH_TRIGSRC1_bm  (1<<1)  /* Channel Trigger Source bit 1 mask. */
-#define DMA_CH_TRIGSRC1_bp  1  /* Channel Trigger Source bit 1 position. */
-#define DMA_CH_TRIGSRC2_bm  (1<<2)  /* Channel Trigger Source bit 2 mask. */
-#define DMA_CH_TRIGSRC2_bp  2  /* Channel Trigger Source bit 2 position. */
-#define DMA_CH_TRIGSRC3_bm  (1<<3)  /* Channel Trigger Source bit 3 mask. */
-#define DMA_CH_TRIGSRC3_bp  3  /* Channel Trigger Source bit 3 position. */
-#define DMA_CH_TRIGSRC4_bm  (1<<4)  /* Channel Trigger Source bit 4 mask. */
-#define DMA_CH_TRIGSRC4_bp  4  /* Channel Trigger Source bit 4 position. */
-#define DMA_CH_TRIGSRC5_bm  (1<<5)  /* Channel Trigger Source bit 5 mask. */
-#define DMA_CH_TRIGSRC5_bp  5  /* Channel Trigger Source bit 5 position. */
-#define DMA_CH_TRIGSRC6_bm  (1<<6)  /* Channel Trigger Source bit 6 mask. */
-#define DMA_CH_TRIGSRC6_bp  6  /* Channel Trigger Source bit 6 position. */
-#define DMA_CH_TRIGSRC7_bm  (1<<7)  /* Channel Trigger Source bit 7 mask. */
-#define DMA_CH_TRIGSRC7_bp  7  /* Channel Trigger Source bit 7 position. */
-
-
-/* DMA.CTRL  bit masks and bit positions */
-#define DMA_ENABLE_bm  0x80  /* Enable bit mask. */
-#define DMA_ENABLE_bp  7  /* Enable bit position. */
-
-#define DMA_RESET_bm  0x40  /* Software Reset bit mask. */
-#define DMA_RESET_bp  6  /* Software Reset bit position. */
-
-#define DMA_DBUFMODE_gm  0x0C  /* Double Buffering Mode group mask. */
-#define DMA_DBUFMODE_gp  2  /* Double Buffering Mode group position. */
-#define DMA_DBUFMODE0_bm  (1<<2)  /* Double Buffering Mode bit 0 mask. */
-#define DMA_DBUFMODE0_bp  2  /* Double Buffering Mode bit 0 position. */
-#define DMA_DBUFMODE1_bm  (1<<3)  /* Double Buffering Mode bit 1 mask. */
-#define DMA_DBUFMODE1_bp  3  /* Double Buffering Mode bit 1 position. */
-
-#define DMA_PRIMODE_gm  0x03  /* Channel Priority Mode group mask. */
-#define DMA_PRIMODE_gp  0  /* Channel Priority Mode group position. */
-#define DMA_PRIMODE0_bm  (1<<0)  /* Channel Priority Mode bit 0 mask. */
-#define DMA_PRIMODE0_bp  0  /* Channel Priority Mode bit 0 position. */
-#define DMA_PRIMODE1_bm  (1<<1)  /* Channel Priority Mode bit 1 mask. */
-#define DMA_PRIMODE1_bp  1  /* Channel Priority Mode bit 1 position. */
-
-
-/* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
-
-
-/* DMA.STATUS  bit masks and bit positions */
-#define DMA_CH3BUSY_bm  0x80  /* Channel 3 Block Transfer Busy bit mask. */
-#define DMA_CH3BUSY_bp  7  /* Channel 3 Block Transfer Busy bit position. */
-
-#define DMA_CH2BUSY_bm  0x40  /* Channel 2 Block Transfer Busy bit mask. */
-#define DMA_CH2BUSY_bp  6  /* Channel 2 Block Transfer Busy bit position. */
-
-#define DMA_CH1BUSY_bm  0x20  /* Channel 1 Block Transfer Busy bit mask. */
-#define DMA_CH1BUSY_bp  5  /* Channel 1 Block Transfer Busy bit position. */
-
-#define DMA_CH0BUSY_bm  0x10  /* Channel 0 Block Transfer Busy bit mask. */
-#define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
-
-#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
-
-#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
-
-#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
-
-#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH4MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH5MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH6MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH7MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH4CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH5CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH6CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH7CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_JTAGUSERID_gm  0xFF  /* JTAG User ID group mask. */
-#define NVM_FUSES_JTAGUSERID_gp  0  /* JTAG User ID group position. */
-#define NVM_FUSES_JTAGUSERID0_bm  (1<<0)  /* JTAG User ID bit 0 mask. */
-#define NVM_FUSES_JTAGUSERID0_bp  0  /* JTAG User ID bit 0 position. */
-#define NVM_FUSES_JTAGUSERID1_bm  (1<<1)  /* JTAG User ID bit 1 mask. */
-#define NVM_FUSES_JTAGUSERID1_bp  1  /* JTAG User ID bit 1 position. */
-#define NVM_FUSES_JTAGUSERID2_bm  (1<<2)  /* JTAG User ID bit 2 mask. */
-#define NVM_FUSES_JTAGUSERID2_bp  2  /* JTAG User ID bit 2 position. */
-#define NVM_FUSES_JTAGUSERID3_bm  (1<<3)  /* JTAG User ID bit 3 mask. */
-#define NVM_FUSES_JTAGUSERID3_bp  3  /* JTAG User ID bit 3 position. */
-#define NVM_FUSES_JTAGUSERID4_bm  (1<<4)  /* JTAG User ID bit 4 mask. */
-#define NVM_FUSES_JTAGUSERID4_bp  4  /* JTAG User ID bit 4 position. */
-#define NVM_FUSES_JTAGUSERID5_bm  (1<<5)  /* JTAG User ID bit 5 mask. */
-#define NVM_FUSES_JTAGUSERID5_bp  5  /* JTAG User ID bit 5 position. */
-#define NVM_FUSES_JTAGUSERID6_bm  (1<<6)  /* JTAG User ID bit 6 mask. */
-#define NVM_FUSES_JTAGUSERID6_bp  6  /* JTAG User ID bit 6 position. */
-#define NVM_FUSES_JTAGUSERID7_bm  (1<<7)  /* JTAG User ID bit 7 mask. */
-#define NVM_FUSES_JTAGUSERID7_bp  7  /* JTAG User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-#define NVM_FUSES_JTAGEN_bm  0x01  /* JTAG Interface Enable bit mask. */
-#define NVM_FUSES_JTAGEN_bp  0  /* JTAG Interface Enable bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_DMASEL_gm  0xC0  /* DMA Selection group mask. */
-#define ADC_DMASEL_gp  6  /* DMA Selection group position. */
-#define ADC_DMASEL0_bm  (1<<6)  /* DMA Selection bit 0 mask. */
-#define ADC_DMASEL0_bp  6  /* DMA Selection bit 0 position. */
-#define ADC_DMASEL1_bm  (1<<7)  /* DMA Selection bit 1 mask. */
-#define ADC_DMASEL1_bp  7  /* DMA Selection bit 1 position. */
-
-#define ADC_CH3START_bm  0x20  /* Channel 3 Start Conversion bit mask. */
-#define ADC_CH3START_bp  5  /* Channel 3 Start Conversion bit position. */
-
-#define ADC_CH2START_bm  0x10  /* Channel 2 Start Conversion bit mask. */
-#define ADC_CH2START_bp  4  /* Channel 2 Start Conversion bit position. */
-
-#define ADC_CH1START_bm  0x08  /* Channel 1 Start Conversion bit mask. */
-#define ADC_CH1START_bp  3  /* Channel 1 Start Conversion bit position. */
-
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_FLUSH_bm  0x02  /* Flush Pipeline bit mask. */
-#define ADC_FLUSH_bp  1  /* Flush Pipeline bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH3IF_bm  0x08  /* Channel 3 Interrupt Flag bit mask. */
-#define ADC_CH3IF_bp  3  /* Channel 3 Interrupt Flag bit position. */
-
-#define ADC_CH2IF_bm  0x04  /* Channel 2 Interrupt Flag bit mask. */
-#define ADC_CH2IF_bp  2  /* Channel 2 Interrupt Flag bit position. */
-
-#define ADC_CH1IF_bm  0x02  /* Channel 1 Interrupt Flag bit mask. */
-#define ADC_CH1IF_bp  1  /* Channel 1 Interrupt Flag bit position. */
-
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* DAC - Digital/Analog Converter */
-/* DAC.CTRLA  bit masks and bit positions */
-#define DAC_IDOEN_bm  0x10  /* Internal Output Enable bit mask. */
-#define DAC_IDOEN_bp  4  /* Internal Output Enable bit position. */
-
-#define DAC_CH1EN_bm  0x08  /* Channel 1 Output Enable bit mask. */
-#define DAC_CH1EN_bp  3  /* Channel 1 Output Enable bit position. */
-
-#define DAC_CH0EN_bm  0x04  /* Channel 0 Output Enable bit mask. */
-#define DAC_CH0EN_bp  2  /* Channel 0 Output Enable bit position. */
-
-#define DAC_LPMODE_bm  0x02  /* Low Power Mode bit mask. */
-#define DAC_LPMODE_bp  1  /* Low Power Mode bit position. */
-
-#define DAC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define DAC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* DAC.CTRLB  bit masks and bit positions */
-#define DAC_CHSEL_gm  0x60  /* Channel Select group mask. */
-#define DAC_CHSEL_gp  5  /* Channel Select group position. */
-#define DAC_CHSEL0_bm  (1<<5)  /* Channel Select bit 0 mask. */
-#define DAC_CHSEL0_bp  5  /* Channel Select bit 0 position. */
-#define DAC_CHSEL1_bm  (1<<6)  /* Channel Select bit 1 mask. */
-#define DAC_CHSEL1_bp  6  /* Channel Select bit 1 position. */
-
-#define DAC_CH1TRIG_bm  0x02  /* Channel 1 Event Trig Enable bit mask. */
-#define DAC_CH1TRIG_bp  1  /* Channel 1 Event Trig Enable bit position. */
-
-#define DAC_CH0TRIG_bm  0x01  /* Channel 0 Event Trig Enable bit mask. */
-#define DAC_CH0TRIG_bp  0  /* Channel 0 Event Trig Enable bit position. */
-
-
-/* DAC.CTRLC  bit masks and bit positions */
-#define DAC_REFSEL_gm  0x18  /* Reference Select group mask. */
-#define DAC_REFSEL_gp  3  /* Reference Select group position. */
-#define DAC_REFSEL0_bm  (1<<3)  /* Reference Select bit 0 mask. */
-#define DAC_REFSEL0_bp  3  /* Reference Select bit 0 position. */
-#define DAC_REFSEL1_bm  (1<<4)  /* Reference Select bit 1 mask. */
-#define DAC_REFSEL1_bp  4  /* Reference Select bit 1 position. */
-
-#define DAC_LEFTADJ_bm  0x01  /* Left-adjust Result bit mask. */
-#define DAC_LEFTADJ_bp  0  /* Left-adjust Result bit position. */
-
-
-/* DAC.EVCTRL  bit masks and bit positions */
-#define DAC_EVSEL_gm  0x07  /* Event Input Selection group mask. */
-#define DAC_EVSEL_gp  0  /* Event Input Selection group position. */
-#define DAC_EVSEL0_bm  (1<<0)  /* Event Input Selection bit 0 mask. */
-#define DAC_EVSEL0_bp  0  /* Event Input Selection bit 0 position. */
-#define DAC_EVSEL1_bm  (1<<1)  /* Event Input Selection bit 1 mask. */
-#define DAC_EVSEL1_bp  1  /* Event Input Selection bit 1 position. */
-#define DAC_EVSEL2_bm  (1<<2)  /* Event Input Selection bit 2 mask. */
-#define DAC_EVSEL2_bp  2  /* Event Input Selection bit 2 position. */
-
-
-/* DAC.TIMCTRL  bit masks and bit positions */
-#define DAC_CONINTVAL_gm  0x70  /* Conversion Intercal group mask. */
-#define DAC_CONINTVAL_gp  4  /* Conversion Intercal group position. */
-#define DAC_CONINTVAL0_bm  (1<<4)  /* Conversion Intercal bit 0 mask. */
-#define DAC_CONINTVAL0_bp  4  /* Conversion Intercal bit 0 position. */
-#define DAC_CONINTVAL1_bm  (1<<5)  /* Conversion Intercal bit 1 mask. */
-#define DAC_CONINTVAL1_bp  5  /* Conversion Intercal bit 1 position. */
-#define DAC_CONINTVAL2_bm  (1<<6)  /* Conversion Intercal bit 2 mask. */
-#define DAC_CONINTVAL2_bp  6  /* Conversion Intercal bit 2 position. */
-
-#define DAC_REFRESH_gm  0x0F  /* Refresh Timing Control group mask. */
-#define DAC_REFRESH_gp  0  /* Refresh Timing Control group position. */
-#define DAC_REFRESH0_bm  (1<<0)  /* Refresh Timing Control bit 0 mask. */
-#define DAC_REFRESH0_bp  0  /* Refresh Timing Control bit 0 position. */
-#define DAC_REFRESH1_bm  (1<<1)  /* Refresh Timing Control bit 1 mask. */
-#define DAC_REFRESH1_bp  1  /* Refresh Timing Control bit 1 position. */
-#define DAC_REFRESH2_bm  (1<<2)  /* Refresh Timing Control bit 2 mask. */
-#define DAC_REFRESH2_bp  2  /* Refresh Timing Control bit 2 position. */
-#define DAC_REFRESH3_bm  (1<<3)  /* Refresh Timing Control bit 3 mask. */
-#define DAC_REFRESH3_bp  3  /* Refresh Timing Control bit 3 position. */
-
-
-/* DAC.STATUS  bit masks and bit positions */
-#define DAC_CH1DRE_bm  0x02  /* Channel 1 Data Register Empty bit mask. */
-#define DAC_CH1DRE_bp  1  /* Channel 1 Data Register Empty bit position. */
-
-#define DAC_CH0DRE_bm  0x01  /* Channel 0 Data Register Empty bit mask. */
-#define DAC_CH0DRE_bp  0  /* Channel 0 Data Register Empty bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
-#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
-
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRL  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-/* AES - AES Module */
-/* AES.CTRL  bit masks and bit positions */
-#define AES_START_bm  0x80  /* Start/Run bit mask. */
-#define AES_START_bp  7  /* Start/Run bit position. */
-
-#define AES_AUTO_bm  0x40  /* Auto Start Trigger bit mask. */
-#define AES_AUTO_bp  6  /* Auto Start Trigger bit position. */
-
-#define AES_RESET_bm  0x20  /* AES Software Reset bit mask. */
-#define AES_RESET_bp  5  /* AES Software Reset bit position. */
-
-#define AES_DECRYPT_bm  0x10  /* Decryption / Direction bit mask. */
-#define AES_DECRYPT_bp  4  /* Decryption / Direction bit position. */
-
-#define AES_XOR_bm  0x04  /* State XOR Load Enable bit mask. */
-#define AES_XOR_bp  2  /* State XOR Load Enable bit position. */
-
-
-/* AES.STATUS  bit masks and bit positions */
-#define AES_ERROR_bm  0x80  /* AES Error bit mask. */
-#define AES_ERROR_bp  7  /* AES Error bit position. */
-
-#define AES_SRIF_bm  0x01  /* State Ready Interrupt Flag bit mask. */
-#define AES_SRIF_bp  0  /* State Ready Interrupt Flag bit position. */
-
-
-/* AES.INTCTRL  bit masks and bit positions */
-#define AES_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define AES_INTLVL_gp  0  /* Interrupt level group position. */
-#define AES_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define AES_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define AES_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define AES_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* DMA interrupt vectors */
-#define DMA_CH0_vect_num  6
-#define DMA_CH0_vect      _VECTOR(6)  /* Channel 0 Interrupt */
-#define DMA_CH1_vect_num  7
-#define DMA_CH1_vect      _VECTOR(7)  /* Channel 1 Interrupt */
-#define DMA_CH2_vect_num  8
-#define DMA_CH2_vect      _VECTOR(8)  /* Channel 2 Interrupt */
-#define DMA_CH3_vect_num  9
-#define DMA_CH3_vect      _VECTOR(9)  /* Channel 3 Interrupt */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* USARTC1 interrupt vectors */
-#define USARTC1_RXC_vect_num  28
-#define USARTC1_RXC_vect      _VECTOR(28)  /* Reception Complete Interrupt */
-#define USARTC1_DRE_vect_num  29
-#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
-#define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
-
-/* AES interrupt vectors */
-#define AES_INT_vect_num  31
-#define AES_INT_vect      _VECTOR(31)  /* AES Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* ACB interrupt vectors */
-#define ACB_AC0_vect_num  36
-#define ACB_AC0_vect      _VECTOR(36)  /* AC0 Interrupt */
-#define ACB_AC1_vect_num  37
-#define ACB_AC1_vect      _VECTOR(37)  /* AC1 Interrupt */
-#define ACB_ACW_vect_num  38
-#define ACB_ACW_vect      _VECTOR(38)  /* ACW Window Mode Interrupt */
-
-/* ADCB interrupt vectors */
-#define ADCB_CH0_vect_num  39
-#define ADCB_CH0_vect      _VECTOR(39)  /* Interrupt 0 */
-#define ADCB_CH1_vect_num  40
-#define ADCB_CH1_vect      _VECTOR(40)  /* Interrupt 1 */
-#define ADCB_CH2_vect_num  41
-#define ADCB_CH2_vect      _VECTOR(41)  /* Interrupt 2 */
-#define ADCB_CH3_vect_num  42
-#define ADCB_CH3_vect      _VECTOR(42)  /* Interrupt 3 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TWIE interrupt vectors */
-#define TWIE_TWIS_vect_num  45
-#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
-#define TWIE_TWIM_vect_num  46
-#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* TCE1 interrupt vectors */
-#define TCE1_OVF_vect_num  53
-#define TCE1_OVF_vect      _VECTOR(53)  /* Overflow Interrupt */
-#define TCE1_ERR_vect_num  54
-#define TCE1_ERR_vect      _VECTOR(54)  /* Error Interrupt */
-#define TCE1_CCA_vect_num  55
-#define TCE1_CCA_vect      _VECTOR(55)  /* Compare or Capture A Interrupt */
-#define TCE1_CCB_vect_num  56
-#define TCE1_CCB_vect      _VECTOR(56)  /* Compare or Capture B Interrupt */
-
-/* SPIE interrupt vectors */
-#define SPIE_INT_vect_num  57
-#define SPIE_INT_vect      _VECTOR(57)  /* SPI Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* USARTE1 interrupt vectors */
-#define USARTE1_RXC_vect_num  61
-#define USARTE1_RXC_vect      _VECTOR(61)  /* Reception Complete Interrupt */
-#define USARTE1_DRE_vect_num  62
-#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
-#define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-#define ADCA_CH1_vect_num  72
-#define ADCA_CH1_vect      _VECTOR(72)  /* Interrupt 1 */
-#define ADCA_CH2_vect_num  73
-#define ADCA_CH2_vect      _VECTOR(73)  /* Interrupt 2 */
-#define ADCA_CH3_vect_num  74
-#define ADCA_CH3_vect      _VECTOR(74)  /* Interrupt 3 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* TCD1 interrupt vectors */
-#define TCD1_OVF_vect_num  83
-#define TCD1_OVF_vect      _VECTOR(83)  /* Overflow Interrupt */
-#define TCD1_ERR_vect_num  84
-#define TCD1_ERR_vect      _VECTOR(84)  /* Error Interrupt */
-#define TCD1_CCA_vect_num  85
-#define TCD1_CCA_vect      _VECTOR(85)  /* Compare or Capture A Interrupt */
-#define TCD1_CCB_vect_num  86
-#define TCD1_CCB_vect      _VECTOR(86)  /* Compare or Capture B Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* USARTD1 interrupt vectors */
-#define USARTD1_RXC_vect_num  91
-#define USARTD1_RXC_vect      _VECTOR(91)  /* Reception Complete Interrupt */
-#define USARTD1_DRE_vect_num  92
-#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
-#define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-/* USARTF0 interrupt vectors */
-#define USARTF0_RXC_vect_num  119
-#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
-#define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
-#define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (69632)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (65536)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x0F000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x10000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (12288)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (4096)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0  (unsigned char)~_BV(0)  /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1  (unsigned char)~_BV(1)  /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2  (unsigned char)~_BV(2)  /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3  (unsigned char)~_BV(3)  /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4  (unsigned char)~_BV(4)  /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5  (unsigned char)~_BV(5)  /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6  (unsigned char)~_BV(6)  /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7  (unsigned char)~_BV(7)  /* JTAG User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_JTAGEN  (unsigned char)~_BV(0)  /* JTAG Interface Enable */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x42
-
-/**@}*/
-#endif /* _AVR_ATxmega64A3_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox64d3.h b/cpukit/score/cpu/avr/avr/iox64d3.h
deleted file mode 100644
index 5a0bdb5584..0000000000
--- a/cpukit/score/cpu/avr/avr/iox64d3.h
+++ /dev/null
@@ -1,5669 +0,0 @@
-/**
- * @file avr/iox64d3.h
- *
- * @brief Definitions for ATxmega64D3
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2009 Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iox64d3.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATxmega64D3_H_
-#define _AVR_ATxmega64D3_H_ 1
-
-/**
- *  @defgroup Avr_iox64d3 ATxmega64D3 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Ungrouped common registers */
-#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
-#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
-#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
-#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
-#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
-#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
-#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
-#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
-#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
-#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
-#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
-#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
-#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
-#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
-#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
-#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
-
-#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
-#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
-#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
-#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
-#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
-#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
-#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
-#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
-#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
-
-
-/* C Language Only */
-#if !defined (__ASSEMBLER__)
-
-#include <stdint.h>
-
-typedef volatile uint8_t register8_t;
-typedef volatile uint16_t register16_t;
-typedef volatile uint32_t register32_t;
-
-
-#ifdef _WORDREGISTER
-#undef _WORDREGISTER
-#endif
-#define _WORDREGISTER(regname)   \
-    __extension__ union \
-    { \
-        register16_t regname; \
-        struct \
-        { \
-            register8_t regname ## L; \
-            register8_t regname ## H; \
-        }; \
-    }
-
-#ifdef _DWORDREGISTER
-#undef _DWORDREGISTER
-#endif
-#define _DWORDREGISTER(regname)  \
-   __extension__  union \
-    { \
-        register32_t regname; \
-        struct \
-        { \
-            register8_t regname ## 0; \
-            register8_t regname ## 1; \
-            register8_t regname ## 2; \
-            register8_t regname ## 3; \
-        }; \
-    }
-
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
-
-/*
---------------------------------------------------------------------------
-XOCD - On-Chip Debug System
---------------------------------------------------------------------------
-*/
-
-/* On-Chip Debug System */
-typedef struct OCD_struct
-{
-    register8_t OCDR0;  /* OCD Register 0 */
-    register8_t OCDR1;  /* OCD Register 1 */
-} OCD_t;
-
-
-/* CCP signatures */
-typedef enum CCP_enum
-{
-    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
-    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
-} CCP_t;
-
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Clock System */
-typedef struct CLK_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t PSCTRL;  /* Prescaler Control Register */
-    register8_t LOCK;  /* Lock register */
-    register8_t RTCCTRL;  /* RTC Control Register */
-} CLK_t;
-
-/*
---------------------------------------------------------------------------
-CLK - Clock System
---------------------------------------------------------------------------
-*/
-
-/* Power Reduction */
-typedef struct PR_struct
-{
-    register8_t PRGEN;  /* General Power Reduction */
-    register8_t PRPA;  /* Power Reduction Port A */
-    register8_t PRPB;  /* Power Reduction Port B */
-    register8_t PRPC;  /* Power Reduction Port C */
-    register8_t PRPD;  /* Power Reduction Port D */
-    register8_t PRPE;  /* Power Reduction Port E */
-    register8_t PRPF;  /* Power Reduction Port F */
-} PR_t;
-
-/* System Clock Selection */
-typedef enum CLK_SCLKSEL_enum
-{
-    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
-    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
-    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
-    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
-} CLK_SCLKSEL_t;
-
-/* Prescaler A Division Factor */
-typedef enum CLK_PSADIV_enum
-{
-    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
-    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
-    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
-    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
-    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
-    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
-    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
-    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
-    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
-    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
-} CLK_PSADIV_t;
-
-/* Prescaler B and C Division Factor */
-typedef enum CLK_PSBCDIV_enum
-{
-    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
-    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
-    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
-    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
-} CLK_PSBCDIV_t;
-
-/* RTC Clock Source */
-typedef enum CLK_RTCSRC_enum
-{
-    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
-} CLK_RTCSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-SLEEP - Sleep Controller
---------------------------------------------------------------------------
-*/
-
-/* Sleep Controller */
-typedef struct SLEEP_struct
-{
-    register8_t CTRL;  /* Control Register */
-} SLEEP_t;
-
-/* Sleep Mode */
-typedef enum SLEEP_SMODE_enum
-{
-    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
-    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
-    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
-    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
-    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
-} SLEEP_SMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-OSC - Oscillator
---------------------------------------------------------------------------
-*/
-
-/* Oscillator */
-typedef struct OSC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
-    register8_t PLLCTRL;  /* PLL Control REgister */
-    register8_t DFLLCTRL;  /* DFLL Control Register */
-} OSC_t;
-
-/* Oscillator Frequency Range */
-typedef enum OSC_FRQRANGE_enum
-{
-    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
-    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
-    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
-    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
-} OSC_FRQRANGE_t;
-
-/* External Oscillator Selection and Startup Time */
-typedef enum OSC_XOSCSEL_enum
-{
-    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
-    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
-    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
-    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
-    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
-} OSC_XOSCSEL_t;
-
-/* PLL Clock Source */
-typedef enum OSC_PLLSRC_enum
-{
-    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
-    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
-    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
-} OSC_PLLSRC_t;
-
-
-/*
---------------------------------------------------------------------------
-DFLL - DFLL
---------------------------------------------------------------------------
-*/
-
-/* DFLL */
-typedef struct DFLL_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t CALA;  /* Calibration Register A */
-    register8_t CALB;  /* Calibration Register B */
-    register8_t COMP0;  /* Oscillator Compare Register 0 */
-    register8_t COMP1;  /* Oscillator Compare Register 1 */
-    register8_t COMP2;  /* Oscillator Compare Register 2 */
-    register8_t reserved_0x07;
-} DFLL_t;
-
-
-/*
---------------------------------------------------------------------------
-RST - Reset
---------------------------------------------------------------------------
-*/
-
-/* Reset */
-typedef struct RST_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t CTRL;  /* Control Register */
-} RST_t;
-
-
-/*
---------------------------------------------------------------------------
-WDT - Watch-Dog Timer
---------------------------------------------------------------------------
-*/
-
-/* Watch-Dog Timer */
-typedef struct WDT_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t WINCTRL;  /* Windowed Mode Control */
-    register8_t STATUS;  /* Status */
-} WDT_t;
-
-/* Period setting */
-typedef enum WDT_PER_enum
-{
-    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_PER_t;
-
-/* Closed window period */
-typedef enum WDT_WPER_enum
-{
-    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
-    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
-    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
-    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
-    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
-    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
-    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
-    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
-    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
-    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
-    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
-} WDT_WPER_t;
-
-
-/*
---------------------------------------------------------------------------
-MCU - MCU Control
---------------------------------------------------------------------------
-*/
-
-/* MCU Control */
-typedef struct MCU_struct
-{
-    register8_t DEVID0;  /* Device ID byte 0 */
-    register8_t DEVID1;  /* Device ID byte 1 */
-    register8_t DEVID2;  /* Device ID byte 2 */
-    register8_t REVID;  /* Revision ID */
-    register8_t JTAGUID;  /* JTAG User ID */
-    register8_t reserved_0x05;
-    register8_t MCUCR;  /* MCU Control */
-    register8_t reserved_0x07;
-    register8_t EVSYSLOCK;  /* Event System Lock */
-    register8_t AWEXLOCK;  /* AWEX Lock */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-} MCU_t;
-
-
-/*
---------------------------------------------------------------------------
-PMIC - Programmable Multi-level Interrupt Controller
---------------------------------------------------------------------------
-*/
-
-/* Programmable Multi-level Interrupt Controller */
-typedef struct PMIC_struct
-{
-    register8_t STATUS;  /* Status Register */
-    register8_t INTPRI;  /* Interrupt Priority */
-    register8_t CTRL;  /* Control Register */
-} PMIC_t;
-
-
-/*
---------------------------------------------------------------------------
-EVSYS - Event System
---------------------------------------------------------------------------
-*/
-
-/* Event System */
-typedef struct EVSYS_struct
-{
-    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
-    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
-    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
-    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
-    register8_t CH0CTRL;  /* Channel 0 Control Register */
-    register8_t CH1CTRL;  /* Channel 1 Control Register */
-    register8_t CH2CTRL;  /* Channel 2 Control Register */
-    register8_t CH3CTRL;  /* Channel 3 Control Register */
-    register8_t STROBE;  /* Event Strobe */
-    register8_t DATA;  /* Event Data */
-} EVSYS_t;
-
-/* Quadrature Decoder Index Recognition Mode */
-typedef enum EVSYS_QDIRM_enum
-{
-    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
-    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
-    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
-    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
-} EVSYS_QDIRM_t;
-
-/* Digital filter coefficient */
-typedef enum EVSYS_DIGFILT_enum
-{
-    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
-    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
-    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
-    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
-    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
-    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
-    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
-    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
-} EVSYS_DIGFILT_t;
-
-/* Event Channel multiplexer input selection */
-typedef enum EVSYS_CHMUX_enum
-{
-    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
-    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
-    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
-    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
-    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
-    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
-    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
-    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
-    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
-    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
-    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
-    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
-    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
-    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
-    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
-    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
-    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
-    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
-    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
-    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
-    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
-    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
-    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
-    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
-    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
-    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
-    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
-    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
-    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
-    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
-    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
-    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
-    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
-    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
-    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
-    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
-    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
-    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
-    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
-    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
-    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
-    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
-    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
-    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
-    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
-    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
-    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
-    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
-    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
-    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
-    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
-    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
-    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
-    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
-    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
-    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
-    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
-    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
-    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
-    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
-    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
-    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
-    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
-    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
-    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
-    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
-    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
-    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
-    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
-    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
-    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
-    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
-    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
-    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
-    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
-    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
-    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
-    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
-} EVSYS_CHMUX_t;
-
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Non-volatile Memory Controller */
-typedef struct NVM_struct
-{
-    register8_t ADDR0;  /* Address Register 0 */
-    register8_t ADDR1;  /* Address Register 1 */
-    register8_t ADDR2;  /* Address Register 2 */
-    register8_t reserved_0x03;
-    register8_t DATA0;  /* Data Register 0 */
-    register8_t DATA1;  /* Data Register 1 */
-    register8_t DATA2;  /* Data Register 2 */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t CMD;  /* Command */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t INTCTRL;  /* Interrupt Control */
-    register8_t reserved_0x0E;
-    register8_t STATUS;  /* Status */
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Lock Bits */
-typedef struct NVM_LOCKBITS_struct
-{
-    register8_t LOCKBITS;  /* Lock Bits */
-} NVM_LOCKBITS_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Fuses */
-typedef struct NVM_FUSES_struct
-{
-    register8_t FUSEBYTE0;  /* User ID */
-    register8_t FUSEBYTE1;  /* Watchdog Configuration */
-    register8_t FUSEBYTE2;  /* Reset Configuration */
-    register8_t reserved_0x03;
-    register8_t FUSEBYTE4;  /* Start-up Configuration */
-    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
-} NVM_FUSES_t;
-
-/*
---------------------------------------------------------------------------
-NVM - Non Volatile Memory Controller
---------------------------------------------------------------------------
-*/
-
-/* Production Signatures */
-typedef struct NVM_PROD_SIGNATURES_struct
-{
-    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
-    register8_t reserved_0x01;
-    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
-    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
-    register8_t reserved_0x04;
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
-    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
-    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
-    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
-    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
-    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t WAFNUM;  /* Wafer Number */
-    register8_t reserved_0x11;
-    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
-    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
-    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
-    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
-    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
-    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
-    register8_t reserved_0x26;
-    register8_t reserved_0x27;
-    register8_t reserved_0x28;
-    register8_t reserved_0x29;
-    register8_t reserved_0x2A;
-    register8_t reserved_0x2B;
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
-    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
-    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
-    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
-    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    register8_t reserved_0x36;
-    register8_t reserved_0x37;
-    register8_t reserved_0x38;
-    register8_t reserved_0x39;
-    register8_t reserved_0x3A;
-    register8_t reserved_0x3B;
-    register8_t reserved_0x3C;
-    register8_t reserved_0x3D;
-    register8_t reserved_0x3E;
-} NVM_PROD_SIGNATURES_t;
-
-/* NVM Command */
-typedef enum NVM_CMD_enum
-{
-    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
-    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
-    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
-    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
-    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
-    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
-    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
-    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
-    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
-    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
-    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
-    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
-    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
-    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
-    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
-    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
-    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
-    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
-    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
-} NVM_CMD_t;
-
-/* SPM ready interrupt level */
-typedef enum NVM_SPMLVL_enum
-{
-    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
-    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
-    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
-    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
-} NVM_SPMLVL_t;
-
-/* EEPROM ready interrupt level */
-typedef enum NVM_EELVL_enum
-{
-    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
-    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
-    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
-} NVM_EELVL_t;
-
-/* Boot lock bits - boot setcion */
-typedef enum NVM_BLBB_enum
-{
-    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
-    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
-    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
-    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
-} NVM_BLBB_t;
-
-/* Boot lock bits - application section */
-typedef enum NVM_BLBA_enum
-{
-    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
-    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
-    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
-    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
-} NVM_BLBA_t;
-
-/* Boot lock bits - application table section */
-typedef enum NVM_BLBAT_enum
-{
-    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
-    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
-    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
-    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
-} NVM_BLBAT_t;
-
-/* Lock bits */
-typedef enum NVM_LB_enum
-{
-    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
-    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
-    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
-} NVM_LB_t;
-
-/* Boot Loader Section Reset Vector */
-typedef enum BOOTRST_enum
-{
-    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
-    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
-} BOOTRST_t;
-
-/* BOD operation */
-typedef enum BOD_enum
-{
-    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
-    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
-    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
-} BOD_t;
-
-/* Watchdog (Window) Timeout Period */
-typedef enum WD_enum
-{
-    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
-    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
-    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
-    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
-    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
-    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
-    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
-    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
-    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
-    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
-    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
-} WD_t;
-
-/* Start-up Time */
-typedef enum SUT_enum
-{
-    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
-    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
-    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
-} SUT_t;
-
-/* Brown Out Detection Voltage Level */
-typedef enum BODLVL_enum
-{
-    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
-    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
-    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
-    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
-    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
-    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
-    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
-} BODLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-AC - Analog Comparator
---------------------------------------------------------------------------
-*/
-
-/* Analog Comparator */
-typedef struct AC_struct
-{
-    register8_t AC0CTRL;  /* Comparator 0 Control */
-    register8_t AC1CTRL;  /* Comparator 1 Control */
-    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
-    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t WINCTRL;  /* Window Mode Control */
-    register8_t STATUS;  /* Status */
-} AC_t;
-
-/* Interrupt mode */
-typedef enum AC_INTMODE_enum
-{
-    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
-    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
-    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
-} AC_INTMODE_t;
-
-/* Interrupt level */
-typedef enum AC_INTLVL_enum
-{
-    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
-    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
-    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
-    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
-} AC_INTLVL_t;
-
-/* Hysteresis mode selection */
-typedef enum AC_HYSMODE_enum
-{
-    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
-    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
-    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
-} AC_HYSMODE_t;
-
-/* Positive input multiplexer selection */
-typedef enum AC_MUXPOS_enum
-{
-    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
-    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
-    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
-    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
-    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
-    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
-    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
-    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
-} AC_MUXPOS_t;
-
-/* Negative input multiplexer selection */
-typedef enum AC_MUXNEG_enum
-{
-    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
-    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
-    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
-    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
-    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
-    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
-    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
-    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
-} AC_MUXNEG_t;
-
-/* Windows interrupt mode */
-typedef enum AC_WINTMODE_enum
-{
-    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
-    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
-    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
-    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
-} AC_WINTMODE_t;
-
-/* Window interrupt level */
-typedef enum AC_WINTLVL_enum
-{
-    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
-    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
-    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
-} AC_WINTLVL_t;
-
-/* Window mode state */
-typedef enum AC_WSTATE_enum
-{
-    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
-    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
-    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
-} AC_WSTATE_t;
-
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* ADC Channel */
-typedef struct ADC_CH_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t MUXCTRL;  /* MUX Control */
-    register8_t INTCTRL;  /* Channel Interrupt Control */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    _WORDREGISTER(RES);  /* Channel Result */
-    register8_t reserved_0x6;
-    register8_t reserved_0x7;
-} ADC_CH_t;
-
-/*
---------------------------------------------------------------------------
-ADC - Analog/Digital Converter
---------------------------------------------------------------------------
-*/
-
-/* Analog-to-Digital Converter */
-typedef struct ADC_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t REFCTRL;  /* Reference Control */
-    register8_t EVCTRL;  /* Event Control */
-    register8_t PRESCALER;  /* Clock Prescaler */
-    register8_t CALCTRL;  /* Calibration Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t reserved_0x07;
-    register8_t reserved_0x08;
-    register8_t reserved_0x09;
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    _WORDREGISTER(CAL);  /* Calibration Value */
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
-    _WORDREGISTER(CMP);  /* Compare Value */
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    ADC_CH_t CH0;  /* ADC Channel 0 */
-} ADC_t;
-
-/* Positive input multiplexer selection */
-typedef enum ADC_CH_MUXPOS_enum
-{
-    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
-    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
-    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
-    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
-    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
-    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
-    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
-    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
-} ADC_CH_MUXPOS_t;
-
-/* Internal input multiplexer selections */
-typedef enum ADC_CH_MUXINT_enum
-{
-    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
-    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
-    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
-    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
-} ADC_CH_MUXINT_t;
-
-/* Negative input multiplexer selection */
-typedef enum ADC_CH_MUXNEG_enum
-{
-    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
-    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
-    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
-    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
-    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
-    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
-    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
-    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
-} ADC_CH_MUXNEG_t;
-
-/* Input mode */
-typedef enum ADC_CH_INPUTMODE_enum
-{
-    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
-    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
-} ADC_CH_INPUTMODE_t;
-
-/* Gain factor */
-typedef enum ADC_CH_GAIN_enum
-{
-    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
-    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
-    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
-    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
-    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
-    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
-    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
-} ADC_CH_GAIN_t;
-
-/* Conversion result resolution */
-typedef enum ADC_RESOLUTION_enum
-{
-    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
-    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
-} ADC_RESOLUTION_t;
-
-/* Voltage reference selection */
-typedef enum ADC_REFSEL_enum
-{
-    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
-    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
-    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
-    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
-} ADC_REFSEL_t;
-
-/* Channel sweep selection */
-typedef enum ADC_SWEEP_enum
-{
-    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
-} ADC_SWEEP_t;
-
-/* Event channel input selection */
-typedef enum ADC_EVSEL_enum
-{
-    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
-    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
-    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
-    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
-    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
-    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
-    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
-    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
-} ADC_EVSEL_t;
-
-/* Event action selection */
-typedef enum ADC_EVACT_enum
-{
-    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
-    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
-} ADC_EVACT_t;
-
-/* Interupt mode */
-typedef enum ADC_CH_INTMODE_enum
-{
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
-} ADC_CH_INTMODE_t;
-
-/* Interrupt level */
-typedef enum ADC_CH_INTLVL_enum
-{
-    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
-    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
-    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
-    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
-} ADC_CH_INTLVL_t;
-
-/* Clock prescaler */
-typedef enum ADC_PRESCALER_enum
-{
-    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
-    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
-    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
-    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
-    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
-    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
-    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
-    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
-} ADC_PRESCALER_t;
-
-
-/*
---------------------------------------------------------------------------
-RTC - Real-Time Clounter
---------------------------------------------------------------------------
-*/
-
-/* Real-Time Counter */
-typedef struct RTC_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INTFLAGS;  /* Interrupt Flags */
-    register8_t TEMP;  /* Temporary register */
-    register8_t reserved_0x05;
-    register8_t reserved_0x06;
-    register8_t reserved_0x07;
-    _WORDREGISTER(CNT);  /* Count Register */
-    _WORDREGISTER(PER);  /* Period Register */
-    _WORDREGISTER(COMP);  /* Compare Register */
-} RTC_t;
-
-/* Prescaler Factor */
-typedef enum RTC_PRESCALER_enum
-{
-    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
-    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
-    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
-    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
-    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
-    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
-    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
-    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
-} RTC_PRESCALER_t;
-
-/* Compare Interrupt level */
-typedef enum RTC_COMPINTLVL_enum
-{
-    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} RTC_COMPINTLVL_t;
-
-/* Overflow Interrupt level */
-typedef enum RTC_OVFINTLVL_enum
-{
-    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} RTC_OVFINTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* EBI Chip Select Module */
-typedef struct EBI_CS_struct
-{
-    register8_t CTRLA;  /* Chip Select Control Register A */
-    register8_t CTRLB;  /* Chip Select Control Register B */
-    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
-} EBI_CS_t;
-
-/*
---------------------------------------------------------------------------
-EBI - External Bus Interface
---------------------------------------------------------------------------
-*/
-
-/* External Bus Interface */
-typedef struct EBI_struct
-{
-    register8_t CTRL;  /* Control */
-    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
-    register8_t reserved_0x02;
-    register8_t reserved_0x03;
-    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
-    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
-    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
-    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
-    register8_t reserved_0x0A;
-    register8_t reserved_0x0B;
-    register8_t reserved_0x0C;
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    EBI_CS_t CS0;  /* Chip Select 0 */
-    EBI_CS_t CS1;  /* Chip Select 1 */
-    EBI_CS_t CS2;  /* Chip Select 2 */
-    EBI_CS_t CS3;  /* Chip Select 3 */
-} EBI_t;
-
-/* Chip Select adress space */
-typedef enum EBI_CS_ASPACE_enum
-{
-    EBI_CS_ASPACE_256B_gc = (0x00<<2),  /* 256 bytes */
-    EBI_CS_ASPACE_512B_gc = (0x01<<2),  /* 512 bytes */
-    EBI_CS_ASPACE_1KB_gc = (0x02<<2),  /* 1K bytes */
-    EBI_CS_ASPACE_2KB_gc = (0x03<<2),  /* 2K bytes */
-    EBI_CS_ASPACE_4KB_gc = (0x04<<2),  /* 4K bytes */
-    EBI_CS_ASPACE_8KB_gc = (0x05<<2),  /* 8K bytes */
-    EBI_CS_ASPACE_16KB_gc = (0x06<<2),  /* 16K bytes */
-    EBI_CS_ASPACE_32KB_gc = (0x07<<2),  /* 32K bytes */
-    EBI_CS_ASPACE_64KB_gc = (0x08<<2),  /* 64K bytes */
-    EBI_CS_ASPACE_128KB_gc = (0x09<<2),  /* 128K bytes */
-    EBI_CS_ASPACE_256KB_gc = (0x0A<<2),  /* 256K bytes */
-    EBI_CS_ASPACE_512KB_gc = (0x0B<<2),  /* 512K bytes */
-    EBI_CS_ASPACE_1MB_gc = (0x0C<<2),  /* 1M bytes */
-    EBI_CS_ASPACE_2MB_gc = (0x0D<<2),  /* 2M bytes */
-    EBI_CS_ASPACE_4MB_gc = (0x0E<<2),  /* 4M bytes */
-    EBI_CS_ASPACE_8MB_gc = (0x0F<<2),  /* 8M bytes */
-    EBI_CS_ASPACE_16M_gc = (0x10<<2),  /* 16M bytes */
-} EBI_CS_ASPACE_t;
-
-/*  */
-typedef enum EBI_CS_SRWS_enum
-{
-    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_CS_SRWS_t;
-
-/* Chip Select address mode */
-typedef enum EBI_CS_MODE_enum
-{
-    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
-    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
-    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
-    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
-} EBI_CS_MODE_t;
-
-/* Chip Select SDRAM mode */
-typedef enum EBI_CS_SDMODE_enum
-{
-    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
-    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
-} EBI_CS_SDMODE_t;
-
-/*  */
-typedef enum EBI_SDDATAW_enum
-{
-    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
-    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
-} EBI_SDDATAW_t;
-
-/*  */
-typedef enum EBI_LPCMODE_enum
-{
-    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
-    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
-} EBI_LPCMODE_t;
-
-/*  */
-typedef enum EBI_SRMODE_enum
-{
-    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
-    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
-    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
-    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
-} EBI_SRMODE_t;
-
-/*  */
-typedef enum EBI_IFMODE_enum
-{
-    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
-    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
-    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
-    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
-} EBI_IFMODE_t;
-
-/*  */
-typedef enum EBI_SDCOL_enum
-{
-    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
-    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
-    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
-    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
-} EBI_SDCOL_t;
-
-/*  */
-typedef enum EBI_MRDLY_enum
-{
-    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_MRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCYCDLY_enum
-{
-    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ROWCYCDLY_t;
-
-/*  */
-typedef enum EBI_RPDLY_enum
-{
-    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_RPDLY_t;
-
-/*  */
-typedef enum EBI_WRDLY_enum
-{
-    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
-    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
-    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
-    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
-} EBI_WRDLY_t;
-
-/*  */
-typedef enum EBI_ESRDLY_enum
-{
-    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
-    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
-    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
-    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
-    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
-    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
-    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
-    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
-} EBI_ESRDLY_t;
-
-/*  */
-typedef enum EBI_ROWCOLDLY_enum
-{
-    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
-    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
-    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
-    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
-    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
-    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
-    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
-    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
-} EBI_ROWCOLDLY_t;
-
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_MASTER_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t STATUS;  /* Status Register */
-    register8_t BAUD;  /* Baurd Rate Control Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-} TWI_MASTER_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/*  */
-typedef struct TWI_SLAVE_struct
-{
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t STATUS;  /* Status Register */
-    register8_t ADDR;  /* Address Register */
-    register8_t DATA;  /* Data Register */
-    register8_t ADDRMASK;  /* Address Mask Register */
-} TWI_SLAVE_t;
-
-/*
---------------------------------------------------------------------------
-TWI - Two-Wire Interface
---------------------------------------------------------------------------
-*/
-
-/* Two-Wire Interface */
-typedef struct TWI_struct
-{
-    register8_t CTRL;  /* TWI Common Control Register */
-    TWI_MASTER_t MASTER;  /* TWI master module */
-    TWI_SLAVE_t SLAVE;  /* TWI slave module */
-} TWI_t;
-
-/* Master Interrupt Level */
-typedef enum TWI_MASTER_INTLVL_enum
-{
-    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_MASTER_INTLVL_t;
-
-/* Inactive Timeout */
-typedef enum TWI_MASTER_TIMEOUT_enum
-{
-    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
-    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
-    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
-    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
-} TWI_MASTER_TIMEOUT_t;
-
-/* Master Command */
-typedef enum TWI_MASTER_CMD_enum
-{
-    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
-    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
-    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
-} TWI_MASTER_CMD_t;
-
-/* Master Bus State */
-typedef enum TWI_MASTER_BUSSTATE_enum
-{
-    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
-    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
-    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
-} TWI_MASTER_BUSSTATE_t;
-
-/* Slave Interrupt Level */
-typedef enum TWI_SLAVE_INTLVL_enum
-{
-    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TWI_SLAVE_INTLVL_t;
-
-/* Slave Command */
-typedef enum TWI_SLAVE_CMD_enum
-{
-    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
-} TWI_SLAVE_CMD_t;
-
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O port Configuration */
-typedef struct PORTCFG_struct
-{
-    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
-    register8_t reserved_0x01;
-    register8_t VPCTRLA;  /* Virtual Port Control Register A */
-    register8_t VPCTRLB;  /* Virtual Port Control Register B */
-    register8_t CLKEVOUT;  /* Clock and Event Out Register */
-} PORTCFG_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* Virtual Port */
-typedef struct VPORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t IN;  /* I/O Port Input */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-} VPORT_t;
-
-/*
---------------------------------------------------------------------------
-PORT - Port Configuration
---------------------------------------------------------------------------
-*/
-
-/* I/O Ports */
-typedef struct PORT_struct
-{
-    register8_t DIR;  /* I/O Port Data Direction */
-    register8_t DIRSET;  /* I/O Port Data Direction Set */
-    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
-    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
-    register8_t OUT;  /* I/O Port Output */
-    register8_t OUTSET;  /* I/O Port Output Set */
-    register8_t OUTCLR;  /* I/O Port Output Clear */
-    register8_t OUTTGL;  /* I/O Port Output Toggle */
-    register8_t IN;  /* I/O port Input */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
-    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t reserved_0x0F;
-    register8_t PIN0CTRL;  /* Pin 0 Control Register */
-    register8_t PIN1CTRL;  /* Pin 1 Control Register */
-    register8_t PIN2CTRL;  /* Pin 2 Control Register */
-    register8_t PIN3CTRL;  /* Pin 3 Control Register */
-    register8_t PIN4CTRL;  /* Pin 4 Control Register */
-    register8_t PIN5CTRL;  /* Pin 5 Control Register */
-    register8_t PIN6CTRL;  /* Pin 6 Control Register */
-    register8_t PIN7CTRL;  /* Pin 7 Control Register */
-} PORT_t;
-
-/* Virtual Port 0 Mapping */
-typedef enum PORTCFG_VP0MAP_enum
-{
-    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP0MAP_t;
-
-/* Virtual Port 1 Mapping */
-typedef enum PORTCFG_VP1MAP_enum
-{
-    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP1MAP_t;
-
-/* Virtual Port 2 Mapping */
-typedef enum PORTCFG_VP2MAP_enum
-{
-    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
-    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
-    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
-    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
-    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
-    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
-    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
-    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
-    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
-    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
-    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
-    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
-    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
-    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
-    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
-    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
-} PORTCFG_VP2MAP_t;
-
-/* Virtual Port 3 Mapping */
-typedef enum PORTCFG_VP3MAP_enum
-{
-    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
-    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
-    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
-    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
-    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
-    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
-    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
-    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
-    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
-    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
-    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
-    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
-    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
-    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
-    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
-    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
-} PORTCFG_VP3MAP_t;
-
-/* Clock Output Port */
-typedef enum PORTCFG_CLKOUT_enum
-{
-    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
-    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
-    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
-    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
-} PORTCFG_CLKOUT_t;
-
-/* Event Output Port */
-typedef enum PORTCFG_EVOUT_enum
-{
-    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
-} PORTCFG_EVOUT_t;
-
-/* Port Interrupt 0 Level */
-typedef enum PORT_INT0LVL_enum
-{
-    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
-    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
-    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
-} PORT_INT0LVL_t;
-
-/* Port Interrupt 1 Level */
-typedef enum PORT_INT1LVL_enum
-{
-    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
-    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
-    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
-} PORT_INT1LVL_t;
-
-/* Output/Pull Configuration */
-typedef enum PORT_OPC_enum
-{
-    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
-    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
-    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
-    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
-    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
-    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
-    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
-} PORT_OPC_t;
-
-/* Input/Sense Configuration */
-typedef enum PORT_ISC_enum
-{
-    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
-    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
-    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
-    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
-    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
-} PORT_ISC_t;
-
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 0 */
-typedef struct TC0_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    _WORDREGISTER(CCC);  /* Compare or Capture C */
-    _WORDREGISTER(CCD);  /* Compare or Capture D */
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
-    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
-} TC0_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* 16-bit Timer/Counter 1 */
-typedef struct TC1_struct
-{
-    register8_t CTRLA;  /* Control  Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control register C */
-    register8_t CTRLD;  /* Control Register D */
-    register8_t CTRLE;  /* Control Register E */
-    register8_t reserved_0x05;
-    register8_t INTCTRLA;  /* Interrupt Control Register A */
-    register8_t INTCTRLB;  /* Interrupt Control Register B */
-    register8_t CTRLFCLR;  /* Control Register F Clear */
-    register8_t CTRLFSET;  /* Control Register F Set */
-    register8_t CTRLGCLR;  /* Control Register G Clear */
-    register8_t CTRLGSET;  /* Control Register G Set */
-    register8_t INTFLAGS;  /* Interrupt Flag Register */
-    register8_t reserved_0x0D;
-    register8_t reserved_0x0E;
-    register8_t TEMP;  /* Temporary Register For 16-bit Access */
-    register8_t reserved_0x10;
-    register8_t reserved_0x11;
-    register8_t reserved_0x12;
-    register8_t reserved_0x13;
-    register8_t reserved_0x14;
-    register8_t reserved_0x15;
-    register8_t reserved_0x16;
-    register8_t reserved_0x17;
-    register8_t reserved_0x18;
-    register8_t reserved_0x19;
-    register8_t reserved_0x1A;
-    register8_t reserved_0x1B;
-    register8_t reserved_0x1C;
-    register8_t reserved_0x1D;
-    register8_t reserved_0x1E;
-    register8_t reserved_0x1F;
-    _WORDREGISTER(CNT);  /* Count */
-    register8_t reserved_0x22;
-    register8_t reserved_0x23;
-    register8_t reserved_0x24;
-    register8_t reserved_0x25;
-    _WORDREGISTER(PER);  /* Period */
-    _WORDREGISTER(CCA);  /* Compare or Capture A */
-    _WORDREGISTER(CCB);  /* Compare or Capture B */
-    register8_t reserved_0x2C;
-    register8_t reserved_0x2D;
-    register8_t reserved_0x2E;
-    register8_t reserved_0x2F;
-    register8_t reserved_0x30;
-    register8_t reserved_0x31;
-    register8_t reserved_0x32;
-    register8_t reserved_0x33;
-    register8_t reserved_0x34;
-    register8_t reserved_0x35;
-    _WORDREGISTER(PERBUF);  /* Period Buffer */
-    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
-    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
-} TC1_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* Advanced Waveform Extension */
-typedef struct AWEX_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t reserved_0x01;
-    register8_t FDEMASK;  /* Fault Detection Event Mask */
-    register8_t FDCTRL;  /* Fault Detection Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x05;
-    register8_t DTBOTH;  /* Dead Time Both Sides */
-    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
-    register8_t DTLS;  /* Dead Time Low Side */
-    register8_t DTHS;  /* Dead Time High Side */
-    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
-    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
-    register8_t OUTOVEN;  /* Output Override Enable */
-} AWEX_t;
-
-/*
---------------------------------------------------------------------------
-TC - 16-bit Timer/Counter With PWM
---------------------------------------------------------------------------
-*/
-
-/* High-Resolution Extension */
-typedef struct HIRES_struct
-{
-    register8_t CTRLA;  /* Control Register */
-} HIRES_t;
-
-/* Clock Selection */
-typedef enum TC_CLKSEL_enum
-{
-    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
-    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
-    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
-    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
-    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
-    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
-    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
-    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
-    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_CLKSEL_t;
-
-/* Waveform Generation Mode */
-typedef enum TC_WGMODE_enum
-{
-    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
-    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
-    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
-    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
-    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
-} TC_WGMODE_t;
-
-/* Event Action */
-typedef enum TC_EVACT_enum
-{
-    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
-    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
-    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
-    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
-    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
-    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
-    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
-} TC_EVACT_t;
-
-/* Event Selection */
-typedef enum TC_EVSEL_enum
-{
-    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
-    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
-    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
-    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
-    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
-    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
-    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
-    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
-} TC_EVSEL_t;
-
-/* Error Interrupt Level */
-typedef enum TC_ERRINTLVL_enum
-{
-    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_ERRINTLVL_t;
-
-/* Overflow Interrupt Level */
-typedef enum TC_OVFINTLVL_enum
-{
-    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_OVFINTLVL_t;
-
-/* Compare or Capture D Interrupt Level */
-typedef enum TC_CCDINTLVL_enum
-{
-    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
-    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
-    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
-    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
-} TC_CCDINTLVL_t;
-
-/* Compare or Capture C Interrupt Level */
-typedef enum TC_CCCINTLVL_enum
-{
-    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} TC_CCCINTLVL_t;
-
-/* Compare or Capture B Interrupt Level */
-typedef enum TC_CCBINTLVL_enum
-{
-    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} TC_CCBINTLVL_t;
-
-/* Compare or Capture A Interrupt Level */
-typedef enum TC_CCAINTLVL_enum
-{
-    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} TC_CCAINTLVL_t;
-
-/* Timer/Counter Command */
-typedef enum TC_CMD_enum
-{
-    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
-    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
-    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
-    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
-} TC_CMD_t;
-
-/* Fault Detect Action */
-typedef enum AWEX_FDACT_enum
-{
-    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
-    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
-} AWEX_FDACT_t;
-
-/* High Resolution Enable */
-typedef enum HIRES_HREN_enum
-{
-    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
-} HIRES_HREN_t;
-
-
-/*
---------------------------------------------------------------------------
-USART - Universal Asynchronous Receiver-Transmitter
---------------------------------------------------------------------------
-*/
-
-/* Universal Synchronous/Asynchronous Receiver/Transmitter */
-typedef struct USART_struct
-{
-    register8_t DATA;  /* Data Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t reserved_0x02;
-    register8_t CTRLA;  /* Control Register A */
-    register8_t CTRLB;  /* Control Register B */
-    register8_t CTRLC;  /* Control Register C */
-    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
-    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
-} USART_t;
-
-/* Receive Complete Interrupt level */
-typedef enum USART_RXCINTLVL_enum
-{
-    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
-    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
-    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
-    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
-} USART_RXCINTLVL_t;
-
-/* Transmit Complete Interrupt level */
-typedef enum USART_TXCINTLVL_enum
-{
-    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
-    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
-    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
-    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
-} USART_TXCINTLVL_t;
-
-/* Data Register Empty Interrupt level */
-typedef enum USART_DREINTLVL_enum
-{
-    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
-} USART_DREINTLVL_t;
-
-/* Character Size */
-typedef enum USART_CHSIZE_enum
-{
-    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
-    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
-    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
-    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
-    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
-} USART_CHSIZE_t;
-
-/* Communication Mode */
-typedef enum USART_CMODE_enum
-{
-    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
-    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
-    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
-    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
-} USART_CMODE_t;
-
-/* Parity Mode */
-typedef enum USART_PMODE_enum
-{
-    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
-    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
-    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
-} USART_PMODE_t;
-
-
-/*
---------------------------------------------------------------------------
-SPI - Serial Peripheral Interface
---------------------------------------------------------------------------
-*/
-
-/* Serial Peripheral Interface */
-typedef struct SPI_struct
-{
-    register8_t CTRL;  /* Control Register */
-    register8_t INTCTRL;  /* Interrupt Control Register */
-    register8_t STATUS;  /* Status Register */
-    register8_t DATA;  /* Data Register */
-} SPI_t;
-
-/* SPI Mode */
-typedef enum SPI_MODE_enum
-{
-    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
-    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
-    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
-    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
-} SPI_MODE_t;
-
-/* Prescaler setting */
-typedef enum SPI_PRESCALER_enum
-{
-    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
-    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
-    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
-    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
-} SPI_PRESCALER_t;
-
-/* Interrupt level */
-typedef enum SPI_INTLVL_enum
-{
-    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
-    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
-    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
-    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
-} SPI_INTLVL_t;
-
-
-/*
---------------------------------------------------------------------------
-IRCOM - IR Communication Module
---------------------------------------------------------------------------
-*/
-
-/* IR Communication Module */
-typedef struct IRCOM_struct
-{
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
-    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
-    register8_t CTRL;  /* Control Register */
-} IRCOM_t;
-
-/* Event channel selection */
-typedef enum IRDA_EVSEL_enum
-{
-    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
-    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
-    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
-    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
-    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
-    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
-    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
-    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
-    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
-} IRDA_EVSEL_t;
-
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
-#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
-#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
-#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
-#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
-#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
-#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
-#define CPU    (*(CPU_t *) 0x0030)  /* CPU Registers */
-#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
-#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
-#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
-#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
-#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
-#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
-#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
-#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
-#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
-#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
-#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
-#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
-#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
-#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
-#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
-#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
-#define ACB    (*(AC_t *) 0x0390)  /* Analog Comparator B */
-#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
-#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
-#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
-#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
-#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
-#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
-#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
-#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
-#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
-#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
-#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
-#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
-#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
-#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
-#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
-#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
-#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
-#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
-
-
-#endif /* !defined (__ASSEMBLER__) */
-
-
-/* ========== Flattened fully qualified IO register names ========== */
-
-/* GPIO - General Purpose IO Registers */
-#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
-#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
-#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
-#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
-#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
-#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
-#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
-#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
-#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
-#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
-#define GPIO_GPIORA  _SFR_MEM8(0x000A)
-#define GPIO_GPIORB  _SFR_MEM8(0x000B)
-#define GPIO_GPIORC  _SFR_MEM8(0x000C)
-#define GPIO_GPIORD  _SFR_MEM8(0x000D)
-#define GPIO_GPIORE  _SFR_MEM8(0x000E)
-#define GPIO_GPIORF  _SFR_MEM8(0x000F)
-
-/* VPORT0 - Virtual Port 0 */
-#define VPORT0_DIR  _SFR_MEM8(0x0010)
-#define VPORT0_OUT  _SFR_MEM8(0x0011)
-#define VPORT0_IN  _SFR_MEM8(0x0012)
-#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
-
-/* VPORT1 - Virtual Port 1 */
-#define VPORT1_DIR  _SFR_MEM8(0x0014)
-#define VPORT1_OUT  _SFR_MEM8(0x0015)
-#define VPORT1_IN  _SFR_MEM8(0x0016)
-#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
-
-/* VPORT2 - Virtual Port 2 */
-#define VPORT2_DIR  _SFR_MEM8(0x0018)
-#define VPORT2_OUT  _SFR_MEM8(0x0019)
-#define VPORT2_IN  _SFR_MEM8(0x001A)
-#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
-
-/* VPORT3 - Virtual Port 3 */
-#define VPORT3_DIR  _SFR_MEM8(0x001C)
-#define VPORT3_OUT  _SFR_MEM8(0x001D)
-#define VPORT3_IN  _SFR_MEM8(0x001E)
-#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
-
-/* OCD - On-Chip Debug System */
-#define OCD_OCDR0  _SFR_MEM8(0x002E)
-#define OCD_OCDR1  _SFR_MEM8(0x002F)
-
-/* CPU - CPU Registers */
-#define CPU_CCP  _SFR_MEM8(0x0034)
-#define CPU_RAMPD  _SFR_MEM8(0x0038)
-#define CPU_RAMPX  _SFR_MEM8(0x0039)
-#define CPU_RAMPY  _SFR_MEM8(0x003A)
-#define CPU_RAMPZ  _SFR_MEM8(0x003B)
-#define CPU_EIND  _SFR_MEM8(0x003C)
-#define CPU_SPL  _SFR_MEM8(0x003D)
-#define CPU_SPH  _SFR_MEM8(0x003E)
-#define CPU_SREG  _SFR_MEM8(0x003F)
-
-/* CLK - Clock System */
-#define CLK_CTRL  _SFR_MEM8(0x0040)
-#define CLK_PSCTRL  _SFR_MEM8(0x0041)
-#define CLK_LOCK  _SFR_MEM8(0x0042)
-#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
-
-/* SLEEP - Sleep Controller */
-#define SLEEP_CTRL  _SFR_MEM8(0x0048)
-
-/* OSC - Oscillator Control */
-#define OSC_CTRL  _SFR_MEM8(0x0050)
-#define OSC_STATUS  _SFR_MEM8(0x0051)
-#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
-#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
-#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
-#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
-#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
-
-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
-#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
-#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
-#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
-#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
-#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
-#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
-
-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
-#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
-#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
-#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
-#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
-#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
-#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
-
-/* PR - Power Reduction */
-#define PR_PRGEN  _SFR_MEM8(0x0070)
-#define PR_PRPA  _SFR_MEM8(0x0071)
-#define PR_PRPB  _SFR_MEM8(0x0072)
-#define PR_PRPC  _SFR_MEM8(0x0073)
-#define PR_PRPD  _SFR_MEM8(0x0074)
-#define PR_PRPE  _SFR_MEM8(0x0075)
-#define PR_PRPF  _SFR_MEM8(0x0076)
-
-/* RST - Reset Controller */
-#define RST_STATUS  _SFR_MEM8(0x0078)
-#define RST_CTRL  _SFR_MEM8(0x0079)
-
-/* WDT - Watch-Dog Timer */
-#define WDT_CTRL  _SFR_MEM8(0x0080)
-#define WDT_WINCTRL  _SFR_MEM8(0x0081)
-#define WDT_STATUS  _SFR_MEM8(0x0082)
-
-/* MCU - MCU Control */
-#define MCU_DEVID0  _SFR_MEM8(0x0090)
-#define MCU_DEVID1  _SFR_MEM8(0x0091)
-#define MCU_DEVID2  _SFR_MEM8(0x0092)
-#define MCU_REVID  _SFR_MEM8(0x0093)
-#define MCU_JTAGUID  _SFR_MEM8(0x0094)
-#define MCU_MCUCR  _SFR_MEM8(0x0096)
-#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
-#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
-
-/* PMIC - Programmable Interrupt Controller */
-#define PMIC_STATUS  _SFR_MEM8(0x00A0)
-#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
-#define PMIC_CTRL  _SFR_MEM8(0x00A2)
-
-/* PORTCFG - Port Configuration */
-#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
-#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
-#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
-#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
-
-/* EVSYS - Event System */
-#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
-#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
-#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
-#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
-#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
-#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
-#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
-#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
-#define EVSYS_STROBE  _SFR_MEM8(0x0190)
-#define EVSYS_DATA  _SFR_MEM8(0x0191)
-
-/* NVM - Non Volatile Memory Controller */
-#define NVM_ADDR0  _SFR_MEM8(0x01C0)
-#define NVM_ADDR1  _SFR_MEM8(0x01C1)
-#define NVM_ADDR2  _SFR_MEM8(0x01C2)
-#define NVM_DATA0  _SFR_MEM8(0x01C4)
-#define NVM_DATA1  _SFR_MEM8(0x01C5)
-#define NVM_DATA2  _SFR_MEM8(0x01C6)
-#define NVM_CMD  _SFR_MEM8(0x01CA)
-#define NVM_CTRLA  _SFR_MEM8(0x01CB)
-#define NVM_CTRLB  _SFR_MEM8(0x01CC)
-#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
-#define NVM_STATUS  _SFR_MEM8(0x01CF)
-#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
-
-/* ADCA - Analog to Digital Converter A */
-#define ADCA_CTRLA  _SFR_MEM8(0x0200)
-#define ADCA_CTRLB  _SFR_MEM8(0x0201)
-#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
-#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
-#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
-#define ADCA_CALCTRL  _SFR_MEM8(0x0205)
-#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
-#define ADCA_CAL  _SFR_MEM16(0x020C)
-#define ADCA_CH0RES  _SFR_MEM16(0x0210)
-#define ADCA_CMP  _SFR_MEM16(0x0218)
-#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
-#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
-#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
-#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
-#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
-
-/* DACB - Digital to Analog Converter B */
-
-/* ACA - Analog Comparator A */
-#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
-#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
-#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
-#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
-#define ACA_CTRLA  _SFR_MEM8(0x0384)
-#define ACA_CTRLB  _SFR_MEM8(0x0385)
-#define ACA_WINCTRL  _SFR_MEM8(0x0386)
-#define ACA_STATUS  _SFR_MEM8(0x0387)
-
-/* ACB - Analog Comparator B */
-#define ACB_AC0CTRL  _SFR_MEM8(0x0390)
-#define ACB_AC1CTRL  _SFR_MEM8(0x0391)
-#define ACB_AC0MUXCTRL  _SFR_MEM8(0x0392)
-#define ACB_AC1MUXCTRL  _SFR_MEM8(0x0393)
-#define ACB_CTRLA  _SFR_MEM8(0x0394)
-#define ACB_CTRLB  _SFR_MEM8(0x0395)
-#define ACB_WINCTRL  _SFR_MEM8(0x0396)
-#define ACB_STATUS  _SFR_MEM8(0x0397)
-
-/* RTC - Real-Time Counter */
-#define RTC_CTRL  _SFR_MEM8(0x0400)
-#define RTC_STATUS  _SFR_MEM8(0x0401)
-#define RTC_INTCTRL  _SFR_MEM8(0x0402)
-#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
-#define RTC_TEMP  _SFR_MEM8(0x0404)
-#define RTC_CNT  _SFR_MEM16(0x0408)
-#define RTC_PER  _SFR_MEM16(0x040A)
-#define RTC_COMP  _SFR_MEM16(0x040C)
-
-/* TWIC - Two-Wire Interface C */
-#define TWIC_CTRL  _SFR_MEM8(0x0480)
-#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0482)
-#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0483)
-#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0484)
-#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0485)
-#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0486)
-#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0487)
-#define TWIC_MASTER_DATA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
-#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
-#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
-#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
-#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
-#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
-
-/* PORTA - Port A */
-#define PORTA_DIR  _SFR_MEM8(0x0600)
-#define PORTA_DIRSET  _SFR_MEM8(0x0601)
-#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
-#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
-#define PORTA_OUT  _SFR_MEM8(0x0604)
-#define PORTA_OUTSET  _SFR_MEM8(0x0605)
-#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
-#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
-#define PORTA_IN  _SFR_MEM8(0x0608)
-#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
-#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
-#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
-#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
-#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
-#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
-#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
-#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
-#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
-#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
-#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
-#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
-
-/* PORTB - Port B */
-#define PORTB_DIR  _SFR_MEM8(0x0620)
-#define PORTB_DIRSET  _SFR_MEM8(0x0621)
-#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
-#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
-#define PORTB_OUT  _SFR_MEM8(0x0624)
-#define PORTB_OUTSET  _SFR_MEM8(0x0625)
-#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
-#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
-#define PORTB_IN  _SFR_MEM8(0x0628)
-#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
-#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
-#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
-#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
-#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
-#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
-#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
-#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
-#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
-#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
-#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
-#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
-
-/* PORTC - Port C */
-#define PORTC_DIR  _SFR_MEM8(0x0640)
-#define PORTC_DIRSET  _SFR_MEM8(0x0641)
-#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
-#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
-#define PORTC_OUT  _SFR_MEM8(0x0644)
-#define PORTC_OUTSET  _SFR_MEM8(0x0645)
-#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
-#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
-#define PORTC_IN  _SFR_MEM8(0x0648)
-#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
-#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
-#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
-#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
-#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
-#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
-#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
-#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
-#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
-#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
-#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
-#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
-
-/* PORTD - Port D */
-#define PORTD_DIR  _SFR_MEM8(0x0660)
-#define PORTD_DIRSET  _SFR_MEM8(0x0661)
-#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
-#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
-#define PORTD_OUT  _SFR_MEM8(0x0664)
-#define PORTD_OUTSET  _SFR_MEM8(0x0665)
-#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
-#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
-#define PORTD_IN  _SFR_MEM8(0x0668)
-#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
-#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
-#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
-#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
-#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
-#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
-#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
-#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
-#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
-#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
-#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
-#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
-
-/* PORTE - Port E */
-#define PORTE_DIR  _SFR_MEM8(0x0680)
-#define PORTE_DIRSET  _SFR_MEM8(0x0681)
-#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
-#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
-#define PORTE_OUT  _SFR_MEM8(0x0684)
-#define PORTE_OUTSET  _SFR_MEM8(0x0685)
-#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
-#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
-#define PORTE_IN  _SFR_MEM8(0x0688)
-#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
-#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
-#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
-#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
-#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
-#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
-#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
-#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
-#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
-#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
-#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
-#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
-
-/* PORTF - Port F */
-#define PORTF_DIR  _SFR_MEM8(0x06A0)
-#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
-#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
-#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
-#define PORTF_OUT  _SFR_MEM8(0x06A4)
-#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
-#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
-#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
-#define PORTF_IN  _SFR_MEM8(0x06A8)
-#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
-#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
-#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
-#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
-#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
-#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
-#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
-#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
-#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
-#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
-#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
-#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
-
-/* PORTR - Port R */
-#define PORTR_DIR  _SFR_MEM8(0x07E0)
-#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
-#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
-#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
-#define PORTR_OUT  _SFR_MEM8(0x07E4)
-#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
-#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
-#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
-#define PORTR_IN  _SFR_MEM8(0x07E8)
-#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
-#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
-#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
-#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
-#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
-#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
-#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
-#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
-#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
-#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
-#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
-#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
-
-/* TCC0 - Timer/Counter C0 */
-#define TCC0_CTRLA  _SFR_MEM8(0x0800)
-#define TCC0_CTRLB  _SFR_MEM8(0x0801)
-#define TCC0_CTRLC  _SFR_MEM8(0x0802)
-#define TCC0_CTRLD  _SFR_MEM8(0x0803)
-#define TCC0_CTRLE  _SFR_MEM8(0x0804)
-#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
-#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
-#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
-#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
-#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
-#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
-#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
-#define TCC0_TEMP  _SFR_MEM8(0x080F)
-#define TCC0_CNT  _SFR_MEM16(0x0820)
-#define TCC0_PER  _SFR_MEM16(0x0826)
-#define TCC0_CCA  _SFR_MEM16(0x0828)
-#define TCC0_CCB  _SFR_MEM16(0x082A)
-#define TCC0_CCC  _SFR_MEM16(0x082C)
-#define TCC0_CCD  _SFR_MEM16(0x082E)
-#define TCC0_PERBUF  _SFR_MEM16(0x0836)
-#define TCC0_CCABUF  _SFR_MEM16(0x0838)
-#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
-#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
-#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
-
-/* TCC1 - Timer/Counter C1 */
-#define TCC1_CTRLA  _SFR_MEM8(0x0840)
-#define TCC1_CTRLB  _SFR_MEM8(0x0841)
-#define TCC1_CTRLC  _SFR_MEM8(0x0842)
-#define TCC1_CTRLD  _SFR_MEM8(0x0843)
-#define TCC1_CTRLE  _SFR_MEM8(0x0844)
-#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
-#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
-#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
-#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
-#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
-#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
-#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
-#define TCC1_TEMP  _SFR_MEM8(0x084F)
-#define TCC1_CNT  _SFR_MEM16(0x0860)
-#define TCC1_PER  _SFR_MEM16(0x0866)
-#define TCC1_CCA  _SFR_MEM16(0x0868)
-#define TCC1_CCB  _SFR_MEM16(0x086A)
-#define TCC1_PERBUF  _SFR_MEM16(0x0876)
-#define TCC1_CCABUF  _SFR_MEM16(0x0878)
-#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
-
-/* AWEXC - Advanced Waveform Extension C */
-#define AWEXC_CTRL  _SFR_MEM8(0x0880)
-#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
-#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
-#define AWEXC_STATUS  _SFR_MEM8(0x0884)
-#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
-#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
-#define AWEXC_DTLS  _SFR_MEM8(0x0888)
-#define AWEXC_DTHS  _SFR_MEM8(0x0889)
-#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
-#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
-#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
-
-/* HIRESC - High-Resolution Extension C */
-#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
-
-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC0_DATA  _SFR_MEM8(0x08A0)
-#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
-#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
-#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
-#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
-#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
-#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
-
-/* SPIC - Serial Peripheral Interface C */
-#define SPIC_CTRL  _SFR_MEM8(0x08C0)
-#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
-#define SPIC_STATUS  _SFR_MEM8(0x08C2)
-#define SPIC_DATA  _SFR_MEM8(0x08C3)
-
-/* IRCOM - IR Communication Module */
-#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F8)
-#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08F9)
-#define IRCOM_CTRL  _SFR_MEM8(0x08FA)
-
-/* TCD0 - Timer/Counter D0 */
-#define TCD0_CTRLA  _SFR_MEM8(0x0900)
-#define TCD0_CTRLB  _SFR_MEM8(0x0901)
-#define TCD0_CTRLC  _SFR_MEM8(0x0902)
-#define TCD0_CTRLD  _SFR_MEM8(0x0903)
-#define TCD0_CTRLE  _SFR_MEM8(0x0904)
-#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
-#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
-#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
-#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
-#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
-#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
-#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
-#define TCD0_TEMP  _SFR_MEM8(0x090F)
-#define TCD0_CNT  _SFR_MEM16(0x0920)
-#define TCD0_PER  _SFR_MEM16(0x0926)
-#define TCD0_CCA  _SFR_MEM16(0x0928)
-#define TCD0_CCB  _SFR_MEM16(0x092A)
-#define TCD0_CCC  _SFR_MEM16(0x092C)
-#define TCD0_CCD  _SFR_MEM16(0x092E)
-#define TCD0_PERBUF  _SFR_MEM16(0x0936)
-#define TCD0_CCABUF  _SFR_MEM16(0x0938)
-#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
-#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
-#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
-
-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD0_DATA  _SFR_MEM8(0x09A0)
-#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
-#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
-#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
-#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
-#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
-#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
-
-/* SPID - Serial Peripheral Interface D */
-#define SPID_CTRL  _SFR_MEM8(0x09C0)
-#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
-#define SPID_STATUS  _SFR_MEM8(0x09C2)
-#define SPID_DATA  _SFR_MEM8(0x09C3)
-
-/* TCE0 - Timer/Counter E0 */
-#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
-#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
-#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
-#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
-#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
-#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
-#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
-#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
-#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
-#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
-#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
-#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
-#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
-#define TCE0_CNT  _SFR_MEM16(0x0A20)
-#define TCE0_PER  _SFR_MEM16(0x0A26)
-#define TCE0_CCA  _SFR_MEM16(0x0A28)
-#define TCE0_CCB  _SFR_MEM16(0x0A2A)
-#define TCE0_CCC  _SFR_MEM16(0x0A2C)
-#define TCE0_CCD  _SFR_MEM16(0x0A2E)
-#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
-#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
-#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
-#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
-#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
-
-/* AWEXE - Advanced Waveform Extension E */
-#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
-#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
-#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
-#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
-#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
-#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
-#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
-#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
-#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
-#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
-#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
-
-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
-#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
-#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
-#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
-#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
-#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
-#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
-
-/* SPIE - Serial Peripheral Interface E */
-#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
-#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
-#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
-#define SPIE_DATA  _SFR_MEM8(0x0AC3)
-
-/* TCF0 - Timer/Counter F0 */
-#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
-#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
-#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
-#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
-#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
-#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
-#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
-#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
-#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
-#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
-#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
-#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
-#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
-#define TCF0_CNT  _SFR_MEM16(0x0B20)
-#define TCF0_PER  _SFR_MEM16(0x0B26)
-#define TCF0_CCA  _SFR_MEM16(0x0B28)
-#define TCF0_CCB  _SFR_MEM16(0x0B2A)
-#define TCF0_CCC  _SFR_MEM16(0x0B2C)
-#define TCF0_CCD  _SFR_MEM16(0x0B2E)
-#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
-#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
-#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
-#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
-#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
-
-
-
-/*================== Bitfield Definitions ================== */
-
-/* XOCD - On-Chip Debug System */
-/* OCD.OCDR1  bit masks and bit positions */
-#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
-#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
-
-
-/* CPU - CPU */
-/* CPU.CCP  bit masks and bit positions */
-#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
-#define CPU_CCP_gp  0  /* CCP signature group position. */
-#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
-#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
-#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
-#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
-#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
-#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
-#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
-#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
-#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
-#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
-#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
-#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
-#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
-#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
-#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
-#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
-
-
-/* CPU.SREG  bit masks and bit positions */
-#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
-#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
-
-#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
-#define CPU_T_bp  6  /* Transfer Bit bit position. */
-
-#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
-#define CPU_H_bp  5  /* Half Carry Flag bit position. */
-
-#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
-#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
-
-#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
-#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
-
-#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
-#define CPU_N_bp  2  /* Negative Flag bit position. */
-
-#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
-#define CPU_Z_bp  1  /* Zero Flag bit position. */
-
-#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
-#define CPU_C_bp  0  /* Carry Flag bit position. */
-
-
-/* CLK - Clock System */
-/* CLK.CTRL  bit masks and bit positions */
-#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
-#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
-#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
-#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
-#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
-#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
-#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
-#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
-
-
-/* CLK.PSCTRL  bit masks and bit positions */
-#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
-#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
-#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
-#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
-#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
-#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
-#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
-#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
-#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
-#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
-#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
-#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
-
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
-
-
-/* CLK.LOCK  bit masks and bit positions */
-#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
-#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
-
-
-/* CLK.RTCCTRL  bit masks and bit positions */
-#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
-#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
-#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
-#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
-#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
-#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
-#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
-#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
-
-#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
-#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
-
-
-/* PR.PRGEN  bit masks and bit positions */
-#define PR_AES_bm  0x10  /* AES bit mask. */
-#define PR_AES_bp  4  /* AES bit position. */
-
-#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
-#define PR_EBI_bp  3  /* External Bus Interface bit position. */
-
-#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
-#define PR_RTC_bp  2  /* Real-time Counter bit position. */
-
-#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
-#define PR_EVSYS_bp  1  /* Event System bit position. */
-
-#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
-#define PR_DMA_bp  0  /* DMA-Controller bit position. */
-
-
-/* PR.PRPA  bit masks and bit positions */
-#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
-#define PR_DAC_bp  2  /* Port A DAC bit position. */
-
-#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
-#define PR_ADC_bp  1  /* Port A ADC bit position. */
-
-#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
-#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
-
-
-/* PR.PRPB  bit masks and bit positions */
-/* PR_DAC_bm  Predefined. */
-/* PR_DAC_bp  Predefined. */
-
-/* PR_ADC_bm  Predefined. */
-/* PR_ADC_bp  Predefined. */
-
-/* PR_AC_bm  Predefined. */
-/* PR_AC_bp  Predefined. */
-
-
-/* PR.PRPC  bit masks and bit positions */
-#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
-#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
-
-#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
-#define PR_USART1_bp  5  /* Port C USART1 bit position. */
-
-#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
-#define PR_USART0_bp  4  /* Port C USART0 bit position. */
-
-#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
-#define PR_SPI_bp  3  /* Port C SPI bit position. */
-
-#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
-#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
-
-#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
-#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
-
-#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
-#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
-
-
-/* PR.PRPD  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPE  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* PR.PRPF  bit masks and bit positions */
-/* PR_TWI_bm  Predefined. */
-/* PR_TWI_bp  Predefined. */
-
-/* PR_USART1_bm  Predefined. */
-/* PR_USART1_bp  Predefined. */
-
-/* PR_USART0_bm  Predefined. */
-/* PR_USART0_bp  Predefined. */
-
-/* PR_SPI_bm  Predefined. */
-/* PR_SPI_bp  Predefined. */
-
-/* PR_HIRES_bm  Predefined. */
-/* PR_HIRES_bp  Predefined. */
-
-/* PR_TC1_bm  Predefined. */
-/* PR_TC1_bp  Predefined. */
-
-/* PR_TC0_bm  Predefined. */
-/* PR_TC0_bp  Predefined. */
-
-
-/* SLEEP - Sleep Controller */
-/* SLEEP.CTRL  bit masks and bit positions */
-#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
-#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
-#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
-#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
-#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
-#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
-#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
-#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
-
-#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
-#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
-
-
-/* OSC - Oscillator */
-/* OSC.CTRL  bit masks and bit positions */
-#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
-#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
-
-#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
-#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
-
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
-
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
-
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
-
-
-/* OSC.STATUS  bit masks and bit positions */
-#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
-#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
-
-#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
-#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
-
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
-
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
-
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
-
-
-/* OSC.XOSCCTRL  bit masks and bit positions */
-#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
-#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
-#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
-#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
-#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
-#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
-
-#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
-#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
-
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
-
-
-/* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
-
-#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
-#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
-
-
-/* OSC.PLLCTRL  bit masks and bit positions */
-#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
-#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
-#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
-#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
-#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
-#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
-
-#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
-#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
-#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
-#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
-#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
-#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
-#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
-#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
-#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
-#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
-#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
-#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
-
-
-/* OSC.DFLLCTRL  bit masks and bit positions */
-#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
-#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
-
-#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
-#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
-
-
-/* DFLL - DFLL */
-/* DFLL.CTRL  bit masks and bit positions */
-#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
-#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
-
-
-/* DFLL.CALA  bit masks and bit positions */
-#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
-#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
-#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
-#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
-#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
-#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
-#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
-#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
-#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
-#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
-#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
-#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
-#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
-#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
-#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
-#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
-
-
-/* DFLL.CALB  bit masks and bit positions */
-#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
-#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
-#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
-#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
-#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
-#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
-#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
-#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
-#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
-#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
-#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
-#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
-#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
-#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
-
-
-/* RST - Reset */
-/* RST.STATUS  bit masks and bit positions */
-#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
-#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
-
-#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
-#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
-
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
-
-#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
-#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
-
-#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
-#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
-
-#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
-#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
-
-#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
-#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
-
-
-/* RST.CTRL  bit masks and bit positions */
-#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
-#define RST_SWRST_bp  0  /* Software Reset bit position. */
-
-
-/* WDT - Watch-Dog Timer */
-/* WDT.CTRL  bit masks and bit positions */
-#define WDT_PER_gm  0x3C  /* Period group mask. */
-#define WDT_PER_gp  2  /* Period group position. */
-#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
-#define WDT_PER0_bp  2  /* Period bit 0 position. */
-#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
-#define WDT_PER1_bp  3  /* Period bit 1 position. */
-#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
-#define WDT_PER2_bp  4  /* Period bit 2 position. */
-#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
-#define WDT_PER3_bp  5  /* Period bit 3 position. */
-
-#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
-#define WDT_ENABLE_bp  1  /* Enable bit position. */
-
-#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
-#define WDT_CEN_bp  0  /* Change Enable bit position. */
-
-
-/* WDT.WINCTRL  bit masks and bit positions */
-#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
-#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
-#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
-#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
-#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
-#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
-#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
-#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
-#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
-#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
-
-#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
-#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
-
-#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
-#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
-
-
-/* WDT.STATUS  bit masks and bit positions */
-#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
-#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
-
-
-/* MCU - MCU Control */
-/* MCU.MCUCR  bit masks and bit positions */
-#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
-#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
-
-
-/* MCU.EVSYSLOCK  bit masks and bit positions */
-#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
-#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
-
-#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
-#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
-
-
-/* MCU.AWEXLOCK  bit masks and bit positions */
-#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
-#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
-
-#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
-#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
-
-
-/* PMIC - Programmable Multi-level Interrupt Controller */
-/* PMIC.STATUS  bit masks and bit positions */
-#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
-#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
-
-#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
-#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
-
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
-
-#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
-#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
-
-
-/* PMIC.CTRL  bit masks and bit positions */
-#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
-#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
-
-#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
-#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
-
-#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
-#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
-
-#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
-#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
-
-#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
-#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
-
-
-/* EVSYS - Event System */
-/* EVSYS.CH0MUX  bit masks and bit positions */
-#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
-#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
-#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
-#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
-#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
-#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
-#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
-#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
-#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
-#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
-#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
-#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
-#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
-#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
-#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
-#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
-#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
-#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
-
-
-/* EVSYS.CH1MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH2MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH3MUX  bit masks and bit positions */
-/* EVSYS_CHMUX_gm  Predefined. */
-/* EVSYS_CHMUX_gp  Predefined. */
-/* EVSYS_CHMUX0_bm  Predefined. */
-/* EVSYS_CHMUX0_bp  Predefined. */
-/* EVSYS_CHMUX1_bm  Predefined. */
-/* EVSYS_CHMUX1_bp  Predefined. */
-/* EVSYS_CHMUX2_bm  Predefined. */
-/* EVSYS_CHMUX2_bp  Predefined. */
-/* EVSYS_CHMUX3_bm  Predefined. */
-/* EVSYS_CHMUX3_bp  Predefined. */
-/* EVSYS_CHMUX4_bm  Predefined. */
-/* EVSYS_CHMUX4_bp  Predefined. */
-/* EVSYS_CHMUX5_bm  Predefined. */
-/* EVSYS_CHMUX5_bp  Predefined. */
-/* EVSYS_CHMUX6_bm  Predefined. */
-/* EVSYS_CHMUX6_bp  Predefined. */
-/* EVSYS_CHMUX7_bm  Predefined. */
-/* EVSYS_CHMUX7_bp  Predefined. */
-
-
-/* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
-
-#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
-#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
-
-#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
-#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
-
-#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
-#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
-#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
-#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
-#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
-#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
-#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
-#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
-
-
-/* EVSYS.CH1CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH2CTRL  bit masks and bit positions */
-/* EVSYS_QDIRM_gm  Predefined. */
-/* EVSYS_QDIRM_gp  Predefined. */
-/* EVSYS_QDIRM0_bm  Predefined. */
-/* EVSYS_QDIRM0_bp  Predefined. */
-/* EVSYS_QDIRM1_bm  Predefined. */
-/* EVSYS_QDIRM1_bp  Predefined. */
-
-/* EVSYS_QDIEN_bm  Predefined. */
-/* EVSYS_QDIEN_bp  Predefined. */
-
-/* EVSYS_QDEN_bm  Predefined. */
-/* EVSYS_QDEN_bp  Predefined. */
-
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* EVSYS.CH3CTRL  bit masks and bit positions */
-/* EVSYS_DIGFILT_gm  Predefined. */
-/* EVSYS_DIGFILT_gp  Predefined. */
-/* EVSYS_DIGFILT0_bm  Predefined. */
-/* EVSYS_DIGFILT0_bp  Predefined. */
-/* EVSYS_DIGFILT1_bm  Predefined. */
-/* EVSYS_DIGFILT1_bp  Predefined. */
-/* EVSYS_DIGFILT2_bm  Predefined. */
-/* EVSYS_DIGFILT2_bp  Predefined. */
-
-
-/* NVM - Non Volatile Memory Controller */
-/* NVM.CMD  bit masks and bit positions */
-#define NVM_CMD_gm  0xFF  /* Command group mask. */
-#define NVM_CMD_gp  0  /* Command group position. */
-#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define NVM_CMD0_bp  0  /* Command bit 0 position. */
-#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define NVM_CMD1_bp  1  /* Command bit 1 position. */
-#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
-#define NVM_CMD2_bp  2  /* Command bit 2 position. */
-#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
-#define NVM_CMD3_bp  3  /* Command bit 3 position. */
-#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
-#define NVM_CMD4_bp  4  /* Command bit 4 position. */
-#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
-#define NVM_CMD5_bp  5  /* Command bit 5 position. */
-#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
-#define NVM_CMD6_bp  6  /* Command bit 6 position. */
-#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
-#define NVM_CMD7_bp  7  /* Command bit 7 position. */
-
-
-/* NVM.CTRLA  bit masks and bit positions */
-#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
-#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
-
-
-/* NVM.CTRLB  bit masks and bit positions */
-#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
-#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
-
-#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
-#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
-
-#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
-#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
-
-#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
-#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
-
-
-/* NVM.INTCTRL  bit masks and bit positions */
-#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
-#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
-#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
-#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
-#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
-#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
-
-#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
-#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
-#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
-#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
-#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
-#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
-
-
-/* NVM.STATUS  bit masks and bit positions */
-#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
-#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
-
-#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
-#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
-
-#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
-
-#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
-#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
-
-
-/* NVM.LOCKBITS  bit masks and bit positions */
-#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
-
-#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
-#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
-#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
-#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
-#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
-#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
-#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
-#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
-#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
-#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
-#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
-#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
-#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
-#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
-#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
-#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
-#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
-#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
-#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
-#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
-#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
-#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
-#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
-#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
-
-
-/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
-
-#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
-#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
-#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
-#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
-#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
-#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
-
-
-/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
-#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
-#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
-
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
-
-
-/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
-#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
-#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
-#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
-#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
-#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
-#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
-
-#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
-#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
-
-
-/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
-
-
-/* AC - Analog Comparator */
-/* AC.AC0CTRL  bit masks and bit positions */
-#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
-#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
-#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
-#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
-#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
-#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
-
-#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
-#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
-#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
-#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
-#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
-#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
-
-#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
-#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
-
-#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
-#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
-#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
-#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
-#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
-#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
-
-#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
-#define AC_ENABLE_bp  0  /* Enable bit position. */
-
-
-/* AC.AC1CTRL  bit masks and bit positions */
-/* AC_INTMODE_gm  Predefined. */
-/* AC_INTMODE_gp  Predefined. */
-/* AC_INTMODE0_bm  Predefined. */
-/* AC_INTMODE0_bp  Predefined. */
-/* AC_INTMODE1_bm  Predefined. */
-/* AC_INTMODE1_bp  Predefined. */
-
-/* AC_INTLVL_gm  Predefined. */
-/* AC_INTLVL_gp  Predefined. */
-/* AC_INTLVL0_bm  Predefined. */
-/* AC_INTLVL0_bp  Predefined. */
-/* AC_INTLVL1_bm  Predefined. */
-/* AC_INTLVL1_bp  Predefined. */
-
-/* AC_HSMODE_bm  Predefined. */
-/* AC_HSMODE_bp  Predefined. */
-
-/* AC_HYSMODE_gm  Predefined. */
-/* AC_HYSMODE_gp  Predefined. */
-/* AC_HYSMODE0_bm  Predefined. */
-/* AC_HYSMODE0_bp  Predefined. */
-/* AC_HYSMODE1_bm  Predefined. */
-/* AC_HYSMODE1_bp  Predefined. */
-
-/* AC_ENABLE_bm  Predefined. */
-/* AC_ENABLE_bp  Predefined. */
-
-
-/* AC.AC0MUXCTRL  bit masks and bit positions */
-#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
-#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
-#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
-#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
-#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
-#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
-#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
-#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
-
-#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
-#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
-#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
-#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
-#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
-#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
-#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
-#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
-
-
-/* AC.AC1MUXCTRL  bit masks and bit positions */
-/* AC_MUXPOS_gm  Predefined. */
-/* AC_MUXPOS_gp  Predefined. */
-/* AC_MUXPOS0_bm  Predefined. */
-/* AC_MUXPOS0_bp  Predefined. */
-/* AC_MUXPOS1_bm  Predefined. */
-/* AC_MUXPOS1_bp  Predefined. */
-/* AC_MUXPOS2_bm  Predefined. */
-/* AC_MUXPOS2_bp  Predefined. */
-
-/* AC_MUXNEG_gm  Predefined. */
-/* AC_MUXNEG_gp  Predefined. */
-/* AC_MUXNEG0_bm  Predefined. */
-/* AC_MUXNEG0_bp  Predefined. */
-/* AC_MUXNEG1_bm  Predefined. */
-/* AC_MUXNEG1_bp  Predefined. */
-/* AC_MUXNEG2_bm  Predefined. */
-/* AC_MUXNEG2_bp  Predefined. */
-
-
-/* AC.CTRLA  bit masks and bit positions */
-#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
-#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
-
-
-/* AC.CTRLB  bit masks and bit positions */
-#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
-#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
-#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
-#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
-#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
-#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
-#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
-#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
-#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
-#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
-#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
-#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
-#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
-#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
-
-
-/* AC.WINCTRL  bit masks and bit positions */
-#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
-#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
-
-#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
-#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
-#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
-#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
-#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
-#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
-
-#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
-#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
-#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
-#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
-#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
-#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
-
-
-/* AC.STATUS  bit masks and bit positions */
-#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
-#define AC_WSTATE_gp  6  /* Window Mode State group position. */
-#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
-#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
-#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
-#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
-
-#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
-#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
-
-#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
-#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
-
-#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
-#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
-
-#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
-#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
-
-#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
-#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
-
-
-/* ADC - Analog/Digital Converter */
-/* ADC_CH.CTRL  bit masks and bit positions */
-#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
-#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
-
-#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
-#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
-#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
-#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
-#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
-#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
-#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
-#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
-
-#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
-#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
-#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
-#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
-#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
-#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
-
-
-/* ADC_CH.MUXCTRL  bit masks and bit positions */
-#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
-#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
-#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
-#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
-#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
-#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
-#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
-#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
-#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
-#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
-
-#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
-#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
-#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
-#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
-#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
-#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
-#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
-#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
-#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
-#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
-
-#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
-#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
-#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
-#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
-#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
-#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
-
-
-/* ADC_CH.INTCTRL  bit masks and bit positions */
-#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
-#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
-#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
-#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
-#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
-#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
-
-#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
-#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
-#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
-#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
-#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
-#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
-
-
-/* ADC_CH.INTFLAGS  bit masks and bit positions */
-#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
-#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
-
-
-/* ADC.CTRLA  bit masks and bit positions */
-#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
-#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
-
-#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
-#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
-
-
-/* ADC.CTRLB  bit masks and bit positions */
-#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
-#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
-
-#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
-#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
-
-#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
-#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
-#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
-#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
-#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
-#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
-
-
-/* ADC.REFCTRL  bit masks and bit positions */
-#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
-#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
-#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
-#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
-#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
-#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
-
-#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
-#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
-
-#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
-#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
-
-
-/* ADC.EVCTRL  bit masks and bit positions */
-#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
-#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
-#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
-#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
-#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
-#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
-
-#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
-#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
-#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
-#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
-#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
-#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
-#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
-#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
-
-#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
-#define ADC_EVACT_gp  0  /* Event Action Select group position. */
-#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
-#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
-#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
-#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
-#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
-#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
-
-
-/* ADC.PRESCALER  bit masks and bit positions */
-#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
-#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
-#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
-#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
-#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
-#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
-#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
-#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
-
-
-/* ADC.CALCTRL  bit masks and bit positions */
-#define ADC_CAL_bm  0x01  /* ADC Calibration Start bit mask. */
-#define ADC_CAL_bp  0  /* ADC Calibration Start bit position. */
-
-
-/* ADC.INTFLAGS  bit masks and bit positions */
-#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
-#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
-
-
-/* RTC - Real-Time Clounter */
-/* RTC.CTRL  bit masks and bit positions */
-#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
-#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
-#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
-#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
-#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
-#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
-#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
-#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
-
-
-/* RTC.STATUS  bit masks and bit positions */
-#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
-#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
-
-
-/* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
-
-#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
-#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
-#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
-#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
-#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
-#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
-
-
-/* RTC.INTFLAGS  bit masks and bit positions */
-#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
-#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
-
-#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* EBI - External Bus Interface */
-/* EBI_CS.CTRLA  bit masks and bit positions */
-#define EBI_CS_ASPACE_gm  0x7C  /* Address Space group mask. */
-#define EBI_CS_ASPACE_gp  2  /* Address Space group position. */
-#define EBI_CS_ASPACE0_bm  (1<<2)  /* Address Space bit 0 mask. */
-#define EBI_CS_ASPACE0_bp  2  /* Address Space bit 0 position. */
-#define EBI_CS_ASPACE1_bm  (1<<3)  /* Address Space bit 1 mask. */
-#define EBI_CS_ASPACE1_bp  3  /* Address Space bit 1 position. */
-#define EBI_CS_ASPACE2_bm  (1<<4)  /* Address Space bit 2 mask. */
-#define EBI_CS_ASPACE2_bp  4  /* Address Space bit 2 position. */
-#define EBI_CS_ASPACE3_bm  (1<<5)  /* Address Space bit 3 mask. */
-#define EBI_CS_ASPACE3_bp  5  /* Address Space bit 3 position. */
-#define EBI_CS_ASPACE4_bm  (1<<6)  /* Address Space bit 4 mask. */
-#define EBI_CS_ASPACE4_bp  6  /* Address Space bit 4 position. */
-
-#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
-#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
-#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
-#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
-#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
-#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
-
-
-/* EBI_CS.CTRLB  bit masks and bit positions */
-#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
-#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
-#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
-#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
-#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
-#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
-#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
-#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
-
-#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
-#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
-
-#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
-#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
-
-#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
-#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
-#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
-#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
-#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
-#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
-
-
-/* EBI.CTRL  bit masks and bit positions */
-#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
-#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
-#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
-#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
-#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
-#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
-
-#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
-#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
-#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
-#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
-#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
-#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
-
-#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
-#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
-#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
-#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
-#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
-#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
-
-#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
-#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
-#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
-#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
-#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
-#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
-
-
-/* EBI.SDRAMCTRLA  bit masks and bit positions */
-#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
-#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
-
-#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
-#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
-
-#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
-#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
-#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
-#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
-#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
-#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
-
-
-/* EBI.SDRAMCTRLB  bit masks and bit positions */
-#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
-#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
-#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
-#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
-#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
-#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
-
-#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
-#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
-#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
-#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
-#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
-#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
-#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
-#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
-
-#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
-#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
-#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
-#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
-#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
-#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
-#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
-#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
-
-
-/* EBI.SDRAMCTRLC  bit masks and bit positions */
-#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
-#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
-#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
-#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
-#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
-#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
-
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
-
-#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
-#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
-#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
-#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
-#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
-#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
-#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
-#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
-
-
-/* TWI - Two-Wire Interface */
-/* TWI_MASTER.CTRLA  bit masks and bit positions */
-#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
-#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
-
-#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
-#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
-
-#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
-#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
-
-
-/* TWI_MASTER.CTRLB  bit masks and bit positions */
-#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
-#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
-#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
-#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
-#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
-#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
-
-#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
-#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
-
-#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_MASTER.CTRLC  bit masks and bit positions */
-#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
-#define TWI_MASTER_CMD_gp  0  /* Command group position. */
-#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_MASTER.STATUS  bit masks and bit positions */
-#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
-#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
-
-#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
-#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
-
-#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
-#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
-
-#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
-#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
-#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
-#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
-#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
-#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
-
-
-/* TWI_SLAVE.CTRLA  bit masks and bit positions */
-#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
-#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
-#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
-#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
-#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
-#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
-
-#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
-#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
-
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
-#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
-
-#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
-
-#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
-#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
-
-#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
-#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
-
-
-/* TWI_SLAVE.CTRLB  bit masks and bit positions */
-#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
-#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
-
-#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
-#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
-#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
-#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
-#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
-#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
-
-
-/* TWI_SLAVE.STATUS  bit masks and bit positions */
-#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
-#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
-
-#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
-#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
-
-#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
-#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
-
-#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
-#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
-
-#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
-#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
-
-#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
-#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
-
-#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
-#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
-
-#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
-#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
-
-
-/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
-#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
-#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
-#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
-#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
-#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
-#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
-#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
-#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
-#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
-#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
-#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
-#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
-#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
-#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
-#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
-#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
-
-#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
-#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
-
-
-/* TWI.CTRL  bit masks and bit positions */
-#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
-#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
-
-#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
-#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
-
-
-/* PORT - Port Configuration */
-/* PORTCFG.VPCTRLA  bit masks and bit positions */
-#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
-#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
-#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
-#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
-#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
-#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
-#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
-#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
-#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
-#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
-
-#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
-#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
-#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
-#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
-#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
-#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
-#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
-#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
-#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
-#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
-
-
-/* PORTCFG.VPCTRLB  bit masks and bit positions */
-#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
-#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
-#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
-#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
-#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
-#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
-#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
-#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
-#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
-#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
-
-#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
-#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
-#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
-#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
-#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
-#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
-#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
-#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
-#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
-#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
-
-
-/* PORTCFG.CLKEVOUT  bit masks and bit positions */
-#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
-#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
-#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
-#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
-#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
-#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
-
-#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
-#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
-#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
-#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
-#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
-#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
-
-
-/* VPORT.INTFLAGS  bit masks and bit positions */
-#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.INTCTRL  bit masks and bit positions */
-#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
-#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
-#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
-#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
-#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
-#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
-
-#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
-#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
-#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
-#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
-#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
-#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
-
-
-/* PORT.INTFLAGS  bit masks and bit positions */
-#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
-#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
-
-#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
-#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
-
-
-/* PORT.PIN0CTRL  bit masks and bit positions */
-#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
-#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
-
-#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
-#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
-
-#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
-#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
-#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
-#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
-#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
-#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
-#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
-#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
-
-#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
-#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
-#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
-#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
-#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
-#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
-#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
-#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
-
-
-/* PORT.PIN1CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN2CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN3CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN4CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN5CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN6CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* PORT.PIN7CTRL  bit masks and bit positions */
-/* PORT_SRLEN_bm  Predefined. */
-/* PORT_SRLEN_bp  Predefined. */
-
-/* PORT_INVEN_bm  Predefined. */
-/* PORT_INVEN_bp  Predefined. */
-
-/* PORT_OPC_gm  Predefined. */
-/* PORT_OPC_gp  Predefined. */
-/* PORT_OPC0_bm  Predefined. */
-/* PORT_OPC0_bp  Predefined. */
-/* PORT_OPC1_bm  Predefined. */
-/* PORT_OPC1_bp  Predefined. */
-/* PORT_OPC2_bm  Predefined. */
-/* PORT_OPC2_bp  Predefined. */
-
-/* PORT_ISC_gm  Predefined. */
-/* PORT_ISC_gp  Predefined. */
-/* PORT_ISC0_bm  Predefined. */
-/* PORT_ISC0_bp  Predefined. */
-/* PORT_ISC1_bm  Predefined. */
-/* PORT_ISC1_bp  Predefined. */
-/* PORT_ISC2_bm  Predefined. */
-/* PORT_ISC2_bp  Predefined. */
-
-
-/* TC - 16-bit Timer/Counter With PWM */
-/* TC0.CTRLA  bit masks and bit positions */
-#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC0.CTRLB  bit masks and bit positions */
-#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
-#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
-
-#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
-#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
-
-#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC0.CTRLC  bit masks and bit positions */
-#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
-#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
-
-#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
-#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
-
-#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC0.CTRLD  bit masks and bit positions */
-#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC0_EVACT_gp  5  /* Event Action group position. */
-#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC0.CTRLE  bit masks and bit positions */
-#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC0.INTCTRLA  bit masks and bit positions */
-#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC0.CTRLFCLR  bit masks and bit positions */
-#define TC0_CMD_gm  0x0C  /* Command group mask. */
-#define TC0_CMD_gp  2  /* Command group position. */
-#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC0_CMD0_bp  2  /* Command bit 0 position. */
-#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC0_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC0_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC0_DIR_bm  0x01  /* Direction bit mask. */
-#define TC0_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC0.CTRLFSET  bit masks and bit positions */
-/* TC0_CMD_gm  Predefined. */
-/* TC0_CMD_gp  Predefined. */
-/* TC0_CMD0_bm  Predefined. */
-/* TC0_CMD0_bp  Predefined. */
-/* TC0_CMD1_bm  Predefined. */
-/* TC0_CMD1_bp  Predefined. */
-
-/* TC0_LUPD_bm  Predefined. */
-/* TC0_LUPD_bp  Predefined. */
-
-/* TC0_DIR_bm  Predefined. */
-/* TC0_DIR_bp  Predefined. */
-
-
-/* TC0.CTRLGCLR  bit masks and bit positions */
-#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
-#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
-
-#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
-#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
-
-#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC0.CTRLGSET  bit masks and bit positions */
-/* TC0_CCDBV_bm  Predefined. */
-/* TC0_CCDBV_bp  Predefined. */
-
-/* TC0_CCCBV_bm  Predefined. */
-/* TC0_CCCBV_bp  Predefined. */
-
-/* TC0_CCBBV_bm  Predefined. */
-/* TC0_CCBBV_bp  Predefined. */
-
-/* TC0_CCABV_bm  Predefined. */
-/* TC0_CCABV_bp  Predefined. */
-
-/* TC0_PERBV_bm  Predefined. */
-/* TC0_PERBV_bp  Predefined. */
-
-
-/* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* TC1.CTRLA  bit masks and bit positions */
-#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
-#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
-#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
-#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
-#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
-#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
-#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
-#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
-#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
-#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
-
-
-/* TC1.CTRLB  bit masks and bit positions */
-#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
-#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
-
-#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
-#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
-
-#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
-#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
-#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
-#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
-#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
-#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
-#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
-#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
-
-
-/* TC1.CTRLC  bit masks and bit positions */
-#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
-#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
-
-#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
-#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
-
-
-/* TC1.CTRLD  bit masks and bit positions */
-#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
-#define TC1_EVACT_gp  5  /* Event Action group position. */
-#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
-#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
-#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
-#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
-#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
-#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
-
-#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
-#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
-
-#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
-#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
-#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
-#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
-#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
-#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
-#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
-#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
-#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
-#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
-
-
-/* TC1.CTRLE  bit masks and bit positions */
-#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
-#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
-
-
-/* TC1.INTCTRLA  bit masks and bit positions */
-#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
-#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
-#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
-#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
-#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
-#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
-
-#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
-#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
-#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
-#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
-#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
-#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
-
-
-/* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
-
-
-/* TC1.CTRLFCLR  bit masks and bit positions */
-#define TC1_CMD_gm  0x0C  /* Command group mask. */
-#define TC1_CMD_gp  2  /* Command group position. */
-#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
-#define TC1_CMD0_bp  2  /* Command bit 0 position. */
-#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
-#define TC1_CMD1_bp  3  /* Command bit 1 position. */
-
-#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
-#define TC1_LUPD_bp  1  /* Lock Update bit position. */
-
-#define TC1_DIR_bm  0x01  /* Direction bit mask. */
-#define TC1_DIR_bp  0  /* Direction bit position. */
-
-
-/* TC1.CTRLFSET  bit masks and bit positions */
-/* TC1_CMD_gm  Predefined. */
-/* TC1_CMD_gp  Predefined. */
-/* TC1_CMD0_bm  Predefined. */
-/* TC1_CMD0_bp  Predefined. */
-/* TC1_CMD1_bm  Predefined. */
-/* TC1_CMD1_bp  Predefined. */
-
-/* TC1_LUPD_bm  Predefined. */
-/* TC1_LUPD_bp  Predefined. */
-
-/* TC1_DIR_bm  Predefined. */
-/* TC1_DIR_bp  Predefined. */
-
-
-/* TC1.CTRLGCLR  bit masks and bit positions */
-#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
-#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
-
-#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
-#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
-
-#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
-#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
-
-
-/* TC1.CTRLGSET  bit masks and bit positions */
-/* TC1_CCBBV_bm  Predefined. */
-/* TC1_CCBBV_bp  Predefined. */
-
-/* TC1_CCABV_bm  Predefined. */
-/* TC1_CCABV_bp  Predefined. */
-
-/* TC1_PERBV_bm  Predefined. */
-/* TC1_PERBV_bp  Predefined. */
-
-
-/* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
-
-#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
-#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
-
-#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
-#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
-
-
-/* AWEX.CTRL  bit masks and bit positions */
-#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
-#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
-
-#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
-#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
-
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
-
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
-
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
-
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
-
-
-/* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
-
-#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
-#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
-
-#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
-#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
-#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
-#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
-#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
-#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
-
-
-/* AWEX.STATUS  bit masks and bit positions */
-#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
-#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
-
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
-
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
-
-
-/* HIRES.CTRLA  bit masks and bit positions */
-#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
-#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
-#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
-#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
-#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
-#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
-
-
-/* USART - Universal Asynchronous Receiver-Transmitter */
-/* USART.STATUS  bit masks and bit positions */
-#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
-#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
-
-#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
-#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
-
-#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
-#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
-
-#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
-#define USART_FERR_bp  4  /* Frame Error bit position. */
-
-#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
-#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
-
-#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
-#define USART_PERR_bp  2  /* Parity Error bit position. */
-
-#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
-#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
-
-
-/* USART.CTRLA  bit masks and bit positions */
-#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
-#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
-#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
-#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
-#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
-#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
-
-#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
-#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
-#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
-#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
-
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
-
-
-/* USART.CTRLB  bit masks and bit positions */
-#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
-#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
-
-#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
-#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
-
-#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
-#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
-
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
-
-#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
-#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
-
-
-/* USART.CTRLC  bit masks and bit positions */
-#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
-#define USART_CMODE_gp  6  /* Communication Mode group position. */
-#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
-#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
-#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
-#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
-
-#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
-#define USART_PMODE_gp  4  /* Parity Mode group position. */
-#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
-#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
-#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
-#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
-
-#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
-#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
-
-#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
-#define USART_CHSIZE_gp  0  /* Character Size group position. */
-#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
-#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
-#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
-#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
-#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
-#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
-
-
-/* USART.BAUDCTRLA  bit masks and bit positions */
-#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
-#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
-
-
-/* USART.BAUDCTRLB  bit masks and bit positions */
-#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
-#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
-#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
-#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
-#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
-#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
-#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
-#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
-#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
-#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
-
-/* USART_BSEL_gm  Predefined. */
-/* USART_BSEL_gp  Predefined. */
-/* USART_BSEL0_bm  Predefined. */
-/* USART_BSEL0_bp  Predefined. */
-/* USART_BSEL1_bm  Predefined. */
-/* USART_BSEL1_bp  Predefined. */
-/* USART_BSEL2_bm  Predefined. */
-/* USART_BSEL2_bp  Predefined. */
-/* USART_BSEL3_bm  Predefined. */
-/* USART_BSEL3_bp  Predefined. */
-
-
-/* SPI - Serial Peripheral Interface */
-/* SPI.CTRL  bit masks and bit positions */
-#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
-#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
-
-#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
-#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
-
-#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
-#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
-
-#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
-#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
-
-#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
-#define SPI_MODE_gp  2  /* SPI Mode group position. */
-#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
-#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
-#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
-#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
-
-#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
-#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
-#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
-#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
-#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
-#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
-
-
-/* SPI.INTCTRL  bit masks and bit positions */
-#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
-#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
-#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
-#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
-#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
-#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
-
-
-/* SPI.STATUS  bit masks and bit positions */
-#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
-#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
-
-#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
-#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
-
-
-/* IRCOM - IR Communication Module */
-/* IRCOM.CTRL  bit masks and bit positions */
-#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
-#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
-#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
-#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
-#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
-#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
-#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
-#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
-#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
-#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
-
-
-
-// Generic Port Pins
-
-#define PIN0_bm 0x01
-#define PIN0_bp 0
-#define PIN1_bm 0x02
-#define PIN1_bp 1
-#define PIN2_bm 0x04
-#define PIN2_bp 2
-#define PIN3_bm 0x08
-#define PIN3_bp 3
-#define PIN4_bm 0x10
-#define PIN4_bp 4
-#define PIN5_bm 0x20
-#define PIN5_bp 5
-#define PIN6_bm 0x40
-#define PIN6_bp 6
-#define PIN7_bm 0x80
-#define PIN7_bp 7
-
-
-/* ========== Interrupt Vector Definitions ========== */
-/* Vector 0 is the reset vector */
-
-/* OSC interrupt vectors */
-#define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
-
-/* PORTC interrupt vectors */
-#define PORTC_INT0_vect_num  2
-#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
-#define PORTC_INT1_vect_num  3
-#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
-
-/* PORTR interrupt vectors */
-#define PORTR_INT0_vect_num  4
-#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
-#define PORTR_INT1_vect_num  5
-#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
-
-/* RTC interrupt vectors */
-#define RTC_OVF_vect_num  10
-#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
-#define RTC_COMP_vect_num  11
-#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
-
-/* TWIC interrupt vectors */
-#define TWIC_TWIS_vect_num  12
-#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
-#define TWIC_TWIM_vect_num  13
-#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
-
-/* TCC0 interrupt vectors */
-#define TCC0_OVF_vect_num  14
-#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
-#define TCC0_ERR_vect_num  15
-#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
-#define TCC0_CCA_vect_num  16
-#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
-#define TCC0_CCB_vect_num  17
-#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
-#define TCC0_CCC_vect_num  18
-#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
-#define TCC0_CCD_vect_num  19
-#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
-
-/* TCC1 interrupt vectors */
-#define TCC1_OVF_vect_num  20
-#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
-#define TCC1_ERR_vect_num  21
-#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
-#define TCC1_CCA_vect_num  22
-#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
-#define TCC1_CCB_vect_num  23
-#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
-
-/* SPIC interrupt vectors */
-#define SPIC_INT_vect_num  24
-#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
-
-/* USARTC0 interrupt vectors */
-#define USARTC0_RXC_vect_num  25
-#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
-#define USARTC0_DRE_vect_num  26
-#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
-#define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
-
-/* NVM interrupt vectors */
-#define NVM_EE_vect_num  32
-#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
-#define NVM_SPM_vect_num  33
-#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
-
-/* PORTB interrupt vectors */
-#define PORTB_INT0_vect_num  34
-#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
-#define PORTB_INT1_vect_num  35
-#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
-
-/* PORTE interrupt vectors */
-#define PORTE_INT0_vect_num  43
-#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
-#define PORTE_INT1_vect_num  44
-#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
-
-/* TCE0 interrupt vectors */
-#define TCE0_OVF_vect_num  47
-#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
-#define TCE0_ERR_vect_num  48
-#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
-#define TCE0_CCA_vect_num  49
-#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
-#define TCE0_CCB_vect_num  50
-#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
-#define TCE0_CCC_vect_num  51
-#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
-#define TCE0_CCD_vect_num  52
-#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
-
-/* USARTE0 interrupt vectors */
-#define USARTE0_RXC_vect_num  58
-#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
-#define USARTE0_DRE_vect_num  59
-#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
-#define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
-
-/* PORTD interrupt vectors */
-#define PORTD_INT0_vect_num  64
-#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
-#define PORTD_INT1_vect_num  65
-#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
-
-/* PORTA interrupt vectors */
-#define PORTA_INT0_vect_num  66
-#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
-#define PORTA_INT1_vect_num  67
-#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
-
-/* ACA interrupt vectors */
-#define ACA_AC0_vect_num  68
-#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
-#define ACA_AC1_vect_num  69
-#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
-#define ACA_ACW_vect_num  70
-#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
-
-/* ADCA interrupt vectors */
-#define ADCA_CH0_vect_num  71
-#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
-
-/* TCD0 interrupt vectors */
-#define TCD0_OVF_vect_num  77
-#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
-#define TCD0_ERR_vect_num  78
-#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
-#define TCD0_CCA_vect_num  79
-#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
-#define TCD0_CCB_vect_num  80
-#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
-#define TCD0_CCC_vect_num  81
-#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
-#define TCD0_CCD_vect_num  82
-#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
-
-/* SPID interrupt vectors */
-#define SPID_INT_vect_num  87
-#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
-
-/* USARTD0 interrupt vectors */
-#define USARTD0_RXC_vect_num  88
-#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
-#define USARTD0_DRE_vect_num  89
-#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
-#define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
-
-/* PORTF interrupt vectors */
-#define PORTF_INT0_vect_num  104
-#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
-#define PORTF_INT1_vect_num  105
-#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
-
-/* TCF0 interrupt vectors */
-#define TCF0_OVF_vect_num  108
-#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
-#define TCF0_ERR_vect_num  109
-#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
-#define TCF0_CCA_vect_num  110
-#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
-#define TCF0_CCB_vect_num  111
-#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
-#define TCF0_CCC_vect_num  112
-#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
-#define TCF0_CCD_vect_num  113
-#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
-
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
-
-
-/* ========== Constants ========== */
-
-#define PROGMEM_START     (0x0000)
-#define PROGMEM_SIZE      (69632)
-#define PROGMEM_PAGE_SIZE (256)
-#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
-
-#define APP_SECTION_START     (0x0000)
-#define APP_SECTION_SIZE      (65536)
-#define APP_SECTION_PAGE_SIZE (256)
-#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
-
-#define APPTABLE_SECTION_START     (0x0F000)
-#define APPTABLE_SECTION_SIZE      (4096)
-#define APPTABLE_SECTION_PAGE_SIZE (256)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
-
-#define BOOT_SECTION_START     (0x10000)
-#define BOOT_SECTION_SIZE      (4096)
-#define BOOT_SECTION_PAGE_SIZE (256)
-#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
-
-#define DATAMEM_START     (0x0000)
-#define DATAMEM_SIZE      (12288)
-#define DATAMEM_PAGE_SIZE (0)
-#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
-
-#define IO_START     (0x0000)
-#define IO_SIZE      (4096)
-#define IO_PAGE_SIZE (0)
-#define IO_END       (IO_START + IO_SIZE - 1)
-
-#define MAPPED_EEPROM_START     (0x1000)
-#define MAPPED_EEPROM_SIZE      (2048)
-#define MAPPED_EEPROM_PAGE_SIZE (0)
-#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
-
-#define INTERNAL_SRAM_START     (0x2000)
-#define INTERNAL_SRAM_SIZE      (4096)
-#define INTERNAL_SRAM_PAGE_SIZE (0)
-#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
-
-#define EEPROM_START     (0x0000)
-#define EEPROM_SIZE      (2048)
-#define EEPROM_PAGE_SIZE (32)
-#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
-
-#define FUSE_START     (0x0000)
-#define FUSE_SIZE      (6)
-#define FUSE_PAGE_SIZE (0)
-#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
-
-#define LOCKBIT_START     (0x0000)
-#define LOCKBIT_SIZE      (1)
-#define LOCKBIT_PAGE_SIZE (0)
-#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
-
-#define SIGNATURES_START     (0x0000)
-#define SIGNATURES_SIZE      (3)
-#define SIGNATURES_PAGE_SIZE (0)
-#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
-
-#define USER_SIGNATURES_START     (0x0000)
-#define USER_SIGNATURES_SIZE      (256)
-#define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
-
-#define PROD_SIGNATURES_START     (0x0000)
-#define PROD_SIGNATURES_SIZE      (52)
-#define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
-
-#define FLASHEND     PROGMEM_END
-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
-#define RAMSTART     INTERNAL_SRAM_START
-#define RAMSIZE      INTERNAL_SRAM_SIZE
-#define RAMEND       INTERNAL_SRAM_END
-#define XRAMSTART    EXTERNAL_SRAM_START
-#define XRAMSIZE     EXTERNAL_SRAM_SIZE
-#define XRAMEND      INTERNAL_SRAM_END
-#define E2END        EEPROM_END
-#define E2PAGESIZE   EEPROM_PAGE_SIZE
-
-
-/* ========== Fuses ========== */
-#define FUSE_MEMORY_SIZE 6
-
-/* Fuse Byte 0 */
-#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
-#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
-#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
-#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
-#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
-#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
-#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
-#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
-#define FUSE0_DEFAULT  (0xFF)
-
-/* Fuse Byte 1 */
-#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
-#define FUSE1_DEFAULT  (0xFF)
-
-/* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
-#define FUSE2_DEFAULT  (0xFF)
-
-/* Fuse Byte 3 Reserved */
-
-/* Fuse Byte 4 */
-#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
-#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
-#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
-#define FUSE4_DEFAULT  (0xFF)
-
-/* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE5_DEFAULT  (0xFF)
-
-
-/* ========== Lock Bits ========== */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
-#define __BOOT_LOCK_APPLICATION_BITS_EXIST
-#define __BOOT_LOCK_BOOT_BITS_EXIST
-
-
-/* ========== Signature ========== */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x4A
-
-/**@}*/
-#endif /* _AVR_ATxmega64D3_H_ */
diff --git a/cpukit/score/cpu/avr/avr/lock.h b/cpukit/score/cpu/avr/avr/lock.h
deleted file mode 100644
index 182f0f4cd8..0000000000
--- a/cpukit/score/cpu/avr/avr/lock.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/**
- * @file avr/lock.h
- *
- * @brief Lock Bits API
- *  \par Introduction
- *
- *  The Lockbit API allows a user to specify the lockbit settings for the
- *  specific AVR device they are compiling for. These lockbit settings will be
- *  placed in a special section in the ELF output file, after linking.
- *
- *  Programming tools can take advantage of the lockbit information embedded in
- *  the ELF file, by extracting this information and determining if the lockbits
- *  need to be programmed after programming the Flash and EEPROM memories.
- *  This also allows a single ELF file to contain all the
- *  information needed to program an AVR.
- *
- *  To use the Lockbit API, include the <avr/io.h> header file, which in turn
- *  automatically includes the individual I/O header file and the <avr/lock.h>
- *  file. These other two files provides everything necessary to set the AVR
- *  lockbits.
- *
- *  \par Lockbit API
- *
- *  Each I/O header file may define up to 3 macros that controls what kinds
- *  of lockbits are available to the user.
- *
- *  If __LOCK_BITS_EXIST is defined, then two lock bits are available to the
- *  user and 3 mode settings are defined for these two bits.
- *
- *  If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are
- *  available to the user and 4 mode settings are defined for these two bits.
- *
- *  If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are
- *  available to the user and 4 mode settings are defined for these two bits.
- *
- *  If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits
- *  are available to set the locking mode for the Application Table Section
- *  (which is used in the XMEGA family).
- *
- *  If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are
- *  available to set the locking mode for the Application Section (which is used
- *  in the XMEGA family).
- *
- *  If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available
- *  to set the locking mode for the Boot Loader Section (which is used in the
- *  XMEGA family).
- *
- *  The AVR lockbit modes have inverted values, logical 1 for an unprogrammed
- *  (disabled) bit and logical 0 for a programmed (enabled) bit. The defined
- *  macros for each individual lock bit represent this in their definition by a
- *  bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined
- *  as:
- *  \code
- *  #define LB_MODE_3  (0xFC)
- *  \endcode
- *
- *  To combine the lockbit mode macros together to represent a whole byte,
- *  use the bitwise AND operator, like so:
- *  \code
- *  (LB_MODE_3 & BLB0_MODE_2)
- *  \endcode
- *
- *  <avr/lock.h> also defines a macro that provides a default lockbit value:
- *  LOCKBITS_DEFAULT which is defined to be 0xFF.
- *
- *  See the AVR device specific datasheet for more details about these
- *  lock bits and the available mode settings.
- *
- *  A convenience macro, LOCKMEM, is defined as a GCC attribute for a
- *  custom-named section of ".lock".
- *
- *  A convenience macro, LOCKBITS, is defined that declares a variable, __lock,
- *  of type unsigned char with the attribute defined by LOCKMEM. This variable
- *  allows the end user to easily set the lockbit data.
- *
- *  \note If a device-specific I/O header file has previously defined LOCKMEM,
- *  then LOCKMEM is not redefined. If a device-specific I/O header file has
- *  previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is
- *  currently known to be defined in the I/O header files for the XMEGA devices.
- *
- *  \par API Usage Example
- *
- *  Putting all of this together is easy:
- *
- *  \code
- *  #include <avr/io.h>
- *
- *  LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
- *
- *  int main(void)
- *  {
- *      return 0;
- *  }
- *  \endcode
- *
- *  Or:
- *
- *  \code
- *  #include <avr/io.h>
- *
- *  unsigned char __lock __attribute__((section (".lock"))) =
- *      (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
- *
- *  int main(void)
- *  {
- *      return 0;
- *  }
- *  \endcode
- *
- *
- *
- *  However there are a number of caveats that you need to be aware of to
- *  use this API properly.
- *
- *  Be sure to include <avr/io.h> to get all of the definitions for the API.
- *  The LOCKBITS macro defines a global variable to store the lockbit data. This
- *  variable is assigned to its own linker section. Assign the desired lockbit
- *  values immediately in the variable initialization.
- *
- *  The .lock section in the ELF file will get its values from the initial
- *  variable assignment ONLY. This means that you can NOT assign values to
- *  this variable in functions and the new values will not be put into the
- *  ELF .lock section.
- *
- *  The global variable is declared in the LOCKBITS macro has two leading
- *  underscores, which means that it is reserved for the "implementation",
- *  meaning the library, so it will not conflict with a user-named variable.
- *
- *  You must initialize the lockbit variable to some meaningful value, even
- *  if it is the default value. This is because the lockbits default to a
- *  logical 1, meaning unprogrammed. Normal uninitialized data defaults to all
- *  locgial zeros. So it is vital that all lockbits are initialized, even with
- *  default data. If they are not, then the lockbits may not programmed to the
- *  desired settings and can possibly put your device into an unrecoverable
- *  state.
- *
- *  Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
- *  your linker command line to have the correct device selected and to have
- *  the correct I/O header file included when you include <avr/io.h>.
- *
- *  You can print out the contents of the .lock section in the ELF file by
- *  using this command line:
- *  \code
- *  avr-objdump -s -j .lock <ELF file>
- *  \endcode
- */
-
-/*
- *  Copyright (c) 2007, Atmel Corporation
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_LOCK_H_
-#define _AVR_LOCK_H_  1
-
-/**
- *  @defgroup avr_lock Lockbit Support
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef __ASSEMBLER__
-
-#ifndef LOCKMEM
-#define LOCKMEM  __attribute__((section (".lock")))
-#endif
-
-#ifndef LOCKBITS
-#define LOCKBITS unsigned char __lock LOCKMEM
-#endif
-
-#endif  /* !__ASSEMBLER */
-
-
-/* Lock Bit Modes */
-#if defined(__LOCK_BITS_EXIST)
-#define LB_MODE_1  (0xFF)
-#define LB_MODE_2  (0xFE)
-#define LB_MODE_3  (0xFC)
-#endif
-
-#if defined(__BOOT_LOCK_BITS_0_EXIST)
-#define BLB0_MODE_1  (0xFF)
-#define BLB0_MODE_2  (0xFB)
-#define BLB0_MODE_3  (0xF3)
-#define BLB0_MODE_4  (0xF7)
-#endif
-
-#if defined(__BOOT_LOCK_BITS_1_EXIST)
-#define BLB1_MODE_1  (0xFF)
-#define BLB1_MODE_2  (0xEF)
-#define BLB1_MODE_3  (0xCF)
-#define BLB1_MODE_4  (0xDF)
-#endif
-
-#if defined(__BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST)
-#define BLBAT0 ~_BV(2)
-#define BLBAT1 ~_BV(3)
-#endif
-
-#if defined(__BOOT_LOCK_APPLICATION_BITS_EXIST)
-#define BLBA0 ~_BV(4)
-#define BLBA1 ~_BV(5)
-#endif
-
-#if defined(__BOOT_LOCK_BOOT_BITS_EXIST)
-#define BLBB0 ~_BV(6)
-#define BLBB1 ~_BV(7)
-#endif
-
-
-#define LOCKBITS_DEFAULT (0xFF)
-
-/**@}*/
-#endif /* _AVR_LOCK_H_ */
diff --git a/cpukit/score/cpu/avr/avr/parity.h b/cpukit/score/cpu/avr/avr/parity.h
deleted file mode 100644
index e01148e7dd..0000000000
--- a/cpukit/score/cpu/avr/avr/parity.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file
- *
- * @brief Koved to <util/parity.h>
- */
-
-/*
- * Copyright (c) 2005 Joerg Wunsch
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_PARITY_H_
-#define _AVR_PARITY_H_
-
-/**
- * @defgroup AvrParity Parity
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#warning "This file has been moved to <util/parity.h>."
-#include <util/parity.h>
-
-/** @} */
-#endif /* _AVR_PARITY_H_ */
diff --git a/cpukit/score/cpu/avr/avr/pgmspace.h b/cpukit/score/cpu/avr/avr/pgmspace.h
deleted file mode 100644
index 42010168b1..0000000000
--- a/cpukit/score/cpu/avr/avr/pgmspace.h
+++ /dev/null
@@ -1,887 +0,0 @@
-/**
- * @file pgmspace.h
- *
- * @brief Definitions for ATmega640
- *
- *  The functions in this module provide interfaces for a program to access
- *  data stored in program space (flash memory) of the device.  In order to
- *  use these functions, the target device must support either the \c LPM or
- *  \c ELPM instructions.
- *
- *  @note These functions are an attempt to provide some compatibility with
- *  header files that come with IAR C, to make porting applications between
- *  different compilers easier.  This is not 100% compatibility though (GCC
- *  does not have full support for multiple address spaces yet).
- *
- *  @note If you are working with strings which are completely based in ram,
- *   use the standard string functions described in \ref avr_string.
- *
- *  \note If possible, put your constant tables in the lower 64 KB and use
- *  pgm_read_byte_near() or pgm_read_word_near() instead of
- *  pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that
- *  way, and you can still use the upper 64K for executable code.
- *  All functions that are suffixed with a \c _P \e require their
- *  arguments to be in the lower 64 KB of the flash ROM, as they do
- *  not use ELPM instructions.  This is normally not a big concern as
- *  the linker setup arranges any program space constants declared
- *  using the macros from this header file so they are placed right after
- *  the interrupt vectors, and in front of any executable code.  However,
- *  it can become a problem if there are too many of these constants, or
- *  for bootloaders on devices with more than 64 KB of ROM.
- *  <em>All these functions will not work in that situation.</em>
- *
- * Contributors:
- *   Created by Marek Michalkiewicz <marekm@linux.org.pl>
- *   Eric B. Weddington <eric@ecentral.com>
- *   Wolfgang Haidinger <wh@vmars.tuwien.ac.at> (pgm_read_dword())
- *   Ivanov Anton <anton@arc.com.ru> (pgm_read_float())
- */
-
-/*
- * Copyright (c) 2002 - 2007  Marek Michalkiewicz
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PGMSPACE_H_
-#define __PGMSPACE_H_ 1
-
-/**
- * @defgroup avr_pgmspace Program Space Utilities
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#define __need_size_t
-#include <inttypes.h>
-#include <stddef.h>
-#include <avr/io.h>
-
-#ifndef __ATTR_CONST__
-#define __ATTR_CONST__ __attribute__((__const__))
-#endif
-
-#ifndef __ATTR_PROGMEM__
-#define __ATTR_PROGMEM__ __attribute__((__progmem__))
-#endif
-
-#ifndef __ATTR_PURE__
-#define __ATTR_PURE__ __attribute__((__pure__))
-#endif
-
-/**
-   \ingroup avr_pgmspace
-   \def PROGMEM
-
-   Attribute to use in order to declare an object being located in
-   flash ROM.
- */
-#define PROGMEM __ATTR_PROGMEM__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__DOXYGEN__)
-/*
- * Doxygen doesn't grok the appended attribute syntax of
- * GCC, and confuses the typedefs with function decls, so
- * supply a doxygen-friendly view.
- */
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_void
-
-   Type of a "void" object located in flash ROM.  Does not make much
-   sense by itself, but can be used to declare a "void *" object in
-   flash ROM.
-*/
-typedef void PROGMEM prog_void;
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_char
-
-   Type of a "char" object located in flash ROM.
-*/
-typedef char PROGMEM prog_char;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_uchar
-
-   Type of an "unsigned char" object located in flash ROM.
-*/
-typedef unsigned char PROGMEM prog_uchar;
-
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_int8_t
-
-   Type of an "int8_t" object located in flash ROM.
-*/
-typedef int8_t PROGMEM prog_int8_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_uint8_t
-
-   Type of an "uint8_t" object located in flash ROM.
-*/
-typedef uint8_t PROGMEM prog_uint8_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_int16_t
-
-   Type of an "int16_t" object located in flash ROM.
-*/
-typedef int16_t PROGMEM prog_int16_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_uint16_t
-
-   Type of an "uint16_t" object located in flash ROM.
-*/
-typedef uint16_t PROGMEM prog_uint16_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_int32_t
-
-   Type of an "int32_t" object located in flash ROM.
-*/
-typedef int32_t PROGMEM prog_int32_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_uint32_t
-
-   Type of an "uint32_t" object located in flash ROM.
-*/
-typedef uint32_t PROGMEM prog_uint32_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_int64_t
-
-   Type of an "int64_t" object located in flash ROM.
-
-   \note This type is not available when the compiler
-   option -mint8 is in effect.
-*/
-typedef int64_t PROGMEM prog_int64_t;
-
-/**
-   \ingroup avr_pgmspace
-   \typedef prog_uint64_t
-
-   Type of an "uint64_t" object located in flash ROM.
-
-   \note This type is not available when the compiler
-   option -mint8 is in effect.
-*/
-typedef uint64_t PROGMEM prog_uint64_t;
-#else  /* !DOXYGEN */
-typedef void prog_void PROGMEM;
-typedef char prog_char PROGMEM;
-typedef unsigned char prog_uchar PROGMEM;
-
-typedef int8_t    prog_int8_t   PROGMEM;
-typedef uint8_t   prog_uint8_t  PROGMEM;
-typedef int16_t   prog_int16_t  PROGMEM;
-typedef uint16_t  prog_uint16_t PROGMEM;
-typedef int32_t   prog_int32_t  PROGMEM;
-typedef uint32_t  prog_uint32_t PROGMEM;
-#if !__USING_MINT8
-typedef int64_t   prog_int64_t  PROGMEM;
-typedef uint64_t  prog_uint64_t PROGMEM;
-#endif
-#endif /* defined(__DOXYGEN__) */
-
-/* Although in C, we can get away with just using __c, it does not work in
-   C++. We need to use &__c[0] to avoid the compiler puking. Dave Hylands
-   explaned it thusly,
-
-     Let's suppose that we use PSTR("Test"). In this case, the type returned
-     by __c is a prog_char[5] and not a prog_char *. While these are
-     compatible, they aren't the same thing (especially in C++). The type
-     returned by &__c[0] is a prog_char *, which explains why it works
-     fine. */
-
-#if defined(__DOXYGEN__)
-/*
- * The #define below is just a dummy that serves documentation
- * purposes only.
- */
-/** \ingroup avr_pgmspace
-    \def PSTR(s)
-
-    Used to declare a static pointer to a string in program space. */
-# define PSTR(s) ((const PROGMEM char *)(s))
-#else  /* !DOXYGEN */
-/* The real thing. */
-# define PSTR(s) (__extension__({static char __c[] PROGMEM = (s); &__c[0];}))
-#endif /* DOXYGEN */
-
-#define __LPM_classic__(addr)   \
-(__extension__({                \
-    uint16_t __addr16 = (uint16_t)(addr); \
-    uint8_t __result;           \
-    __asm__                     \
-    (                           \
-        "lpm" "\n\t"            \
-        "mov %0, r0" "\n\t"     \
-        : "=r" (__result)       \
-        : "z" (__addr16)        \
-        : "r0"                  \
-    );                          \
-    __result;                   \
-}))
-
-#define __LPM_enhanced__(addr)  \
-(__extension__({                \
-    uint16_t __addr16 = (uint16_t)(addr); \
-    uint8_t __result;           \
-    __asm__                     \
-    (                           \
-        "lpm %0, Z" "\n\t"      \
-        : "=r" (__result)       \
-        : "z" (__addr16)        \
-    );                          \
-    __result;                   \
-}))
-
-#define __LPM_word_classic__(addr)          \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    uint16_t __result;                      \
-    __asm__                                 \
-    (                                       \
-        "lpm"           "\n\t"              \
-        "mov %A0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %B0, r0"   "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-        : "r0"                              \
-    );                                      \
-    __result;                               \
-}))
-
-#define __LPM_word_enhanced__(addr)         \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    uint16_t __result;                      \
-    __asm__                                 \
-    (                                       \
-        "lpm %A0, Z+"   "\n\t"              \
-        "lpm %B0, Z"    "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-    );                                      \
-    __result;                               \
-}))
-
-#define __LPM_dword_classic__(addr)         \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    uint32_t __result;                      \
-    __asm__                                 \
-    (                                       \
-        "lpm"           "\n\t"              \
-        "mov %A0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %B0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %C0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %D0, r0"   "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-        : "r0"                              \
-    );                                      \
-    __result;                               \
-}))
-
-#define __LPM_dword_enhanced__(addr)        \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    uint32_t __result;                      \
-    __asm__                                 \
-    (                                       \
-        "lpm %A0, Z+"   "\n\t"              \
-        "lpm %B0, Z+"   "\n\t"              \
-        "lpm %C0, Z+"   "\n\t"              \
-        "lpm %D0, Z"    "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-    );                                      \
-    __result;                               \
-}))
-
-#define __LPM_float_classic__(addr)         \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    float __result;                         \
-    __asm__                                 \
-    (                                       \
-        "lpm"           "\n\t"              \
-        "mov %A0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %B0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %C0, r0"   "\n\t"              \
-        "adiw r30, 1"   "\n\t"              \
-        "lpm"           "\n\t"              \
-        "mov %D0, r0"   "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-        : "r0"                              \
-    );                                      \
-    __result;                               \
-}))
-
-#define __LPM_float_enhanced__(addr)        \
-(__extension__({                            \
-    uint16_t __addr16 = (uint16_t)(addr);   \
-    float __result;                         \
-    __asm__                                 \
-    (                                       \
-        "lpm %A0, Z+"   "\n\t"              \
-        "lpm %B0, Z+"   "\n\t"              \
-        "lpm %C0, Z+"   "\n\t"              \
-        "lpm %D0, Z"    "\n\t"              \
-        : "=r" (__result), "=z" (__addr16)  \
-        : "1" (__addr16)                    \
-    );                                      \
-    __result;                               \
-}))
-
-#if defined (__AVR_HAVE_LPMX__)
-#define __LPM(addr)         __LPM_enhanced__(addr)
-#define __LPM_word(addr)    __LPM_word_enhanced__(addr)
-#define __LPM_dword(addr)   __LPM_dword_enhanced__(addr)
-#define __LPM_float(addr)   __LPM_float_enhanced__(addr)
-#else
-#define __LPM(addr)         __LPM_classic__(addr)
-#define __LPM_word(addr)    __LPM_word_classic__(addr)
-#define __LPM_dword(addr)   __LPM_dword_classic__(addr)
-#define __LPM_float(addr)   __LPM_float_classic__(addr)
-#endif
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_byte_near(address_short)
-    Read a byte from the program space with a 16-bit (near) address.
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_byte_near(address_short) __LPM((uint16_t)(address_short))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_word_near(address_short)
-    Read a word from the program space with a 16-bit (near) address.
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_dword_near(address_short)
-    Read a double word from the program space with a 16-bit (near) address.
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_dword_near(address_short) \
-    __LPM_dword((uint16_t)(address_short))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_float_near(address_short)
-    Read a float from the program space with a 16-bit (near) address.
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_float_near(address_short) \
-    __LPM_float((uint16_t)(address_short))
-
-#if defined(RAMPZ) || defined(__DOXYGEN__)
-
-/* Only for devices with more than 64K of program memory.
-   RAMPZ must be defined (see iom103.h, iom128.h).
-*/
-
-/* The classic functions are needed for ATmega103. */
-
-#define __ELPM_classic__(addr)      \
-(__extension__({                    \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint8_t __result;               \
-    __asm__                         \
-    (                               \
-        "out %2, %C1" "\n\t"        \
-        "mov r31, %B1" "\n\t"       \
-        "mov r30, %A1" "\n\t"       \
-        "elpm" "\n\t"               \
-        "mov %0, r0" "\n\t"         \
-        : "=r" (__result)           \
-        : "r" (__addr32),           \
-          "I" (_SFR_IO_ADDR(RAMPZ)) \
-        : "r0", "r30", "r31"        \
-    );                              \
-    __result;                       \
-}))
-
-#define __ELPM_enhanced__(addr)     \
-(__extension__({                    \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint8_t __result;               \
-    __asm__                         \
-    (                               \
-        "out %2, %C1" "\n\t"        \
-        "movw r30, %1" "\n\t"       \
-        "elpm %0, Z+" "\n\t"        \
-        : "=r" (__result)           \
-        : "r" (__addr32),           \
-          "I" (_SFR_IO_ADDR(RAMPZ)) \
-        : "r30", "r31"              \
-    );                              \
-    __result;                       \
-}))
-
-#define __ELPM_xmega__(addr)        \
-(__extension__({                    \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint8_t __result;               \
-    __asm__                         \
-    (                               \
-        "in __tmp_reg__, %2" "\n\t" \
-        "out %2, %C1" "\n\t"        \
-        "movw r30, %1" "\n\t"       \
-        "elpm %0, Z+" "\n\t"        \
-        "out %2, __tmp_reg__"       \
-        : "=r" (__result)           \
-        : "r" (__addr32),           \
-          "I" (_SFR_IO_ADDR(RAMPZ)) \
-        : "r30", "r31"              \
-    );                              \
-    __result;                       \
-}))
-
-#define __ELPM_word_classic__(addr)     \
-(__extension__({                        \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint16_t __result;                  \
-    __asm__                             \
-    (                                   \
-        "out %2, %C1"   "\n\t"          \
-        "mov r31, %B1"  "\n\t"          \
-        "mov r30, %A1"  "\n\t"          \
-        "elpm"          "\n\t"          \
-        "mov %A0, r0"   "\n\t"          \
-        "in r0, %2"     "\n\t"          \
-        "adiw r30, 1"   "\n\t"          \
-        "adc r0, __zero_reg__" "\n\t"   \
-        "out %2, r0"    "\n\t"          \
-        "elpm"          "\n\t"          \
-        "mov %B0, r0"   "\n\t"          \
-        : "=r" (__result)               \
-        : "r" (__addr32),               \
-          "I" (_SFR_IO_ADDR(RAMPZ))     \
-        : "r0", "r30", "r31"            \
-    );                                  \
-    __result;                           \
-}))
-
-#define __ELPM_word_enhanced__(addr)    \
-(__extension__({                        \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint16_t __result;                  \
-    __asm__                             \
-    (                                   \
-        "out %2, %C1"   "\n\t"          \
-        "movw r30, %1"  "\n\t"          \
-        "elpm %A0, Z+"  "\n\t"          \
-        "elpm %B0, Z"   "\n\t"          \
-        : "=r" (__result)               \
-        : "r" (__addr32),               \
-          "I" (_SFR_IO_ADDR(RAMPZ))     \
-        : "r30", "r31"                  \
-    );                                  \
-    __result;                           \
-}))
-
-#define __ELPM_word_xmega__(addr)       \
-(__extension__({                        \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint16_t __result;                  \
-    __asm__                             \
-    (                                   \
-        "in __tmp_reg__, %2" "\n\t"     \
-        "out %2, %C1"   "\n\t"          \
-        "movw r30, %1"  "\n\t"          \
-        "elpm %A0, Z+"  "\n\t"          \
-        "elpm %B0, Z"   "\n\t"          \
-        "out %2, __tmp_reg__"           \
-        : "=r" (__result)               \
-        : "r" (__addr32),               \
-          "I" (_SFR_IO_ADDR(RAMPZ))     \
-        : "r30", "r31"                  \
-    );                                  \
-    __result;                           \
-}))
-
-#define __ELPM_dword_classic__(addr)      \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint32_t __result;                    \
-    __asm__                               \
-    (                                     \
-        "out %2, %C1"          "\n\t"     \
-        "mov r31, %B1"         "\n\t"     \
-        "mov r30, %A1"         "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %A0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %B0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %C0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %D0, r0"          "\n\t"     \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r0", "r30", "r31"              \
-    );                                    \
-    __result;                             \
-}))
-
-#define __ELPM_dword_enhanced__(addr)     \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint32_t __result;                    \
-    __asm__                               \
-    (                                     \
-        "out %2, %C1"   "\n\t"            \
-        "movw r30, %1"  "\n\t"            \
-        "elpm %A0, Z+"  "\n\t"            \
-        "elpm %B0, Z+"  "\n\t"            \
-        "elpm %C0, Z+"  "\n\t"            \
-        "elpm %D0, Z"   "\n\t"            \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r30", "r31"                    \
-    );                                    \
-    __result;                             \
-}))
-
-#define __ELPM_dword_xmega__(addr)        \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    uint32_t __result;                    \
-    __asm__                               \
-    (                                     \
-        "in __tmp_reg__, %2" "\n\t"       \
-        "out %2, %C1"   "\n\t"            \
-        "movw r30, %1"  "\n\t"            \
-        "elpm %A0, Z+"  "\n\t"            \
-        "elpm %B0, Z+"  "\n\t"            \
-        "elpm %C0, Z+"  "\n\t"            \
-        "elpm %D0, Z"   "\n\t"            \
-        "out %2, __tmp_reg__"             \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r30", "r31"                    \
-    );                                    \
-    __result;                             \
-}))
-
-#define __ELPM_float_classic__(addr)      \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    float __result;                       \
-    __asm__                               \
-    (                                     \
-        "out %2, %C1"          "\n\t"     \
-        "mov r31, %B1"         "\n\t"     \
-        "mov r30, %A1"         "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %A0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %B0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %C0, r0"          "\n\t"     \
-        "in r0, %2"            "\n\t"     \
-        "adiw r30, 1"          "\n\t"     \
-        "adc r0, __zero_reg__" "\n\t"     \
-        "out %2, r0"           "\n\t"     \
-        "elpm"                 "\n\t"     \
-        "mov %D0, r0"          "\n\t"     \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r0", "r30", "r31"              \
-    );                                    \
-    __result;                             \
-}))
-
-#define __ELPM_float_enhanced__(addr)     \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    float __result;                       \
-    __asm__                               \
-    (                                     \
-        "out %2, %C1"   "\n\t"            \
-        "movw r30, %1"  "\n\t"            \
-        "elpm %A0, Z+"  "\n\t"            \
-        "elpm %B0, Z+"  "\n\t"            \
-        "elpm %C0, Z+"  "\n\t"            \
-        "elpm %D0, Z"   "\n\t"            \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r30", "r31"                    \
-    );                                    \
-    __result;                             \
-}))
-
-#define __ELPM_float_xmega__(addr)        \
-(__extension__({                          \
-    uint32_t __addr32 = (uint32_t)(addr); \
-    float __result;                       \
-    __asm__                               \
-    (                                     \
-        "in __tmp_reg__, %2" "\n\t"       \
-        "out %2, %C1"   "\n\t"            \
-        "movw r30, %1"  "\n\t"            \
-        "elpm %A0, Z+"  "\n\t"            \
-        "elpm %B0, Z+"  "\n\t"            \
-        "elpm %C0, Z+"  "\n\t"            \
-        "elpm %D0, Z"   "\n\t"            \
-        "out %2, __tmp_reg__"             \
-        : "=r" (__result)                 \
-        : "r" (__addr32),                 \
-          "I" (_SFR_IO_ADDR(RAMPZ))       \
-        : "r30", "r31"                    \
-    );                                    \
-    __result;                             \
-}))
-
-/*
-Check for architectures that implement RAMPD (avrxmega3, avrxmega5,
-avrxmega7) as they need to save/restore RAMPZ for ELPM macros so it does
-not interfere with data accesses.
-*/
-#if defined (__AVR_HAVE_RAMPD__)
-
-#define __ELPM(addr)        __ELPM_xmega__(addr)
-#define __ELPM_word(addr)   __ELPM_word_xmega__(addr)
-#define __ELPM_dword(addr)  __ELPM_dword_xmega__(addr)
-#define __ELPM_float(addr)  __ELPM_float_xmega__(addr)
-
-#else
-
-#if defined (__AVR_HAVE_LPMX__)
-
-#define __ELPM(addr)        __ELPM_enhanced__(addr)
-#define __ELPM_word(addr)   __ELPM_word_enhanced__(addr)
-#define __ELPM_dword(addr)  __ELPM_dword_enhanced__(addr)
-#define __ELPM_float(addr)  __ELPM_float_enhanced__(addr)
-
-#else
-
-#define __ELPM(addr)        __ELPM_classic__(addr)
-#define __ELPM_word(addr)   __ELPM_word_classic__(addr)
-#define __ELPM_dword(addr)  __ELPM_dword_classic__(addr)
-#define __ELPM_float(addr)  __ELPM_float_classic__(addr)
-
-#endif  /* __AVR_HAVE_LPMX__ */
-
-#endif  /* __AVR_HAVE_RAMPD__ */
-
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_byte_far(address_long)
-    Read a byte from the program space with a 32-bit (far) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_byte_far(address_long)  __ELPM((uint32_t)(address_long))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_word_far(address_long)
-    Read a word from the program space with a 32-bit (far) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_word_far(address_long)  __ELPM_word((uint32_t)(address_long))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_dword_far(address_long)
-    Read a double word from the program space with a 32-bit (far) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_dword_far(address_long) __ELPM_dword((uint32_t)(address_long))
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_float_far(address_long)
-    Read a float from the program space with a 32-bit (far) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_float_far(address_long) __ELPM_float((uint32_t)(address_long))
-
-#endif /* RAMPZ or __DOXYGEN__ */
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_byte(address_short)
-    Read a byte from the program space with a 16-bit (near) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_byte(address_short)    pgm_read_byte_near(address_short)
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_word(address_short)
-    Read a word from the program space with a 16-bit (near) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_word(address_short)    pgm_read_word_near(address_short)
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_dword(address_short)
-    Read a double word from the program space with a 16-bit (near) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_dword(address_short)   pgm_read_dword_near(address_short)
-
-/** \ingroup avr_pgmspace
-    \def pgm_read_float(address_short)
-    Read a float from the program space with a 16-bit (near) address.
-
-    \note The address is a byte address.
-    The address is in the program space. */
-
-#define pgm_read_float(address_short)   pgm_read_float_near(address_short)
-
-/** \ingroup avr_pgmspace
-    \def PGM_P
-
-    Used to declare a variable that is a pointer to a string in program
-    space. */
-
-#ifndef PGM_P
-#define PGM_P const prog_char *
-#endif
-
-/** \ingroup avr_pgmspace
-    \def PGM_VOID_P
-
-    Used to declare a generic pointer to an object in program space. */
-
-#ifndef PGM_VOID_P
-#define PGM_VOID_P const prog_void *
-#endif
-
-extern PGM_VOID_P memchr_P(PGM_VOID_P, int __val, size_t __len) __ATTR_CONST__;
-extern int memcmp_P(const void *, PGM_VOID_P, size_t) __ATTR_PURE__;
-extern void *memccpy_P(void *, PGM_VOID_P, int __val, size_t);
-extern void *memcpy_P(void *, PGM_VOID_P, size_t);
-extern void *memmem_P(const void *, size_t, PGM_VOID_P, size_t) __ATTR_PURE__;
-extern PGM_VOID_P memrchr_P(PGM_VOID_P, int __val, size_t __len) __ATTR_CONST__;
-extern char *strcat_P(char *, PGM_P);
-extern PGM_P strchr_P(PGM_P, int __val) __ATTR_CONST__;
-extern PGM_P strchrnul_P(PGM_P, int __val) __ATTR_CONST__;
-extern int strcmp_P(const char *, PGM_P) __ATTR_PURE__;
-extern char *strcpy_P(char *, PGM_P);
-extern int strcasecmp_P(const char *, PGM_P) __ATTR_PURE__;
-extern char *strcasestr_P(const char *, PGM_P) __ATTR_PURE__;
-extern size_t strcspn_P(const char *__s, PGM_P __reject) __ATTR_PURE__;
-extern size_t strlcat_P (char *, PGM_P, size_t );
-extern size_t strlcpy_P (char *, PGM_P, size_t );
-extern size_t strlen_P(PGM_P) __ATTR_CONST__; /* program memory can't change */
-extern size_t strnlen_P(PGM_P, size_t) __ATTR_CONST__; /* program memory can't change */
-extern int strncmp_P(const char *, PGM_P, size_t) __ATTR_PURE__;
-extern int strncasecmp_P(const char *, PGM_P, size_t) __ATTR_PURE__;
-extern char *strncat_P(char *, PGM_P, size_t);
-extern char *strncpy_P(char *, PGM_P, size_t);
-extern char *strpbrk_P(const char *__s, PGM_P __accept) __ATTR_PURE__;
-extern PGM_P strrchr_P(PGM_P, int __val) __ATTR_CONST__;
-extern char *strsep_P(char **__sp, PGM_P __delim);
-extern size_t strspn_P(const char *__s, PGM_P __accept) __ATTR_PURE__;
-extern char *strstr_P(const char *, PGM_P) __ATTR_PURE__;
-extern char *strtok_P(char *__s, PGM_P __delim);
-extern char *strtok_rP(char *__s, PGM_P __delim, char **__last);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif /* __PGMSPACE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/portpins.h b/cpukit/score/cpu/avr/avr/portpins.h
deleted file mode 100644
index 5c84e9db89..0000000000
--- a/cpukit/score/cpu/avr/avr/portpins.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/**
- * @file
- *
- * @brief Define Generic PORTn, DDn, and PINn Values
- */
-
-/* Copyright (c) 2003  Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-#ifndef _AVR_PORTPINS_H_
-#define _AVR_PORTPINS_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-/* Port Data Register (generic) */
-#define    PORT7        7
-#define    PORT6        6
-#define    PORT5        5
-#define    PORT4        4
-#define    PORT3        3
-#define    PORT2        2
-#define    PORT1        1
-#define    PORT0        0
-
-/* Port Data Direction Register (generic) */
-#define    DD7          7
-#define    DD6          6
-#define    DD5          5
-#define    DD4          4
-#define    DD3          3
-#define    DD2          2
-#define    DD1          1
-#define    DD0          0
-
-/* Port Input Pins (generic) */
-#define    PIN7         7
-#define    PIN6         6
-#define    PIN5         5
-#define    PIN4         4
-#define    PIN3         3
-#define    PIN2         2
-#define    PIN1         1
-#define    PIN0         0
-
-/* Define PORTxn an Pxn values for all possible port pins 
- * if not defined already by io.h. 
- */
-
-/* PORT A */
-
-#if defined(PA0) && !defined(PORTA0)
-#  define PORTA0 PA0
-#elif defined(PORTA0) && !defined(PA0)
-#  define PA0 PORTA0
-#endif
-#if defined(PA1) && !defined(PORTA1)
-#  define PORTA1 PA1
-#elif defined(PORTA1) && !defined(PA1)
-#  define PA1 PORTA1
-#endif
-#if defined(PA2) && !defined(PORTA2)
-#  define PORTA2 PA2
-#elif defined(PORTA2) && !defined(PA2)
-#  define PA2 PORTA2
-#endif
-#if defined(PA3) && !defined(PORTA3)
-#  define PORTA3 PA3
-#elif defined(PORTA3) && !defined(PA3)
-#  define PA3 PORTA3
-#endif
-#if defined(PA4) && !defined(PORTA4)
-#  define PORTA4 PA4
-#elif defined(PORTA4) && !defined(PA4)
-#  define PA4 PORTA4
-#endif
-#if defined(PA5) && !defined(PORTA5)
-#  define PORTA5 PA5
-#elif defined(PORTA5) && !defined(PA5)
-#  define PA5 PORTA5
-#endif
-#if defined(PA6) && !defined(PORTA6)
-#  define PORTA6 PA6
-#elif defined(PORTA6) && !defined(PA6)
-#  define PA6 PORTA6
-#endif
-#if defined(PA7) && !defined(PORTA7)
-#  define PORTA7 PA7
-#elif defined(PORTA7) && !defined(PA7)
-#  define PA7 PORTA7
-#endif
-
-/* PORT B */
-
-#if defined(PB0) && !defined(PORTB0)
-#  define PORTB0 PB0
-#elif defined(PORTB0) && !defined(PB0)
-#  define PB0 PORTB0
-#endif
-#if defined(PB1) && !defined(PORTB1)
-#  define PORTB1 PB1
-#elif defined(PORTB1) && !defined(PB1)
-#  define PB1 PORTB1
-#endif
-#if defined(PB2) && !defined(PORTB2)
-#  define PORTB2 PB2
-#elif defined(PORTB2) && !defined(PB2)
-#  define PB2 PORTB2
-#endif
-#if defined(PB3) && !defined(PORTB3)
-#  define PORTB3 PB3
-#elif defined(PORTB3) && !defined(PB3)
-#  define PB3 PORTB3
-#endif
-#if defined(PB4) && !defined(PORTB4)
-#  define PORTB4 PB4
-#elif defined(PORTB4) && !defined(PB4)
-#  define PB4 PORTB4
-#endif
-#if defined(PB5) && !defined(PORTB5)
-#  define PORTB5 PB5
-#elif defined(PORTB5) && !defined(PB5)
-#  define PB5 PORTB5
-#endif
-#if defined(PB6) && !defined(PORTB6)
-#  define PORTB6 PB6
-#elif defined(PORTB6) && !defined(PB6)
-#  define PB6 PORTB6
-#endif
-#if defined(PB7) && !defined(PORTB7)
-#  define PORTB7 PB7
-#elif defined(PORTB7) && !defined(PB7)
-#  define PB7 PORTB7
-#endif
-
-/* PORT C */
-
-#if defined(PC0) && !defined(PORTC0)
-#  define PORTC0 PC0
-#elif defined(PORTC0) && !defined(PC0)
-#  define PC0 PORTC0
-#endif
-#if defined(PC1) && !defined(PORTC1)
-#  define PORTC1 PC1
-#elif defined(PORTC1) && !defined(PC1)
-#  define PC1 PORTC1
-#endif
-#if defined(PC2) && !defined(PORTC2)
-#  define PORTC2 PC2
-#elif defined(PORTC2) && !defined(PC2)
-#  define PC2 PORTC2
-#endif
-#if defined(PC3) && !defined(PORTC3)
-#  define PORTC3 PC3
-#elif defined(PORTC3) && !defined(PC3)
-#  define PC3 PORTC3
-#endif
-#if defined(PC4) && !defined(PORTC4)
-#  define PORTC4 PC4
-#elif defined(PORTC4) && !defined(PC4)
-#  define PC4 PORTC4
-#endif
-#if defined(PC5) && !defined(PORTC5)
-#  define PORTC5 PC5
-#elif defined(PORTC5) && !defined(PC5)
-#  define PC5 PORTC5
-#endif
-#if defined(PC6) && !defined(PORTC6)
-#  define PORTC6 PC6
-#elif defined(PORTC6) && !defined(PC6)
-#  define PC6 PORTC6
-#endif
-#if defined(PC7) && !defined(PORTC7)
-#  define PORTC7 PC7
-#elif defined(PORTC7) && !defined(PC7)
-#  define PC7 PORTC7
-#endif
-
-/* PORT D */
-
-#if defined(PD0) && !defined(PORTD0)
-#  define PORTD0 PD0
-#elif defined(PORTD0) && !defined(PD0)
-#  define PD0 PORTD0
-#endif
-#if defined(PD1) && !defined(PORTD1)
-#  define PORTD1 PD1
-#elif defined(PORTD1) && !defined(PD1)
-#  define PD1 PORTD1
-#endif
-#if defined(PD2) && !defined(PORTD2)
-#  define PORTD2 PD2
-#elif defined(PORTD2) && !defined(PD2)
-#  define PD2 PORTD2
-#endif
-#if defined(PD3) && !defined(PORTD3)
-#  define PORTD3 PD3
-#elif defined(PORTD3) && !defined(PD3)
-#  define PD3 PORTD3
-#endif
-#if defined(PD4) && !defined(PORTD4)
-#  define PORTD4 PD4
-#elif defined(PORTD4) && !defined(PD4)
-#  define PD4 PORTD4
-#endif
-#if defined(PD5) && !defined(PORTD5)
-#  define PORTD5 PD5
-#elif defined(PORTD5) && !defined(PD5)
-#  define PD5 PORTD5
-#endif
-#if defined(PD6) && !defined(PORTD6)
-#  define PORTD6 PD6
-#elif defined(PORTD6) && !defined(PD6)
-#  define PD6 PORTD6
-#endif
-#if defined(PD7) && !defined(PORTD7)
-#  define PORTD7 PD7
-#elif defined(PORTD7) && !defined(PD7)
-#  define PD7 PORTD7
-#endif
-
-/* PORT E */
-
-#if defined(PE0) && !defined(PORTE0)
-#  define PORTE0 PE0
-#elif defined(PORTE0) && !defined(PE0)
-#  define PE0 PORTE0
-#endif
-#if defined(PE1) && !defined(PORTE1)
-#  define PORTE1 PE1
-#elif defined(PORTE1) && !defined(PE1)
-#  define PE1 PORTE1
-#endif
-#if defined(PE2) && !defined(PORTE2)
-#  define PORTE2 PE2
-#elif defined(PORTE2) && !defined(PE2)
-#  define PE2 PORTE2
-#endif
-#if defined(PE3) && !defined(PORTE3)
-#  define PORTE3 PE3
-#elif defined(PORTE3) && !defined(PE3)
-#  define PE3 PORTE3
-#endif
-#if defined(PE4) && !defined(PORTE4)
-#  define PORTE4 PE4
-#elif defined(PORTE4) && !defined(PE4)
-#  define PE4 PORTE4
-#endif
-#if defined(PE5) && !defined(PORTE5)
-#  define PORTE5 PE5
-#elif defined(PORTE5) && !defined(PE5)
-#  define PE5 PORTE5
-#endif
-#if defined(PE6) && !defined(PORTE6)
-#  define PORTE6 PE6
-#elif defined(PORTE6) && !defined(PE6)
-#  define PE6 PORTE6
-#endif
-#if defined(PE7) && !defined(PORTE7)
-#  define PORTE7 PE7
-#elif defined(PORTE7) && !defined(PE7)
-#  define PE7 PORTE7
-#endif
-
-/* PORT F */
-
-#if defined(PF0) && !defined(PORTF0)
-#  define PORTF0 PF0
-#elif defined(PORTF0) && !defined(PF0)
-#  define PF0 PORTF0
-#endif
-#if defined(PF1) && !defined(PORTF1)
-#  define PORTF1 PF1
-#elif defined(PORTF1) && !defined(PF1)
-#  define PF1 PORTF1
-#endif
-#if defined(PF2) && !defined(PORTF2)
-#  define PORTF2 PF2
-#elif defined(PORTF2) && !defined(PF2)
-#  define PF2 PORTF2
-#endif
-#if defined(PF3) && !defined(PORTF3)
-#  define PORTF3 PF3
-#elif defined(PORTF3) && !defined(PF3)
-#  define PF3 PORTF3
-#endif
-#if defined(PF4) && !defined(PORTF4)
-#  define PORTF4 PF4
-#elif defined(PORTF4) && !defined(PF4)
-#  define PF4 PORTF4
-#endif
-#if defined(PF5) && !defined(PORTF5)
-#  define PORTF5 PF5
-#elif defined(PORTF5) && !defined(PF5)
-#  define PF5 PORTF5
-#endif
-#if defined(PF6) && !defined(PORTF6)
-#  define PORTF6 PF6
-#elif defined(PORTF6) && !defined(PF6)
-#  define PF6 PORTF6
-#endif
-#if defined(PF7) && !defined(PORTF7)
-#  define PORTF7 PF7
-#elif defined(PORTF7) && !defined(PF7)
-#  define PF7 PORTF7
-#endif
-
-/* PORT G */
-
-#if defined(PG0) && !defined(PORTG0)
-#  define PORTG0 PG0
-#elif defined(PORTG0) && !defined(PG0)
-#  define PG0 PORTG0
-#endif
-#if defined(PG1) && !defined(PORTG1)
-#  define PORTG1 PG1
-#elif defined(PORTG1) && !defined(PG1)
-#  define PG1 PORTG1
-#endif
-#if defined(PG2) && !defined(PORTG2)
-#  define PORTG2 PG2
-#elif defined(PORTG2) && !defined(PG2)
-#  define PG2 PORTG2
-#endif
-#if defined(PG3) && !defined(PORTG3)
-#  define PORTG3 PG3
-#elif defined(PORTG3) && !defined(PG3)
-#  define PG3 PORTG3
-#endif
-#if defined(PG4) && !defined(PORTG4)
-#  define PORTG4 PG4
-#elif defined(PORTG4) && !defined(PG4)
-#  define PG4 PORTG4
-#endif
-#if defined(PG5) && !defined(PORTG5)
-#  define PORTG5 PG5
-#elif defined(PORTG5) && !defined(PG5)
-#  define PG5 PORTG5
-#endif
-#if defined(PG6) && !defined(PORTG6)
-#  define PORTG6 PG6
-#elif defined(PORTG6) && !defined(PG6)
-#  define PG6 PORTG6
-#endif
-#if defined(PG7) && !defined(PORTG7)
-#  define PORTG7 PG7
-#elif defined(PORTG7) && !defined(PG7)
-#  define PG7 PORTG7
-#endif
-
-/* PORT H */
-
-#if defined(PH0) && !defined(PORTH0)
-#  define PORTH0 PH0
-#elif defined(PORTH0) && !defined(PH0)
-#  define PH0 PORTH0
-#endif
-#if defined(PH1) && !defined(PORTH1)
-#  define PORTH1 PH1
-#elif defined(PORTH1) && !defined(PH1)
-#  define PH1 PORTH1
-#endif
-#if defined(PH2) && !defined(PORTH2)
-#  define PORTH2 PH2
-#elif defined(PORTH2) && !defined(PH2)
-#  define PH2 PORTH2
-#endif
-#if defined(PH3) && !defined(PORTH3)
-#  define PORTH3 PH3
-#elif defined(PORTH3) && !defined(PH3)
-#  define PH3 PORTH3
-#endif
-#if defined(PH4) && !defined(PORTH4)
-#  define PORTH4 PH4
-#elif defined(PORTH4) && !defined(PH4)
-#  define PH4 PORTH4
-#endif
-#if defined(PH5) && !defined(PORTH5)
-#  define PORTH5 PH5
-#elif defined(PORTH5) && !defined(PH5)
-#  define PH5 PORTH5
-#endif
-#if defined(PH6) && !defined(PORTH6)
-#  define PORTH6 PH6
-#elif defined(PORTH6) && !defined(PH6)
-#  define PH6 PORTH6
-#endif
-#if defined(PH7) && !defined(PORTH7)
-#  define PORTH7 PH7
-#elif defined(PORTH7) && !defined(PH7)
-#  define PH7 PORTH7
-#endif
-
-/* PORT J */
-
-#if defined(PJ0) && !defined(PORTJ0)
-#  define PORTJ0 PJ0
-#elif defined(PORTJ0) && !defined(PJ0)
-#  define PJ0 PORTJ0
-#endif
-#if defined(PJ1) && !defined(PORTJ1)
-#  define PORTJ1 PJ1
-#elif defined(PORTJ1) && !defined(PJ1)
-#  define PJ1 PORTJ1
-#endif
-#if defined(PJ2) && !defined(PORTJ2)
-#  define PORTJ2 PJ2
-#elif defined(PORTJ2) && !defined(PJ2)
-#  define PJ2 PORTJ2
-#endif
-#if defined(PJ3) && !defined(PORTJ3)
-#  define PORTJ3 PJ3
-#elif defined(PORTJ3) && !defined(PJ3)
-#  define PJ3 PORTJ3
-#endif
-#if defined(PJ4) && !defined(PORTJ4)
-#  define PORTJ4 PJ4
-#elif defined(PORTJ4) && !defined(PJ4)
-#  define PJ4 PORTJ4
-#endif
-#if defined(PJ5) && !defined(PORTJ5)
-#  define PORTJ5 PJ5
-#elif defined(PORTJ5) && !defined(PJ5)
-#  define PJ5 PORTJ5
-#endif
-#if defined(PJ6) && !defined(PORTJ6)
-#  define PORTJ6 PJ6
-#elif defined(PORTJ6) && !defined(PJ6)
-#  define PJ6 PORTJ6
-#endif
-#if defined(PJ7) && !defined(PORTJ7)
-#  define PORTJ7 PJ7
-#elif defined(PORTJ7) && !defined(PJ7)
-#  define PJ7 PORTJ7
-#endif
-
-/* PORT K */
-
-#if defined(PK0) && !defined(PORTK0)
-#  define PORTK0 PK0
-#elif defined(PORTK0) && !defined(PK0)
-#  define PK0 PORTK0
-#endif
-#if defined(PK1) && !defined(PORTK1)
-#  define PORTK1 PK1
-#elif defined(PORTK1) && !defined(PK1)
-#  define PK1 PORTK1
-#endif
-#if defined(PK2) && !defined(PORTK2)
-#  define PORTK2 PK2
-#elif defined(PORTK2) && !defined(PK2)
-#  define PK2 PORTK2
-#endif
-#if defined(PK3) && !defined(PORTK3)
-#  define PORTK3 PK3
-#elif defined(PORTK3) && !defined(PK3)
-#  define PK3 PORTK3
-#endif
-#if defined(PK4) && !defined(PORTK4)
-#  define PORTK4 PK4
-#elif defined(PORTK4) && !defined(PK4)
-#  define PK4 PORTK4
-#endif
-#if defined(PK5) && !defined(PORTK5)
-#  define PORTK5 PK5
-#elif defined(PORTK5) && !defined(PK5)
-#  define PK5 PORTK5
-#endif
-#if defined(PK6) && !defined(PORTK6)
-#  define PORTK6 PK6
-#elif defined(PORTK6) && !defined(PK6)
-#  define PK6 PORTK6
-#endif
-#if defined(PK7) && !defined(PORTK7)
-#  define PORTK7 PK7
-#elif defined(PORTK7) && !defined(PK7)
-#  define PK7 PORTK7
-#endif
-
-/* PORT L */
-
-#if defined(PL0) && !defined(PORTL0)
-#  define PORTL0 PL0
-#elif defined(PORTL0) && !defined(PL0)
-#  define PL0 PORTL0
-#endif
-#if defined(PL1) && !defined(PORTL1)
-#  define PORTL1 PL1
-#elif defined(PORTL1) && !defined(PL1)
-#  define PL1 PORTL1
-#endif
-#if defined(PL2) && !defined(PORTL2)
-#  define PORTL2 PL2
-#elif defined(PORTL2) && !defined(PL2)
-#  define PL2 PORTL2
-#endif
-#if defined(PL3) && !defined(PORTL3)
-#  define PORTL3 PL3
-#elif defined(PORTL3) && !defined(PL3)
-#  define PL3 PORTL3
-#endif
-#if defined(PL4) && !defined(PORTL4)
-#  define PORTL4 PL4
-#elif defined(PORTL4) && !defined(PL4)
-#  define PL4 PORTL4
-#endif
-#if defined(PL5) && !defined(PORTL5)
-#  define PORTL5 PL5
-#elif defined(PORTL5) && !defined(PL5)
-#  define PL5 PORTL5
-#endif
-#if defined(PL6) && !defined(PORTL6)
-#  define PORTL6 PL6
-#elif defined(PORTL6) && !defined(PL6)
-#  define PL6 PORTL6
-#endif
-#if defined(PL7) && !defined(PORTL7)
-#  define PORTL7 PL7
-#elif defined(PORTL7) && !defined(PL7)
-#  define PL7 PORTL7
-#endif
-
-#endif /* _AVR_PORTPINS_H_ */
diff --git a/cpukit/score/cpu/avr/avr/power.h b/cpukit/score/cpu/avr/avr/power.h
deleted file mode 100644
index b101f3bcbd..0000000000
--- a/cpukit/score/cpu/avr/avr/power.h
+++ /dev/null
@@ -1,1201 +0,0 @@
-/**
- * @file avr/iom644PA.h
- *
- * @brief Power Reduction Management
- *
- * Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
- * allow you to reduce power consumption by disabling or enabling various on-board
- * peripherals as needed.
- *
- * There are many macros in this header file that provide an easy interface
- * to enable or disable on-board peripherals to reduce power. See the table below.
- *
- * @note Not all AVR devices have a Power Reduction Register (for example
- * the ATmega128). On those devices without a Power Reduction Register, these
- * macros are not available.
- *
- * @note Not all AVR devices contain the same peripherals (for example, the LCD
- * interface), or they will be named differently (for example, USART and
- * USART0). Please consult your device's datasheet, or the header file, to
- * find out which macros are applicable to your device.
- */
-
-/*
- *  Copyright (c) 2006, 2007, 2008  Eric B. Weddington
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_POWER_H_
-#define _AVR_POWER_H_   1
-
-#include <avr/io.h>
-#include <stdint.h>
-
-/**
- *  @defgroup avr_power Power Reduction Management
- *
- *  @ingroup avr
- *
- *  @addtogroup avr_power
- */
-/**@{*/
-
-
-#if defined(__AVR_ATxmega16A4__) \
-|| defined(__AVR_ATxmega16D4__) \
-|| defined(__AVR_ATxmega32A4__) \
-|| defined(__AVR_ATxmega32D4__) \
-|| defined(__AVR_ATxmega64A1__) \
-|| defined(__AVR_ATxmega64A3__) \
-|| defined(__AVR_ATxmega64D3__) \
-|| defined(__AVR_ATxmega128A1__) \
-|| defined(__AVR_ATxmega128A3__) \
-|| defined(__AVR_ATxmega128D3__) \
-|| defined(__AVR_ATxmega192A3__) \
-|| defined(__AVR_ATxmega192D3__) \
-|| defined(__AVR_ATxmega256D3__) \
-|| defined(__AVR_ATxmega256A3__) \
-|| defined(__AVR_ATxmega256A3B__)
-
-/*
-#define power_aes_enable()  (PR_PR &= (uint8_t)~(PR_AES_bm))
-#define power_aes_disable() (PR_PR |= (uint8_t)PR_AES_bm)
-*/
-
-#define power_ebi_enable()  (PR_PR &= (uint8_t)~(PR_EBI_bm))
-#define power_ebi_disable() (PR_PR |= (uint8_t)PR_EBI_bm)
-
-#define power_rtc_enable()  (PR_PR &= (uint8_t)~(PR_RTC_bm))
-#define power_rtc_disable() (PR_PR |= (uint8_t)PR_RTC_bm)
-
-#define power_evsys_enable()    (PR_PR &= (uint8_t)~(PR_EVSYS_bm))
-#define power_evsys_disable()   (PR_PR |= (uint8_t)PR_EVSYS_bm)
-
-#define power_dma_enable()    (PR_PR &= (uint8_t)~(PR_DMA_bm))
-#define power_dma_disable()   (PR_PR |= (uint8_t)PR_DMA_bm)
-
-#define power_daca_enable()     (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
-#define power_daca_disable()    (PR_PRPA |= (uint8_t)PR_DAC_bm)
-#define power_dacb_enable()     (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
-#define power_dacb_disable()    (PR_PRPB |= (uint8_t)PR_DAC_bm)
-
-#define power_adca_enable()     (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
-#define power_adca_disable()    (PR_PRPA |= (uint8_t)PR_ADC_bm)
-#define power_adcb_enable()     (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
-#define power_adcb_disable()    (PR_PRPB |= (uint8_t)PR_ADC_bm)
-
-#define power_aca_enable()      (PR_PRPA &= (uint8_t)~(PR_AC_bm))
-#define power_aca_disable()     (PR_PRPA |= (uint8_t)PR_AC_bm)
-#define power_acb_enable()      (PR_PRPB &= (uint8_t)~(PR_AC_bm))
-#define power_acb_disable()     (PR_PRPB |= (uint8_t)PR_AC_bm)
-
-#define power_twic_enable()     (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
-#define power_twic_disable()    (PR_PRPC |= (uint8_t)PR_TWI_bm)
-#define power_twid_enable()     (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
-#define power_twid_disable()    (PR_PRPD |= (uint8_t)PR_TWI_bm)
-#define power_twie_enable()     (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
-#define power_twie_disable()    (PR_PRPE |= (uint8_t)PR_TWI_bm)
-#define power_twif_enable()     (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
-#define power_twif_disable()    (PR_PRPF |= (uint8_t)PR_TWI_bm)
-
-#define power_usartc1_enable()  (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
-#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
-#define power_usartd1_enable()  (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
-#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
-#define power_usarte1_enable()  (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
-#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
-#define power_usartf1_enable()  (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
-#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
-
-#define power_usartc0_enable()  (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
-#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
-#define power_usartd0_enable()  (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
-#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
-#define power_usarte0_enable()  (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
-#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
-#define power_usartf0_enable()  (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
-#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
-
-#define power_spic_enable()     (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
-#define power_spic_disable()    (PR_PRPC |= (uint8_t)PR_SPI_bm)
-#define power_spid_enable()     (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
-#define power_spid_disable()    (PR_PRPD |= (uint8_t)PR_SPI_bm)
-#define power_spie_enable()     (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
-#define power_spie_disable()    (PR_PRPE |= (uint8_t)PR_SPI_bm)
-#define power_spif_enable()     (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
-#define power_spif_disable()    (PR_PRPF |= (uint8_t)PR_SPI_bm)
-
-#define power_hiresc_enable()   (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
-#define power_hiresc_disable()  (PR_PRPC |= (uint8_t)PR_HIRES_bm)
-#define power_hiresd_enable()   (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
-#define power_hiresd_disable()  (PR_PRPD |= (uint8_t)PR_HIRES_bm)
-#define power_hirese_enable()   (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
-#define power_hirese_disable()  (PR_PRPE |= (uint8_t)PR_HIRES_bm)
-#define power_hiresf_enable()   (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
-#define power_hiresf_disable()  (PR_PRPF |= (uint8_t)PR_HIRES_bm)
-
-#define power_tc1c_enable()     (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
-#define power_tc1c_disable()    (PR_PRPC |= (uint8_t)PR_TC1_bm)
-#define power_tc1d_enable()     (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
-#define power_tc1d_disable()    (PR_PRPD |= (uint8_t)PR_TC1_bm)
-#define power_tc1e_enable()     (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
-#define power_tc1e_disable()    (PR_PRPE |= (uint8_t)PR_TC1_bm)
-#define power_tc1f_enable()     (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
-#define power_tc1f_disable()    (PR_PRPF |= (uint8_t)PR_TC1_bm)
-
-#define power_tc0c_enable()     (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
-#define power_tc0c_disable()    (PR_PRPC |= (uint8_t)PR_TC0_bm)
-#define power_tc0d_enable()     (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
-#define power_tc0d_disable()    (PR_PRPD |= (uint8_t)PR_TC0_bm)
-#define power_tc0e_enable()     (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
-#define power_tc0e_disable()    (PR_PRPE |= (uint8_t)PR_TC0_bm)
-#define power_tc0f_enable()     (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
-#define power_tc0f_disable()    (PR_PRPF |= (uint8_t)PR_TC0_bm)
-
-#define power_all_enable() \
-do { \
-    /* PR_PR &= (uint8_t)~(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); */ \
-    PR_PR &= (uint8_t)~(PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
-    PR_PRPA &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
-    PR_PRPB &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
-    PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-} while(0)
-
-
-#define power_all_disable() \
-do { \
-    /* PM_PR_PR |= (uint8_t)(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); */ \
-    PR_PR |= (uint8_t)(PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
-    PR_PRPA |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
-    PR_PRPB |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
-    PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-    PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
-} while(0)
-
-
-#elif defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__)
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_timer4_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM4))
-#define power_timer4_disable()  (PRR1 |= (uint8_t)(1 << PRTIM4))
-
-#define power_timer5_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM5))
-#define power_timer5_disable()  (PRR1 |= (uint8_t)(1 << PRTIM5))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_usart2_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART2))
-#define power_usart2_disable()  (PRR1 |= (uint8_t)(1 << PRUSART2))
-
-#define power_usart3_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART3))
-#define power_usart3_disable()  (PRR1 |= (uint8_t)(1 << PRUSART3))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
-    PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
-    PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)); \
-}while(0)
-
-
-#elif defined(__AVR_ATmega128RFA1__)
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_timer4_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM4))
-#define power_timer4_disable()  (PRR1 |= (uint8_t)(1 << PRTIM4))
-
-#define power_timer5_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM5))
-#define power_timer5_disable()  (PRR1 |= (uint8_t)(1 << PRTIM5))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
-    PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)); \
-    PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTIM5)|(1<<PRUSART1)); \
-}while(0)
-
-
-#elif defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__)
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_usb_enable()      (PRR1 &= (uint8_t)~(1 << PRUSB))
-#define power_usb_disable()     (PRR1 |= (uint8_t)(1 << PRUSB))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-
-#elif defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega16U4__)
-
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_usb_enable()      (PRR1 &= (uint8_t)~(1 << PRUSB))
-#define power_usb_disable()     (PRR1 |= (uint8_t)(1 << PRUSB))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-
-#elif defined(__AVR_ATmega32U6__)
-
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_usb_enable()      (PRR1 &= (uint8_t)~(1 << PRUSB))
-#define power_usb_disable()     (PRR1 |= (uint8_t)(1 << PRUSB))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 &= (uint8_t)~((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)); \
-    PRR1 |= (uint8_t)((1<<PRTIM3)|(1<<PRUSART1)|(1<<PRUSB)); \
-}while(0)
-
-
-#elif defined(__AVR_AT90PWM1__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-/* Power Stage Controller 0 */
-#define power_psc0_enable()     (PRR &= (uint8_t)~(1 << PRPSC0))
-#define power_psc0_disable()    (PRR |= (uint8_t)(1 << PRPSC0))
-
-/* Power Stage Controller 1 */
-#define power_psc1_enable()     (PRR &= (uint8_t)~(1 << PRPSC1))
-#define power_psc1_disable()    (PRR |= (uint8_t)(1 << PRPSC1))
-
-/* Power Stage Controller 2 */
-#define power_psc2_enable()     (PRR &= (uint8_t)~(1 << PRPSC2))
-#define power_psc2_disable()    (PRR |= (uint8_t)(1 << PRPSC2))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
-
-
-#elif defined(__AVR_AT90PWM2__) \
-|| defined(__AVR_AT90PWM2B__) \
-|| defined(__AVR_AT90PWM3__) \
-|| defined(__AVR_AT90PWM3B__) \
-|| defined(__AVR_AT90PWM216__) \
-|| defined(__AVR_AT90PWM316__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_usart_enable()    (PRR &= (uint8_t)~(1 << PRUSART))
-#define power_usart_disable()   (PRR |= (uint8_t)(1 << PRUSART))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-/* Power Stage Controller 0 */
-#define power_psc0_enable()     (PRR &= (uint8_t)~(1 << PRPSC0))
-#define power_psc0_disable()    (PRR |= (uint8_t)(1 << PRPSC0))
-
-/* Power Stage Controller 1 */
-#define power_psc1_enable()     (PRR &= (uint8_t)~(1 << PRPSC1))
-#define power_psc1_disable()    (PRR |= (uint8_t)(1 << PRPSC1))
-
-/* Power Stage Controller 2 */
-#define power_psc2_enable()     (PRR &= (uint8_t)~(1 << PRPSC2))
-#define power_psc2_disable()    (PRR |= (uint8_t)(1 << PRPSC2))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2)))
-
-
-#elif defined(__AVR_AT90PWM81__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-/* Power Stage Controller 0 */
-#define power_psc0_enable()     (PRR &= (uint8_t)~(1 << PRPSC0))
-#define power_psc0_disable()    (PRR |= (uint8_t)(1 << PRPSC0))
-
-/* Power Stage Controller 2 */
-#define power_psc2_enable()     (PRR &= (uint8_t)~(1 << PRPSC2))
-#define power_psc2_disable()    (PRR |= (uint8_t)(1 << PRPSC2))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC2)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC2)))
-
-
-#elif defined(__AVR_ATmega165__) \
-|| defined(__AVR_ATmega165A__) \
-|| defined(__AVR_ATmega165P__) \
-|| defined(__AVR_ATmega325__) \
-|| defined(__AVR_ATmega3250__) \
-|| defined(__AVR_ATmega645__) \
-|| defined(__AVR_ATmega645A__) \
-|| defined(__AVR_ATmega645P__) \
-|| defined(__AVR_ATmega6450__) \
-|| defined(__AVR_ATmega6450A__) \
-|| defined(__AVR_ATmega6450P__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_usart0_enable()   (PRR &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR |= (uint8_t)(1 << PRUSART0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)))
-
-
-#elif defined(__AVR_ATmega169__) \
-|| defined(__AVR_ATmega169A__) \
-|| defined(__AVR_ATmega169P__) \
-|| defined(__AVR_ATmega169PA__) \
-|| defined(__AVR_ATmega329__) \
-|| defined(__AVR_ATmega329P__) \
-|| defined(__AVR_ATmega329PA__) \
-|| defined(__AVR_ATmega3290__) \
-|| defined(__AVR_ATmega3290P__) \
-|| defined(__AVR_ATmega649__) \
-|| defined(__AVR_ATmega649A__) \
-|| defined(__AVR_ATmega649P__) \
-|| defined(__AVR_ATmega6490__) \
-|| defined(__AVR_ATmega6490A__) \
-|| defined(__AVR_ATmega6490P__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_usart0_enable()   (PRR &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR |= (uint8_t)(1 << PRUSART0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-#define power_lcd_enable()      (PRR &= (uint8_t)~(1 << PRLCD))
-#define power_lcd_disable()     (PRR |= (uint8_t)(1 << PRLCD))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)|(1<<PRLCD)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)|(1<<PRLCD)))
-
-
-#elif defined(__AVR_ATmega164A__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega324A__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega324PA__)
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_usart1_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR0 |= (uint8_t)(1 << PRUSART1))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_all_enable()      (PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)))
-#define power_all_disable()     (PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)))
-
-
-#elif defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644A__) \
-|| defined(__AVR_ATmega644P__)
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_all_enable()      (PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
-#define power_all_disable()     (PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
-
-
-#elif defined(__AVR_ATmega406__)
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-/* Voltage ADC */
-#define power_vadc_enable()     (PRR0 &= (uint8_t)~(1 << PRVADC))
-#define power_vadc_disable()    (PRR0 |= (uint8_t)(1 << PRVADC))
-
-#define power_all_enable()      (PRR0 &= (uint8_t)~((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)))
-#define power_all_disable()     (PRR0 |= (uint8_t)((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)))
-
-
-#elif defined(__AVR_ATmega48__) \
-|| defined(__AVR_ATmega48A__) \
-|| defined(__AVR_ATmega48P__) \
-|| defined(__AVR_ATmega88__) \
-|| defined(__AVR_ATmega88A__) \
-|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATmega88PA__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega168A__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega328__) \
-|| defined(__AVR_ATmega328P__) \
-|| defined(__AVR_ATtiny48__) \
-|| defined(__AVR_ATtiny88__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_usart0_enable()   (PRR &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR |= (uint8_t)(1 << PRUSART0))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR |= (uint8_t)(1 << PRTIM2))
-
-#define power_twi_enable()      (PRR &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR |= (uint8_t)(1 << PRTWI))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
-
-
-#elif defined(__AVR_ATtiny24__) \
-|| defined(__AVR_ATtiny24A__) \
-|| defined(__AVR_ATtiny44__) \
-|| defined(__AVR_ATtiny44A__) \
-|| defined(__AVR_ATtiny84__) \
-|| defined(__AVR_ATtiny25__) \
-|| defined(__AVR_ATtiny45__) \
-|| defined(__AVR_ATtiny85__) \
-|| defined(__AVR_ATtiny261__) \
-|| defined(__AVR_ATtiny261A__) \
-|| defined(__AVR_ATtiny461__) \
-|| defined(__AVR_ATtiny461A__) \
-|| defined(__AVR_ATtiny861__) \
-|| defined(__AVR_ATtiny861A__) \
-|| defined(__AVR_ATtiny43U__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-/* Universal Serial Interface */
-#define power_usi_enable()      (PRR &= (uint8_t)~(1 << PRUSI))
-#define power_usi_disable()     (PRR |= (uint8_t)(1 << PRUSI))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRUSI)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRUSI)))
-
-
-#elif defined(__AVR_ATmega1284P__)
-
-
-#define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_timer3_enable()   (PRR1 &= (uint8_t)~(1 << PRTIM3))
-#define power_timer3_disable()  (PRR1 |= (uint8_t)(1 << PRTIM3))
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_usart1_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR0 |= (uint8_t)(1 << PRUSART1))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)|(1<<PRUSART1)); \
-    PRR1 &= (uint8_t)~(1<<PRTIM3); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRUSART0)|(1<<PRUSART1)); \
-    PRR1 |= (uint8_t)(1<<PRTIM3); \
-}while(0)
-
-
-#elif defined(__AVR_ATmega32HVB__)
-
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-/* Voltage ADC */
-#define power_vadc_enable()     (PRR0 &= (uint8_t)~(1 << PRVADC))
-#define power_vadc_disable()    (PRR0 |= (uint8_t)(1 << PRVADC))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_vrm_enable()      (PRR0 &= (uint8_t)~(1 << PRVRM))
-#define power_vrm_disable()     (PRR0 |= (uint8_t)(1 << PRVRM))
-
-#define power_all_enable()      (PRR0 &= (uint8_t)~((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)|(1<<PRSPI)|(1<<PRVRM)))
-#define power_all_disable()     (PRR0 |= (uint8_t)((1<<PRTWI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRVADC)|(1<<PRSPI)|(1<<PRVRM)))
-
-
-#elif defined(__AVR_ATmega16M1__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32M1__) \
-|| defined(__AVR_ATmega64C1__) \
-|| defined(__AVR_ATmega64M1__)
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_lin_enable()      (PRR &= (uint8_t)~(1 << PRLIN))
-#define power_lin_disable()     (PRR |= (uint8_t)(1 << PRLIN))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-#define power_psc_enable()      (PRR &= (uint8_t)~(1 << PRPSC))
-#define power_psc_disable()     (PRR |= (uint8_t)(1 << PRPSC))
-
-#define power_can_enable()      (PRR &= (uint8_t)~(1 << PRCAN))
-#define power_can_disable()     (PRR |= (uint8_t)(1 << PRCAN))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRLIN)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC)|(1<<PRCAN)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRLIN)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC)|(1<<PRCAN)))
-
-
-#elif defined(__AVR_ATtiny167__) \
-|| defined(__AVR_ATtiny87__)
-
-
-#define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_usi_enable()      (PRR &= (uint8_t)~(1 << PRUSI))
-#define power_usi_disable()     (PRR |= (uint8_t)(1 << PRUSI))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
-
-#define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
-
-#define power_lin_enable()      (PRR &= (uint8_t)~(1 << PRLIN))
-#define power_lin_disable()     (PRR |= (uint8_t)(1 << PRLIN))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN)))
-
-
-#elif defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_ATmega8U2__) \
-|| defined(__AVR_ATmega16U2__) \
-|| defined(__AVR_ATmega32U2__)
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_usb_enable()      (PRR1 &= (uint8_t)~(1 << PRUSB))
-#define power_usb_disable()     (PRR1 |= (uint8_t)(1 << PRUSB))
-
-#define power_usart1_enable()   (PRR1 &= (uint8_t)~(1 << PRUSART1))
-#define power_usart1_disable()  (PRR1 |= (uint8_t)(1 << PRUSART1))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)); \
-    PRR1 &= (uint8_t)~((1<<PRUSB)|(1<<PRUSART1)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)); \
-    PRR1 |= (uint8_t)((1<<PRUSB)|(1<<PRUSART1)); \
-}while(0)
-
-
-#elif defined(__AVR_AT90SCR100__)
-
-#define power_usart0_enable()   (PRR0 &= (uint8_t)~(1 << PRUSART0))
-#define power_usart0_disable()  (PRR0 |= (uint8_t)(1 << PRUSART0))
-
-#define power_spi_enable()      (PRR0 &= (uint8_t)~(1 << PRSPI))
-#define power_spi_disable()     (PRR0 |= (uint8_t)(1 << PRSPI))
-
-#define power_timer1_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer1_disable()  (PRR0 |= (uint8_t)(1 << PRTIM1))
-
-#define power_timer0_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR0 |= (uint8_t)(1 << PRTIM0))
-
-#define power_timer2_enable()   (PRR0 &= (uint8_t)~(1 << PRTIM2))
-#define power_timer2_disable()  (PRR0 |= (uint8_t)(1 << PRTIM2))
-
-#define power_twi_enable()      (PRR0 &= (uint8_t)~(1 << PRTWI))
-#define power_twi_disable()     (PRR0 |= (uint8_t)(1 << PRTWI))
-
-#define power_usbh_enable()     (PRR1 &= (uint8_t)~(1 << PRUSBH))
-#define power_usbh_disable()    (PRR1 |= (uint8_t)(1 << PRUSBH))
-
-#define power_usb_enable()      (PRR1 &= (uint8_t)~(1 << PRUSB))
-#define power_usb_disable()     (PRR1 |= (uint8_t)(1 << PRUSB))
-
-#define power_hsspi_enable()    (PRR1 &= (uint8_t)~(1 << PRHSSPI))
-#define power_hsspi_disable()   (PRR1 |= (uint8_t)(1 << PRHSSPI))
-
-#define power_sci_enable()      (PRR1 &= (uint8_t)~(1 << PRSCI))
-#define power_sci_disable()     (PRR1 |= (uint8_t)(1 << PRSCI))
-
-#define power_aes_enable()      (PRR1 &= (uint8_t)~(1 << PRAES))
-#define power_aes_disable()     (PRR1 |= (uint8_t)(1 << PRAES))
-
-#define power_kb_enable()       (PRR1 &= (uint8_t)~(1 << PRKB))
-#define power_kb_disable()      (PRR1 |= (uint8_t)(1 << PRKB))
-
-#define power_all_enable() \
-do{ \
-    PRR0 &= (uint8_t)~((1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)); \
-    PRR1 &= (uint8_t)~((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB)); \
-}while(0)
-
-#define power_all_disable() \
-do{ \
-    PRR0 |= (uint8_t)((1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)); \
-    PRR1 |= (uint8_t)((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB)); \
-}while(0)
-
-
-#elif defined(__AVR_ATtiny13A__)
-
-#define power_adc_enable()   (PRR &= (uint8_t)~(1 << PRADC))
-#define power_adc_disable()  (PRR |= (uint8_t)(1 << PRADC))
-
-#define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
-#define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
-
-#define power_all_enable()      (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)))
-#define power_all_disable()     (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)))
-
-#endif
-
-
-#if defined(__AVR_AT90CAN32__) \
-|| defined(__AVR_AT90CAN64__) \
-|| defined(__AVR_AT90CAN128__) \
-|| defined(__AVR_AT90PWM1__) \
-|| defined(__AVR_AT90PWM2__) \
-|| defined(__AVR_AT90PWM2B__) \
-|| defined(__AVR_AT90PWM3__) \
-|| defined(__AVR_AT90PWM3B__) \
-|| defined(__AVR_AT90PWM216__) \
-|| defined(__AVR_AT90PWM316__) \
-|| defined(__AVR_AT90SCR100__) \
-|| defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega128RFA1__) \
-|| defined(__AVR_ATmega1284P__) \
-|| defined(__AVR_ATmega162__) \
-|| defined(__AVR_ATmega164A__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega165__) \
-|| defined(__AVR_ATmega165A__) \
-|| defined(__AVR_ATmega165P__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega169__) \
-|| defined(__AVR_ATmega169A__) \
-|| defined(__AVR_ATmega169P__) \
-|| defined(__AVR_ATmega169PA__) \
-|| defined(__AVR_ATmega16U4__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) \
-|| defined(__AVR_ATmega324A__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega325__) \
-|| defined(__AVR_ATmega3250__) \
-|| defined(__AVR_ATmega328P__) \
-|| defined(__AVR_ATmega329__) \
-|| defined(__AVR_ATmega329P__) \
-|| defined(__AVR_ATmega329PA__) \
-|| defined(__AVR_ATmega3290__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32HVB__) \
-|| defined(__AVR_ATmega32M1__) \
-|| defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega32U6__) \
-|| defined(__AVR_ATmega48__) \
-|| defined(__AVR_ATmega48P__) \
-|| defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega649P__) \
-|| defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644A__) \
-|| defined(__AVR_ATmega644P__) \
-|| defined(__AVR_ATmega644PA__) \
-|| defined(__AVR_ATmega645__) \
-|| defined(__AVR_ATmega645A__) \
-|| defined(__AVR_ATmega645P__) \
-|| defined(__AVR_ATmega6450__) \
-|| defined(__AVR_ATmega6450A__) \
-|| defined(__AVR_ATmega6450P__) \
-|| defined(__AVR_ATmega649__) \
-|| defined(__AVR_ATmega649A__) \
-|| defined(__AVR_ATmega6490__) \
-|| defined(__AVR_ATmega6490A__) \
-|| defined(__AVR_ATmega6490P__) \
-|| defined(__AVR_ATmega88__) \
-|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATtiny48__) \
-|| defined(__AVR_ATtiny167__) \
-|| defined(__DOXYGEN__)
-
-
-/** \addtogroup avr_power
-
-Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
-allows you to decrease the system clock frequency and the power consumption
-when the need for processing power is low. Below are two macros and an
-enumerated type that can be used to interface to the Clock Prescale Register.
-
-\note Not all AVR devices have a Clock Prescale Register. On those devices
-without a Clock Prescale Register, these macros are not available.
-*/
-
-
-/** \addtogroup avr_power
-\code
-typedef enum
-{
-    clock_div_1 = 0,
-    clock_div_2 = 1,
-    clock_div_4 = 2,
-    clock_div_8 = 3,
-    clock_div_16 = 4,
-    clock_div_32 = 5,
-    clock_div_64 = 6,
-    clock_div_128 = 7,
-    clock_div_256 = 8,
-    clock_div_1_rc = 15, // ATmega128RFA1 only
-} clock_div_t;
-\endcode
-Clock prescaler setting enumerations.
-
-*/
-typedef enum
-{
-    clock_div_1 = 0,
-    clock_div_2 = 1,
-    clock_div_4 = 2,
-    clock_div_8 = 3,
-    clock_div_16 = 4,
-    clock_div_32 = 5,
-    clock_div_64 = 6,
-    clock_div_128 = 7,
-    clock_div_256 = 8,
-#if defined(__AVR_ATmega128RFA1__)
-    clock_div_1_rc = 15,
-#endif
-} clock_div_t;
-
-
-static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
-
-/** \addtogroup avr_power
-\code clock_prescale_set(x) \endcode
-
-Set the clock prescaler register select bits, selecting a system clock
-division setting. This function is inlined, even if compiler
-optimizations are disabled.
-
-The type of x is clock_div_t.
-*/
-void clock_prescale_set(clock_div_t __x)
-{
-    uint8_t __tmp = _BV(CLKPCE);
-    __asm__ __volatile__ (
-        "in __tmp_reg__,__SREG__" "\n\t"
-        "cli" "\n\t"
-        "sts %1, %0" "\n\t"
-        "sts %1, %2" "\n\t"
-        "out __SREG__, __tmp_reg__"
-        : /* no outputs */
-        : "d" (__tmp),
-          "M" (_SFR_MEM_ADDR(CLKPR)),
-          "d" (__x)
-        : "r0");
-}
-
-/** \addtogroup avr_power
-\code clock_prescale_get() \endcode
-Gets and returns the clock prescaler register setting. The return type is clock_div_t.
-
-*/
-#define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
-
-
-#elif defined(__AVR_ATtiny24__) \
-|| defined(__AVR_ATtiny24A__) \
-|| defined(__AVR_ATtiny44__) \
-|| defined(__AVR_ATtiny44A__) \
-|| defined(__AVR_ATtiny84__) \
-|| defined(__AVR_ATtiny25__) \
-|| defined(__AVR_ATtiny45__) \
-|| defined(__AVR_ATtiny85__) \
-|| defined(__AVR_ATtiny261A__) \
-|| defined(__AVR_ATtiny261__) \
-|| defined(__AVR_ATtiny461__) \
-|| defined(__AVR_ATtiny461A__) \
-|| defined(__AVR_ATtiny861__) \
-|| defined(__AVR_ATtiny861A__) \
-|| defined(__AVR_ATtiny2313__) \
-|| defined(__AVR_ATtiny2313A__) \
-|| defined(__AVR_ATtiny4313__) \
-|| defined(__AVR_ATtiny13__) \
-|| defined(__AVR_ATtiny13A__) \
-|| defined(__AVR_ATtiny43U__) \
-
-typedef enum
-{
-    clock_div_1 = 0,
-    clock_div_2 = 1,
-    clock_div_4 = 2,
-    clock_div_8 = 3,
-    clock_div_16 = 4,
-    clock_div_32 = 5,
-    clock_div_64 = 6,
-    clock_div_128 = 7,
-    clock_div_256 = 8
-} clock_div_t;
-
-
-void clock_prescale_set(clock_div_t __x)
-{
-    uint8_t __tmp = _BV(CLKPCE);
-    __asm__ __volatile__ (
-        "in __tmp_reg__,__SREG__" "\n\t"
-        "cli" "\n\t"
-        "out %1, %0" "\n\t"
-        "out %1, %2" "\n\t"
-        "out __SREG__, __tmp_reg__"
-        : /* no outputs */
-        : "d" (__tmp),
-          "I" (_SFR_IO_ADDR(CLKPR)),
-          "d" (__x)
-        : "r0");
-}
-
-
-#define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
-
-
-#endif
-
-/**@}*/
-#endif /* _AVR_POWER_H_ */
diff --git a/cpukit/score/cpu/avr/avr/sfr_defs.h b/cpukit/score/cpu/avr/avr/sfr_defs.h
deleted file mode 100644
index 2b8392689a..0000000000
--- a/cpukit/score/cpu/avr/avr/sfr_defs.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/**
- * @file
- *
- * @brief Macros for Accessing AVR Special Function Registers
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz <marekm@amelek.gda.pl>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.  */
-
-/* avr/sfr_defs.h - macros for accessing AVR special function registers */
-
-
-#ifndef _AVR_SFR_DEFS_H_
-#define _AVR_SFR_DEFS_H_ 1
-
-/**
- * @defgroup avr_sfr_notes Additional notes from <avr/sfr_defs.h>
- *
- * @ingroup avr_sfr
- *
- * The @c <avr/sfr_defs.h> file is included by all of the @c <avr/ioXXXX.h>
- * files, which use macros defined here to make the special function register
- * definitions look like C variables or simple constants, depending on the
- * <tt>_SFR_ASM_COMPAT</tt> define.  Some examples from @c <avr/iocanxx.h> to
- * show how to define such macros:
- *
- * @code
- * #define PORTA   _SFR_IO8(0x02)
- * #define EEAR    _SFR_IO16(0x21)
- * #define UDR0    _SFR_MEM8(0xC6)
- * #define TCNT3   _SFR_MEM16(0x94)
- * #define CANIDT  _SFR_MEM32(0xF0)
- * @endcode
- *
- * If @c _SFR_ASM_COMPAT is not defined, C programs can use names like
- * <tt>PORTA</tt> directly in C expressions (also on the left side of
- * assignment operators) and GCC will do the right thing (use short I/O
- * instructions if possible).  The @c __SFR_OFFSET definition is not used in
- * any way in this case.
- *
- * Define @c _SFR_ASM_COMPAT as 1 to make these names work as simple constants
- * (addresses of the I/O registers).  This is necessary when included in
- * preprocessed assembler (*.S) source files, so it is done automatically if
- * @c __ASSEMBLER__ is defined.  By default, all addresses are defined as if
- * they were memory addresses (used in @c lds/sts instructions).  To use these
- * addresses in @c in/out instructions, you must subtract 0x20 from them.
- *
- * For more backwards compatibility, insert the following at the start of your
- * old assembler source file:
- *
- * @code
- * #define __SFR_OFFSET 0
- * @endcode
- *
- * This automatically subtracts 0x20 from I/O space addresses, but it's a
- * hack, so it is recommended to change your source: wrap such addresses in
- * macros defined here, as shown below.  After this is done, the
- * <tt>__SFR_OFFSET</tt> definition is no longer necessary and can be removed.
-
- * Real example - this code could be used in a boot loader that is portable
- * between devices with @c SPMCR at different addresses.
- *
- * @verbatim
- * <avr/iom163.h>: #define SPMCR _SFR_IO8(0x37)
- * <avr/iom128.h>: #define SPMCR _SFR_MEM8(0x68)
- * @endverbatim
- *
- * @code
- * #if _SFR_IO_REG_P(SPMCR)
- * 	out	_SFR_IO_ADDR(SPMCR), r24
- * #else
- *	sts	_SFR_MEM_ADDR(SPMCR), r24
- * #endif
- * @endcode
- *
- * You can use the @c in/out/cbi/sbi/sbic/sbis instructions, without the
- * <tt>_SFR_IO_REG_P</tt> test, if you know that the register is in the I/O
- * space (as with @c SREG, for example).  If it isn't, the assembler will
- * complain (I/O address out of range 0...0x3f), so this should be fairly
- * safe.
- *
- * If you do not define @c __SFR_OFFSET (so it will be 0x20 by default), all
- * special register addresses are defined as memory addresses (so @c SREG is
- * 0x5f), and (if code size and speed are not important, and you don't like
- * the ugly \#if above) you can always use lds/sts to access them.  But, this
- * will not work if <tt>__SFR_OFFSET</tt> != 0x20, so use a different macro
- * (defined only if <tt>__SFR_OFFSET</tt> == 0x20) for safety:
- *
- * @code
- *	sts	_SFR_ADDR(SPMCR), r24
- * @endcode
- *
- * In C programs, all 3 combinations of @c _SFR_ASM_COMPAT and
- * <tt>__SFR_OFFSET</tt> are supported - the @c _SFR_ADDR(SPMCR) macro can be
- * used to get the address of the @c SPMCR register (0x57 or 0x68 depending on
- * device).
- */
-/**@{**/
-
-#ifdef __ASSEMBLER__
-#define _SFR_ASM_COMPAT 1
-#elif !defined(_SFR_ASM_COMPAT)
-#define _SFR_ASM_COMPAT 0
-#endif
-
-#ifndef __ASSEMBLER__
-/* These only work in C programs.  */
-#include <inttypes.h>
-
-#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr))
-#define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr))
-#define _MMIO_DWORD(mem_addr) (*(volatile uint32_t *)(mem_addr))
-#endif
-
-#if _SFR_ASM_COMPAT
-
-#ifndef __SFR_OFFSET
-/* Define as 0 before including this file for compatibility with old asm
-   sources that don't subtract __SFR_OFFSET from symbolic I/O addresses.  */
-#  if __AVR_ARCH__ >= 100
-#    define __SFR_OFFSET 0x00
-#  else
-#    define __SFR_OFFSET 0x20
-#  endif
-#endif
-
-#if (__SFR_OFFSET != 0) && (__SFR_OFFSET != 0x20)
-#error "__SFR_OFFSET must be 0 or 0x20"
-#endif
-
-#define _SFR_MEM8(mem_addr) (mem_addr)
-#define _SFR_MEM16(mem_addr) (mem_addr)
-#define _SFR_MEM32(mem_addr) (mem_addr)
-#define _SFR_IO8(io_addr) ((io_addr) + __SFR_OFFSET)
-#define _SFR_IO16(io_addr) ((io_addr) + __SFR_OFFSET)
-
-#define _SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET)
-#define _SFR_MEM_ADDR(sfr) (sfr)
-#define _SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET)
-
-#if (__SFR_OFFSET == 0x20)
-/* No need to use ?: operator, so works in assembler too.  */
-#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr)
-#elif !defined(__ASSEMBLER__)
-#define _SFR_ADDR(sfr) (_SFR_IO_REG_P(sfr) ? (_SFR_IO_ADDR(sfr) + 0x20) : _SFR_MEM_ADDR(sfr))
-#endif
-
-#else  /* !_SFR_ASM_COMPAT */
-
-#ifndef __SFR_OFFSET
-#  if __AVR_ARCH__ >= 100
-#    define __SFR_OFFSET 0x00
-#  else
-#    define __SFR_OFFSET 0x20
-#  endif
-#endif
-
-#define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr)
-#define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr)
-#define _SFR_MEM32(mem_addr) _MMIO_DWORD(mem_addr)
-#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + __SFR_OFFSET)
-#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + __SFR_OFFSET)
-
-#define _SFR_MEM_ADDR(sfr) ((uint16_t) &(sfr))
-#define _SFR_IO_ADDR(sfr) (_SFR_MEM_ADDR(sfr) - __SFR_OFFSET)
-#define _SFR_IO_REG_P(sfr) (_SFR_MEM_ADDR(sfr) < 0x40 + __SFR_OFFSET)
-
-#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr)
-
-#endif /* !_SFR_ASM_COMPAT */
-
-#define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr))
-#define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr))
-#define _SFR_DWORD(sfr) _MMIO_DWORD(_SFR_ADDR(sfr))
-
-/**
- * @name Bit Manipulation
- */
-/**@{**/
-
-/**
- * @code #include <avr/io.h> @endcode
- *
- * Converts a bit number into a byte value.
- *
- * @note The bit shift is performed by the compiler which then inserts the
- *       result into the code. Thus, there is no run-time overhead when using
- *       _BV().
- */   
-#define _BV(bit) (1 << (bit))
-
-/** @} */
-
-#ifndef _VECTOR
-#define _VECTOR(N) __vector_ ## N
-#endif
-
-#ifndef __ASSEMBLER__
-
-
-/**
- * @name IO Register Bit Manipulation
- */
-/**@{**/
-
-/**
- * @code #include <avr/io.h> @endcode
- *
- * Test whether bit @c bit in IO register @c sfr is set.
- * This will return a 0 if the bit is clear, and non-zero
- * if the bit is set.
- */
-#define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit))
-
-/**
- * @code #include <avr/io.h> @endcode
- *
- * Test whether bit @c bit in IO register @c sfr is clear.
- * This will return non-zero if the bit is clear, and a 0
- * if the bit is set.
- */
-
-#define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit)))
-
-/**
- * @code #include <avr/io.h> @endcode
- *
- * Wait until bit @c bit in IO register @c sfr is set.
- */
-#define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit))
-
-/**
- * @code #include <avr/io.h> @endcode
- *
- * Wait until bit @c bit in IO register @c sfr is clear.
- */
-#define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit))
-
-/** @} */
-
-/** @} */
-
-#endif /* !__ASSEMBLER__ */
-
-#endif  /* _SFR_DEFS_H_ */
diff --git a/cpukit/score/cpu/avr/avr/signal.h b/cpukit/score/cpu/avr/avr/signal.h
deleted file mode 100644
index 898df4acb8..0000000000
--- a/cpukit/score/cpu/avr/avr/signal.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * @file
- *
- * @brief Use <avr/interrupt.h>
- */
-
-/*
- *  Copyright (c) 2002, 2005, 2006 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_SIGNAL_H_
-#define _AVR_SIGNAL_H_
-
-/**
- *  @defgroup Avr_signal Signal
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#warning "This header file is obsolete.  Use <avr/interrupt.h>."
-#include <avr/interrupt.h>
-
-/**@}*/
-#endif /* _AVR_SIGNAL_H_ */
diff --git a/cpukit/score/cpu/avr/avr/signature.h b/cpukit/score/cpu/avr/avr/signature.h
deleted file mode 100644
index 06aedce580..0000000000
--- a/cpukit/score/cpu/avr/avr/signature.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * @file
- *
- * @brief Signature Support
- */
-
-/* Copyright (c) 2009, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/signature.h - Signature API */
-
-#ifndef _AVR_SIGNATURE_H_
-#define _AVR_SIGNATURE_H_ 1
-
-/**
- * @defgroup avr_signature Signature Support
- *
- * @par Introduction
- *
- * The <avr/signature.h> header file allows the user to automatically
- * and easily include the device's signature data in a special section of
- * the final linked ELF file.
- *
- * This value can then be used by programming software to compare the 
- * on-device signature with the signature recorded in the ELF file
- * to look for a match before programming the device.
- * 
- * @par API Usage Example
- *
- * Usage is very simple; just include the header file:
- *
- * @code{.c}
- * #include <avr/signature.h>
- * @endcode
- *
- * This will declare a constant unsigned char array and it is initialized with
- * the three signature bytes, MSB first, that are defined in the device I/O
- * header file. This array is then placed in the .signature section in the
- * resulting linked ELF file.
- * 
- * The three signature bytes that are used to initialize the array are 
- * these defined macros in the device I/O header file, from MSB to LSB:
- * SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
- * 
- * This header file should only be included once in an application.
- */
-
-#ifndef __ASSEMBLER__
-
-#include <avr/io.h>
-
-#if defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2)
-
-const unsigned char __signature[3] __attribute__((section (".signature"))) =
-        { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 };
-        
-/* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
-#endif
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* _AVR_SIGNATURE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/sleep.h b/cpukit/score/cpu/avr/avr/sleep.h
deleted file mode 100644
index 9a2556c85c..0000000000
--- a/cpukit/score/cpu/avr/avr/sleep.h
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
- * @file
- *
- * @brief Power Management and Sleep Modes
- * 
- */
-
-/* Copyright (c) 2002, 2004 Theodore A. Roth
-   Copyright (c) 2004, 2007, 2008 Eric B. Weddington
-   Copyright (c) 2005, 2006, 2007 Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE. */
-
-
-#ifndef _AVR_SLEEP_H_
-#define _AVR_SLEEP_H_ 1
-
-#include <avr/io.h>
-#include <stdint.h>
-
-/**
- * @defgroup avr_sleep Power Management and Sleep Modes
- * 
- * Use of the @c SLEEP instruction can allow an application to reduce its
- * power comsumption considerably. AVR devices can be put into different
- * sleep modes. Refer to the datasheet for the details relating to the device
- * you are using.
- * 
- * There are several macros provided in this header file to actually
- * put the device into sleep mode.  The simplest way is to optionally
- * set the desired sleep mode using @c set_sleep_mode() (it usually
- * defaults to idle mode where the CPU is put on sleep but all
- * peripheral clocks are still running), and then call
- * @c sleep_mode(). This macro automatically sets the sleep enable bit, goes 
- * to sleep, and clears the sleep enable bit.
- *   
- * Example:
- * @code{.c}
- * #include <avr/sleep.h>
- * 
- * ...
- *   set_sleep_mode(<mode>);
- *   sleep_mode();
- * @endcode
- *   
- * Note that unless your purpose is to completely lock the CPU (until a 
- * hardware reset), interrupts need to be enabled before going to sleep.
- *
- * As the @c sleep_mode() macro might cause race conditions in some
- * situations, the individual steps of manipulating the sleep enable
- * (SE) bit, and actually issuing the @c SLEEP instruction, are provided
- * in the macros @c sleep_enable(), @c sleep_disable(), and
- * @c sleep_cpu().  This also allows for test-and-sleep scenarios that
- * take care of not missing the interrupt that will awake the device
- * from sleep.
- *
- * Example:
- * @code{.c}
- * #include <avr/interrupt.h>
- * #include <avr/sleep.h>*
- *
- * ...
- *   set_sleep_mode(<mode>);
- *   cli();
- *   if (some_condition)
- *   {
- *     sleep_enable();
- *     sei();
- *     sleep_cpu();
- *     sleep_disable();
- *   }
- *   sei();
- * @endcode
- * 
- * This sequence ensures an atomic test of @c some_condition with
- * interrupts being disabled.  If the condition is met, sleep mode
- * will be prepared, and the @c SLEEP instruction will be scheduled
- * immediately after an @c SEI instruction.  As the intruction right
- * after the @c SEI is guaranteed to be executed before an interrupt
- * could trigger, it is sure the device will really be put to sleep.
- * 
- * Some devices have the ability to disable the Brown Out Detector (BOD) 
- * before going to sleep. This will also reduce power while sleeping. If the
- * specific AVR device has this ability then an additional macro is defined:
- * @c sleep_bod_disable(). This macro generates inlined assembly code
- * that will correctly implement the timed sequence for disabling the BOD
- * before sleeping. However, there is a limited number of cycles after the
- * BOD has been disabled that the device can be put into sleep mode, otherwise
- * the BOD will not truly be disabled. Recommended practice is to disable
- * the BOD (@c sleep_bod_disable()), set the interrupts (@c sei()), and then
- * put the device to sleep (@c sleep_cpu()), like so:
- * 
- * @code{.c}
- * #include <avr/interrupt.h>
- * #include <avr/sleep.h>*
- *
- * ...
- *   set_sleep_mode(<mode>);
- *   cli();
- *   if (some_condition)
- *   {
- *     sleep_enable();
- *     sleep_bod_disable();
- *     sei();
- *     sleep_cpu();
- *     sleep_disable();
- *  }
- *   sei();
- * @endcode
- * 
- */
-/**@{**/
-
-
-/* 
- * Define an internal sleep control register and 
- * an internal sleep enable bit mask. 
- */
-#if defined(SLEEP_CTRL)
-
-    /* XMEGA devices */
-    #define _SLEEP_CONTROL_REG  SLEEP_CTRL
-    #define _SLEEP_ENABLE_MASK  SLEEP_SEN_bm
-
-#elif defined(SMCR)
-
-    #define _SLEEP_CONTROL_REG  SMCR
-    #define _SLEEP_ENABLE_MASK  _BV(SE)
-
-#elif defined(__AVR_AT94K__)
-
-    #define _SLEEP_CONTROL_REG  MCUR
-    #define _SLEEP_ENABLE_MASK  _BV(SE)
-
-#else
-
-    #define _SLEEP_CONTROL_REG  MCUCR
-    #define _SLEEP_ENABLE_MASK  _BV(SE)
-
-#endif
-
-
-/* Define set_sleep_mode() and sleep mode values per device. */
-#if defined(__AVR_ATmega161__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_PWR_DOWN     1
-    #define SLEEP_MODE_PWR_SAVE     2
-
-    #define set_sleep_mode(mode) \
-    do { \
-        MCUCR = ((MCUCR & ~_BV(SM1)) | \
-        ((mode) == SLEEP_MODE_PWR_DOWN || \
-        (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
-        EMCUCR = ((EMCUCR & ~_BV(SM0)) | \
-        ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
-    } while(0)
-
-
-#elif defined(__AVR_ATmega162__) \
-|| defined(__AVR_ATmega8515__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_PWR_DOWN     1
-    #define SLEEP_MODE_PWR_SAVE     2
-    #define SLEEP_MODE_ADC          3
-    #define SLEEP_MODE_STANDBY      4
-    #define SLEEP_MODE_EXT_STANDBY  5
-
-    #define set_sleep_mode(mode) \
-    do { \
-        MCUCR = ((MCUCR & ~_BV(SM1)) | \
-        ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
-        MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || \
-        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
-        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || \
-        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
-    } while(0)
-
-#elif defined(__AVR_AT90S2313__) \
-|| defined(__AVR_AT90S2323__) \
-|| defined(__AVR_AT90S2333__) \
-|| defined(__AVR_AT90S2343__) \
-|| defined(__AVR_AT43USB320__) \
-|| defined(__AVR_AT43USB355__) \
-|| defined(__AVR_AT90S4414__) \
-|| defined(__AVR_AT90S4433__) \
-|| defined(__AVR_AT90S8515__) \
-|| defined(__AVR_ATtiny22__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM)
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~__BV(SM)) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_ATtiny167__) \
-|| defined(__AVR_ATtiny87__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_ADC          _BV(SM0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG &  \
-        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_AT90S4434__) \
-|| defined(__AVR_AT76C711__) \
-|| defined(__AVR_AT90S8535__) \
-|| defined(__AVR_ATmega103__) \
-|| defined(__AVR_ATmega161__) \
-|| defined(__AVR_ATmega163__) \
-|| defined(__AVR_ATtiny13__) \
-|| defined(__AVR_ATtiny13A__) \
-|| defined(__AVR_ATtiny15__) \
-|| defined(__AVR_ATtiny24__) \
-|| defined(__AVR_ATtiny24A__) \
-|| defined(__AVR_ATtiny44__) \
-|| defined(__AVR_ATtiny44A__) \
-|| defined(__AVR_ATtiny84__) \
-|| defined(__AVR_ATtiny25__) \
-|| defined(__AVR_ATtiny45__) \
-|| defined(__AVR_ATtiny48__) \
-|| defined(__AVR_ATtiny85__) \
-|| defined(__AVR_ATtiny261__) \
-|| defined(__AVR_ATtiny261A__) \
-|| defined(__AVR_ATtiny461__) \
-|| defined(__AVR_ATtiny461A__) \
-|| defined(__AVR_ATtiny861__) \
-|| defined(__AVR_ATtiny861A__) \
-|| defined(__AVR_ATtiny88__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_ADC          _BV(SM0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_ATtiny2313__) \
-|| defined(__AVR_ATtiny2313A__) \
-|| defined(__AVR_ATtiny4313__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_PWR_DOWN     (_BV(SM0) | _BV(SM1))
-    #define SLEEP_MODE_STANDBY      _BV(SM1)
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_AT94K__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_ATtiny26__) \
-|| defined(__AVR_ATtiny43U__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_ADC          _BV(SM0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_STANDBY      (_BV(SM0) | _BV(SM1))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_AT90PWM216__) \
-|| defined(__AVR_AT90PWM316__) \
-|| defined(__AVR_AT90PWM81__)
-
-    #define SLEEP_MODE_IDLE         0
-    #define SLEEP_MODE_ADC          _BV(SM0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_AT90CAN128__) \
-|| defined(__AVR_AT90CAN32__) \
-|| defined(__AVR_AT90CAN64__) \
-|| defined(__AVR_AT90PWM1__) \
-|| defined(__AVR_AT90PWM2__) \
-|| defined(__AVR_AT90PWM2B__) \
-|| defined(__AVR_AT90PWM3__) \
-|| defined(__AVR_AT90PWM3B__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__) \
-|| defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_ATmega128__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega1284P__) \
-|| defined(__AVR_ATmega128RFA1__) \
-|| defined(__AVR_ATmega16__) \
-|| defined(__AVR_ATmega16A__) \
-|| defined(__AVR_ATmega162__) \
-|| defined(__AVR_ATmega164A__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega165__) \
-|| defined(__AVR_ATmega165A__) \
-|| defined(__AVR_ATmega165P__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega168A__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega169__) \
-|| defined(__AVR_ATmega169A__) \
-|| defined(__AVR_ATmega169P__) \
-|| defined(__AVR_ATmega169PA__) \
-|| defined(__AVR_ATmega16HVA__) \
-|| defined(__AVR_ATmega16HVA2__) \
-|| defined(__AVR_ATmega16HVB__) \
-|| defined(__AVR_ATmega16M1__) \
-|| defined(__AVR_ATmega16U2__) \
-|| defined(__AVR_ATmega16U4__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) \
-|| defined(__AVR_ATmega32__) \
-|| defined(__AVR_ATmega323__) \
-|| defined(__AVR_ATmega324A__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega324PA__) \
-|| defined(__AVR_ATmega325__) \
-|| defined(__AVR_ATmega3250__) \
-|| defined(__AVR_ATmega328__) \
-|| defined(__AVR_ATmega328P__) \
-|| defined(__AVR_ATmega329__) \
-|| defined(__AVR_ATmega329P__) \
-|| defined(__AVR_ATmega329PA__) \
-|| defined(__AVR_ATmega3290__) \
-|| defined(__AVR_ATmega3290P__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32HVB__) \
-|| defined(__AVR_ATmega32M1__) \
-|| defined(__AVR_ATmega32U2__) \
-|| defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega32U6__) \
-|| defined(__AVR_ATmega406__) \
-|| defined(__AVR_ATmega48__) \
-|| defined(__AVR_ATmega48A__) \
-|| defined(__AVR_ATmega48P__) \
-|| defined(__AVR_ATmega64__) \
-|| defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644A__) \
-|| defined(__AVR_ATmega644P__) \
-|| defined(__AVR_ATmega644PA__) \
-|| defined(__AVR_ATmega645__) \
-|| defined(__AVR_ATmega645A__) \
-|| defined(__AVR_ATmega645P__) \
-|| defined(__AVR_ATmega6450__) \
-|| defined(__AVR_ATmega6450A__) \
-|| defined(__AVR_ATmega6450P__) \
-|| defined(__AVR_ATmega649__) \
-|| defined(__AVR_ATmega649A__) \
-|| defined(__AVR_ATmega6490__) \
-|| defined(__AVR_ATmega6490A__) \
-|| defined(__AVR_ATmega6490P__) \
-|| defined(__AVR_ATmega649P__) \
-|| defined(__AVR_ATmega64C1__) \
-|| defined(__AVR_ATmega64HVE__) \
-|| defined(__AVR_ATmega64M1__) \
-|| defined(__AVR_ATmega8__) \
-|| defined(__AVR_ATmega8515__) \
-|| defined(__AVR_ATmega8535__) \
-|| defined(__AVR_ATmega88__) \
-|| defined(__AVR_ATmega88A__) \
-|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATmega88PA__) \
-|| defined(__AVR_ATmega8HVA__) \
-|| defined(__AVR_ATmega8U2__)
-
-
-    #define SLEEP_MODE_IDLE         (0)
-    #define SLEEP_MODE_ADC          _BV(SM0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
-    #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
-
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_ATxmega16A4__) \
-|| defined(__AVR_ATxmega16D4__) \
-|| defined(__AVR_ATxmega32A4__) \
-|| defined(__AVR_ATxmega32D4__) \
-|| defined(__AVR_ATxmega64A1__) \
-|| defined(__AVR_ATxmega64A3__) \
-|| defined(__AVR_ATxmega64D3__) \
-|| defined(__AVR_ATxmega128A1__) \
-|| defined(__AVR_ATxmega128A3__) \
-|| defined(__AVR_ATxmega128D3__) \
-|| defined(__AVR_ATxmega192A3__) \
-|| defined(__AVR_ATxmega192D3__) \
-|| defined(__AVR_ATxmega256A3__) \
-|| defined(__AVR_ATxmega256D3__) \
-|| defined(__AVR_ATxmega256A3B__)
-
-    #define SLEEP_MODE_IDLE         (0)
-    #define SLEEP_MODE_PWR_DOWN     (SLEEP_SMODE1_bm)
-    #define SLEEP_MODE_PWR_SAVE     (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
-    #define SLEEP_MODE_STANDBY      (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
-    #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | \
-                                     SLEEP_SMODE0_bm)
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_AT90SCR100__)
-
-    #define SLEEP_MODE_IDLE         (0)
-    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
-    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
-    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
-    #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
-    } while(0)
-
-#elif defined(__AVR_ATA6289__)
-
-    #define SLEEP_MODE_IDLE                     (0)
-    #define SLEEP_MODE_SENSOR_NOISE_REDUCTION   (_BV(SM0))
-    #define SLEEP_MODE_PWR_DOWN                 (_BV(SM1))
-
-    #define set_sleep_mode(mode) \
-    do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
-        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
-    } while(0)
-
-#else
-
-    #error "No SLEEP mode defined for this device."
-
-#endif
-
-
-
-/**
- * Put the device in sleep mode. How the device is brought out of sleep mode
- * depends on the specific mode selected with the set_sleep_mode() function.
- * See the data sheet for your device for more details. 
- */
-
-
-#if defined(__DOXYGEN__)
-
-/**
- * Set the SE (sleep enable) bit.
-*/
-extern void sleep_enable (void);
-
-#else
-
-#define sleep_enable()             \
-do {                               \
-  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK;   \
-} while(0)
-
-#endif
-
-
-#if defined(__DOXYGEN__)
-
-/**
- * Clear the SE (sleep enable) bit.
- */
-extern void sleep_disable (void);
-
-#else
-
-#define sleep_disable()            \
-do {                               \
-  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK);  \
-} while(0)
-
-#endif
-
-
-/**
- * Put the device into sleep mode.  The SE bit must be set
- * beforehand, and it is recommended to clear it afterwards.
- */
-#if defined(__DOXYGEN__)
-
-extern void sleep_cpu (void);
-
-#else
-
-#define sleep_cpu()                              \
-do {                                             \
-  __asm__ __volatile__ ( "sleep" "\n\t" :: );    \
-} while(0)
-
-#endif
-
-
-#if defined(__DOXYGEN__)
-
-extern void sleep_mode (void);
-
-#else
-
-#define sleep_mode() \
-do {                 \
-    sleep_enable();  \
-    sleep_cpu();     \
-    sleep_disable(); \
-} while (0)
-
-#endif
-
-
-#if defined(__DOXYGEN__)
-
-extern void sleep_bod_disable (void);
-
-#else
-
-#if defined(BODS) && defined(BODSE)
-
-#define sleep_bod_disable() \
-do { \
-  uint8_t tempreg; \
-  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
-                       "ori %[tempreg], %[bods_bodse]" "\n\t" \
-                       "out %[mcucr], %[tempreg]" "\n\t" \
-                       "andi %[tempreg], %[not_bodse]" "\n\t" \
-                       "out %[mcucr], %[tempreg]" \
-                       : [tempreg] "=&d" (tempreg) \
-                       : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
-                         [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
-                         [not_bodse] "i" (~_BV(BODSE))); \
-} while (0)
-
-#endif
-
-#endif
-
-
-/** @} */
-
-#endif /* _AVR_SLEEP_H_ */
diff --git a/cpukit/score/cpu/avr/avr/version.h b/cpukit/score/cpu/avr/avr/version.h
deleted file mode 100644
index 7af5025921..0000000000
--- a/cpukit/score/cpu/avr/avr/version.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * @file avr/iom644PA.h
- *
- * @brief Current Version of avr-libc
- *
- * This header file defines macros that contain version numbers and
- * strings describing the current version of avr-libc.
- *
- * The version number itself basically consists of three pieces that
- * are separated by a dot: the major number, the minor number, and
- * the revision number.  For development versions (which use an odd
- * minor number), the string representation additionally gets the
- * date code (YYYYMMDD) appended.
- *
- * This file will also be included by \c <avr/io.h>.  That way,
- * portable tests can be implemented using \c <avr/io.h> that can be
- * used in code that wants to remain backwards-compatible to library
- * versions prior to the date when the library version API had been
- * added, as referenced but undefined C preprocessor macros
- * automatically evaluate to 0.
- */
-
-/*
- *  Copyright (c) 2005, Joerg Wunsch
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- *  @defgroup avr_version avr-libc Version Macros
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_VERSION_H_
-#define _AVR_VERSION_H_
-
-/** \ingroup avr_version
-    String literal representation of the current library version. */
-#define __AVR_LIBC_VERSION_STRING__ "1.6.8"
-
-/** \ingroup avr_version
-    Numerical representation of the current library version.
-
-    In the numerical representation, the major number is multiplied by
-    10000, the minor number by 100, and all three parts are then
-    added.  It is intented to provide a monotonically increasing
-    numerical value that can easily be used in numerical checks.
- */
-#define __AVR_LIBC_VERSION__        10608UL
-
-/** \ingroup avr_version
-    String literal representation of the release date. */
-#define __AVR_LIBC_DATE_STRING__    "20100211"
-
-/** \ingroup avr_version
-    Numerical representation of the release date. */
-#define __AVR_LIBC_DATE_            20100211UL
-
-/** \ingroup avr_version
-    Library major version number. */
-#define __AVR_LIBC_MAJOR__          1
-
-/** \ingroup avr_version
-    Library minor version number. */
-#define __AVR_LIBC_MINOR__          6
-
-/** \ingroup avr_version
-    Library revision number. */
-#define __AVR_LIBC_REVISION__       8
-
-/**@}*/
-#endif /* _AVR_VERSION_H_ */
diff --git a/cpukit/score/cpu/avr/avr/wdt.h b/cpukit/score/cpu/avr/avr/wdt.h
deleted file mode 100644
index 7337e273b3..0000000000
--- a/cpukit/score/cpu/avr/avr/wdt.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/**
- * @file
- * 
- * @brief Watchdog Timer Handling
- */
-/* Copyright (c) 2002, 2004 Marek Michalkiewicz
-   Copyright (c) 2005, 2006, 2007 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/*
-   avr/wdt.h - macros for AVR watchdog timer
- */
-
-#ifndef _AVR_WDT_H_
-#define _AVR_WDT_H_
-
-#include <avr/io.h>
-#include <stdint.h>
-
-/** 
- * @defgroup avr_watchdog Watchdog Timer Handling
- *
- * This header file declares the interface to some inline macros
- * handling the watchdog timer present in many AVR devices.  In order
- * to prevent the watchdog timer configuration from being
- * accidentally altered by a crashing application, a special timed
- * equence is required in order to change it.  The macros within
- * this header file handle the required sequence automatically
- * before changing any value.  Interrupts will be disabled during
- * the manipulation.
- * 
- * Note: Depending on the fuse configuration of the particular
- * device, further restrictions might apply, in particular it might
- * be disallowed to turn off the watchdog timer.
- * 
- * Note that for newer devices (ATmega88 and newer, effectively any
- * AVR that has the option to also generate interrupts), the watchdog
- * timer remains active even after a system reset (except a power-on
- * condition), using the fastest prescaler value (approximately 15
- * ms).  It is therefore required to turn off the watchdog early
- * during program startup, the datasheet recommends a sequence like
- * the following:
- * 
- * @code{.c}
- * #include <stdint.h>
- * #include <avr/wdt.h>
- *
- * uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
- *
- * void get_mcusr(void) \
- *   __attribute__((naked)) \
- *   __attribute__((section(".init3")));
- * void get_mcusr(void)
- * {
- *   mcusr_mirror = MCUSR;
- *   MCUSR = 0;
- *   wdt_disable();
- * }
- * @endcode
- *
- * Saving the value of MCUSR in @c mcusr_mirror is only needed if the
- * application later wants to examine the reset source, but in particular, 
- * clearing the watchdog reset flag before disabling the
- * watchdog is required, according to the datasheet.
- * @{
-*/
-
-/**
- * @brief Watchdog Timer Reset
- * 
- * Reset the watchdog timer.  When the watchdog timer is enabled,
- * a call to this instruction is required before the timer expires,
- * otherwise a watchdog-initiated device reset will occur. 
-*/
-
-#define wdt_reset() __asm__ __volatile__ ("wdr")
-
-
-#if defined(WDP3)
-# define _WD_PS3_MASK       _BV(WDP3)
-#else
-# define _WD_PS3_MASK       0x00
-#endif
-
-#if defined(WDTCSR)
-#  define _WD_CONTROL_REG     WDTCSR
-#else
-#  define _WD_CONTROL_REG     WDTCR
-#endif
-
-#if defined(WDTOE)
-#define _WD_CHANGE_BIT      WDTOE
-#else
-#define _WD_CHANGE_BIT      WDCE
-#endif
-
-
-/**
- * Enable the watchdog timer, configuring it for expiry after
- * @c timeout (which is a combination of the @c WDP0 through
- * @c WDP2 bits to write into the @c WDTCR register; For those devices 
- * that have a @c WDTCSR register, it uses the combination of the @c WDP0 
- * through @c WDP3 bits).
- *
- * See also the symbolic constants @c WDTO_15MS et al.
-*/
-
-
-#if defined(__AVR_ATxmega16A4__) \
-|| defined(__AVR_ATxmega16D4__) \
-|| defined(__AVR_ATxmega32A4__) \
-|| defined(__AVR_ATxmega32D4__) \
-|| defined(__AVR_ATxmega64A1__) \
-|| defined(__AVR_ATxmega64A3__) \
-|| defined(__AVR_ATxmega64D3__) \
-|| defined(__AVR_ATxmega128A1__) \
-|| defined(__AVR_ATxmega128A3__) \
-|| defined(__AVR_ATxmega128D3__) \
-|| defined(__AVR_ATxmega192A3__) \
-|| defined(__AVR_ATxmega192D3__) \
-|| defined(__AVR_ATxmega256A3__) \
-|| defined(__AVR_ATxmega256D3__) \
-|| defined(__AVR_ATxmega256A3B__)
-
-/*
-    wdt_enable(WDT_PER_8KCLK_gc);
-*/
-#define wdt_enable(value) \
-__asm__ __volatile__ ( \
-    "in __tmp_reg__, %0"  "\n\t" \
-    "out %1, %3"          "\n\t" \
-    "sts %2, %4"          "\n\t" \
-    "wdr"                 "\n\t" \
-    "out %0, __tmp_reg__" "\n\t" \
-    : \
-    : "M" (_SFR_MEM_ADDR(RAMPD)), \
-      "M" (_SFR_MEM_ADDR(CCP)), \
-      "M" (_SFR_MEM_ADDR(WDT_CTRL)), \
-      "r" ((uint8_t)0xD8), \
-      "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \
-    : "r0" \
-)
-
-
-#elif defined(__AVR_AT90CAN32__) \
-|| defined(__AVR_AT90CAN64__) \
-|| defined(__AVR_AT90CAN128__) \
-|| defined(__AVR_AT90PWM1__) \
-|| defined(__AVR_AT90PWM2__) \
-|| defined(__AVR_AT90PWM216__) \
-|| defined(__AVR_AT90PWM2B__) \
-|| defined(__AVR_AT90PWM3__) \
-|| defined(__AVR_AT90PWM316__) \
-|| defined(__AVR_AT90PWM3B__) \
-|| defined(__AVR_AT90PWM81__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_AT90USB82__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega1284P__) \
-|| defined(__AVR_ATmega128RFA1__) \
-|| defined(__AVR_ATmega164__) \
-|| defined(__AVR_ATmega164A__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega165__) \
-|| defined(__AVR_ATmega165A__) \
-|| defined(__AVR_ATmega165P__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega168A__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega169__) \
-|| defined(__AVR_ATmega169A__) \
-|| defined(__AVR_ATmega169P__) \
-|| defined(__AVR_ATmega169PA__) \
-|| defined(__AVR_ATmega16HVA__) \
-|| defined(__AVR_ATmega16HVA2__) \
-|| defined(__AVR_ATmega16HVB__) \
-|| defined(__AVR_ATmega16M1__) \
-|| defined(__AVR_ATmega16U2__) \
-|| defined(__AVR_ATmega16U4__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) \
-|| defined(__AVR_ATmega324__) \
-|| defined(__AVR_ATmega324A__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega324PA__) \
-|| defined(__AVR_ATmega325__) \
-|| defined(__AVR_ATmega3250__) \
-|| defined(__AVR_ATmega328__) \
-|| defined(__AVR_ATmega328P__) \
-|| defined(__AVR_ATmega329__) \
-|| defined(__AVR_ATmega329P__) \
-|| defined(__AVR_ATmega329PA__) \
-|| defined(__AVR_ATmega3290__) \
-|| defined(__AVR_ATmega3290P__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32HVB__) \
-|| defined(__AVR_ATmega32M1__) \
-|| defined(__AVR_ATmega32U2__) \
-|| defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega32U6__) \
-|| defined(__AVR_ATmega406__) \
-|| defined(__AVR_ATmega48__) \
-|| defined(__AVR_ATmega48A__) \
-|| defined(__AVR_ATmega48P__) \
-|| defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644A__) \
-|| defined(__AVR_ATmega644P__) \
-|| defined(__AVR_ATmega644PA__) \
-|| defined(__AVR_ATmega645__) \
-|| defined(__AVR_ATmega645A__) \
-|| defined(__AVR_ATmega645P__) \
-|| defined(__AVR_ATmega6450__) \
-|| defined(__AVR_ATmega6450A__) \
-|| defined(__AVR_ATmega6450P__) \
-|| defined(__AVR_ATmega649__) \
-|| defined(__AVR_ATmega649A__) \
-|| defined(__AVR_ATmega6490__) \
-|| defined(__AVR_ATmega6490A__) \
-|| defined(__AVR_ATmega6490P__) \
-|| defined(__AVR_ATmega649P__) \
-|| defined(__AVR_ATmega64C1__) \
-|| defined(__AVR_ATmega64HVE__) \
-|| defined(__AVR_ATmega64M1__) \
-|| defined(__AVR_ATmega88__) \
-|| defined(__AVR_ATmega88A__) \
-|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATmega88PA__) \
-|| defined(__AVR_ATmega8HVA__) \
-|| defined(__AVR_ATmega8U2__) \
-|| defined(__AVR_ATtiny48__) \
-|| defined(__AVR_ATtiny88__) \
-|| defined(__AVR_ATtiny87__) \
-|| defined(__AVR_ATtiny167__) \
-|| defined(__AVR_AT90SCR100__) \
-|| defined(__AVR_ATA6289__)
-
-/* Use STS instruction. */
- 
-#define wdt_enable(value)   \
-__asm__ __volatile__ (  \
-    "in __tmp_reg__,__SREG__" "\n\t"    \
-    "cli" "\n\t"    \
-    "wdr" "\n\t"    \
-    "sts %0,%1" "\n\t"  \
-    "out __SREG__,__tmp_reg__" "\n\t"   \
-    "sts %0,%2" "\n\t" \
-    : /* no outputs */  \
-    : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
-    "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
-    "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
-        _BV(WDE) | (value & 0x07)) ) \
-    : "r0"  \
-)
-
-#define wdt_disable() \
-__asm__ __volatile__ (  \
-    "in __tmp_reg__, __SREG__" "\n\t" \
-    "cli" "\n\t" \
-    "sts %0, %1" "\n\t" \
-    "sts %0, __zero_reg__" "\n\t" \
-    "out __SREG__,__tmp_reg__" "\n\t" \
-    : /* no outputs */ \
-    : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
-    "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
-    : "r0" \
-)
-
-
-    
-#else  
-
-/* Use OUT instruction. */
-
-#define wdt_enable(value)   \
-    __asm__ __volatile__ (  \
-        "in __tmp_reg__,__SREG__" "\n\t"    \
-        "cli" "\n\t"    \
-        "wdr" "\n\t"    \
-        "out %0,%1" "\n\t"  \
-        "out __SREG__,__tmp_reg__" "\n\t"   \
-        "out %0,%2" \
-        : /* no outputs */  \
-        : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
-        "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)),   \
-        "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
-            _BV(WDE) | (value & 0x07)) ) \
-        : "r0"  \
-    )
-
-/**
- *  Disable the watchdog timer, if possible.  This attempts to turn off the 
- *  Enable bit in the watchdog control register. See the datasheet for 
- *  details.
-*/
-#define wdt_disable() \
-__asm__ __volatile__ (  \
-    "in __tmp_reg__, __SREG__" "\n\t" \
-     "cli" "\n\t" \
-    "out %0, %1" "\n\t" \
-    "out %0, __zero_reg__" "\n\t" \
-    "out __SREG__,__tmp_reg__" "\n\t" \
-    : /* no outputs */ \
-    : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
-    "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
-    : "r0" \
-)
-
-#endif
-
-
-
-/**
- *  Symbolic constants for the watchdog timeout.  Since the watchdog
- *  timer is based on a free-running RC oscillator, the times are
- *  approximate only and apply to a supply voltage of 5 V.  At lower
- *  supply voltages, the times will increase.  For older devices, the
- *  times will be as large as three times when operating at Vcc = 3 V,
- *  while the newer devices (e. g. ATmega128, ATmega8) only experience
- *  a negligible change.
- * 
- *  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
- *  500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
- *  Symbolic constants are formed by the prefix
- *  @c WDTO_, followed by the time.
- * 
- *  Example that would select a watchdog timer expiry of approximately
- *  500 ms:
- * 
- *  @code{.c}
- *  wdt_enable(WDTO_500MS);
- *  @endcode
-*/
-#define WDTO_15MS   0
-
-/** @see WDT0_15MS */
-#define WDTO_30MS   1
-
-/** @see WDT0_15MS */
-#define WDTO_60MS   2
-
-/** @see WDT0_15MS */
-#define WDTO_120MS  3
-
-/** @see WDT0_15MS */
-#define WDTO_250MS  4
-
-/** @see WDT0_15MS */
-#define WDTO_500MS  5
-
-/** @see WDT0_15MS */
-#define WDTO_1S     6
-
-/** @see WDT0_15MS */
-#define WDTO_2S     7
-
-#if defined(__DOXYGEN__) || defined(WDP3)
-
-/**
- * @see WDT0_15MS
- * 
- * Note: This is only available on:
- * ATtiny2313, 
- * ATtiny24, ATtiny44, ATtiny84, 
- * ATtiny25, ATtiny45, ATtiny85, 
- * ATtiny261, ATtiny461, ATtiny861, 
- * ATmega48, ATmega88, ATmega168,
- * ATmega48P, ATmega88P, ATmega168P, ATmega328P,
- * ATmega164P, ATmega324P, ATmega644P, ATmega644,
- * ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
- * ATmega8HVA, ATmega16HVA, ATmega32HVB,
- * ATmega406, ATmega1284P,
- * AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
- * AT90PWM81,
- * AT90USB82, AT90USB162,
- * AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
- * ATtiny48, ATtiny88.
- */
-#define WDTO_4S     8
-
-/** @see WDTO_4S */
-#define WDTO_8S     9
-
-#endif  /* defined(__DOXYGEN__) || defined(WDP3) */
-/** @} */   
-
-#endif /* _AVR_WDT_H_ */
diff --git a/cpukit/score/cpu/avr/cpu.c b/cpukit/score/cpu/avr/cpu.c
deleted file mode 100644
index f22a7a0855..0000000000
--- a/cpukit/score/cpu/avr/cpu.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- *  @file
- *
- *  @brief AVR CPU Dependent Source
- */
-
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/wkspace.h>
-
-#include <rtems/bspIo.h> /* XXX remove me later */
-
-void _CPU_Initialize(void)
-{
-
-  /*
-   *  If there is not an easy way to initialize the FP context
-   *  during Context_Initialize, then it is usually easier to
-   *  save an "uninitialized" FP context here and copy it to
-   *  the task's during Context_Initialize.
-   */
-
-  /* FP context initialization support goes here */
-}
-
-uint32_t   _CPU_ISR_Get_level( void )
-{
-  /*
-   *  This routine returns the current interrupt level.
-   */
-  if((SREG & 0x80))return 1;
-  else 	return 0;
-
-}
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  /*
-   *  This is where we install the interrupt handler into the "raw" interrupt
-   *  table used by the CPU to dispatch interrupt handlers.
-   */
-}
-
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  If the interrupt vector table is a table of pointer to isr entry
-    *  points, then we need to install the appropriate RTEMS interrupt
-    *  handler for this vector number.
-    */
-
-   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */	
-
-    _ISR_Vector_table[ vector ] = new_handler;
-}
-
-/*
- *  _CPU_Install_interrupt_stack
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Install_interrupt_stack( void )
-{
-}
-
-/*
- *  _CPU_Thread_Idle_body
- *
- *  NOTES:
- *
- *  1. This is the same as the regular CPU independent algorithm.
- *
- *  2. If you implement this using a "halt", "idle", or "shutdown"
- *     instruction, then don't forget to put it in an infinite loop.
- *
- *  3. Be warned. Some processors with onboard DMA have been known
- *     to stop the DMA if the CPU were put in IDLE mode.  This might
- *     also be a problem with other on-chip peripherals.  So use this
- *     hook with caution.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void *_CPU_Thread_Idle_body( uintptr_t ignored )
-{
-
-  for( ; ; ) __asm__ volatile ("sleep"::);
-    /* insert your "halt" instruction here */ ;
-  return (void *) 0;
-}
diff --git a/cpukit/score/cpu/avr/cpu_asm.S b/cpukit/score/cpu/avr/cpu_asm.S
deleted file mode 100644
index 475a370d9a..0000000000
--- a/cpukit/score/cpu/avr/cpu_asm.S
+++ /dev/null
@@ -1,458 +0,0 @@
-/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
- *
- *  This file contains the basic algorithms for all assembly code used
- *  in an specific CPU port of RTEMS.  These algorithms must be implemented
- *  in assembly language
- *
- *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
- *
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-/*
- *  This is supposed to be an assembly file.  This means that system.h
- *  and cpu.h should not be included in a "real" cpu_asm file.  An
- *  implementation in assembly should include "cpu_asm.h>
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/asm.h>
-#include <avr/sfr_defs.h>
-#include <rtems/score/percpu.h>
-
-
-#define jmpb_hi 	r25
-#define jmpb_lo 	r24
-#define val_hi 		r23
-#define val_lo 		r22
-
-#define ret_lo		r24
-#define ret_hi 		r25
-
-	PUBLIC( setjmp )
-
-SYM( setjmp ):
-	X_movw		XL, jmpb_lo
-/*;save call-saved registers and frame pointer*/
-	.irp		.L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29	
-	st		X+, r\.L_regno
-	.endr
-/*;get return address*/
-	
-	pop		ZH
-	pop		ZL
-/*save stack pointer (after popping)*/
-	
-	in 		ret_lo, 	AVR_STACK_POINTER_LO_ADDR
-	st		X+, ret_lo
-	
-#ifdef _HAVE_AVR_STACK_POINTER_HI
-	in 		ret_lo, AVR_STACK_POINTER_HI_ADDR
-	st 		X+, ret_lo
-#else
-	st		X+, ret_lo
-#endif
-/*save status reg (I flag)*/
-	in		ret_lo, AVR_STATUS_ADDR
-	st		X+, ret_lo
-/*save return addr*/
-	st		X+, ZL
-	st		X+, ZH
-/*return zero*/
-	clr 		ret_hi
-	clr		ret_lo
-	ijmp
-
-	.size		_U(setjmp),.-_U(setjmp)
-
-
-	.global _U(longjmp)
-	.type _U(longjmp), @function
-
-_U(longjmp):
-	X_movw		XL, jmpb_lo
-/*return value*/
-	X_movw		ret_lo, val_lo
-/*if zero, change to 1*/
-	cpi		ret_lo, 1
-	cpc		ret_hi, __zero_reg__
-	adc		ret_lo, __zero_reg__
-/*restore call-saved registers and frame pointer*/
-	.irp	.L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29
-	ld	r\.L_regno, X+
-	.endr
-/*; restore stack pointer (SP value before the setjmp() call) and SREG*/
-	ld	ZL, X+
-	ld	ZH, X+
-	ld	__tmp_reg__, X+
-#if  defined (__AVR_XMEGA__) && __AVR_XMEGA__
-	/* A write to SPL will automatically disable interrupts for up to 4
-	   instructions or until the next I/O memory write.	*/
-	out	AVR_STATUS_ADDR, __tmp_reg__
-	out	AVR_STACK_POINTER_LO_ADDR, ZL
-	out	AVR_STACK_POINTER_HI_ADDR, ZH
-#else
-# ifdef _HAVE_AVR_STACK_POINTER_HI
-	/* interrupts disabled for shortest possible time (3 cycles) */
-	cli
-	out	AVR_STACK_POINTER_HI_ADDR, ZH
-# endif
-	/* Restore status register (including the interrupt enable flag).
-	   Interrupts are re-enabled only after the next instruction.  */
-	out	AVR_STATUS_ADDR, __tmp_reg__
-	out	AVR_STACK_POINTER_LO_ADDR, ZL
-#endif
-  ; get return address and jump
-	ld	ZL, X+
-	ld	ZH, X+
-#if  defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__
-	ld	__tmp_reg__, X+
-.L_jmp3:
-	push	ZL
-	push	ZH
-	push	__tmp_reg__
-	ret
-#else
-	ijmp
-#endif
-	.size	_U(longjmp), . - _U(longjmp)
-
-
-
-/*
- *  _CPU_Context_save_fp_context
- *
- *  This routine is responsible for saving the FP context
- *  at *fp_context_ptr.  If the point to load the FP context
- *  from is changed then the pointer is modified by this routine.
- *
- *  Sometimes a macro implementation of this is in cpu.h which dereferences
- *  the ** and a similarly named routine in this file is passed something
- *  like a (Context_Control_fp *).  The general rule on making this decision
- *  is to avoid writing assembly language.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
-
-
-void _CPU_Context_save_fp(
-  Context_Control_fp **fp_context_ptr
-)
-{
-}
-*/
-
-	PUBLIC(_CPU_Context_save_fp)
-
-SYM(_CPU_Context_save_fp):
-	ret
-
-
-	
-
-
-
-
-/*
- *  _CPU_Context_restore_fp_context
- *
- *  This routine is responsible for restoring the FP context
- *  at *fp_context_ptr.  If the point to load the FP context
- *  from is changed then the pointer is modified by this routine.
- *
- *  Sometimes a macro implementation of this is in cpu.h which dereferences
- *  the ** and a similarly named routine in this file is passed something
- *  like a (Context_Control_fp *).  The general rule on making this decision
- *  is to avoid writing assembly language.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
-
-
-void _CPU_Context_restore_fp(
-  Context_Control_fp **fp_context_ptr
-)
-{
-}
-*/
-
-
-	PUBLIC(_CPU_Context_restore_fp)
-
-SYM(_CPU_Context_restore_fp):
-	ret
-
-
-
-/*  _CPU_Context_switch
- *
- *  This routine performs a normal non-FP context switch.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- void _CPU_Context_switch(
-  Context_Control  *run,
-  Context_Control  *heir
-);
-
-*/
-
-	PUBLIC(_CPU_Context_switch)
-SYM(_CPU_Context_switch):
-	mov	r26, r24 	/*r26,r27 is X*/
-	mov	r27, r25
-	mov	r24, r22
- 	mov	r25, r23
-	/*save registers*/
-#if 1
-/*if this section is removed there is a problem.*/
-/*debug section start*/
-	pop	r22
-	pop	r23
-	push	r22
-	push	r23
-/*debug section end*/
-#endif
-
-	push	r2
-	push	r3
-	push	r4
-	push	r5
-	push	r6
-	push	r7
-	push	r8
-	push	r9
-	push	r10
-	push	r11
-	push	r12
-	push	r13
-	push	r14
-	push	r15
-	push	r16
-	push	r17
-
-	push	r28
-	push	r29
-
-	/*load sreg*/
-	lds 	r23,0x5f  /*load sreg*/
-	/*disable interrupts*/
-	cli
-	/*load stack pointer*/
-	lds	r22,0x5d /*spl*/
-	lds 	r21,0x5e /*sph*/
-	/*save sreg and sp to context struct*/
-
-	/*save low then high byte --- verify this delete when verified*/
-	st	X+, r22
-	st	X+, r21
-	st 	X, r23
-
-	PUBLIC(_CPU_Context_restore)
-
-SYM(_CPU_Context_restore):
-	mov	r26,r24         /* R26/27 are X */
-	mov	r27,r25
-
-	/*restore stack pointer*/
-	ld	r25, X+
-	ld	r24, X+	
-	sts	0x5E,r24  /*sph*/
-	sts 	0x5D ,r25 /*spl*/
-	/*restore registers from stack*/
-
-
-	pop	r29
-	pop	r28
-
-
-	pop	r17
-	pop	r16
-	pop	r15
-	pop	r14
-	pop	r13
-	pop	r12
-	pop	r11
-	pop	r10
-	pop	r9
-	pop	r8
-	pop	r7
-	pop	r6
-	pop	r5
-	pop	r4
-	pop	r3
-	pop	r2
-
-	/*restore sreg*/
-	ld	r25, X
-	sts	0x5f,r25 /*sreg*/
-	pop	r30
-	pop	r31
-	IJMP
-	ret
-
-
-
-/*
- *  _CPU_Context_Initialize
- *
- *  This kernel routine initializes the basic non-FP context area associated
- *  with each thread.
- *
- *  Input parameters:
- *    the_context  - pointer to the context area
- *    stack_base   - address of memory for the SPARC
- *    size         - size in bytes of the stack area
- *    new_level    - interrupt level for this context area
- *    entry_point  - the starting execution point for this this context
- *    is_fp        - TRUE if this context is associated with an FP thread
- *
- *	the_context is in r25,r24
- *	entry point is in r13,r12
- *	stack base is in r23, r22
- *	size is in r21, r20, r19,r18
- *	newleve is in r14,r15, r16, 17
- *
- *
- *  Output parameters: NONE
- */
-
-	PUBLIC(_CPU_Context_Initialize)
-SYM(_CPU_Context_Initialize):
-	//save caller saved regs
-	PUSH	R10
-	PUSH 	R11
-	PUSH	R12
-	PUSH 	R13
-	PUSH 	R14
-	PUSH 	R15
-	PUSH 	R16
-	PUSH	R17
-	PUSH	R28
-	PUSH	R29
-	//calculate new stack pointer
-	ADD	R22, R18
-	ADC	R23, R19
-	MOV	R26, R22
-	MOV	R27, R23
-	//Initialize stack with entry point
-	ST	-X, R13
-	ST	-X, R12
-	//store new stack pointer in context control
-	SBIW	R26, 0X13	/*subtract 33 to account for registers*/
-	MOV	R28, R24
-	MOV	R29, R25
-	STD	Y+1, R27	//save stack pointer high to context control
-	ST	Y, R26		//save stack pointer low to context control
-	//set interrupt level in new context
-	LDI	R18, 0		//set sreg in new context to zero
-	STD	Y+2, R18 	//interrupts not enabled		
-	MOV	R18, R14
-	CPI	R18, 0
-	BRNE	NEW_LEVEL_ZERO
-	LDI	R18, 0X80	//set sreg in new context to 0x80
-	STD	Y+2, R18	//interupts enabled
-NEW_LEVEL_ZERO:
-	//restore caller saved regs
-	POP	R29
-	POP	R28
-	POP	R17
-	POP	R16
-	POP	R15
-	POP	R14
-	POP	R13
-	POP	R12
-	POP	R11
-	POP	R10
-	RET
-	
-
-
-/*  void __ISR_Handler()
- *
- *  This routine provides the RTEMS interrupt management.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
-
-
-void _ISR_Handler(void)
-{
-
-*/
-   /*
-    *  This discussion ignores a lot of the ugly details in a real
-    *  implementation such as saving enough registers/state to be
-    *  able to do something real.  Keep in mind that the goal is
-    *  to invoke a user's ISR handler which is written in C and
-    *  uses a certain set of registers.
-    *
-    *  Also note that the exact order is to a large extent flexible.
-    *  Hardware will dictate a sequence for a certain subset of
-    *  _ISR_Handler while requirements for setting
-    */
-
-  /*
-   *  At entry to "common" _ISR_Handler, the vector number must be
-   *  available.  On some CPUs the hardware puts either the vector
-   *  number or the offset into the vector table for this ISR in a
-   *  known place.  If the hardware does not give us this information,
-   *  then the assembly portion of RTEMS for this port will contain
-   *  a set of distinct interrupt entry points which somehow place
-   *  the vector number in a known place (which is safe if another
-   *  interrupt nests this one) and branches to _ISR_Handler.
-   *
-   *  save some or all context on stack
-   *  may need to save some special interrupt information for exit
-   *
-   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
-   *    if ( _ISR_Nest_level == 0 )
-   *      switch to software interrupt stack
-   *  #endif
-   *
-   *  _ISR_Nest_level++;
-   *
-   *  _Thread_Dispatch_disable_level++;
-   *
-   *  (*_ISR_Vector_table[ vector ])( vector );
-   *
-   *  _Thread_Dispatch_disable_level--;
-   *
-   *  --_ISR_Nest_level;
-   *
-   *  if ( _ISR_Nest_level )
-   *    goto the label "exit interrupt (simple case)"
-   *
-   *  if ( _Thread_Dispatch_disable_level )
-   *    goto the label "exit interrupt (simple case)"
-   *
-   *  if ( _Thread_Dispatch_necessary ) {
-   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
-   *    prepare to get out of interrupt
-   *    return from interrupt  (maybe to _ISR_Dispatch)
-   *
-   *  LABEL "exit interrupt (simple case):
-   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
-   *    if outermost interrupt
-   *      restore stack
-   *  #endif
-   *  prepare to get out of interrupt
-   *  return from interrupt
-   */
-/*}    */
-	PUBLIC(_ISR_Handler)
-
-SYM(_ISR_Handler):
-	ret
diff --git a/cpukit/score/cpu/avr/preinstall.am b/cpukit/score/cpu/avr/preinstall.am
deleted file mode 100644
index ffa25a2b89..0000000000
--- a/cpukit/score/cpu/avr/preinstall.am
+++ /dev/null
@@ -1,646 +0,0 @@
-## Automatically generated by ampolish3 - Do not edit
-
-if AMPOLISH3
-$(srcdir)/preinstall.am: Makefile.am
-	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
-endif
-
-PREINSTALL_DIRS =
-DISTCLEANFILES = $(PREINSTALL_DIRS)
-
-all-am: $(PREINSTALL_FILES)
-
-PREINSTALL_FILES =
-CLEANFILES = $(PREINSTALL_FILES)
-
-$(PROJECT_INCLUDE)/rtems/$(dirstamp):
-	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
-	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
-
-$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
-
-$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
-	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
-	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-
-$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
-
-$(PROJECT_INCLUDE)/rtems/score/avr.h: rtems/score/avr.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/avr.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/avr.h
-
-$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
-
-$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
-
-$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
-
-$(PROJECT_INCLUDE)/avr/$(dirstamp):
-	@$(MKDIR_P) $(PROJECT_INCLUDE)/avr
-	@: > $(PROJECT_INCLUDE)/avr/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/avr/$(dirstamp)
-
-$(PROJECT_INCLUDE)/avr/boot.h: avr/boot.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/boot.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/boot.h
-
-$(PROJECT_INCLUDE)/avr/common.h: avr/common.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/common.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/common.h
-
-$(PROJECT_INCLUDE)/avr/crc16.h: avr/crc16.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/crc16.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/crc16.h
-
-$(PROJECT_INCLUDE)/avr/delay.h: avr/delay.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/delay.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/delay.h
-
-$(PROJECT_INCLUDE)/avr/eeprom.h: avr/eeprom.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/eeprom.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/eeprom.h
-
-$(PROJECT_INCLUDE)/avr/fuse.h: avr/fuse.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/fuse.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/fuse.h
-
-$(PROJECT_INCLUDE)/avr/interrupt.h: avr/interrupt.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/interrupt.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/interrupt.h
-
-$(PROJECT_INCLUDE)/avr/io1200.h: avr/io1200.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io1200.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io1200.h
-
-$(PROJECT_INCLUDE)/avr/io2313.h: avr/io2313.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io2313.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io2313.h
-
-$(PROJECT_INCLUDE)/avr/io2323.h: avr/io2323.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io2323.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io2323.h
-
-$(PROJECT_INCLUDE)/avr/io2333.h: avr/io2333.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io2333.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io2333.h
-
-$(PROJECT_INCLUDE)/avr/io2343.h: avr/io2343.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io2343.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io2343.h
-
-$(PROJECT_INCLUDE)/avr/io43u32x.h: avr/io43u32x.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io43u32x.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io43u32x.h
-
-$(PROJECT_INCLUDE)/avr/io43u35x.h: avr/io43u35x.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io43u35x.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io43u35x.h
-
-$(PROJECT_INCLUDE)/avr/io4414.h: avr/io4414.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io4414.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io4414.h
-
-$(PROJECT_INCLUDE)/avr/io4433.h: avr/io4433.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io4433.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io4433.h
-
-$(PROJECT_INCLUDE)/avr/io4434.h: avr/io4434.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io4434.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io4434.h
-
-$(PROJECT_INCLUDE)/avr/io76c711.h: avr/io76c711.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io76c711.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io76c711.h
-
-$(PROJECT_INCLUDE)/avr/io8515.h: avr/io8515.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io8515.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io8515.h
-
-$(PROJECT_INCLUDE)/avr/io8534.h: avr/io8534.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io8534.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io8534.h
-
-$(PROJECT_INCLUDE)/avr/io8535.h: avr/io8535.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io8535.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io8535.h
-
-$(PROJECT_INCLUDE)/avr/io86r401.h: avr/io86r401.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io86r401.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io86r401.h
-
-$(PROJECT_INCLUDE)/avr/io90pwm1.h: avr/io90pwm1.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io90pwm1.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io90pwm1.h
-
-$(PROJECT_INCLUDE)/avr/io90pwm216.h: avr/io90pwm216.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io90pwm216.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io90pwm216.h
-
-$(PROJECT_INCLUDE)/avr/io90pwm2b.h: avr/io90pwm2b.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io90pwm2b.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io90pwm2b.h
-
-$(PROJECT_INCLUDE)/avr/io90pwm316.h: avr/io90pwm316.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io90pwm316.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/io90pwm316.h
-
-$(PROJECT_INCLUDE)/avr/io90pwm3b.h: avr/io90pwm3b.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/io90pwm3b.h
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-
-$(PROJECT_INCLUDE)/avr/iotnx4.h: avr/iotnx4.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iotnx4.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iotnx4.h
-
-$(PROJECT_INCLUDE)/avr/iotnx5.h: avr/iotnx5.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iotnx5.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iotnx5.h
-
-$(PROJECT_INCLUDE)/avr/iotnx61.h: avr/iotnx61.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iotnx61.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iotnx61.h
-
-$(PROJECT_INCLUDE)/avr/iousb1286.h: avr/iousb1286.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb1286.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb1286.h
-
-$(PROJECT_INCLUDE)/avr/iousb1287.h: avr/iousb1287.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb1287.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb1287.h
-
-$(PROJECT_INCLUDE)/avr/iousb162.h: avr/iousb162.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb162.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb162.h
-
-$(PROJECT_INCLUDE)/avr/iousb646.h: avr/iousb646.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb646.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb646.h
-
-$(PROJECT_INCLUDE)/avr/iousb647.h: avr/iousb647.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb647.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb647.h
-
-$(PROJECT_INCLUDE)/avr/iousb82.h: avr/iousb82.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousb82.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousb82.h
-
-$(PROJECT_INCLUDE)/avr/iousbxx2.h: avr/iousbxx2.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousbxx2.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousbxx2.h
-
-$(PROJECT_INCLUDE)/avr/iousbxx6_7.h: avr/iousbxx6_7.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iousbxx6_7.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iousbxx6_7.h
-
-$(PROJECT_INCLUDE)/avr/iox128a1.h: avr/iox128a1.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox128a1.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox128a1.h
-
-$(PROJECT_INCLUDE)/avr/iox128a3.h: avr/iox128a3.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox128a3.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox128a3.h
-
-$(PROJECT_INCLUDE)/avr/iox16a4.h: avr/iox16a4.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox16a4.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox16a4.h
-
-$(PROJECT_INCLUDE)/avr/iox16d4.h: avr/iox16d4.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox16d4.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox16d4.h
-
-$(PROJECT_INCLUDE)/avr/iox256a3b.h: avr/iox256a3b.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox256a3b.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox256a3b.h
-
-$(PROJECT_INCLUDE)/avr/iox256a3.h: avr/iox256a3.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox256a3.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox256a3.h
-
-$(PROJECT_INCLUDE)/avr/iox32a4.h: avr/iox32a4.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox32a4.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox32a4.h
-
-$(PROJECT_INCLUDE)/avr/iox32d4.h: avr/iox32d4.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox32d4.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox32d4.h
-
-$(PROJECT_INCLUDE)/avr/iox64a1.h: avr/iox64a1.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox64a1.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox64a1.h
-
-$(PROJECT_INCLUDE)/avr/iox64a3.h: avr/iox64a3.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/iox64a3.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/iox64a3.h
-
-$(PROJECT_INCLUDE)/avr/lock.h: avr/lock.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/lock.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/lock.h
-
-$(PROJECT_INCLUDE)/avr/parity.h: avr/parity.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/parity.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/parity.h
-
-$(PROJECT_INCLUDE)/avr/pgmspace.h: avr/pgmspace.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/pgmspace.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/pgmspace.h
-
-$(PROJECT_INCLUDE)/avr/portpins.h: avr/portpins.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/portpins.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/portpins.h
-
-$(PROJECT_INCLUDE)/avr/power.h: avr/power.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/power.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/power.h
-
-$(PROJECT_INCLUDE)/avr/sfr_defs.h: avr/sfr_defs.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/sfr_defs.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/sfr_defs.h
-
-$(PROJECT_INCLUDE)/avr/signal.h: avr/signal.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/signal.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/signal.h
-
-$(PROJECT_INCLUDE)/avr/sleep.h: avr/sleep.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/sleep.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/sleep.h
-
-$(PROJECT_INCLUDE)/avr/version.h: avr/version.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/version.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/version.h
-
-$(PROJECT_INCLUDE)/avr/wdt.h: avr/wdt.h $(PROJECT_INCLUDE)/avr/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/avr/wdt.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/avr/wdt.h
-
diff --git a/cpukit/score/cpu/avr/rtems/asm.h b/cpukit/score/cpu/avr/rtems/asm.h
deleted file mode 100644
index e93841d06e..0000000000
--- a/cpukit/score/cpu/avr/rtems/asm.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/**
- * @file
- *
- * @brief Address the Problems Caused by Incompatible Flavor of
- * Assemblers and Toolsets
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets.  It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- *
- * @note The spacing in the use of these macros
- *       is critical to them working as advertised.
- */
-
-/*
- *  COPYRIGHT:
- *
- *  This file is based on similar code found in newlib available
- *  from ftp.cygnus.com.  The file which was used had no copyright
- *  notice.  This file is freely distributable as long as the source
- *  of the file is noted.  This file is:
- *
- *  COPYRIGHT (c) 1994-1997.
- *  On-Line Applications Research Corporation (OAR).
- */
-
-#ifndef _RTEMS_ASM_H
-#define _RTEMS_ASM_H
-
-/*
- *  Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/avr.h>
-
-/*
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
- */
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-#include <rtems/concat.h>
-
-/* Use the right prefix for global labels.  */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/* Use the right prefix for registers.  */
-
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/*
- *  define macros for all of the registers on this CPU
- *
- *  EXAMPLE:     #define d0 REG (d0)
- */
-
-
-/*
- *  Define macros to handle section beginning and ends.
- */
-
-
-#define BEGIN_CODE_DCL .text
-#define END_CODE_DCL
-#define BEGIN_DATA_DCL .data
-#define END_DATA_DCL
-#define BEGIN_CODE .text
-#define END_CODE
-#define BEGIN_DATA
-#define END_DATA
-#define BEGIN_BSS
-#define END_BSS
-#define END
-
-/*
- *  Following must be tailor for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
- */
-
-#define PUBLIC(sym) .globl SYM (sym)
-#define EXTERN(sym) .globl SYM (sym)
-
-/* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz
-   Copyright (c) 2006 Dmitry Xmelkov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/*
-   macros.inc - macros for use in assembler sources
-
-   Contributors:
-     Created by Marek Michalkiewicz <marekm@linux.org.pl>
- */
-
-#include <avr/common.h>
-
-/* if not defined, assume old version with underscores */
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-/* the assembler line separator (just in case it ever changes) */
-#define _L $
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-#define _U(x) CONCAT1(__USER_LABEL_PREFIX__, x)
-
-#define _R(x) CONCAT1(__REGISTER_PREFIX__, x)
-
-/* these should help to fix the "can't have function named r1()" bug
-   which may require adding '%' in front of register names.  */
-
-#define r0 _R(r0)
-#define r1 _R(r1)
-#define r2 _R(r2)
-#define r3 _R(r3)
-#define r4 _R(r4)
-#define r5 _R(r5)
-#define r6 _R(r6)
-#define r7 _R(r7)
-#define r8 _R(r8)
-#define r9 _R(r9)
-#define r10 _R(r10)
-#define r11 _R(r11)
-#define r12 _R(r12)
-#define r13 _R(r13)
-#define r14 _R(r14)
-#define r15 _R(r15)
-#define r16 _R(r16)
-#define r17 _R(r17)
-#define r18 _R(r18)
-#define r19 _R(r19)
-#define r20 _R(r20)
-#define r21 _R(r21)
-#define r22 _R(r22)
-#define r23 _R(r23)
-#define r24 _R(r24)
-#define r25 _R(r25)
-#define r26 _R(r26)
-#define r27 _R(r27)
-#define r28 _R(r28)
-#define r29 _R(r29)
-#define r30 _R(r30)
-#define r31 _R(r31)
-
-#ifndef __tmp_reg__
-#define __tmp_reg__ r0
-#endif
-
-#ifndef __zero_reg__
-#define __zero_reg__ r1
-#endif
-
-#if __AVR_MEGA__
-  #define XJMP jmp
-  #define XCALL call
-#else
-  #define XJMP rjmp
-  #define XCALL rcall
-#endif
-
-/* used only by fplib/strtod.S - libgcc internal function calls */
-#define PROLOGUE_SAVES(offset) XJMP (__prologue_saves__ + 2 * (offset))
-#define EPILOGUE_RESTORES(offset) XJMP (__epilogue_restores__ + 2 * (offset))
-
-#if FLASHEND > 0x10000  /* ATmega103 */
-  #define BIG_CODE 1
-#else
-  #define BIG_CODE 0
-#endif
-
-#ifndef __AVR_HAVE_MOVW__
-#  if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#   define __AVR_HAVE_MOVW__ 1
-#  endif
-#endif
-
-#ifndef __AVR_HAVE_LPMX__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_LPMX__ 1
-# endif
-#endif
-
-#ifndef __AVR_HAVE_MUL__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_MUL__ 1
-# endif
-#endif
-
-/*
-   Smart version of movw:
-    - uses "movw" if possible (supported by MCU, and both registers even)
-    - handles overlapping register pairs correctly
-    - no instruction generated if source and destination are the same
-   (may expand to 0, 1 or 2 instructions).
- */
-
-.macro  X_movw dst src
-	.L_movw_dst = -1
-	.L_movw_src = -1
-	.L_movw_n = 0
-	.irp  reg,	r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \
-			r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \
-			r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \
-			r30,r31
-		.ifc  \reg,\dst
-			.L_movw_dst = .L_movw_n
-		.endif
-		.ifc  \reg,\src
-			.L_movw_src = .L_movw_n
-		.endif
-		.L_movw_n = .L_movw_n + 1
-	.endr
-	.L_movw_n = 0
-	.irp  reg,	R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \
-			R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \
-			R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \
-			R30,R31
-		.ifc  \reg,\dst
-			.L_movw_dst = .L_movw_n
-		.endif
-		.ifc  \reg,\src
-			.L_movw_src = .L_movw_n
-		.endif
-		.L_movw_n = .L_movw_n + 1
-	.endr
-	.if   .L_movw_dst < 0
-		.L_movw_n = 0
-		.rept   32
-			.if \dst == .L_movw_n
-				.L_movw_dst = .L_movw_n
-			.endif
-			.L_movw_n = .L_movw_n + 1
-		.endr
-	.endif
-	.if   .L_movw_src < 0
-		.L_movw_n = 0
-		.rept   32
-			.if \src == .L_movw_n
-				.L_movw_src = .L_movw_n
-			.endif
-			.L_movw_n = .L_movw_n + 1
-		.endr
-	.endif
-	.if   (.L_movw_dst < 0) || (.L_movw_src < 0)
-		.err    ; Invalid 'X_movw' arg.
-	.endif
-
-	.if ((.L_movw_src) - (.L_movw_dst))  /* different registers */
-		.if (((.L_movw_src) | (.L_movw_dst)) & 0x01)
-			.if (((.L_movw_src)-(.L_movw_dst)) & 0x80) /* src < dest */
-				mov     (.L_movw_dst)+1, (.L_movw_src)+1
-				mov     (.L_movw_dst), (.L_movw_src)
-			.else                                      /* src > dest */
-				mov     (.L_movw_dst), (.L_movw_src)
-				mov     (.L_movw_dst)+1, (.L_movw_src)+1
-			.endif
-		.else  /* both even -> overlap not possible */
-#if  defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__
-			movw    \dst, \src
-#else
-			mov     (.L_movw_dst), (.L_movw_src)
-			mov     (.L_movw_dst)+1, (.L_movw_src)+1
-#endif
-		.endif
-	.endif
-.endm
-
-/* Macro 'X_lpm' extends enhanced lpm instruction for classic chips.
-   Usage:
-	X_lpm	reg, dst
-   where
-	reg	is 0..31, r0..r31 or R0..R31
-	dst	is z, Z, z+ or Z+
-   It is possible to omit both arguments.
-
-   Possible results for classic chips:
-	lpm
-	lpm / mov Rd,r0
-	lpm / adiw ZL,1
-	lpm / mov Rd,r0 / adiw ZL,1
-
-   For enhanced chips it is one instruction always.
-
-   ATTENTION:  unlike enhanced chips SREG (S,V,N,Z,C) flags are
-   changed in case of 'Z+' dst.  R0 is scratch.
- */
-.macro	X_lpm	dst=r0, src=Z
-
-  /* dst evaluation	*/
-  .L_lpm_dst = -1
-
-  .L_lpm_n = 0
-  .irp  reg,  r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \
-	     r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \
-	     r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \
-	     r30,r31
-    .ifc  \reg,\dst
-      .L_lpm_dst = .L_lpm_n
-    .endif
-    .L_lpm_n = .L_lpm_n + 1
-  .endr
-
-  .L_lpm_n = 0
-  .irp  reg,  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \
-	     R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \
-	     R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \
-	     R30,R31
-    .ifc  \reg,\dst
-      .L_lpm_dst = .L_lpm_n
-    .endif
-    .L_lpm_n = .L_lpm_n + 1
-  .endr
-
-  .if  .L_lpm_dst < 0
-    .L_lpm_n = 0
-    .rept 32
-      .if  \dst == .L_lpm_n
-	.L_lpm_dst = .L_lpm_n
-      .endif
-      .L_lpm_n = .L_lpm_n + 1
-    .endr
-  .endif
-
-  .if  (.L_lpm_dst < 0)
-    .err	; Invalid dst arg of 'X_lpm' macro.
-  .endif
-
-  /* src evaluation	*/
-  .L_lpm_src = -1
-  .L_lpm_n = 0
-  .irp  reg,  z,Z,z+,Z+
-    .ifc  \reg,\src
-      .L_lpm_src = .L_lpm_n
-    .endif
-    .L_lpm_n = .L_lpm_n + 1
-  .endr
-
-  .if  (.L_lpm_src < 0)
-    .err	; Invalid src arg of 'X_lpm' macro.
-  .endif
-
-  /* instruction(s)	*/
-  .if  .L_lpm_src < 2
-    .if  .L_lpm_dst == 0
-	lpm
-    .else
-#if  defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__
-	lpm	.L_lpm_dst, Z
-#else
-	lpm
-	mov	.L_lpm_dst, r0
-#endif
-    .endif
-  .else
-    .if  (.L_lpm_dst >= 30)
-      .err	; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst.
-    .endif
-#if  defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__
-	lpm	.L_lpm_dst, Z+
-#else
-	lpm
-    .if  .L_lpm_dst
-	mov	.L_lpm_dst, r0
-    .endif
-	adiw	r30, 1
-#endif
-  .endif
-.endm
-
-/*
-   LPM_R0_ZPLUS_INIT is used before the loop to initialize RAMPZ
-   for future devices with RAMPZ:Z auto-increment - [e]lpm r0, Z+.
-
-   LPM_R0_ZPLUS_NEXT is used inside the loop to load a byte from
-   the program memory at [RAMPZ:]Z to R0, and increment [RAMPZ:]Z.
-
-   The argument in both macros is a register that contains the
-   high byte (bits 23-16) of the address, bits 15-0 should be in
-   the Z (r31:r30) register.  It can be any register except for:
-   r0, r1 (__zero_reg__ - assumed to always contain 0), r30, r31.
- */
-
-	.macro	LPM_R0_ZPLUS_INIT hhi
-#if __AVR_ENHANCED__
-  #if BIG_CODE
-	out	AVR_RAMPZ_ADDR, \hhi
-  #endif
-#endif
-	.endm
-
-	.macro	LPM_R0_ZPLUS_NEXT hhi
-#if __AVR_ENHANCED__
-  #if BIG_CODE
-    /* ELPM with RAMPZ:Z post-increment, load RAMPZ only once */
-	elpm	r0, Z+
-  #else
-    /* LPM with Z post-increment, max 64K, no RAMPZ (ATmega83/161/163/32) */
-	lpm	r0, Z+
-  #endif
-#else
-  #if BIG_CODE
-    /* ELPM without post-increment, load RAMPZ each time (ATmega103) */
-	out	AVR_RAMPZ_ADDR, \hhi
-	elpm
-	adiw	r30,1
-	adc	\hhi, __zero_reg__
-  #else
-    /* LPM without post-increment, max 64K, no RAMPZ (AT90S*) */
-	lpm
-	adiw	r30,1
-  #endif
-#endif
-	.endm
-
-#endif /* _RTEMS_ASM_H */
diff --git a/cpukit/score/cpu/avr/rtems/score/avr.h b/cpukit/score/cpu/avr/rtems/score/avr.h
deleted file mode 100644
index 064a2c8762..0000000000
--- a/cpukit/score/cpu/avr/rtems/score/avr.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * @file
- *
- * @brief Intel AVR Set up Basic CPU Dependency Settings Based on
- * Compiler Settings
- *
- * This file sets up basic CPU dependency settings based on
- * compiler settings.  For example, it can determine if
- * floating point is available.  This particular implementation
- * is specified to the avr port.
- */
-
-/*
- *  COPYRIGHT 2004, Ralf Corsepius, Ulm, Germany.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_AVR_H
-#define _RTEMS_SCORE_AVR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This file contains the information required to build
- *  RTEMS for a particular member of the NO CPU family.
- *  It does this by setting variables to indicate which
- *  implementation dependent features are present in a particular
- *  member of the family.
- *
- *  This is a good place to list all the known CPU models
- *  that this port supports and which RTEMS CPU model they correspond
- *  to.
- */
-
-/*
- *  Figure out all CPU Model Feature Flags based upon compiler
- *  predefines.
- */
-#if defined(__AVR__)
-
-#if defined(__AVR_ARCH__)
-#if   __AVR_ARCH__ == 1
-#define CPU_MODEL_NAME  "avr1"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 2
-#define CPU_MODEL_NAME  "avr2"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 3
-#define CPU_MODEL_NAME  "avr3"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 4
-#define CPU_MODEL_NAME  "avr4"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 5
-#define CPU_MODEL_NAME  "avr5"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 25
-#define CPU_MODEL_NAME  "avr25"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 31
-#define CPU_MODEL_NAME  "avr31"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 35
-#define CPU_MODEL_NAME  "avr35"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 51
-#define CPU_MODEL_NAME  "avr51"
-#define AVR_HAS_FPU     1
-
-#elif __AVR_ARCH__ == 6
-#define CPU_MODEL_NAME  "avr6"
-#define AVR_HAS_FPU     1
-
-#else
-#error "Unsupported __AVR_ARCH__"
-#endif
-#else
-#error "__AVR_ARCH__ undefined"
-#endif
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-
-/*
- *  Define the name of the CPU family.
- */
-
-#define CPU_NAME "avr"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTEMS_SCORE_AVR_H */
diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h
deleted file mode 100644
index f3baec4451..0000000000
--- a/cpukit/score/cpu/avr/rtems/score/cpu.h
+++ /dev/null
@@ -1,1176 +0,0 @@
-/**
- * @file
- *
- * @brief Intel AVR CPU Department Source
- *
- * This include file contains information pertaining to the AVR
- * processor.
- */
-
-/*
- *  COPYRIGHT (c) 1989-2006.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPU_H
-#define _RTEMS_SCORE_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-#include <rtems/score/avr.h>
-#include <avr/common.h>
-
-/* conditional compilation parameters */
-
-#ifndef	RTEMS_USE_16_BIT_OBJECT
-#define RTEMS_USE_16_BIT_OBJECT
-#endif
-
-/*
- *  Should the calls to _Thread_Enable_dispatch be inlined?
- *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
- *
- *  Basically this is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
- *  [NOTE: In general, the _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls _Thread_Enable_dispatch which in turns calls
- *  _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.]
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH       FALSE
-
-/*
- *  Does RTEMS manage a dedicated interrupt stack in software?
- *
- *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
- *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
- *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
- *
- *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
-
-/*
- *  Does this CPU have hardware support for a dedicated interrupt stack?
- *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
- *
- *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
-
-/*
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
- *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-/*
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- *  Does the CPU follow the simple vectored interrupt model?
- *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
-
-/*
- *  Does the CPU have hardware floating point?
- *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
- *
- *  The macro name "AVR_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
- *
- *  The CPU_SOFTWARE_FP is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#if ( AVR_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP     TRUE
-#else
-#define CPU_HARDWARE_FP     FALSE
-#endif
-#define CPU_SOFTWARE_FP     FALSE
-
-/*
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
- *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
- *
- *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_ALL_TASKS_ARE_FP     TRUE
-
-/*
- *  Should the IDLE task have a floating point context?
- *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
- *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_IDLE_TASK_IS_FP      FALSE
-
-/*
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
- *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
- *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
- *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
- *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
-
-/*
- *  Does this port provide a CPU dependent IDLE task implementation?
- *
- *  If TRUE, then the routine _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  _CPU_Thread_Idle_body.
- *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
- *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
- *
- *  The order of precedence for selecting the IDLE thread body is:
- *
- *    1.  BSP provided
- *    2.  CPU dependent (if provided)
- *    3.  generic (if no BSP and no CPU dependent)
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
-
-/*
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
- *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_STACK_GROWS_UP               FALSE
-
-/*
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
- *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
- *
- *      __attribute__ ((aligned (32)))
- *
- *  NOTE:  Currently only the Priority Bit Map table uses this feature.
- *         To benefit from using this, the data must be heavily
- *         used so it will stay in the cache and used frequently enough
- *         in the executive to justify turning this on.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_STRUCTURE_ALIGNMENT
-
-#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
-
-/*
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_BIG_ENDIAN                           TRUE
-#define CPU_LITTLE_ENDIAN                        FALSE
-
-/*
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_MODES_INTERRUPT_MASK   0x00000001
-
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
-/*
- *  Processor defined structures required for cpukit/score.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-/* may need to put some structures here.  */
-
-#ifndef ASM
-
-typedef struct {
-  /* There is no CPU specific per-CPU state */
-} CPU_Per_CPU_control;
-
-/*
- * Contexts
- *
- *  Generally there are 2 types of context to save.
- *     1. Interrupt registers to save
- *     2. Task level registers to save
- *
- *  This means we have the following 3 context items:
- *     1. task level context stuff::  Context_Control
- *     2. floating point task stuff:: Context_Control_fp
- *     3. special interrupt level context :: Context_Control_interrupt
- *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
- *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
- *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-typedef struct {
-    	uint16_t 	stack_pointer;
-   	uint8_t		status; /* SREG */
-} Context_Control;
-
-#define _CPU_Context_Get_SP( _context ) \
-  (_context)->stack_pointer
-
-
-
-
-typedef struct {
-    double      some_float_register;
-} Context_Control_fp;
-
-typedef struct {
-    uint32_t   special_interrupt_register;
-} CPU_Interrupt_frame;
-
-/*
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  _CPU_Initialize and copied into the task's FP context area during
- *  _CPU_Context_Initialize.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
-
-#endif /* ASM */
-
-/*
- *  Nothing prevents the porter from declaring more CPU specific variables.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-/* XXX: if needed, put more variables here */
-
-/*
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/*
- *  This defines the number of entries in the ISR_Vector_table managed
- *  by RTEMS.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/*
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/*
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_STACK_MINIMUM_SIZE          512
-
-/*
- *  Maximum priority of a thread. Note based from 0 which is the idle task.
- */
-#define CPU_PRIORITY_MAXIMUM             15
-
-#define CPU_SIZEOF_POINTER 2
-
-/*
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_ALIGNMENT              4
-
-/*
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
- *  then this should be set to CPU_ALIGNMENT.
- *
- *  NOTE:  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
- *
- *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
-
-/*
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
- *  enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- *  NOTE:  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
-
-/*
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
- *  is strict enough for the stack, then this should be set to 0.
- *
- *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_STACK_ALIGNMENT        0
-
-/*
- *  ISR handler macros
- */
-
-/*
- *  Support routine to initialize the RTEMS vector table after it is allocated.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_Initialize_vectors()
-
-/*
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in _level.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_ISR_Disable( _isr_cookie ) \
-  do { \
-    	(_isr_cookie) = SREG; \
-	__asm__ volatile ("cli"::); \
-  } while (0)
-
-/*
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  _level is not modified.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_ISR_Enable( _isr_cookie )  \
-  do { \
-	SREG  = _isr_cookie; \
-	__asm__ volatile ("sei"::); \
-  } while (0)
-
-/*
- *  This temporarily restores the interrupt to _level before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter _level is not
- * modified.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_ISR_Flash( _isr_cookie ) \
-  do { \
-	SREG=(_isr_cookie); \
-	__asm__ volatile("sei"::); \
-	(_isr_cookie) = SREG; \
-	__asm__ volatile("cli"::); \
-  } while (0)
-
-/*
- *  Map interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
- *
- *  The get routine usually must be implemented as a subroutine.
- *
- *  AVR Specific Information:
- *
- *  TODO: As of 8 October 2014, this method is not implemented.
- */
-#ifndef ASM
-static inline void _CPU_ISR_Set_level( unsigned int new_level )
-{
-}
-
-
-uint32_t   _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/* Context handler macros */
-
-/*
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-/*
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
-                                 _isr, _entry_point, _is_fp ) \
-  \
-	do { \
-	uint16_t *_stack;\
-	_stack	= (uint16_t) (_stack_base) + (uint16_t)(_size);\
-    	(_the_context)->stack_pointer = _stack-1;	\
-	*(_stack) = *(_entry_point);	\
-	printk("the ret address is %x\n", *(uint16_t *)(_stack));\
-	printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \
-	printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\
-	printk("struct starting address = 0x%x\n", _the_context);\
-	printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\
-	} while ( 0 )
-
-*/
-/*
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  Context_Restore should work most of the time.  It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
-   _CPU_Context_restore( _the_context );
-
-/*
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
- *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
-   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-/*
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
- *
- *  Other models include (1) not doing anything, and (2) putting
- *  a "null FP status word" in the correct place in the FP context.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
-  { \
-   *(*(_destination)) = _CPU_Null_fp_context; \
-  }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define _CPU_Fatal_halt( _source, _error ) \
-  { \
-  }
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- *  This routine sets _output to the bit number of the first bit
- *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
- *  This type may be either 16 or 32 bits wide although only the 16
- *  least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    (1) What happens when run on a value of zero?
- *    (2) Bits may be numbered from MSB to LSB or vice-versa.
- *    (3) The numbering may be zero or one based.
- *    (4) The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- *  _CPU_Priority_bits_index().  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by _CPU_Priority_mask().
- *  The basic major and minor values calculated by _Priority_Major()
- *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for _Priority_Get_highest() to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
- *
- *    - a series of 16 bit test instructions
- *    - a "binary search using if's"
- *    - _number = 0
- *      if _value > 0x00ff
- *        _value >>=8
- *        _number = 8;
- *
- *      if _value > 0x0000f
- *        _value >=8
- *        _number += 4
- *
- *      _number += bit_set_table[ _value ]
- *
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
-  { \
-    (_output) = 0;   /* do something to prevent warnings */ \
-  }
-
-#endif
-
-/* end of Bitfield handler macros */
-
-/*
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
- *  for that routine.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_Mask( _bit_number ) \
-  ( 1 << (_bit_number) )
-
-#endif
-
-/*
- *  This routine translates the bit numbers returned by
- *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_bits_index( _priority ) \
-  (_priority)
-
-#endif
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*context_initialize asm-function*/
-
-void context_initialize(unsigned short* context,
-		unsigned short stack_add,
-		unsigned short entry_point);
-
-/*
- *  _CPU_Context_Initialize
- *
- *  This kernel routine initializes the basic non-FP context area associated
- *  with each thread.
- *
- *  Input parameters:
- *    the_context  - pointer to the context area
- *    stack_base   - address of memory for the SPARC
- *    size         - size in bytes of the stack area
- *    new_level    - interrupt level for this context area
- *    entry_point  - the starting execution point for this this context
- *    is_fp        - TRUE if this context is associated with an FP thread
- *
- *  Output parameters: NONE
- */
-
-void _CPU_Context_Initialize(
-  Context_Control  *the_context,
-  uint32_t         *stack_base,
-  uint32_t          size,
-  uint32_t          new_level,
-  void             *entry_point,
-  bool              is_fp,
-  void             *tls_area
-);
-
-/*
-*
-*  _CPU_Push
-*
-*  this routine pushes 2 bytes onto the stack
-*
-*
-*
-*
-*
-*
-*
-*/
-
-void _CPU_Push(uint16_t _SP_, uint16_t entry_point);
-
-
-
-
-/*
- *  _CPU_Initialize
- *
- *  This routine performs CPU dependent initialization.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Initialize(void);
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  This routine installs an interrupt vector.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-/*
- *  _CPU_Install_interrupt_stack
- *
- *  This routine installs the hardware interrupt stack pointer.
- *
- *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- *  _CPU_Thread_Idle_body
- *
- *  This routine is the CPU dependent IDLE thread body.
- *
- *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
- *         is TRUE.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void *_CPU_Thread_Idle_body( uintptr_t ignored );
-
-/*
- *  _CPU_Context_switch
- *
- *  This routine switches from the run context to the heir context.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Context_switch(
-  Context_Control  *run,
-  Context_Control  *heir
-);
-
-/*
- *  _CPU_Context_restore
- *
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in _CPU_Context_switch.
- *
- *  NOTE: May be unnecessary to reload some registers.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Context_restore(
-  Context_Control *new_context
-) RTEMS_NO_RETURN;
-
-/*
- *  _CPU_Context_save_fp
- *
- *  This routine saves the floating point context passed to it.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Context_save_fp(
-  Context_Control_fp **fp_context_ptr
-);
-
-/*
- *  _CPU_Context_restore_fp
- *
- *  This routine restores the floating point context passed to it.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Context_restore_fp(
-  Context_Control_fp **fp_context_ptr
-);
-
-static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
-{
-  /* TODO */
-}
-
-static inline void _CPU_Context_validate( uintptr_t pattern )
-{
-  while (1) {
-    /* TODO */
-  }
-}
-
-/* FIXME */
-typedef CPU_Interrupt_frame CPU_Exception_frame;
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
-
-/*  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
- *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
- *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
- *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-static inline uint32_t CPU_swap_u32(
-  uint32_t value
-)
-{
-  uint32_t   byte1, byte2, byte3, byte4, swapped;
-
-  byte4 = (value >> 24) & 0xff;
-  byte3 = (value >> 16) & 0xff;
-  byte2 = (value >> 8)  & 0xff;
-  byte1 =  value        & 0xff;
-
-  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
-  return( swapped );
-}
-
-#define CPU_swap_u16( value ) \
-  (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-typedef uint32_t CPU_Counter_ticks;
-
-CPU_Counter_ticks _CPU_Counter_read( void );
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
-  CPU_Counter_ticks second,
-  CPU_Counter_ticks first
-)
-{
-  return second - first;
-}
-
-#endif /* ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h b/cpukit/score/cpu/avr/rtems/score/cpu_asm.h
deleted file mode 100644
index af920d143e..0000000000
--- a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * @file
- *
- * @brief Intel AVR Assembly File
- *
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_CPU_ASM_H
-#define _RTEMS_SCORE_CPU_ASM_H
-
-/* pull in the generated offsets */
-
-#include <rtems/score/offsets.h>
-
-/*
- * Hardware General Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Floating Point Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Control Registers
- */
-
-/* put something here */
-
-/*
- * Calling Convention
- */
-
-/* put something here */
-
-/*
- * Temporary registers
- */
-
-/* put something here */
-
-/*
- * Floating Point Registers - SW Conventions
- */
-
-/* put something here */
-
-/*
- * Temporary floating point registers
- */
-
-/* put something here */
-
-#endif
-
-/* end of file */
diff --git a/cpukit/score/cpu/avr/rtems/score/cpuatomic.h b/cpukit/score/cpu/avr/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/avr/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/avr/rtems/score/types.h b/cpukit/score/cpu/avr/rtems/score/types.h
deleted file mode 100644
index f63f5d5a3b..0000000000
--- a/cpukit/score/cpu/avr/rtems/score/types.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
- * @file
- *
- * @brief Intel AVR CPU Type Definitions
- *
- * This include file contains type definitions pertaining to the Intel
- * avr processor family.
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_TYPES_H
-#define _RTEMS_SCORE_TYPES_H
-
-#include <rtems/score/basedefs.h>
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This section defines the basic types for this processor.
- */
-
-/** Type that can store a 32-bit integer or a pointer. */
-typedef unsigned long CPU_Uint32ptr;
-
-typedef uint16_t     Priority_bit_map_Word;
-typedef void avr_isr;
-typedef void ( *avr_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* !ASM */
-
-#endif
diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 4d8ac987a9..ec13a9a661 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -13,7 +13,6 @@ REPLACE2 = $(PERL) $(top_srcdir)/tools/word-replace2
 GENERATED_FILES =
 GENERATED_FILES += general.texi
 GENERATED_FILES += arm.texi
-GENERATED_FILES += avr.texi
 GENERATED_FILES += bfin.texi
 GENERATED_FILES += epiphany.texi
 GENERATED_FILES += i386.texi
@@ -51,11 +50,6 @@ arm.texi: arm.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
-avr.texi: avr.t
-	$(BMENU2) -p "" \
-	    -u "Top" \
-	    -n "" < $< > $@
-
 bfin.texi: bfin.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
diff --git a/doc/cpu_supplement/avr.t b/doc/cpu_supplement/avr.t
deleted file mode 100644
index 9ad4d2ef2c..0000000000
--- a/doc/cpu_supplement/avr.t
+++ /dev/null
@@ -1,133 +0,0 @@
-@c
-@c  COPYRIGHT (c) 1988-2009.
-@c  On-Line Applications Research Corporation (OAR).
-@c  All rights reserved.
-
-@ifinfo
-@end ifinfo
-@chapter Atmel AVR Specific Information
-
-This chapter discusses the AVR architecture dependencies in this
-port of RTEMS.
-
-@subheading Architecture Documents
-
-For information on the AVR architecture, refer to the following
-documents available from Atmel.
-
-TBD
-
-@itemize @bullet
-
-@item See other CPUs for documentation reference formatting examples.
-
-@end itemize
-
-
-@section CPU Model Dependent Features
-
-CPUs of the AVR 53X only differ in the peripherals and thus in the
-device drivers. This port does not yet support the 56X dual core variants.
-
-@subsection Count Leading Zeroes Instruction
-
-The AVR CPU has the XXX instruction which could be used to speed
-up the find first bit operation.  The use of this instruction should
-significantly speed up the scheduling associated with a thread blocking.
-
-@section Calling Conventions
-
-@subsection Processor Background
-
-The AVR architecture supports a simple call and return mechanism.
-A subroutine is invoked via the call (@code{call}) instruction.
-This instruction saves the return address in the @code{RETS} register
-and transfers the execution to the given address.
-
-It is the called funcions responsability to use the link instruction
-to reserve space on the stack for the local variables.  Returning from
-a subroutine is done by using the RTS (@code{RTS}) instruction which
-loads the PC with the adress stored in RETS.
-
-It is is important to note that the @code{call} instruction does not
-automatically save or restore any registers.  It is the responsibility
-of the high-level language compiler to define the register preservation
-and usage convention.
-
-@subsection Register Usage
-
-A called function may clobber all registers, except RETS, R4-R7, P3-P5,
-FP and SP.  It may also modify the first 12 bytes in the caller’s stack
-frame which is used as an argument area for the first three arguments
-(which are passed in R0...R3 but may be placed on the stack by the
-called function).
-
-@subsection Parameter Passing
-
-RTEMS assumes that the AVR GCC calling convention is followed.
-The first three parameters are stored in registers R0, R1, and R2.
-All other parameters are put pushed on the stack.  The result is returned
-through register R0.
-
-@section Memory Model
-
-The AVR family architecutre support a single unified 4 GB byte
-address space using 32-bit addresses. It maps all resources like internal
-and external memory and IO registers into separate sections of this
-common address space.
-
-The AVR architcture supports some form of memory
-protection via its Memory Management Unit. Since the
-AVR port runs in supervisior mode this memory
-protection mechanisms are not used.
-
-@section Interrupt Processing
-
-Discussed in this chapter are the AVR's interrupt response and
-control mechanisms as they pertain to RTEMS.
-
-@subsection Vectoring of an Interrupt Handler
-
-TBD
-
-@subsection Disabling of Interrupts by RTEMS
-
-During interrupt disable critical sections, RTEMS disables interrupts to
-level N (N) before the execution of this section and restores them
-to the previous level upon completion of the section. RTEMS uses the
-instructions CLI and STI to enable and disable Interrupts. Emulation,
-Reset, NMI and Exception Interrupts are never disabled.
-
-@subsection Interrupt Stack
-
-The AVR Architecture works with two different kind of stacks,
-User and Supervisor Stack. Since RTEMS and its Application run
-in supervisor mode, all interrupts will use the interrupted
-tasks stack for execution.
-
-@section Default Fatal Error Processing
-
-The default fatal error handler for the AVR performs the following
-actions:
-
-@itemize @bullet
-@item disables processor interrupts,
-@item places the error code in @b{r0}, and
-@item executes an infinite loop (@code{while(0);} to
-simulate a halt processor instruction.
-@end itemize
-
-@section Symmetric Multiprocessing
-
-SMP is not supported.
-
-@section Thread-Local Storage
-
-Thread-local storage is not supported due to a broken tool chain.
-
-@section Board Support Packages
-
-
-@subsection System Reset
-
-TBD
diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
index 52c1a6f0dc..f1c6bd3d15 100644
--- a/doc/cpu_supplement/cpu_supplement.texi
+++ b/doc/cpu_supplement/cpu_supplement.texi
@@ -63,7 +63,6 @@
 * Preface::
 * Port Specific Information::
 * ARM Specific Information::
-* Atmel AVR Specific Information::
 * Blackfin Specific Information::
 * Epiphany Specific Information::
 * Intel/AMD x86 Specific Information::
@@ -86,7 +85,6 @@
 @include preface.texi
 @include general.texi
 @include arm.texi
-@include avr.texi
 @include bfin.texi
 @include epiphany.texi
 @include i386.texi
diff --git a/doc/user/preface.texi b/doc/user/preface.texi
index f8c0728aab..f4a794cbaf 100644
--- a/doc/user/preface.texi
+++ b/doc/user/preface.texi
@@ -148,7 +148,6 @@ It has been ported to the following processor families:
 @itemize @bullet
 @item Altera NIOS II
 @item Analog Devices Blackfin
-@item Atmel AVR
 @item ARM
 @item Freescale (formerly Motorola) MC68xxx 
 @item Freescale (formerly Motorola) MC683xx
diff --git a/testsuites/support/include/buffer_test_io.h b/testsuites/support/include/buffer_test_io.h
index 3cadc481f5..e5fbd2b0f3 100644
--- a/testsuites/support/include/buffer_test_io.h
+++ b/testsuites/support/include/buffer_test_io.h
@@ -17,9 +17,7 @@ extern "C" {
  */
 
 /* #define TESTS_BUFFER_OUTPUT */
-#if defined(__AVR__)
-#define TESTS_USE_PRINTK
-#endif
+/* #define TESTS_USE_PRINTK */
 
 /*
  *  USE PRINTK TO MINIMIZE SIZE