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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-23 16:15:50 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-30 11:16:28 +0200 |
| commit | bf30999cc697325eda3afd1833b78a7e64255fc4 (patch) | |
| tree | bc365daf0a3c0e6fe7c72cfe33c7603f7da54351 /testsuites/tmtests/tm27/task1.c | |
| parent | sapi: SMP support for chains (diff) | |
| download | rtems-bf30999cc697325eda3afd1833b78a7e64255fc4.tar.bz2 | |
smp: Add and use _Assert_Owner_of_giant()
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Diffstat (limited to 'testsuites/tmtests/tm27/task1.c')
| -rw-r--r-- | testsuites/tmtests/tm27/task1.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuites/tmtests/tm27/task1.c b/testsuites/tmtests/tm27/task1.c index fac889c1f3..7b6726d119 100644 --- a/testsuites/tmtests/tm27/task1.c +++ b/testsuites/tmtests/tm27/task1.c @@ -184,7 +184,7 @@ rtems_task Task_1( _Thread_Dispatch_set_disable_level( 0 ); #if defined(RTEMS_SMP) - rtems_interrupt_disable(level); + _ISR_Disable_without_giant(level); #endif ready_queues = (Chain_Control *) _Scheduler.information; @@ -194,7 +194,7 @@ rtems_task Task_1( _Thread_Dispatch_necessary = 1; #if defined(RTEMS_SMP) - rtems_interrupt_enable(level); + _ISR_Enable_without_giant(level); #endif Interrupt_occurred = 0; |