diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /spec/build/cpukit/optboothartid.yml | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'spec/build/cpukit/optboothartid.yml')
| -rw-r--r-- | spec/build/cpukit/optboothartid.yml | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/spec/build/cpukit/optboothartid.yml b/spec/build/cpukit/optboothartid.yml new file mode 100644 index 0000000000..ede4e5ead8 --- /dev/null +++ b/spec/build/cpukit/optboothartid.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 0 +default-by-variant: +- value: 1 + variants: + - riscv/mpfs64.* +description: | + boot hartid (processor number) of risc-v cpu (default 0) +enabled-by: true +format: '{}' +links: [] +name: RISCV_BOOT_HARTID +type: build |