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| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /spec/build/cpukit/optarchbits.yml | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'spec/build/cpukit/optarchbits.yml')
| -rw-r--r-- | spec/build/cpukit/optarchbits.yml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml index f7b652cc60..0ec4a9fe7e 100644 --- a/spec/build/cpukit/optarchbits.yml +++ b/spec/build/cpukit/optarchbits.yml @@ -11,6 +11,7 @@ default-by-variant: - value: - '64' variants: + - riscv/mpfs64.* - riscv/noel64.* - riscv/rv64.* - value: |