diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /spec/build/bsps/riscv/riscv/abi.yml | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'spec/build/bsps/riscv/riscv/abi.yml')
| -rw-r--r-- | spec/build/bsps/riscv/riscv/abi.yml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml index e975b87c4c..3ef8b0681d 100644 --- a/spec/build/bsps/riscv/riscv/abi.yml +++ b/spec/build/bsps/riscv/riscv/abi.yml @@ -15,6 +15,12 @@ default-by-variant: - -mabi=lp64d - -mcmodel=medany variants: + - riscv/mpfs64imafdc +- value: + - -march=rv64imafdc + - -mabi=lp64d + - -mcmodel=medany + variants: - riscv/rv64imafdc_medany - value: - -march=rv64imafdc |