Renamed a lot and got as much as possible automatically generated.

1 files changed, 1 insertions, 68 deletions

diff --git a/doc/supplements/powerpc/cpumodel.t b/doc/supplements/powerpc/cpumodel.t
index a56cc1fd76..4b4acb4a78 100644
--- a/doc/supplements/powerpc/cpumodel.t
+++ b/doc/supplements/powerpc/cpumodel.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
-@end ifinfo
 @chapter CPU Model Dependent Features
-@ifinfo
-@menu
-* CPU Model Dependent Features Introduction::
-* CPU Model Dependent Features CPU Model Feature Flags::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features, CPU Model Dependent Features
-@end ifinfo
+
 @section Introduction
 
 Microprocessors are generally classified into
@@ -41,26 +29,7 @@ in significant ways, the high level of compatibility makes it
 possible to share the bulk of the CPU dependent executive code
 across the entire family.
 
-@ifinfo
-@node CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Introduction, CPU Model Dependent Features
-@end ifinfo
 @section CPU Model Feature Flags
-@ifinfo
-@menu
-* CPU Model Dependent Features CPU Model Name::
-* CPU Model Dependent Features Floating Point Unit::
-* CPU Model Dependent Features Alignment::
-* CPU Model Dependent Features Cache Alignment::
-* CPU Model Dependent Features Maximum Interrupts::
-* CPU Model Dependent Features Has Double Precision Floating Point::
-* CPU Model Dependent Features Critical Interrupts::
-* CPU Model Dependent Features Use Multiword Load/Store Instructions::
-* CPU Model Dependent Features Instruction Cache Size::
-* CPU Model Dependent Features Data Cache Size::
-* CPU Model Dependent Features Debug Model::
-* CPU Model Dependent Features Low Power Model::
-@end menu
-@end ifinfo
 
 Each processor family supported by RTEMS has a
 list of features which vary between CPU models
@@ -84,26 +53,17 @@ The set of CPU model feature macros are defined in the file
 c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
 model defined on the compilation command line.
 
-@ifinfo
-@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection CPU Model Name
 
 The macro CPU_MODEL_NAME is a string which designates
 the name of this CPU model.  For example, for the PowerPC 603e
 model, this macro is set to the string "PowerPC 603e".
 
-@ifinfo
-@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Floating Point Unit
 
 The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
 has a hardware floating point unit and 0 otherwise.
 
-@ifinfo
-@node CPU Model Dependent Features Alignment, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Alignment
 
 The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
@@ -111,9 +71,6 @@ requirement for data types on a byte boundary.  This value is used
 to derive the alignment restrictions for memory allocated from 
 regions and partitions.
 
-@ifinfo
-@node CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Cache Alignment
 
 The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is
@@ -125,17 +82,11 @@ In addition, the "shortcut" data structure used by the PowerPC implementation
 to ease access to data elements frequently accessed by RTEMS routines
 implemented in assembly language is aligned using this value.
 
-@ifinfo
-@node CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Maximum Interrupts
 
 The macro PPC_INTERRUPT_MAX is set to the number of exception sources
 supported by this PowerPC model.
 
-@ifinfo
-@node CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Has Double Precision Floating Point
 
 The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
@@ -143,17 +94,11 @@ has support for double precision floating point numbers.  This is
 important because the floating point registers need only be four bytes
 wide (not eight) if double precision is not supported.
 
-@ifinfo
-@node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Critical Interrupts
 
 The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
 has the Critical Interrupt capability as defined by the IBM 403 models.
 
-@ifinfo
-@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Use Multiword Load/Store Instructions
 
 The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
@@ -162,23 +107,14 @@ The relative efficiency of multiword load and store instructions versus
 an equivalent set of single word load and store instructions varies based
 upon the PowerPC model.
 
-@ifinfo
-@node CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Instruction Cache Size
 
 The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
 
-@ifinfo
-@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Debug Model, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Data Cache Size
 
 The macro PPC_D_CACHE is set to the size in bytes of the data cache.
 
-@ifinfo
-@node CPU Model Dependent Features Debug Model, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Debug Model
 
 The macro PPC_DEBUG_MODEL is set to indicate the debug support features 
@@ -202,9 +138,6 @@ has only been seen in the IBM 4xx series.
 
 @end table
 
-@ifinfo
-@node CPU Model Dependent Features Low Power Model, Calling Conventions, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Low Power Model
 
 The macro PPC_LOW_POWER_MODE is set to indicate the low power model