Renamed a lot and got as much as possible automatically generated.

11 files changed, 91 insertions, 349 deletions

diff --git a/doc/supplements/powerpc/Makefile b/doc/supplements/powerpc/Makefile
index 4aecbd4623..0b8dc01a90 100644
--- a/doc/supplements/powerpc/Makefile
+++ b/doc/supplements/powerpc/Makefile
@@ -20,13 +20,12 @@ dirs:
 
 COMMON_FILES=../../common/cpright.texi ../../common/setup.texi
 
-GENERATED_FILES= \
-  timing.texi wksheets.texi
+GENERATED_FILES=\
+  cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \
+  bsp.texi cputable.texi timing.texi wksheets.texi timePSIM.texi timeDMV177.texi
 
 FILES= $(PROJECT).texi \
-  bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \
-  intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \
-  timedatadmv177.texi timetbldmv177.texi \
+  preface.texi \
   $(GENERATED_FILES)
 
 INFOFILES=$(wildcard $(PROJECT) $(PROJECT)-*)
@@ -47,23 +46,51 @@ $(PROJECT).ps: $(PROJECT).dvi
 $(PROJECT).dvi: $(FILES)
 	$(TEXI2DVI) $(PROJECT).texi
 
-replace: timedata.texi
-
 #
 #  Chapters which get automatic processing
 #
 
-# CPU Model
-# Calling Conventions
-# Memory Model
+cpumodel.texi: cpumodel.t Makefile
+	$(BMENU) -p "Preface" \
+	    -u "Top" \
+	    -n "Calling Conventions" ${*}.t
+
+callconv.texi: callconv.t Makefile
+	$(BMENU) -p "CPU Model Dependent Features Low Power Model" \
+	    -u "Top" \
+	    -n "Memory Model" ${*}.t
+
+memmodel.texi: memmodel.t Makefile
+	$(BMENU) -p "Calling Conventions User-Provided Routines" \
+	    -u "Top" \
+	    -n "Interrupt Processing" ${*}.t
+
+# Interrupt Chapter:
+#  1.  Replace Times and Sizes
+#  2.  Build Node Structure
+intr.t: intr_NOTIMES.t PSIM_TIMES
+	${REPLACE} -p PSIM_TIMES intr_NOTIMES.t
+	mv intr_NOTIMES.t.fixed intr.t
+
+intr.texi: intr.t Makefile
+	$(BMENU) -p "Memory Model Flat Memory Model" \
+	    -u "Top" \
+	    -n "Default Fatal Error Processing" ${*}.t
 
-intr.texi: intr.t PSIM_TIMES
-	${REPLACE} -p PSIM_TIMES intr.t
-	mv intr.t.fixed intr.texi
+fatalerr.texi: fatalerr.t Makefile
+	$(BMENU) -p "Interrupt Processing Interrupt Stack" \
+	    -u "Top" \
+	    -n "Board Support Packages" ${*}.t
 
-# Fatal Error
-# BSP
-# CPU Table
+bsp.texi: bsp.t Makefile
+	$(BMENU) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \
+	    -u "Top" \
+	    -n "Processor Dependent Information Table" ${*}.t
+
+cputable.texi: cputable.t Makefile
+	$(BMENU) -p "Board Support Packages Processor Initialization" \
+	    -u "Top" \
+	    -n "Memory Requirements" ${*}.t
 
 # Worksheets Chapter:
 #  1.  Obtain the Shared File
@@ -94,29 +121,45 @@ timing.texi: timing.t Makefile
             -u "Top" \
             -n "PSIM Timing Data" ${*}.t
 
-timetbl.t: ../../common/timetbl.t
-	sed -e 's/TIMETABLE_NEXT_LINK/DMV177 Timing Data/' \
-            <../../common/timetbl.t >timetbl.t
-
-timetbldmv177.t: ../../common/timetbl.t
-	sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
-            <../../common/timetbl.t >timetbldmv177.t
-
-timetbl.texi: timetbl.t PSIM_TIMES
-	${REPLACE} -p PSIM_TIMES timetbl.t
-	mv timetbl.t.fixed timetbl.texi
+# Timing Data for PSIM BSP Chapter:
+#  1.  Copy the Shared File
+#  2.  Replace Times and Sizes
+#  3.  Build Node Structure
 
-timedata.texi: timedata.t PSIM_TIMES
-	${REPLACE} -p PSIM_TIMES timedata.t
-	mv timedata.t.fixed timedata.texi
+timePSIM_.t: ../../common/timetbl.t timePSIM.t
+	cat timePSIM.t ../../common/timetbl.t             >timePSIM_.t
+	@echo                                               >>timePSIM_.t
+	@echo "@tex"                                        >>timePSIM_.t
+	@echo "\\global\\advance \\smallskipamount by 4pt"  >>timePSIM_.t
+	@echo "@end tex"                                    >>timePSIM_.t
+	${REPLACE} -p PSIM_TIMES timePSIM_.t
+	mv timePSIM_.t.fixed timePSIM_.t
+
+timePSIM.texi: timePSIM_.t Makefile
+	$(BMENU) -p "Timing Specification Terminology" \
+	    -u "Top" \
+	    -n "DMV177 Timing Data" timePSIM_.t
+	mv timePSIM_.texi timePSIM.texi
 
-timetbldmv177.texi: timetbldmv177.t DMV177_TIMES
-	${REPLACE} -p DMV177_TIMES timetbldmv177.t
-	mv timetbldmv177.t.fixed timetbldmv177.texi
+# Timing Data for DMV177 BSP Chapter:
+#  1.  Copy the Shared File
+#  2.  Replace Times and Sizes
+#  3.  Build Node Structure
 
-timedatadmv177.texi: timedatadmv177.t DMV177_TIMES
-	${REPLACE} -p DMV177_TIMES timedatadmv177.t
-	mv timedatadmv177.t.fixed timedatadmv177.texi
+timeDMV177_.t: ../../common/timetbl.t timeDMV177.t
+	cat timeDMV177.t ../../common/timetbl.t             >timeDMV177_.t
+	@echo                                               >>timeDMV177_.t
+	@echo "@tex"                                        >>timeDMV177_.t
+	@echo "\\global\\advance \\smallskipamount by 4pt"  >>timeDMV177_.t
+	@echo "@end tex"                                    >>timeDMV177_.t
+	${REPLACE} -p DMV177_TIMES timeDMV177_.t
+	mv timeDMV177_.t.fixed timeDMV177_.t
+
+timeDMV177.texi: timeDMV177_.t Makefile
+	$(BMENU) -p "PSIM Timing Data Rate Monotonic Manager" \
+	    -u "Top" \
+	    -n "Command and Variable Index" timeDMV177_.t
+	mv timeDMV177_.texi timeDMV177.texi
 
 html: dirs $(FILES)
 	-mkdir -p $(WWW_INSTALL)/c_$(PROJECT)
@@ -128,8 +171,9 @@ clean:
 	rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE)
 	rm -f $(PROJECT) $(PROJECT)-*
 	rm -f c_$(PROJECT) c_$(PROJECT)-*
-	rm -f timedata.texi timetbl.texi intr.texi $(GENERATED_FILES)
-	rm -f timedatadmv177.texi timetbldmv177.texi
+	rm -f intr.t $(GENERATED_FILES)
 	rm -f timetbl.t wksheets.t wksheets_NOTIMES.t timing.t
+	rm -f timePSIM_.t timePSIM_.texi
+	rm -f timeDMV177_.t timeDMV177_.texi
 	rm -f *.fixed _*
 
diff --git a/doc/supplements/powerpc/bsp.t b/doc/supplements/powerpc/bsp.t
index 015f7347e0..2c9539be88 100644
--- a/doc/supplements/powerpc/bsp.t
+++ b/doc/supplements/powerpc/bsp.t
@@ -6,21 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
-@end ifinfo
 @chapter Board Support Packages
-@ifinfo
-@menu
-* Board Support Packages Introduction::
-* Board Support Packages System Reset::
-* Board Support Packages Processor Initialization::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
-@end ifinfo
+
 @section Introduction
 
 An RTEMS Board Support Package (BSP) must be designed
@@ -30,9 +17,6 @@ For more information on developing a BSP, refer to the chapter
 titled Board Support Packages in the RTEMS
 Applications User's Guide.
 
-@ifinfo
-@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
-@end ifinfo
 @section System Reset
 
 An RTEMS based application is initiated or
@@ -48,9 +32,6 @@ depending upon the setting of the Exception Prefix bit in the MSR.
 If during a soft reset, a Machine Check Exception occurs, then the
 CPU may execute a hard reset.
 
-@ifinfo
-@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
-@end ifinfo
 @section Processor Initialization
 
 It is the responsibility of the application's
diff --git a/doc/supplements/powerpc/callconv.t b/doc/supplements/powerpc/callconv.t
index 1bf2c8fc79..7fc4bfd60f 100644
--- a/doc/supplements/powerpc/callconv.t
+++ b/doc/supplements/powerpc/callconv.t
@@ -6,25 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Low Power Model, Top
-@end ifinfo
 @chapter Calling Conventions
-@ifinfo
-@menu
-* Calling Conventions Introduction::
-* Calling Conventions Programming Model::
-* Calling Conventions Call and Return Mechanism::
-* Calling Conventions Calling Mechanism::
-* Calling Conventions Register Usage::
-* Calling Conventions Parameter Passing::
-* Calling Conventions User-Provided Routines::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Calling Conventions Introduction, Calling Conventions Programming Model, Calling Conventions, Calling Conventions
-@end ifinfo
+
 @section Introduction
 
 Each high-level language compiler generates
@@ -51,24 +34,11 @@ RTEMS supports the Embedded Application Binary Interface (EABI)
 calling convention.  Documentation for EABI is available by sending
 a message with a subject line of "EABI" to eabi@@goth.sis.mot.com.
 
-@ifinfo
-@node Calling Conventions Programming Model, Calling Conventions Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions
-@end ifinfo
 @section Programming Model
-@ifinfo
-@menu
-* Calling Conventions Non-Floating Point Registers::
-* Calling Conventions Floating Point Registers::
-* Calling Conventions Special Registers::
-@end menu
-@end ifinfo
 
 This section discusses the programming model for the
 PowerPC architecture.
 
-@ifinfo
-@node Calling Conventions Non-Floating Point Registers, Calling Conventions Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model
-@end ifinfo
 @subsection Non-Floating Point Registers
 
 The PowerPC architecture defines thirty-two non-floating point registers
@@ -149,9 +119,6 @@ The following table describes the role of each of these registers:
 @end ifset
 
 
-@ifinfo
-@node Calling Conventions Floating Point Registers, Calling Conventions Special Registers, Calling Conventions Non-Floating Point Registers, Calling Conventions Programming Model
-@end ifinfo
 @subsection Floating Point Registers
 
 The PowerPC architecture includes thirty-two, sixty-four bit
@@ -164,9 +131,6 @@ and the type of result generated by floating-point operations.
 Additionally, it controls the rounding mode of operations and allows the
 reporting of floating exceptions to be enabled or disabled.
 
-@ifinfo
-@node Calling Conventions Special Registers, Calling Conventions Call and Return Mechanism, Calling Conventions Floating Point Registers, Calling Conventions Programming Model
-@end ifinfo
 @subsection Special Registers
 
 The PowerPC architecture includes a number of special registers
@@ -195,9 +159,6 @@ for indirect function calls and jumps.
 
 @end table
 
-@ifinfo
-@node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Special Registers, Calling Conventions
-@end ifinfo
 @section Call and Return Mechanism
 
 The PowerPC architecture supports a simple yet effective call
@@ -225,18 +186,12 @@ The LR may be accessed as special purpose register 8 (@code{SPR8}) using the
 "move from special register" (@code{mfspr}) and
 "move to special register" (@code{mtspr}) instructions.
 
-@ifinfo
-@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Call and Return Mechanism, Calling Conventions
-@end ifinfo
 @section Calling Mechanism
 
 All RTEMS directives are invoked using the regular
 PowerPC EABI calling convention via the @code{bl} or
 @code{bla} instructions.
 
-@ifinfo
-@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions
-@end ifinfo
 @section Register Usage
 
 As discussed above, the call instruction does not
@@ -246,9 +201,6 @@ across subroutine calls.  The callee is responsible for saving
 callee-preserved registers to the program stack and restoring them
 before returning to the caller.
 
-@ifinfo
-@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions
-@end ifinfo
 @section Parameter Passing
 
 RTEMS assumes that arguments are placed in the
@@ -268,9 +220,6 @@ load first argument into r3
 invoke directive
 @end example
 
-@ifinfo
-@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions
-@end ifinfo
 @section User-Provided Routines
 
 All user-provided routines invoked by RTEMS, such as
diff --git a/doc/supplements/powerpc/cpumodel.t b/doc/supplements/powerpc/cpumodel.t
index a56cc1fd76..4b4acb4a78 100644
--- a/doc/supplements/powerpc/cpumodel.t
+++ b/doc/supplements/powerpc/cpumodel.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
-@end ifinfo
 @chapter CPU Model Dependent Features
-@ifinfo
-@menu
-* CPU Model Dependent Features Introduction::
-* CPU Model Dependent Features CPU Model Feature Flags::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features, CPU Model Dependent Features
-@end ifinfo
+
 @section Introduction
 
 Microprocessors are generally classified into
@@ -41,26 +29,7 @@ in significant ways, the high level of compatibility makes it
 possible to share the bulk of the CPU dependent executive code
 across the entire family.
 
-@ifinfo
-@node CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Introduction, CPU Model Dependent Features
-@end ifinfo
 @section CPU Model Feature Flags
-@ifinfo
-@menu
-* CPU Model Dependent Features CPU Model Name::
-* CPU Model Dependent Features Floating Point Unit::
-* CPU Model Dependent Features Alignment::
-* CPU Model Dependent Features Cache Alignment::
-* CPU Model Dependent Features Maximum Interrupts::
-* CPU Model Dependent Features Has Double Precision Floating Point::
-* CPU Model Dependent Features Critical Interrupts::
-* CPU Model Dependent Features Use Multiword Load/Store Instructions::
-* CPU Model Dependent Features Instruction Cache Size::
-* CPU Model Dependent Features Data Cache Size::
-* CPU Model Dependent Features Debug Model::
-* CPU Model Dependent Features Low Power Model::
-@end menu
-@end ifinfo
 
 Each processor family supported by RTEMS has a
 list of features which vary between CPU models
@@ -84,26 +53,17 @@ The set of CPU model feature macros are defined in the file
 c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
 model defined on the compilation command line.
 
-@ifinfo
-@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection CPU Model Name
 
 The macro CPU_MODEL_NAME is a string which designates
 the name of this CPU model.  For example, for the PowerPC 603e
 model, this macro is set to the string "PowerPC 603e".
 
-@ifinfo
-@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Floating Point Unit
 
 The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
 has a hardware floating point unit and 0 otherwise.
 
-@ifinfo
-@node CPU Model Dependent Features Alignment, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Alignment
 
 The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
@@ -111,9 +71,6 @@ requirement for data types on a byte boundary.  This value is used
 to derive the alignment restrictions for memory allocated from 
 regions and partitions.
 
-@ifinfo
-@node CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Cache Alignment
 
 The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is
@@ -125,17 +82,11 @@ In addition, the "shortcut" data structure used by the PowerPC implementation
 to ease access to data elements frequently accessed by RTEMS routines
 implemented in assembly language is aligned using this value.
 
-@ifinfo
-@node CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Maximum Interrupts
 
 The macro PPC_INTERRUPT_MAX is set to the number of exception sources
 supported by this PowerPC model.
 
-@ifinfo
-@node CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Has Double Precision Floating Point
 
 The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
@@ -143,17 +94,11 @@ has support for double precision floating point numbers.  This is
 important because the floating point registers need only be four bytes
 wide (not eight) if double precision is not supported.
 
-@ifinfo
-@node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Critical Interrupts
 
 The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
 has the Critical Interrupt capability as defined by the IBM 403 models.
 
-@ifinfo
-@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Use Multiword Load/Store Instructions
 
 The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
@@ -162,23 +107,14 @@ The relative efficiency of multiword load and store instructions versus
 an equivalent set of single word load and store instructions varies based
 upon the PowerPC model.
 
-@ifinfo
-@node CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Instruction Cache Size
 
 The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
 
-@ifinfo
-@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Debug Model, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Data Cache Size
 
 The macro PPC_D_CACHE is set to the size in bytes of the data cache.
 
-@ifinfo
-@node CPU Model Dependent Features Debug Model, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Debug Model
 
 The macro PPC_DEBUG_MODEL is set to indicate the debug support features 
@@ -202,9 +138,6 @@ has only been seen in the IBM 4xx series.
 
 @end table
 
-@ifinfo
-@node CPU Model Dependent Features Low Power Model, Calling Conventions, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags
-@end ifinfo
 @subsection Low Power Model
 
 The macro PPC_LOW_POWER_MODE is set to indicate the low power model
diff --git a/doc/supplements/powerpc/cputable.t b/doc/supplements/powerpc/cputable.t
index e4c2efd0ff..35fabdb6f3 100644
--- a/doc/supplements/powerpc/cputable.t
+++ b/doc/supplements/powerpc/cputable.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top
-@end ifinfo
 @chapter Processor Dependent Information Table
-@ifinfo
-@menu
-* Processor Dependent Information Table Introduction::
-* Processor Dependent Information Table CPU Dependent Information Table::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table
-@end ifinfo
+
 @section Introduction
 
 Any highly processor dependent information required
@@ -28,9 +16,6 @@ Dependent Information Table.  This table is not required for all
 processors supported by RTEMS.  This chapter describes the
 contents, if any, for a particular processor type.
 
-@ifinfo
-@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table
-@end ifinfo
 @section CPU Dependent Information Table
 
 The PowerPC version of the RTEMS CPU Dependent
diff --git a/doc/supplements/powerpc/fatalerr.t b/doc/supplements/powerpc/fatalerr.t
index ab7281368c..df8ac491d0 100644
--- a/doc/supplements/powerpc/fatalerr.t
+++ b/doc/supplements/powerpc/fatalerr.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Interrupt Stack, Top
-@end ifinfo
 @chapter Default Fatal Error Processing
-@ifinfo
-@menu
-* Default Fatal Error Processing Introduction::
-* Default Fatal Error Processing Default Fatal Error Handler Operations::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing
-@end ifinfo
+
 @section Introduction
 
 Upon detection of a fatal error by either the
@@ -32,9 +20,6 @@ default fatal error handler is then invoked.  This chapter
 describes the precise operations of the default fatal error
 handler.
 
-@ifinfo
-@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing
-@end ifinfo
 @section Default Fatal Error Handler Operations
 
 The default fatal error handler which is invoked by
diff --git a/doc/supplements/powerpc/intr_NOTIMES.t b/doc/supplements/powerpc/intr_NOTIMES.t
index 67213010aa..7d5117e7d5 100644
--- a/doc/supplements/powerpc/intr_NOTIMES.t
+++ b/doc/supplements/powerpc/intr_NOTIMES.t
@@ -6,24 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
-@end ifinfo
 @chapter Interrupt Processing
-@ifinfo
-@menu
-* Interrupt Processing Introduction::
-* Interrupt Processing Synchronous Versus Asynchronous Exceptions::
-* Interrupt Processing Vectoring of Interrupt Handler::
-* Interrupt Processing Interrupt Levels::
-* Interrupt Processing Disabling of Interrupts by RTEMS::
-* Interrupt Processing Interrupt Stack::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing, Interrupt Processing
-@end ifinfo
+
 @section Introduction
 
 Different types of processors respond to the
@@ -46,9 +30,6 @@ interrupt and vector.  In the PowerPC architecture, these terms
 correspond to exception and exception handler, respectively.  The terms will
 be used interchangeably in this manual.
 
-@ifinfo
-@node Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing
-@end ifinfo
 @section Synchronous Versus Asynchronous Exceptions
 
 In the PowerPC architecture exceptions can be either precise or 
@@ -72,9 +53,6 @@ floating point enabled exception.  All other synchronous exceptions are
 precise.  The synchronization occuring during asynchronous precise 
 exceptions conforms to the requirements for context synchronization.
 
-@ifinfo
-@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Levels, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing
-@end ifinfo
 @section Vectoring of Interrupt Handler
 
 Upon determining that an exception can be taken the PowerPC automatically
@@ -124,9 +102,6 @@ A nested interrupt is processed similarly with the
 exception that the current stack need not be switched to the
 interrupt stack.
 
-@ifinfo
-@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
-@end ifinfo
 @section Interrupt Levels
 
 The PowerPC architecture supports only a single external
@@ -163,9 +138,6 @@ Setting bit 2 of the interrupt level enables External Interrupt execptions.
 
 All other bits in the RTEMS task interrupt level are ignored.
 
-@ifinfo
-@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing
-@end ifinfo
 @section Disabling of Interrupts by RTEMS
 
 During the execution of directive calls, critical
@@ -189,9 +161,6 @@ unpredictable results may occur due to the inability of RTEMS
 to protect its critical sections.  However, ISRs that make no
 system calls may safely execute as non-maskable interrupts.
 
-@ifinfo
-@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
-@end ifinfo
 @section Interrupt Stack
 
 The PowerPC architecture does not provide for a
diff --git a/doc/supplements/powerpc/memmodel.t b/doc/supplements/powerpc/memmodel.t
index 2865c75e98..a8bd0f66ab 100644
--- a/doc/supplements/powerpc/memmodel.t
+++ b/doc/supplements/powerpc/memmodel.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
-@end ifinfo
 @chapter Memory Model
-@ifinfo
-@menu
-* Memory Model Introduction::
-* Memory Model Flat Memory Model::
-@end menu
-@end ifinfo
 
-@ifinfo
-@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
-@end ifinfo
 @section Introduction
 
 A processor may support any combination of memory
@@ -31,9 +19,6 @@ memory of any kind.  The appropriate memory model for RTEMS
 provided by the targeted processor and related characteristics
 of that model are described in this chapter.
 
-@ifinfo
-@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
-@end ifinfo
 @section Flat Memory Model
 
 The PowerPC architecture supports a variety of memory models.
diff --git a/doc/supplements/powerpc/powerpc.texi b/doc/supplements/powerpc/powerpc.texi
index 5d07269b62..48dfc7da12 100644
--- a/doc/supplements/powerpc/powerpc.texi
+++ b/doc/supplements/powerpc/powerpc.texi
@@ -72,8 +72,8 @@ END-INFO-DIR-ENTRY
 @include cputable.texi
 @include wksheets.texi
 @include timing.texi
-@include timedata.texi
-@include timedatadmv177.texi
+@include timePSIM.texi
+@include timeDMV177.texi
 @ifinfo
 @node Top, Preface, (dir), (dir)
 @top c_powerpc
diff --git a/doc/supplements/powerpc/timeDMV177.t b/doc/supplements/powerpc/timeDMV177.t
index b811a210d0..1117b03f6e 100644
--- a/doc/supplements/powerpc/timeDMV177.t
+++ b/doc/supplements/powerpc/timeDMV177.t
@@ -13,36 +13,8 @@
 \global\advance \smallskipamount by -4pt
 @end tex
 
-@ifinfo
-@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, PSIM Timing Data Rate Monotonic Manager, Top
-@end ifinfo
 @chapter RTEMS_BSP Timing Data
-@ifinfo
-@menu
-* RTEMS_BSP Timing Data Introduction::
-* RTEMS_BSP Timing Data Hardware Platform::
-* RTEMS_BSP Timing Data Interrupt Latency::
-* RTEMS_BSP Timing Data Context Switch::
-* RTEMS_BSP Timing Data Directive Times::
-* RTEMS_BSP Timing Data Task Manager::
-* RTEMS_BSP Timing Data Interrupt Manager::
-* RTEMS_BSP Timing Data Clock Manager::
-* RTEMS_BSP Timing Data Timer Manager::
-* RTEMS_BSP Timing Data Semaphore Manager::
-* RTEMS_BSP Timing Data Message Manager::
-* RTEMS_BSP Timing Data Event Manager::
-* RTEMS_BSP Timing Data Signal Manager::
-* RTEMS_BSP Timing Data Partition Manager::
-* RTEMS_BSP Timing Data Region Manager::
-* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
-* RTEMS_BSP Timing Data I/O Manager::
-* RTEMS_BSP Timing Data Rate Monotonic Manager::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
-@end ifinfo
+
 @section Introduction
 
 The timing data for RTEMS on the DY-4 RTEMS_BSP board
@@ -54,9 +26,6 @@ provided.  Also, provided is a description of the interrupt
 latency and the context switch times as they pertain to the
 PowerPC version of RTEMS.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
-@end ifinfo
 @section Hardware Platform
 
 All times reported in this chapter were measured using a RTEMS_BSP board.
@@ -90,9 +59,6 @@ All sources of hardware interrupts were disabled,
 although traps were enabled and the interrupt level of the
 PowerPC allows all interrupts.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
-@end ifinfo
 @section Interrupt Latency
 
 The maximum period with traps disabled or the
@@ -120,9 +86,6 @@ generated on the PSIM benchmark platform using the PowerPC's
 decrementer register.  This register was programmed to generate
 an interrupt after one countdown.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
-@end ifinfo
 @section Context Switch
 
 The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
@@ -148,10 +111,3 @@ the numeric coprocessor.
 The following table summarizes the context switch
 times for the RTEMS_BSP benchmark platform:
 
-@include timetbldmv177.texi
-
-@tex
-\global\advance \smallskipamount by 4pt
-@end tex
-
-
diff --git a/doc/supplements/powerpc/timePSIM.t b/doc/supplements/powerpc/timePSIM.t
index f5ea26e7fc..520cb6df64 100644
--- a/doc/supplements/powerpc/timePSIM.t
+++ b/doc/supplements/powerpc/timePSIM.t
@@ -13,36 +13,8 @@
 \global\advance \smallskipamount by -4pt
 @end tex
 
-@ifinfo
-@node RTEMS_BSP Timing Data, RTEMS_BSP Timing Data Introduction, Timing Specification Terminology, Top
-@end ifinfo
 @chapter RTEMS_BSP Timing Data
-@ifinfo
-@menu
-* RTEMS_BSP Timing Data Introduction::
-* RTEMS_BSP Timing Data Hardware Platform::
-* RTEMS_BSP Timing Data Interrupt Latency::
-* RTEMS_BSP Timing Data Context Switch::
-* RTEMS_BSP Timing Data Directive Times::
-* RTEMS_BSP Timing Data Task Manager::
-* RTEMS_BSP Timing Data Interrupt Manager::
-* RTEMS_BSP Timing Data Clock Manager::
-* RTEMS_BSP Timing Data Timer Manager::
-* RTEMS_BSP Timing Data Semaphore Manager::
-* RTEMS_BSP Timing Data Message Manager::
-* RTEMS_BSP Timing Data Event Manager::
-* RTEMS_BSP Timing Data Signal Manager::
-* RTEMS_BSP Timing Data Partition Manager::
-* RTEMS_BSP Timing Data Region Manager::
-* RTEMS_BSP Timing Data Dual-Ported Memory Manager::
-* RTEMS_BSP Timing Data I/O Manager::
-* RTEMS_BSP Timing Data Rate Monotonic Manager::
-@end menu
-@end ifinfo
 
-@ifinfo
-@node RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data, RTEMS_BSP Timing Data
-@end ifinfo
 @section Introduction
 
 The timing data for RTEMS on the RTEMS_BSP target 
@@ -54,9 +26,6 @@ provided.  Also, provided is a description of the interrupt
 latency and the context switch times as they pertain to the
 PowerPC version of RTEMS.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Introduction, RTEMS_BSP Timing Data
-@end ifinfo
 @section Hardware Platform
 
 All times reported in this chapter were measured using the PowerPC
@@ -75,9 +44,6 @@ executed.  All sources of hardware interrupts were disabled,
 although traps were enabled and the interrupt level of the
 PowerPC allows all interrupts.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Hardware Platform, RTEMS_BSP Timing Data
-@end ifinfo
 @section Interrupt Latency
 
 The maximum period with traps disabled or the
@@ -105,9 +71,6 @@ generated on the RTEMS_BSP benchmark platform using the PowerPC's
 decrementer register.  This register was programmed to generate
 an interrupt after one countdown.
 
-@ifinfo
-@node RTEMS_BSP Timing Data Context Switch, RTEMS_BSP Timing Data Directive Times, RTEMS_BSP Timing Data Interrupt Latency, RTEMS_BSP Timing Data
-@end ifinfo
 @section Context Switch
 
 The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
@@ -132,11 +95,3 @@ the numeric coprocessor.
 
 The following table summarizes the context switch
 times for the RTEMS_BSP benchmark platform:
-
-@include timetbl.texi
-
-@tex
-\global\advance \smallskipamount by 4pt
-@end tex
-
-