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authorJoel Sherrill <joel.sherrill@OARcorp.com>2006-03-07 20:47:53 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2006-03-07 20:47:53 +0000
commitf0ad529d28688214568532c0d30eb13654db1462 (patch)
tree0b254b2a26f754f598edf2b441c2ebd7576666ea /cpukit/score/include/rtems/system.h
parentNew. (diff)
downloadrtems-f0ad529d28688214568532c0d30eb13654db1462.tar.bz2
2006-03-07 Joel Sherrill <joel@OARcorp.com>
PR 866/rtems * score/include/rtems/system.h, score/include/rtems/score/isr.h, score/inline/rtems/score/thread.inl, score/macros/rtems/score/thread.inl: Added memory barriers to enter and exit of dispatching and interrupt critical sections so GCC will not optimize and reorder code out of a critical section.
Diffstat (limited to 'cpukit/score/include/rtems/system.h')
-rw-r--r--cpukit/score/include/rtems/system.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/cpukit/score/include/rtems/system.h b/cpukit/score/include/rtems/system.h
index 59d5b293af..9558155daf 100644
--- a/cpukit/score/include/rtems/system.h
+++ b/cpukit/score/include/rtems/system.h
@@ -135,6 +135,17 @@ extern "C" {
# define RTEMS_INLINE_ROUTINE
#endif
+/**
+ * The following macro is a compiler specific way to ensure that memory
+ * writes are not reordered around certian points. This specifically can
+ * impact interrupt disable and thread dispatching critical sections.
+ */
+#ifdef __GNUC__
+ #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory")
+#else
+ #define RTEMS_COMPILER_MEMORY_BARRIER()
+#endif
+
#ifdef RTEMS_POSIX_API
/** The following is used by the POSIX implementation to catch bad paths. */
int POSIX_MP_NOT_IMPLEMENTED( void );