diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-03-07 20:47:53 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-03-07 20:47:53 +0000 |
| commit | f0ad529d28688214568532c0d30eb13654db1462 (patch) | |
| tree | 0b254b2a26f754f598edf2b441c2ebd7576666ea /cpukit/score/include | |
| parent | New. (diff) | |
| download | rtems-f0ad529d28688214568532c0d30eb13654db1462.tar.bz2 | |
2006-03-07 Joel Sherrill <joel@OARcorp.com>
PR 866/rtems
* score/include/rtems/system.h, score/include/rtems/score/isr.h,
score/inline/rtems/score/thread.inl,
score/macros/rtems/score/thread.inl: Added memory barriers to enter
and exit of dispatching and interrupt critical sections so GCC will
not optimize and reorder code out of a critical section.
Diffstat (limited to 'cpukit/score/include')
| -rw-r--r-- | cpukit/score/include/rtems/score/isr.h | 16 | ||||
| -rw-r--r-- | cpukit/score/include/rtems/system.h | 11 |
2 files changed, 24 insertions, 3 deletions
diff --git a/cpukit/score/include/rtems/score/isr.h b/cpukit/score/include/rtems/score/isr.h index 320332dfd7..1359e91fd8 100644 --- a/cpukit/score/include/rtems/score/isr.h +++ b/cpukit/score/include/rtems/score/isr.h @@ -104,7 +104,10 @@ void _ISR_Handler_initialization ( void ); * the argument _level will contain the previous interrupt mask level. */ #define _ISR_Disable( _level ) \ - _CPU_ISR_Disable( _level ) + do { \ + _CPU_ISR_Disable( _level ); \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + } while (0) /** * This routine enables interrupts to the previous interrupt mask @@ -112,7 +115,10 @@ void _ISR_Handler_initialization ( void ); * enable interrupts so they can be processed again. */ #define _ISR_Enable( _level ) \ - _CPU_ISR_Enable( _level ) + do { \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + _CPU_ISR_Enable( _level ); \ + } while (0) /** * This routine temporarily enables interrupts to the previous @@ -127,7 +133,11 @@ void _ISR_Handler_initialization ( void ); * properly protects itself. */ #define _ISR_Flash( _level ) \ - _CPU_ISR_Flash( _level ) + do { \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + _CPU_ISR_Flash( _level ); \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + } while (0) /** * This routine installs new_handler as the interrupt service routine diff --git a/cpukit/score/include/rtems/system.h b/cpukit/score/include/rtems/system.h index 59d5b293af..9558155daf 100644 --- a/cpukit/score/include/rtems/system.h +++ b/cpukit/score/include/rtems/system.h @@ -135,6 +135,17 @@ extern "C" { # define RTEMS_INLINE_ROUTINE #endif +/** + * The following macro is a compiler specific way to ensure that memory + * writes are not reordered around certian points. This specifically can + * impact interrupt disable and thread dispatching critical sections. + */ +#ifdef __GNUC__ + #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory") +#else + #define RTEMS_COMPILER_MEMORY_BARRIER() +#endif + #ifdef RTEMS_POSIX_API /** The following is used by the POSIX implementation to catch bad paths. */ int POSIX_MP_NOT_IMPLEMENTED( void ); |