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| author | Daniel Cederman <cederman@gaisler.com> | 2014-07-03 11:18:55 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-08-22 13:10:59 +0200 |
| commit | 54f3476e2493a957efb0e30c77226d496e7fc5a1 (patch) | |
| tree | fb80dacd4bc89121ccc648f905d0e88fde1bafc3 /cpukit/score/cpu/sparc/cpu.c | |
| parent | score: Rename SMP broadcast message function (diff) | |
| download | rtems-54f3476e2493a957efb0e30c77226d496e7fc5a1.tar.bz2 | |
bsp/sparc: Flush icache before first time enabling interrupts
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
Diffstat (limited to 'cpukit/score/cpu/sparc/cpu.c')
0 files changed, 0 insertions, 0 deletions