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| author | Daniel Cederman <cederman@gaisler.com> | 2014-07-03 11:18:55 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-08-22 13:10:59 +0200 |
| commit | 54f3476e2493a957efb0e30c77226d496e7fc5a1 (patch) | |
| tree | fb80dacd4bc89121ccc648f905d0e88fde1bafc3 /cpukit | |
| parent | score: Rename SMP broadcast message function (diff) | |
| download | rtems-54f3476e2493a957efb0e30c77226d496e7fc5a1.tar.bz2 | |
bsp/sparc: Flush icache before first time enabling interrupts
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 39b78258c1..9c38b55e7d 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1203,6 +1203,10 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + void _BSP_Start_multitasking( Context_Control *heir ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + #define _CPU_Start_multitasking _BSP_Start_multitasking + static inline void _CPU_SMP_Processor_event_broadcast( void ) { __asm__ volatile ( "" : : : "memory" ); |