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| author | Andreas Dachsberger <andreas.dachsberger@embedded-brains.de> | 2019-03-27 10:38:56 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-04-02 07:29:30 +0200 |
| commit | 71f90982dc217815ab873698b1852640b9d66534 (patch) | |
| tree | 61acd34a5e703d5656d0bdd99a856a8dea3112c9 /cpukit/score/cpu/riscv/riscv-exception-handler.S | |
| parent | doxygen: score: Add powerpc CPU architecture group (diff) | |
| download | rtems-71f90982dc217815ab873698b1852640b9d66534.tar.bz2 | |
doxygen: score: Add RISC-V CPU architecture group
Update #3706.
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-exception-handler.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index ddb8f39d97..9330f246b1 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -1,7 +1,7 @@ /** * @file * - * @ingroup RTEMSScoreCPU + * @addtogroup RTEMSScoreCPURISCV * * @brief RISC-V exception support implementation. */ |