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| author | Andreas Dachsberger <andreas.dachsberger@embedded-brains.de> | 2019-03-27 10:38:56 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-04-02 07:29:30 +0200 |
| commit | 71f90982dc217815ab873698b1852640b9d66534 (patch) | |
| tree | 61acd34a5e703d5656d0bdd99a856a8dea3112c9 /cpukit/score/cpu | |
| parent | doxygen: score: Add powerpc CPU architecture group (diff) | |
| download | rtems-71f90982dc217815ab873698b1852640b9d66534.tar.bz2 | |
doxygen: score: Add RISC-V CPU architecture group
Update #3706.
Diffstat (limited to 'cpukit/score/cpu')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/asm.h | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 1 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
4 files changed, 26 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h index a2f483536f..4e09d16410 100644 --- a/cpukit/score/cpu/riscv/include/rtems/asm.h +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -59,6 +59,16 @@ #include <rtems/score/cpuopts.h> #include <rtems/score/riscv.h> +/** + * @defgroup RTEMSScoreCPURISCVASM RISC-V Assembler Support + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief RISC-V Assembler Support + * + * @{ + */ + /* * Recent versions of GNU cpp define variables which indicate the * need for underscores and percents. If not using GNU cpp or @@ -192,3 +202,5 @@ .endm #endif + +/** @} */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index bb866d8b02..e08307d372 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -1,5 +1,6 @@ /** * @file + * */ /* diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 5a256e8b75..c381cce110 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -34,6 +34,16 @@ #include <rtems/score/cpu.h> +/** + * @defgroup RTEMSScoreCPURISCV RISC-V + * + * @ingroup RTEMSScoreCPU + * + * @brief RISCV Architecture Support + * + * @{ + */ + #if defined(__riscv_atomic) && __riscv_xlen == 64 #define CPU_PER_CPU_CONTROL_SIZE 48 #elif defined(__riscv_atomic) && __riscv_xlen == 32 @@ -418,4 +428,6 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) #endif /* ASM */ +/** @} */ + #endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index ddb8f39d97..9330f246b1 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -1,7 +1,7 @@ /** * @file * - * @ingroup RTEMSScoreCPU + * @addtogroup RTEMSScoreCPURISCV * * @brief RISC-V exception support implementation. */ |