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| author | Hesham Almatary <heshamelmatary@gmail.com> | 2017-10-27 15:18:40 +1100 |
|---|---|---|
| committer | Hesham Almatary <heshamelmatary@gmail.com> | 2017-11-01 10:10:27 +1100 |
| commit | 11ff3a9e72ca261a6024b16c34c6fb35054fd53a (patch) | |
| tree | ffddc78ce5f3ceff414fa7551f49c7ccb5510672 /cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S | |
| parent | testsuite: Add bspIo for a local printk. (diff) | |
| download | rtems-11ff3a9e72ca261a6024b16c34c6fb35054fd53a.tar.bz2 | |
cpukit: RISC-V - make riscv32 code work for riscv64 - v2
* Use #ifdefs for 32/64 bit code
* Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
* Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
* Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv
Update #3109
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S new file mode 100644 index 0000000000..58ec25b9a5 --- /dev/null +++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> + +.section .text + +PUBLIC(_CPU_Context_volatile_clobber) +SYM(_CPU_Context_volatile_clobber): + + .macro clobber_register reg + addi t0, t0, -1 + mv \reg, t0 + .endm + + clobber_register a0 + clobber_register a1 + clobber_register a2 + clobber_register a3 + clobber_register a4 + clobber_register a5 + clobber_register a6 + + ret |