cpukit: RISC-V - make riscv32 code work for riscv64 - v2

* Use #ifdefs for 32/64 bit code
* Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
* Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
* Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

19 files changed, 69 insertions, 48 deletions

diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index 73c65401f6..4ddbdf0d05 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -14,7 +14,7 @@ DIST_SUBDIRS += nios2
 DIST_SUBDIRS += no_cpu
 DIST_SUBDIRS += or1k
 DIST_SUBDIRS += powerpc
-DIST_SUBDIRS += riscv32
+DIST_SUBDIRS += riscv
 DIST_SUBDIRS += sh
 DIST_SUBDIRS += sparc
 DIST_SUBDIRS += sparc64
diff --git a/cpukit/score/cpu/riscv32/Makefile.am b/cpukit/score/cpu/riscv/Makefile.am
index 1de5b2da42..1de5b2da42 100644
--- a/cpukit/score/cpu/riscv32/Makefile.am
+++ b/cpukit/score/cpu/riscv/Makefile.am
diff --git a/cpukit/score/cpu/riscv32/cpu.c b/cpukit/score/cpu/riscv/cpu.c
index 7061d10024..8d2926e715 100644
--- a/cpukit/score/cpu/riscv32/cpu.c
+++ b/cpukit/score/cpu/riscv/cpu.c
@@ -1,5 +1,5 @@
 /*
- * riscv32 CPU Dependent Source
+ * RISC-V CPU Dependent Source
  *
  * Copyright (c) 2015 University of York.
  * Hesham ALmatary <hesham@alumni.york.ac.uk>
@@ -59,12 +59,12 @@ void _CPU_Initialize(void)
   /* Do nothing */
 }
 
-void _CPU_ISR_Set_level(uint32_t level)
+void _CPU_ISR_Set_level(unsigned long level)
 {
   /* Do nothing */
 }
 
-uint32_t  _CPU_ISR_Get_level( void )
+unsigned long  _CPU_ISR_Get_level( void )
 {
   /* Do nothing */
   return 0;
@@ -80,7 +80,7 @@ void _CPU_ISR_install_raw_handler(
 }
 
 void _CPU_ISR_install_vector(
-  uint32_t    vector,
+  unsigned long    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
 )
diff --git a/cpukit/score/cpu/riscv32/preinstall.am b/cpukit/score/cpu/riscv/preinstall.am
index 14256ba876..14256ba876 100644
--- a/cpukit/score/cpu/riscv32/preinstall.am
+++ b/cpukit/score/cpu/riscv/preinstall.am
diff --git a/cpukit/score/cpu/riscv32/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index f4c3361d81..03fcc5c099 100644
--- a/cpukit/score/cpu/riscv32/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -42,7 +42,7 @@ void _CPU_Context_Initialize(
   Context_Control *context,
   void *stack_area_begin,
   size_t stack_area_size,
-  uint32_t new_level,
+  unsigned long new_level,
   void (*entry_point)( void ),
   bool is_fp,
   void *tls_area
diff --git a/cpukit/score/cpu/riscv32/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S
index acb7fbaec0..0b1a72c66f 100644
--- a/cpukit/score/cpu/riscv32/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -36,9 +36,6 @@
 .section .text, "ax"
 .align 4
 
-# define LREG lw
-# define SREG sw
-
 PUBLIC(_CPU_Context_switch)
 PUBLIC(_CPU_Context_restore)
 PUBLIC(_CPU_Context_restore_fp)
diff --git a/cpukit/score/cpu/riscv32/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S
index 8e9a5d33da..f9918e36f3 100644
--- a/cpukit/score/cpu/riscv32/riscv-context-validate.S
+++ b/cpukit/score/cpu/riscv/riscv-context-validate.S
@@ -32,12 +32,11 @@
 
 .section	.text
 
-#define SREG sw
-#define LREG lw
 
 PUBLIC(_CPU_Context_validate)
 SYM(_CPU_Context_validate):
-  addi sp, sp, -144
+  /* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
+  addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
 
   SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
   /* Skip x2/sp */
@@ -197,5 +196,5 @@ restore:
 
   LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
 
-  addi sp, sp, 144
+  addi sp, sp, 36 * CPU_SIZEOF_POINTER
   ret
diff --git a/cpukit/score/cpu/riscv32/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
index 58ec25b9a5..58ec25b9a5 100644
--- a/cpukit/score/cpu/riscv32/riscv-context-volatile-clobber.S
+++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
diff --git a/cpukit/score/cpu/riscv32/riscv-exception-default.c b/cpukit/score/cpu/riscv/riscv-exception-default.c
index 62d0dd3803..62d0dd3803 100644
--- a/cpukit/score/cpu/riscv32/riscv-exception-default.c
+++ b/cpukit/score/cpu/riscv/riscv-exception-default.c
diff --git a/cpukit/score/cpu/riscv32/riscv-exception-frame-print.c b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c
index 377616ceaa..853f8ccccb 100644
--- a/cpukit/score/cpu/riscv32/riscv-exception-frame-print.c
+++ b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c
@@ -36,6 +36,10 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
   int i;
 
   for ( i = 0; i < 32; ++i ) {
-    printk( "x%02i = 0x%016" PRIx32 "\n", i, frame->x[i]);
+#if __riscv_xlen == 32
+    printk( "x%02i = 0x%032" PRIx32 "\n", i, frame->x[i]);
+#else /* xlen == 64 */
+    printk( "x%02i = 0x%032" PRIx64 "\n", i, frame->x[i]);
+#endif
   }
 }
diff --git a/cpukit/score/cpu/riscv32/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S
index 69bab1fc6c..8aba339453 100644
--- a/cpukit/score/cpu/riscv32/riscv-exception-handler.S
+++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S
@@ -3,7 +3,7 @@
  *
  * @ingroup ScoreCPU
  *
- * @brief riscv32 exception support implementation.
+ * @brief RISC-V exception support implementation.
  */
 
 /*
@@ -41,9 +41,6 @@
 #include <rtems/asm.h>
 #include <rtems/score/percpu.h>
 
-# define LREG lw
-# define SREG sw
-
 EXTERN(bsp_start_vector_table_begin)
 EXTERN(_Thread_Dispatch)
 PUBLIC(ISR_Handler)
@@ -52,7 +49,7 @@ PUBLIC(ISR_Handler)
 .align 4
 TYPE_FUNC(ISR_Handler)
 SYM(ISR_Handler):
-  addi sp, sp, -144
+  addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
 
   SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
   /* Skip x2/sp */
@@ -103,15 +100,15 @@ SYM(ISR_Handler):
   /* Disable multitasking */
   la t1, THREAD_DISPATCH_DISABLE_LEVEL
 
-  LREG t2, (t0)
-  LREG t3, (t1)
+  lw t2, (t0)
+  lw t3, (t1)
   addi t2, t2, 1
   addi t3, t3, 1
-  SREG t2, (t0)
-  SREG t3, (t1)
+  sw t2, (t0)
+  sw t3, (t1)
 
   /* Save interrupted task stack pointer */
-  addi t4, sp, 144
+  addi t4, sp, 36 * CPU_SIZEOF_POINTER
   SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
 
   /* Keep sp (Exception frame address) in s1 */
@@ -126,7 +123,11 @@ SYM(ISR_Handler):
 
   /* calculate the offset */
   la   t5, bsp_start_vector_table_begin
+#if __riscv_xlen == 32
   slli t6, a0, 2
+#else /* xlen = 64 */
+  slli t6, a0, 3
+#endif
   add  t5, t5, t6
   LREG t5, (t5)
 
@@ -152,12 +153,12 @@ jump_to_c_handler:
   /* Enable multitasking */
   la t1, THREAD_DISPATCH_DISABLE_LEVEL
 
-  LREG t2, (t0)
-  LREG t3, (t1)
+  Lw t2, (t0)
+  lw t3, (t1)
   addi t2, t2, -1
   addi t3, t3, -1
-  SREG t2, (t0)
-  SREG t3, (t1)
+  sw t2, (t0)
+  sw t3, (t1)
 
   /* Check if _ISR_Nest_level > 0 */
   bgtz t2, exception_frame_restore
@@ -167,7 +168,7 @@ jump_to_c_handler:
 
   /* Check if dispatch needed */
   la   x31, DISPATCH_NEEDED
-  LREG x31, (x31)
+  lw x31, (x31)
   beqz x31, exception_frame_restore
 
   la x31, _Thread_Dispatch
@@ -215,6 +216,6 @@ jump_to_c_handler:
   LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
 
   /* Unwind exception frame */
-  addi sp, sp, 144
+  addi sp, sp, 36 * CPU_SIZEOF_POINTER
 
   mret
diff --git a/cpukit/score/cpu/riscv32/rtems/asm.h b/cpukit/score/cpu/riscv/rtems/asm.h
index 34b6474515..34b6474515 100644
--- a/cpukit/score/cpu/riscv32/rtems/asm.h
+++ b/cpukit/score/cpu/riscv/rtems/asm.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/cpu.h b/cpukit/score/cpu/riscv/rtems/score/cpu.h
index f77db55932..439b8c2fd4 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/rtems/score/cpu.h
@@ -66,7 +66,7 @@ extern "C" {
 #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
 #define CPU_BIG_ENDIAN                           FALSE
 #define CPU_LITTLE_ENDIAN                        TRUE
-#define CPU_MODES_INTERRUPT_MASK   0x00000001
+#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
 
 /*
  *  Processor defined structures required for cpukit/score.
@@ -75,13 +75,13 @@ extern "C" {
 #ifndef ASM
 
 typedef struct {
-  /* riscv32 has 32 32-bit general purpose registers (x0-x31). */
-  uint32_t  x[32];
+  /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
+  unsigned long x[32];
 
   /* Special purpose registers */
-  uint32_t  mstatus;
-  uint32_t  mcause;
-  uint32_t  mepc;
+  unsigned long mstatus;
+  unsigned long mcause;
+  unsigned long mepc;
 #ifdef RTEMS_SMP
   /**
    * @brief On SMP configurations the thread context must contain a boolean
@@ -138,7 +138,11 @@ typedef Context_Control CPU_Interrupt_frame;
 Context_Control_fp  _CPU_Null_fp_context;
 
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+#if __riscv_xlen == 32
 #define CPU_STACK_MINIMUM_SIZE  4096
+#else
+#define CPU_STACK_MINIMUM_SIZE  4096 * 2
+#endif
 #define CPU_ALIGNMENT 8
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
@@ -152,14 +156,14 @@ Context_Control_fp  _CPU_Null_fp_context;
  *
  */
 
-static inline uint32_t riscv_interrupt_disable( void )
+static inline unsigned long riscv_interrupt_disable( void )
 {
-  register uint32_t status = read_csr(mstatus);
+  register unsigned long status = read_csr(mstatus);
   clear_csr(mstatus, MSTATUS_MIE);
   return status;
 }
 
-static inline void riscv_interrupt_enable(uint32_t level)
+static inline void riscv_interrupt_enable(unsigned long level)
 {
   write_csr(mstatus, level);
 }
@@ -176,14 +180,14 @@ static inline void riscv_interrupt_enable(uint32_t level)
       riscv_interrupt_disable(); \
     } while(0)
 
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
 {
   return ( level & MSTATUS_MIE ) != 0;
 }
 
-void _CPU_ISR_Set_level( uint32_t level );
+void _CPU_ISR_Set_level( unsigned long level );
 
-uint32_t _CPU_ISR_Get_level( void );
+unsigned long _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
@@ -194,7 +198,7 @@ void _CPU_Context_Initialize(
   Context_Control *context,
   void *stack_area_begin,
   size_t stack_area_size,
-  uint32_t new_level,
+  unsigned long new_level,
   void (*entry_point)( void ),
   bool is_fp,
   void *tls_area
@@ -262,15 +266,31 @@ typedef struct {
 } CPU_Per_CPU_control;
 #endif /* ASM */
 
+#if __riscv_xlen == 32
 #define CPU_SIZEOF_POINTER 4
+
+/* 32-bit load/store instructions */
+#define LREG lw
+#define SREG sw
+
 #define CPU_EXCEPTION_FRAME_SIZE 128
+#else /* xlen = 64 */
+#define CPU_SIZEOF_POINTER 8
+
+/* 64-bit load/store instructions */
+#define LREG ld
+#define SREG sd
+
+#define CPU_EXCEPTION_FRAME_SIZE 256
+#endif
+
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
 #ifndef ASM
 typedef uint16_t Priority_bit_map_Word;
 
 typedef struct {
-  uint32_t x[32];;
+  unsigned long x[32];;
 } CPU_Exception_frame;
 
 /**
@@ -321,7 +341,7 @@ void _CPU_ISR_install_raw_handler(
  */
 
 void _CPU_ISR_install_vector(
-  uint32_t    vector,
+  unsigned long    vector,
   proc_ptr   new_handler,
   proc_ptr   *old_handler
 );
@@ -423,8 +443,8 @@ void _CPU_Context_restore_fp(
  *
  */
 
-static inline unsigned int CPU_swap_u32(
-  unsigned int value
+static inline uint32_t CPU_swap_u32(
+  uint32_t value
 )
 {
   uint32_t   byte1, byte2, byte3, byte4, swapped;
diff --git a/cpukit/score/cpu/riscv32/rtems/score/cpu_asm.h b/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h
index b5a56f3e22..b5a56f3e22 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/cpuatomic.h b/cpukit/score/cpu/riscv/rtems/score/cpuatomic.h
index 8ee9606b44..8ee9606b44 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/cpuatomic.h
+++ b/cpukit/score/cpu/riscv/rtems/score/cpuatomic.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/rtems/score/cpuimpl.h
index 3904c84bf9..3904c84bf9 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/rtems/score/cpuimpl.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/rtems/score/riscv-utility.h
index dc4836bee2..dc4836bee2 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
+++ b/cpukit/score/cpu/riscv/rtems/score/riscv-utility.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/riscv.h b/cpukit/score/cpu/riscv/rtems/score/riscv.h
index 6e7f1370c6..6e7f1370c6 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/riscv.h
+++ b/cpukit/score/cpu/riscv/rtems/score/riscv.h
diff --git a/cpukit/score/cpu/riscv32/rtems/score/types.h b/cpukit/score/cpu/riscv/rtems/score/types.h
index fe23b4ff76..d1440fb319 100644
--- a/cpukit/score/cpu/riscv32/rtems/score/types.h
+++ b/cpukit/score/cpu/riscv/rtems/score/types.h
@@ -1,7 +1,7 @@
 /**
  * @file
  *
- * @brief riscv32 Architecture Types API
+ * @brief RISC-V Architecture Types API
  */
 
 /*