From 9704d86f86c5a800a06dd814538df4cd83367fc5 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 26 Jun 2018 08:53:28 +0200 Subject: riscv: Enable interrupts during dispatch after ISR The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433. --- cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 ++ cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'cpukit/score/cpu/riscv/include') diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 30adbbca38..4d9f828086 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -3,6 +3,7 @@ */ /* + * Copyright (c) 2018 embedded brains GmbH * * Copyright (c) 2015 University of York. * Hesham Almatary @@ -75,6 +76,7 @@ typedef struct { unsigned long mstatus; unsigned long mcause; unsigned long mepc; + uint32_t isr_dispatch_disable; #ifdef RTEMS_SMP volatile bool is_executing; #endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 1370e656dd..6279c7c22e 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -38,10 +38,14 @@ #if __riscv_xlen == 32 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140 + #define CPU_INTERRUPT_FRAME_SIZE 144 #elif __riscv_xlen == 64 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280 + #define CPU_INTERRUPT_FRAME_SIZE 288 #endif /* __riscv_xlen */ -- cgit v1.2.3