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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-03 09:54:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-05 07:12:24 +0200 |
| commit | e755782bde234350c6263f893b1c4e8d30bb0a53 (patch) | |
| tree | 996842ed7493ec8423822b9a49ea58cd26d6dc03 /cpukit/score/cpu/riscv/include/rtems/score/cpu.h | |
| parent | posix: Check for new <pthread.h> prototypes (diff) | |
| download | rtems-e755782bde234350c6263f893b1c4e8d30bb0a53.tar.bz2 | |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 2220161c9e..e79ce25510 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -64,8 +64,6 @@ extern "C" { #define CPU_LITTLE_ENDIAN TRUE #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 -#define CPU_PER_CPU_CONTROL_SIZE 0 - #define CPU_CACHE_LINE_BYTES 64 #if __riscv_xlen == 32 @@ -224,10 +222,6 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; #define CPU_MAXIMUM_PROCESSORS 32 -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - typedef uint16_t Priority_bit_map_Word; typedef struct { |