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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-26 08:53:28 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:32 +0200 |
| commit | 9704d86f86c5a800a06dd814538df4cd83367fc5 (patch) | |
| tree | 9b69dc883eea50e0a5987e27590b4f4710a64c07 /cpukit/score/cpu/riscv/cpu.c | |
| parent | riscv: Add _CPU_Get_current_per_CPU_control() (diff) | |
| download | rtems-9704d86f86c5a800a06dd814538df4cd83367fc5.tar.bz2 | |
riscv: Enable interrupts during dispatch after ISR
The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).
Update #2751.
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index deae25d34f..c5d309a5d6 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -1,5 +1,5 @@ /* - * RISC-V CPU Dependent Source + * Copyright (c) 2018 embedded brains GmbH * * Copyright (c) 2015 University of York. * Hesham ALmatary <hesham@alumni.york.ac.uk> @@ -29,10 +29,18 @@ * SUCH DAMAGE. */ -#include <rtems/score/cpu.h> +#include <rtems/score/cpuimpl.h> #include <rtems/score/isr.h> #include <rtems/score/riscv-utility.h> +#define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \ + RTEMS_STATIC_ASSERT( \ + offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \ + riscv_context_offset_ ## field \ + ) + +RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE ); + /* bsp_start_vector_table_begin is the start address of the vector table * containing addresses to ISR Handlers. It's defined at the BSP linkcmds * and may differ from one BSP to another. |