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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 13:30:49 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:08 +0200 |
| commit | 7c3b0df10752cc4bdd1175f5b16fd0978763ff46 (patch) | |
| tree | b3fa7df13c2d4e8c89fc95859e25a91928243f58 /cpukit/score/cpu/riscv/cpu.c | |
| parent | bsp/riscv: Load global pointer (diff) | |
| download | rtems-7c3b0df10752cc4bdd1175f5b16fd0978763ff46.tar.bz2 | |
riscv: Implement ISR set/get level
Fix prototypes.
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index fbdb4c5238..7c14a8bffd 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -59,15 +59,13 @@ void _CPU_Initialize(void) /* Do nothing */ } -void _CPU_ISR_Set_level(unsigned long level) +uint32_t _CPU_ISR_Get_level( void ) { - /* Do nothing */ -} + if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) { + return 0; + } -unsigned long _CPU_ISR_Get_level( void ) -{ - /* Do nothing */ - return 0; + return 1; } void _CPU_ISR_install_raw_handler( |