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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-26 07:13:28 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:03:23 +0200 |
| commit | 3be4478f5a118bd55e0426c0d36f75b1db335ceb (patch) | |
| tree | f8a4c20af552abb66175e41dbef2c258dc9c3373 /cpukit/score/cpu/riscv/cpu.c | |
| parent | riscv: Optimize and fix interrupt disable/enable (diff) | |
| download | rtems-3be4478f5a118bd55e0426c0d36f75b1db335ceb.tar.bz2 | |
riscv: Avoid namespace pollution
Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 7c14a8bffd..deae25d34f 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -29,10 +29,9 @@ * SUCH DAMAGE. */ -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> #include <rtems/score/cpu.h> +#include <rtems/score/isr.h> +#include <rtems/score/riscv-utility.h> /* bsp_start_vector_table_begin is the start address of the vector table * containing addresses to ISR Handlers. It's defined at the BSP linkcmds |