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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-10-21 13:19:09 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-10-21 13:19:09 +0000 |
| commit | 2067679bb3bf52039c653f1c60386c40d77b492e (patch) | |
| tree | e7c07d87058d4132724c785f3ebe9b3bb25d039f /cpukit/score/cpu/powerpc/rtems/score/cpu.h | |
| parent | 2009-10-21 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
| download | rtems-2067679bb3bf52039c653f1c60386c40d77b492e.tar.bz2 | |
* rtems/powerpc/registers.h: Added defines DEAR_BOOKE and DEAR_405.
* rtems/score/cpu.h: Changed fpscr field to an integer type in
Context_Control_fp. Fixed warnings in PPC_Set_timebase_register().
Changed _CPU_Context_Initialize_fp() to initialize all fields and
avoid floating-point instructions.
* rtems/score/powerpc.h: Removed PPC_INIT_FPSCR define.
Diffstat (limited to 'cpukit/score/cpu/powerpc/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpu.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h index c1fbee965c..0d006c4a9d 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h @@ -17,8 +17,10 @@ #define _RTEMS_SCORE_CPU_H #include <rtems/score/powerpc.h> /* pick up machine definitions */ + #ifndef ASM -#include <rtems/score/types.h> + #include <string.h> /* for memset() */ + #include <rtems/score/types.h> #endif /* conditional compilation parameters */ @@ -224,6 +226,7 @@ */ #ifndef ASM + typedef struct { uint32_t gpr1; /* Stack pointer for all */ uint32_t gpr2; /* Reserved SVR4, section ptr EABI + */ @@ -263,15 +266,13 @@ typedef struct { */ #if (PPC_HAS_DOUBLE == 1) double f[32]; - double fpscr; + uint64_t fpscr; #else float f[32]; - float fpscr; + uint32_t fpscr; #endif } Context_Control_fp; -#endif /* ASM */ -#ifndef ASM typedef struct CPU_Interrupt_frame { uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ @@ -302,6 +303,7 @@ typedef struct CPU_Interrupt_frame { uint32_t msr; uint32_t pad[3]; } CPU_Interrupt_frame; + #endif /* ASM */ #include <rtems/new-exceptions/cpu.h> @@ -499,8 +501,8 @@ static inline void PPC_Set_timebase_register (uint64_t tbr) uint32_t tbr_low; uint32_t tbr_high; - tbr_low = (tbr & 0xffffffff) ; - tbr_high = (tbr >> 32) & 0xffffffff; + tbr_low = (uint32_t) tbr; + tbr_high = (uint32_t) (tbr >> 32); asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); @@ -578,9 +580,7 @@ void _CPU_Context_Initialize( */ #define _CPU_Context_Initialize_fp( _destination ) \ - { \ - (*(_destination))->fpscr = PPC_INIT_FPSCR; \ - } + memset( *(_destination), 0, sizeof( **(_destination) ) ) /* end of Context handler macros */ #endif /* ASM */ |