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author | Joel Sherrill <joel@rtems.org> | 2018-03-12 14:53:09 -0500 |
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committer | Joel Sherrill <joel@rtems.org> | 2018-03-13 09:55:23 -0500 |
commit | 0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f (patch) | |
tree | bdb81bd29cb7ad96d43897ac126eae39e49a45a2 /cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h | |
parent | Add ARM Paravirtualization support (diff) | |
download | rtems-0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f.tar.bz2 |
Add PowerPC paravirtualization support
Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.
Provide alternate methods to disable/enable interrupts
Closes #3306.
Diffstat (limited to 'cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h')
-rw-r--r-- | cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h index 4d9350324e..b63060d0a7 100644 --- a/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h +++ b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h @@ -672,6 +672,7 @@ extern "C" { * * A one bit means that this bit should be cleared. */ +#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE) extern char _PPC_INTERRUPT_DISABLE_MASK[]; static inline uint32_t ppc_interrupt_get_disable_mask( void ) @@ -734,6 +735,12 @@ static inline void ppc_interrupt_flash( uint32_t level ) : "r" (level) ); } +#else +uint32_t ppc_interrupt_get_disable_mask( void ); +uint32_t ppc_interrupt_disable( void ); +void ppc_interrupt_enable( uint32_t level ); +void ppc_interrupt_flash( uint32_t level ); +#endif /* PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE */ #define _CPU_ISR_Disable( _isr_cookie ) \ do { \ |