2006-08-09 Kolja Waschk <waschk@telos.de>

	* ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, preinstall.am,
	rtems/asm.h: New files.

1 files changed, 94 insertions, 0 deletions

diff --git a/cpukit/score/cpu/nios2/irq.c b/cpukit/score/cpu/nios2/irq.c
new file mode 100644
index 0000000000..ac9385010d
--- /dev/null
+++ b/cpukit/score/cpu/nios2/irq.c
@@ -0,0 +1,94 @@
+/*
+ *  NIOS2 exception and interrupt handler
+ *
+ *  Derived from c4x/irq.c
+ *
+ *  Copyright (c) 2006
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/thread.h>
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ *
+ *  Upon entry, interrupts are disabled
+ */
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr asm("sp");
+
+void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
+{
+  register uint32_t   level;
+
+  /* Interrupts are disabled upon entry to this Handler */
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 ) {
+    /* Install irq stack */
+    _old_stack_ptr = stack_ptr;
+    stack_ptr = _CPU_Interrupt_stack_high - 4;
+  }
+#endif
+
+  _ISR_Nest_level++;
+
+  _Thread_Dispatch_disable_level++;
+
+  if ( _ISR_Vector_table[ vector] )
+  {
+    (*_ISR_Vector_table[ vector ])(vector, ifr);
+  };
+
+  /* Make sure that interrupts are disabled again */
+  _CPU_ISR_Disable( level );
+
+  _Thread_Dispatch_disable_level--;
+
+  _ISR_Nest_level--;
+
+  if( _ISR_Nest_level == 0)
+  {
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+    stack_ptr = _old_stack_ptr;
+#endif
+
+    if( _Thread_Dispatch_disable_level == 0 )
+    {
+      if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
+      {
+        _ISR_Signals_to_thread_executing = FALSE;
+        _CPU_ISR_Enable( level );
+        _Thread_Dispatch();
+        /* may have switched to another task and not return here immed. */
+        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
+      }
+    }
+    else
+    {
+      _ISR_Signals_to_thread_executing = FALSE;
+    };
+  };
+
+  _CPU_ISR_Enable( level );
+}
+
+void __Exception_Handler(CPU_Exception_frame *efr)
+{
+  _CPU_Fatal_halt(0xECC0);
+}
+
+