2006-08-09 Kolja Waschk <waschk@telos.de>

	* ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, preinstall.am,
	rtems/asm.h: New files.

7 files changed, 853 insertions, 0 deletions

diff --git a/cpukit/score/cpu/nios2/ChangeLog b/cpukit/score/cpu/nios2/ChangeLog
new file mode 100644
index 0000000000..5b656d1cc9
--- /dev/null
+++ b/cpukit/score/cpu/nios2/ChangeLog
@@ -0,0 +1,9 @@
+2006-08-09	Kolja Waschk <waschk@telos.de>
+
+	* ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, preinstall.am,
+	rtems/asm.h: New files.
+
+2005-12-09  Kolja Waschk <rtemsdev@ixo.de>
+
+    Derived from no_cpu 
+
diff --git a/cpukit/score/cpu/nios2/Makefile.am b/cpukit/score/cpu/nios2/Makefile.am
new file mode 100644
index 0000000000..c1680f82fc
--- /dev/null
+++ b/cpukit/score/cpu/nios2/Makefile.am
@@ -0,0 +1,25 @@
+##
+## $Id$
+##
+
+include $(top_srcdir)/automake/compile.am
+
+CLEANFILES =
+DISTCLEANFILES =
+
+include_rtemsdir = $(includedir)/rtems
+include_rtems_HEADERS = rtems/asm.h
+
+include_rtems_scoredir = $(includedir)/rtems/score
+include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/nios2.h \
+    rtems/score/cpu_asm.h rtems/score/types.h
+
+noinst_LIBRARIES = libscorecpu.a
+libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S
+libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
+
+all-local: $(PREINSTALL_FILES)
+
+include $(srcdir)/preinstall.am
+
+include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/nios2/cpu.c b/cpukit/score/cpu/nios2/cpu.c
new file mode 100644
index 0000000000..f2f9863cf0
--- /dev/null
+++ b/cpukit/score/cpu/nios2/cpu.c
@@ -0,0 +1,197 @@
+/*
+ *  NIOS2 CPU Dependent Source
+ *
+ *  COPYRIGHT (c) 1989-2006
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+  /*
+   *  The thread_dispatch argument is the address of the entry point
+   *  for the routine called at the end of an ISR once it has been
+   *  decided a context switch is necessary.  On some compilation
+   *  systems it is difficult to call a high-level language routine
+   *  from assembly.  This allows us to trick these systems.
+   *
+   *  If you encounter this problem save the entry point in a CPU
+   *  dependent variable.
+   */
+
+  _CPU_Thread_dispatch_pointer = thread_dispatch;
+
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+
+  _CPU_Table = *cpu_table;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+ 
+uint32_t   _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+
+  return 0;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+/*PAGE
+ *
+ *  _CPU_Thread_Idle_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Thread_Idle_body( void )
+{
+#if 1
+  for(;;);
+#else
+  for(;;)
+  {
+    uint32_t st = __builtin_rdctl(0); /* read status  register */
+
+    /* Differentiate between IRQ off and on (for debugging) */
+    if(st & 1)
+      for(;;); 
+    else
+      for(;;); 
+ 
+    /* insert your "halt" instruction here */ ;
+  }
+#endif
+}
diff --git a/cpukit/score/cpu/nios2/cpu_asm.S b/cpukit/score/cpu/nios2/cpu_asm.S
new file mode 100644
index 0000000000..2244430703
--- /dev/null
+++ b/cpukit/score/cpu/nios2/cpu_asm.S
@@ -0,0 +1,388 @@
+/*
+ *  $Id$
+ *
+ *  This file contains all assembly code for the
+ *  NIOS2 implementation of RTEMS.
+ *
+ *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
+ *
+ *  Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999,
+ *    On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ */
+
+#include <rtems/asm.h>
+#include <rtems/score/cpu_asm.h>
+
+    .set noat
+
+    .extern _ISR_Nest_level
+    .extern _ISR_Signals_to_thread_executing
+    .extern _Context_Switch_necessary
+    .extern _Thread_Dispatch
+    .extern _Thread_Dispatch_disable_level
+
+/* ===================================================================== */
+
+/*
+ *  void _CPU_Context_switch( run_context, heir_context )
+ *  void _CPU_Context_restore( run_context, heir_context )
+ *
+ *  This routine performs a normal non-FP context switch.
+ */
+
+    .globl _CPU_Context_switch
+
+_CPU_Context_switch:
+
+    rdctl r6, status
+    stw r16,  0(r4)
+    stw r17,  4(r4)
+    stw r18,  8(r4)
+    stw r19, 12(r4)
+    stw r20, 16(r4)
+    stw r21, 20(r4)
+    stw r22, 24(r4)
+    stw r23, 28(r4)
+    stw gp,  32(r4)
+    stw fp,  36(r4)
+    stw sp,  40(r4)
+    stw ra,  44(r4)
+    /* r6 saved status */
+    stw r6,  48(r4)
+
+_CPU_Context_switch_restore:
+
+    ldw r16,  0(r5)
+    ldw r17,  4(r5)
+    ldw r18,  8(r5)
+    ldw r19, 12(r5)
+    ldw r20, 16(r5)
+    ldw r21, 20(r5)
+    ldw r22, 24(r5)
+    ldw r23, 28(r5)
+    ldw gp,  32(r5)
+    ldw fp,  36(r5)
+    ldw sp,  40(r5)
+
+    /* Disable interrupts */
+    wrctl status, r0
+
+    ldw ea,  44(r5)
+    ldw at,  48(r5)
+    /* FIXME: Always have interrupts enabled when we return from Context_switch */
+    ori at, at, 1
+    wrctl estatus, at
+
+    eret
+
+    .globl _CPU_Context_restore
+
+_CPU_Context_restore:
+
+    /* Copy first to second arg, then re-use 2nd half of Context_switch */
+    mov r5, r4
+    br  _CPU_Context_switch_restore
+
+
+/* ===================================================================== */
+
+    .globl _exception_vector
+
+_exception_vector:
+
+    /* 
+     * First, re-wind so we're pointed to the instruction where the exception
+     * occurred.
+     */
+
+    addi ea, ea, -4 
+
+    /*
+     * Now test to determine the cause of the exception.
+     */
+
+    /* TODO: Look at [ea] if there was an unknown/trap instruction */
+
+    /* If interrupts are globally disabled, it certainly was no interrupt */
+    rdctl et, estatus
+    andi et, et, 1
+    beq et, zero, _Exception_Handler
+
+    /* If no interrupts are pending, it was a software exception */
+    rdctl et, ipending
+    beq et, zero, _Exception_Handler
+
+    /*
+     * Falling through to here means that this was a hardware interrupt.
+     */
+
+    br _ISR_Handler
+
+/* ===================================================================== 
+ * Exception handler:
+ *   Responsible for unimplemented instructions and other software
+ *   exceptions. Not responsible for hardware interrupts. Currently,
+ *   software exceptions are regarded as error conditions, and the
+ *   handling isn't perfect. */
+
+_Exception_Handler:
+
+    /* stw et, 108(sp') => stw et, -20(sp) */
+    stw et, -20(sp)
+    mov et, sp
+    addi sp, sp, -128
+
+    stw r1,   0(sp)
+    stw r2,   4(sp)
+    stw r3,   8(sp)
+
+    rdctl r1, estatus
+    rdctl r2, ienable
+    rdctl r3, ipending
+
+    stw r4,   12(sp)
+    stw r5,   16(sp)
+    stw r6,   20(sp)
+    stw r7,   24(sp)
+    stw r8,   28(sp)
+    stw r9,   32(sp)
+    stw r10,  36(sp)
+    stw r11,  40(sp)
+    stw r12,  44(sp)
+    stw r13,  48(sp)
+    stw r14,  52(sp)
+    stw r15,  56(sp)
+    stw r16,  60(sp)
+    stw r17,  64(sp)
+    stw r18,  68(sp)
+    stw r19,  72(sp)
+    stw r20,  76(sp)
+    stw r21,  80(sp)
+    stw r22,  84(sp)
+    stw r23,  88(sp)
+    stw gp,   92(sp)
+    stw fp,   96(sp)
+    /* sp */
+    stw et,  100(sp)
+    stw ra,  104(sp)
+    /* stw et,  108(sp) */
+    stw ea,  112(sp)
+
+    /* status */
+    stw r1, 116(sp)
+    /* ienable */
+    stw r2, 120(sp)
+    /* ipending */
+    stw r3, 124(sp)
+
+    /*
+     * Restore the global pointer.
+     */
+
+    movhi gp, %hiadj(_gp)
+    addi gp, gp, %lo(_gp)
+
+    /*
+     * Pass a pointer to the stack frame as the input argument of the 
+     * exception handler (CPU_Exception_frame *).
+     */
+
+    mov r4, sp
+
+    /*
+     * Call the exception handler.
+     */
+
+    .extern __Exception_Handler
+    call __Exception_Handler
+
+stuck_in_exception:
+    br stuck_in_exception
+
+    /* 
+     * Restore the saved registers, so that all general purpose registers 
+     * have been restored to their state at the time the interrupt occured.
+     */
+
+    ldw r1,   0(sp)
+    ldw r2,   4(sp)
+    ldw r3,   8(sp)
+    ldw r4,   12(sp)
+    ldw r5,   16(sp)
+    ldw r6,   20(sp)
+    ldw r7,   24(sp)
+    ldw r8,   28(sp)
+    ldw r9,   32(sp)
+    ldw r10,  36(sp)
+    ldw r11,  40(sp)
+    ldw r12,  44(sp)
+    ldw r13,  48(sp)
+    ldw r14,  52(sp)
+    ldw r15,  56(sp)
+    ldw r16,  60(sp)
+    ldw r17,  64(sp)
+    ldw r18,  68(sp)
+    ldw r19,  72(sp)
+    ldw r20,  76(sp)
+    ldw r21,  80(sp)
+    ldw r22,  84(sp)
+    ldw r23,  88(sp)
+    ldw gp,   92(sp)
+    ldw fp,   96(sp)
+    ldw ra,  104(sp)
+
+    /* Disable interrupts */
+    wrctl status, r0
+
+    ldw ea,  112(sp)
+    ldw et,  116(sp)
+
+    /* FIXME: Enable interrupts after exception processing */
+    ori et, et, 1
+    wrctl estatus, et
+    ldw et,  108(sp)
+
+    /* Restore stack pointer */
+    ldw sp,  100(sp)
+
+    eret
+
+/* ===================================================================== */
+
+    .section .text
+
+_ISR_Handler:
+
+    /* 
+     * Process an external hardware interrupt. 
+     *
+     * First, preserve all callee saved registers on 
+     * the stack. (See the Nios2 ABI documentation for details).
+     *
+     * Do we really need to save all? 
+     *
+     * If this is interrupting a task (and not another interrupt),
+     * everything is saved into the task's stack, thus putting us
+     * in a situation similar to when the task calls a subroutine
+     * (and only the CPU_Context_Control subset needs to be changed)
+     */
+
+    rdctl et, estatus
+
+    /* Keep this in the same order as CPU_Interrupt_frame: */
+
+    addi sp, sp, -76
+    stw r1,  0(sp)
+    stw r2,  4(sp)
+    stw r3,  8(sp)
+    stw r4,  12(sp)
+    stw r5,  16(sp)
+    stw r6,  20(sp)
+    stw r7,  24(sp)
+    stw r8,  28(sp)
+    stw r9,  32(sp)
+    stw r10, 36(sp)
+    stw r11, 40(sp)
+    stw r12, 44(sp)
+    stw r13, 48(sp)
+    stw r14, 52(sp)
+    stw r15, 56(sp)
+    stw ra,  60(sp)
+    stw gp,  64(sp)
+    /* et contains status */
+    stw et,  68(sp)
+    stw ea,  72(sp)
+
+    /*
+     * Obtain a bitlist of the pending interrupts.
+     */
+
+    rdctl et, ipending
+
+    /*
+     * Restore the global pointer to the expected value.
+     */
+
+    movhi gp, %hiadj(_gp)
+    addi gp, gp, %lo(_gp)
+
+    /*
+     * Search through the bit list stored in r24(et) to find the first enabled
+     * bit. The offset of this bit is the index of the interrupt that is
+     * to be handled.
+     */
+
+    mov r4, zero
+6:
+    andi r3, r24, 1
+    bne r3, zero, 7f
+    addi r4, r4, 1
+    srli r24, r24, 1
+    br 6b
+7:
+
+    /*
+     * Having located the interrupt source, r4 contains the index of the
+     * interrupt to be handled. r5, the 2nd argument to the function,
+     * will point to the CPU_Interrupt_frame.
+     */
+
+    mov     r5, sp
+
+    .extern __ISR_Handler
+    call    __ISR_Handler
+
+    /* 
+     * Now that the interrupt processing is complete, prepare to return to
+     * the interrupted code.
+     */
+
+    /*
+     * Restore the saved registers, so that all general purpose registers 
+     * have been restored to their state at the time the interrupt occured.
+     */
+
+    ldw r1,   0(sp)
+    ldw r2,   4(sp)
+    ldw r3,   8(sp)
+    ldw r4,  12(sp)
+    ldw r5,  16(sp)
+    ldw r6,  20(sp)
+    ldw r7,  24(sp)
+    ldw r8,  28(sp)
+    ldw r9,  32(sp)
+    ldw r10, 36(sp)
+    ldw r11, 40(sp)
+    ldw r12, 44(sp)
+    ldw r13, 48(sp)
+    ldw r14, 52(sp)
+    ldw r15, 56(sp)
+    ldw ra,  60(sp)
+    ldw gp,  64(sp)
+
+    /* Disable interrupts */
+    wrctl status, r0
+
+    /* Restore the exception registers */
+
+    /* load saved ea into ea */
+    ldw ea,  72(sp)
+    /* load saved estatus into et */
+    ldw et,  68(sp)
+    /* Always have interrupts enabled when we return from interrupt */
+    ori et, et, 1
+    wrctl estatus, et
+    /* Restore the stack pointer */
+    addi sp, sp, 76
+
+    /*
+     * Return to the interrupted instruction.
+     */
+    eret
+
+
diff --git a/cpukit/score/cpu/nios2/irq.c b/cpukit/score/cpu/nios2/irq.c
new file mode 100644
index 0000000000..ac9385010d
--- /dev/null
+++ b/cpukit/score/cpu/nios2/irq.c
@@ -0,0 +1,94 @@
+/*
+ *  NIOS2 exception and interrupt handler
+ *
+ *  Derived from c4x/irq.c
+ *
+ *  Copyright (c) 2006
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/thread.h>
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ *
+ *  Upon entry, interrupts are disabled
+ */
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr asm("sp");
+
+void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
+{
+  register uint32_t   level;
+
+  /* Interrupts are disabled upon entry to this Handler */
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 ) {
+    /* Install irq stack */
+    _old_stack_ptr = stack_ptr;
+    stack_ptr = _CPU_Interrupt_stack_high - 4;
+  }
+#endif
+
+  _ISR_Nest_level++;
+
+  _Thread_Dispatch_disable_level++;
+
+  if ( _ISR_Vector_table[ vector] )
+  {
+    (*_ISR_Vector_table[ vector ])(vector, ifr);
+  };
+
+  /* Make sure that interrupts are disabled again */
+  _CPU_ISR_Disable( level );
+
+  _Thread_Dispatch_disable_level--;
+
+  _ISR_Nest_level--;
+
+  if( _ISR_Nest_level == 0)
+  {
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+    stack_ptr = _old_stack_ptr;
+#endif
+
+    if( _Thread_Dispatch_disable_level == 0 )
+    {
+      if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
+      {
+        _ISR_Signals_to_thread_executing = FALSE;
+        _CPU_ISR_Enable( level );
+        _Thread_Dispatch();
+        /* may have switched to another task and not return here immed. */
+        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
+      }
+    }
+    else
+    {
+      _ISR_Signals_to_thread_executing = FALSE;
+    };
+  };
+
+  _CPU_ISR_Enable( level );
+}
+
+void __Exception_Handler(CPU_Exception_frame *efr)
+{
+  _CPU_Fatal_halt(0xECC0);
+}
+
+
diff --git a/cpukit/score/cpu/nios2/preinstall.am b/cpukit/score/cpu/nios2/preinstall.am
new file mode 100644
index 0000000000..59d5889b39
--- /dev/null
+++ b/cpukit/score/cpu/nios2/preinstall.am
@@ -0,0 +1,43 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+PREINSTALL_FILES =
+CLEANFILES += $(PREINSTALL_FILES)
+
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/rtems
+	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/rtems/score
+	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
+
+$(PROJECT_INCLUDE)/rtems/score/nios2.h: rtems/score/nios2.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2.h
+
+$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
+
diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h
new file mode 100644
index 0000000000..390048d353
--- /dev/null
+++ b/cpukit/score/cpu/nios2/rtems/asm.h
@@ -0,0 +1,97 @@
+/**
+ * @file rtems/asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ */
+
+/*
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/nios2.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA
+#define END_DATA
+#define BEGIN_BSS
+#define END_BSS
+#define END
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC(sym) .globl SYM (sym)
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif