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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-07-03 16:58:56 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-07-03 16:58:56 +0000
commit77b8106919ee88678df869cb63467298a5783cc3 (patch)
tree62dbf3157eb8908849d669ddf1781f04515d5e2d /cpukit/score/cpu/mips
parentcacbf4f86a9372cc7bd354adba34f8bd9bd1038d (diff)
downloadrtems-77b8106919ee88678df869cb63467298a5783cc3.tar.bz2
2001-07-03 Joel Sherrill <joel@OARcorp.com>
* cpu.c: Fixed typo.
Diffstat (limited to 'cpukit/score/cpu/mips')
-rw-r--r--cpukit/score/cpu/mips/ChangeLog4
-rw-r--r--cpukit/score/cpu/mips/cpu.c2
2 files changed, 5 insertions, 1 deletions
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index 5be34d5eb3..7afe0b8186 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,7 @@
+2001-07-03 Joel Sherrill <joel@OARcorp.com>
+
+ * cpu.c: Fixed typo.
+
2000-05-24 Joel Sherrill <joel@OARcorp.com>
* rtems/score/mips.h: Added constants for MIPS exception numbers.
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index f0ff09f171..9a5546f683 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -153,7 +153,7 @@ void _CPU_ISR_install_raw_handler(
* table used by the CPU to dispatch interrupt handlers.
*
* Because all interrupts are vectored through the same exception handler
- * this is not necessary on thi sport.
+ * this is not necessary on this port.
*/
}