diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-07-03 16:58:56 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-07-03 16:58:56 +0000 |
| commit | 77b8106919ee88678df869cb63467298a5783cc3 (patch) | |
| tree | 62dbf3157eb8908849d669ddf1781f04515d5e2d | |
| parent | 2001-06-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
| download | rtems-77b8106919ee88678df869cb63467298a5783cc3.tar.bz2 | |
2001-07-03 Joel Sherrill <joel@OARcorp.com>
* cpu.c: Fixed typo.
| -rw-r--r-- | c/src/exec/score/cpu/mips/ChangeLog | 4 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/mips/cpu.c | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/ChangeLog | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/cpu.c | 2 |
4 files changed, 10 insertions, 2 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index 5be34d5eb3..7afe0b8186 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,7 @@ +2001-07-03 Joel Sherrill <joel@OARcorp.com> + + * cpu.c: Fixed typo. + 2000-05-24 Joel Sherrill <joel@OARcorp.com> * rtems/score/mips.h: Added constants for MIPS exception numbers. diff --git a/c/src/exec/score/cpu/mips/cpu.c b/c/src/exec/score/cpu/mips/cpu.c index f0ff09f171..9a5546f683 100644 --- a/c/src/exec/score/cpu/mips/cpu.c +++ b/c/src/exec/score/cpu/mips/cpu.c @@ -153,7 +153,7 @@ void _CPU_ISR_install_raw_handler( * table used by the CPU to dispatch interrupt handlers. * * Because all interrupts are vectored through the same exception handler - * this is not necessary on thi sport. + * this is not necessary on this port. */ } diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index 5be34d5eb3..7afe0b8186 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,7 @@ +2001-07-03 Joel Sherrill <joel@OARcorp.com> + + * cpu.c: Fixed typo. + 2000-05-24 Joel Sherrill <joel@OARcorp.com> * rtems/score/mips.h: Added constants for MIPS exception numbers. diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c index f0ff09f171..9a5546f683 100644 --- a/cpukit/score/cpu/mips/cpu.c +++ b/cpukit/score/cpu/mips/cpu.c @@ -153,7 +153,7 @@ void _CPU_ISR_install_raw_handler( * table used by the CPU to dispatch interrupt handlers. * * Because all interrupts are vectored through the same exception handler - * this is not necessary on thi sport. + * this is not necessary on this port. */ } |