PR 730

	* cpu_asm.S: Collected PR 601 changes for commit to cvshead
	for rtems-4.7

5 files changed, 264 insertions, 17 deletions

diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h
index 0460d34eff..c060bb8091 100644
--- a/cpukit/score/cpu/mips/rtems/asm.h
+++ b/cpukit/score/cpu/mips/rtems/asm.h
@@ -157,3 +157,5 @@ _##name:
 #define R_FP31 	31
 
 #endif
+/* end of include file */
+
diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
index 0e451e7f8f..e1df010d86 100644
--- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
@@ -60,6 +60,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	UT_VEC	K0BASE			/* utlbmiss vector */
 #define DB_VEC  (K0BASE+0x40)           /* debug vector */
 #define E_VEC	(K0BASE+0x80)		/* exception vector */
+#elif  __mips == 32
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K0BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
 #elif  __mips == 3
 #define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
 #define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
@@ -91,6 +96,100 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	MINCACHE	0x200		/* 512       For 3041. */
 #define	MAXCACHE	0x40000		/* 256*1024   256k */	
 
+#if  __mips == 32
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00010000	/* 32 bit */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#ifndef WAIT
+#define WAIT .word 0x42000020
+#endif /* WAIT */
+
+/* Disabled by joel -- horrible overload of common word.
+#ifndef wait 
+#define wait .word 0x42000020
+#endif wait
+*/
+
+#endif
+
 #if  __mips == 3
 /* R4000 configuration register definitions */
 #define CFG_CM		0x80000000	/* Master-Checker mode */
@@ -253,6 +352,41 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define TLBPGMASK_MASK		0x01ffe000
 #endif
 
+#if  __mips == 32
+#define	N_TLB_ENTRIES	16
+
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define TLBLO_CSHIFT	3
+
+#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define TLBPGMASK_MASK		0x01ffe000
+#endif
+
 #if  __mips == 1
 
 
@@ -383,7 +517,58 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define SR_IE		0x00000001	/* Interrupts enabled */
 #endif
 
+#if  __mips == 32
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define SR_RP		0x08000000      /* Reduced power operation */
+#define SR_FR		0x04000000	/* Additional floating point registers */
+#define SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define SR_BEV		0x00400000	/* Use boot exception vectors */
+#define SR_TS		0x00200000	/* TLB shutdown */
+#define SR_SR		0x00100000	/* Soft reset */
+#define SR_CH		0x00040000	/* Cache hit */
+#define SR_CE		0x00020000	/* Use cache ECC  */
+#define SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
 
+#define SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define SR_KSUSER	0x00000010	/* User mode */
+#define SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define SR_ERL		0x00000004	/* Error level */
+#define SR_EXL		0x00000002	/* Exception level */
+#define SR_IE		0x00000001	/* Interrupts enabled */
+#endif
 
 /*
  * Cause Register
@@ -414,6 +599,12 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	C0_TLBLO1	$3		/* tlb entry low 1 */
 #endif
 
+#if  __mips == 32
+#define	C0_TLBLO0	$2		/* tlb entry low 0 */
+#define	C0_TLBLO1	$3		/* tlb entry low 1 */
+#endif
+
+
 #define	C0_CTXT		$4		/* tlb context */
 
 #if  __mips == 3
@@ -421,6 +612,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_WIRED	$6		/* number of wired tlb entries */
 #endif
 
+#if  __mips == 32
+#define C0_PAGEMASK	$5		/* tlb page mask */
+#define C0_WIRED	$6		/* number of wired tlb entries */
+#endif
+
 #if  __mips == 1
 #define C0_TAR          $6
 #endif
@@ -430,6 +626,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if  __mips == 3
 #define C0_COUNT	$9		/* cycle count */
 #endif
+#if  __mips == 32
+#define C0_COUNT	$9		/* cycle count */
+#endif
 
 #define	C0_TLBHI	$10		/* tlb entry hi */
 
@@ -437,6 +636,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_COMPARE	$11		/* cyccle count comparator  */
 #endif
 
+#if  __mips == 32
+#define C0_COMPARE	$11		/* cyccle count comparator  */
+#endif
+
 #define	C0_SR		$12		/* status register */
 #define	C0_CAUSE	$13		/* exception cause */
 #define	C0_EPC		$14		/* exception pc */
@@ -459,6 +662,20 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_ERRPC	$30		/* cache error pc */
 #endif
 
+#if  __mips == 32
+#define C0_CONFIG	$16		/* configuration register */
+#define C0_LLADDR	$17		/* linked load address */
+#define C0_WATCHLO	$18		/* watchpoint trap register */
+#define C0_WATCHHI	$19		/* watchpoint trap register */
+#define C0_XCTXT    $20     /* extended tlb context */
+#define C0_ECC		$26		/* secondary cache ECC control */
+#define C0_CACHEERR	$27		/* cache error status */
+#define C0_TAGLO	$28		/* cache tag lo */
+#define C0_TAGHI	$29		/* cache tag hi */
+#define C0_ERRPC	$30		/* cache error pc */
+#endif
+
+
 #define C1_REVISION     $0
 #define C1_STATUS       $31
 
@@ -475,3 +692,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* _IDTCPU_H__ */
+
diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
index 7abb8d59ba..6b6f2e82f8 100644
--- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h
+++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
@@ -229,7 +229,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define	R_TLBLO		73
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO0	73
 #endif
 
@@ -243,7 +243,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define NREGS		81
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO1	81
 #define R_PAGEMASK	82
 #define R_WIRED		83
@@ -298,7 +298,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	R_SP		R_R29
 #define	R_FP		R_R30
 #define	R_RA		R_R31
-
+#define R_SZ 4
 /* disabled for RTEMS */
 #if 0
 /* Ketan added the following */
@@ -329,3 +329,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* __IREGDEF_H__ */
+
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index a91e8307cd..279e06eb2f 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -1,7 +1,3 @@
-/**
- * @file rtems/score/cpu.h
- */
-
 /*
  *  Mips CPU Dependent Header File
  *
@@ -52,6 +48,16 @@ extern "C" {
 #include <rtems/score/types.h>
 #endif
 
+#ifndef TRUE
+#define TRUE 1
+#warning "TRUE was not defined, assuming default of 1"
+#endif
+#ifndef FALSE
+#define FALSE 0
+#warning "FALSE was not defined, assuming default of 0"
+#endif
+
+
 /* conditional compilation parameters */
 
 /*
@@ -187,6 +193,13 @@ extern "C" {
  *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
  *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
+ *  So far, the only CPU in which this option has been used is the
+ *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
+ *  floating point registers to perform integer multiplies.  If
+ *  a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
  *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  */
 
@@ -314,7 +327,10 @@ extern "C" {
 #define CPU_MODES_INTERRUPT_MASK   0x000000ff
 
 /*
- *  Processor defined structures required for cpukit/score.
+ *  Processor defined structures
+ *
+ *  Examples structures include the descriptor tables from the i386
+ *  and the processor control structure on the i960ca.
  */
 
 /* may need to put some structures here.  */
@@ -357,7 +373,7 @@ extern "C" {
 #ifndef ASSEMBLY_ONLY
 
 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
-#if __mips == 1
+#if (__mips == 1) || (__mips == 32)
 #define __MIPS_REGISTER_TYPE     uint32_t  
 #define __MIPS_FPU_REGISTER_TYPE uint32_t  
 #elif __mips == 3
@@ -534,7 +550,7 @@ typedef struct
   __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
                                   /*         all MIPS CPUs (at least MGV) */
 #endif
-#if  __mips == 3
+#if  (__mips == 3) || (__mips == 32)
   __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
                                   /*         all MIPS CPUs (at least MGV) */
 #endif
@@ -550,7 +566,7 @@ typedef struct
   __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
   __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
   /* end of __mips == 1 so NREGS == 81 */
-#if  __mips == 3
+#if  (__mips == 3) || (__mips == 32)
   __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
   __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
   __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
@@ -685,7 +701,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
  *  that a "reasonable" small application should not have any problems.
  */
 
-#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(uint32_t  ))
+#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
 
 
 /*
@@ -848,8 +864,8 @@ void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
  */
 
 
-#if __mips == 3
-#define _INTON	(SR_EXL | SR_IE)
+#if (__mips == 3) || (__mips == 32)
+#define _INTON	        SR_IE
 #define _EXTRABITS      0
 #endif
 #if __mips == 1
@@ -865,7 +881,7 @@ void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
   	_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
   	(_the_context)->sp = _stack_tmp; \
   	(_the_context)->fp = _stack_tmp; \
-	(_the_context)->ra = (uint64_t  )_entry_point; \
+	(_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
 	(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
 						       0x300 | \
 						       ((_intlvl & 1)?_INTON:0)) ) | \
diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h
index 341dd89d3e..ab75c9a8d1 100644
--- a/cpukit/score/cpu/mips/rtems/score/mips.h
+++ b/cpukit/score/cpu/mips/rtems/score/mips.h
@@ -30,7 +30,7 @@ extern "C" {
  *  NOTE: XXX what about SR_ERL?
  */
 
-#if __mips == 3
+#if (__mips == 3) || (__mips == 32)
 #ifdef ASM
 #define SR_INTERRUPT_ENABLE_BITS 0x01
 #else
@@ -59,9 +59,10 @@ extern "C" {
 #define MIPS_HAS_FPU 1
 #endif 
 
+
 #if (__mips == 1)
 #define CPU_MODEL_NAME  "ISA Level 1 or 2"
-#elif (__mips == 3)
+#elif (__mips == 3) || (__mips == 32)
 #if defined(__mips64)
 #define CPU_MODEL_NAME  "ISA Level 4"
 #else
@@ -218,6 +219,8 @@ extern "C" {
  *  Access FCR31
  */
 
+#if ( MIPS_HAS_FPU == 1 )
+
 #define mips_get_fcr31( _x ) \
   do { \
     asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
@@ -230,6 +233,12 @@ extern "C" {
     asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
   } while(0)
 
+#else
+
+#define mips_get_fcr31( _x )
+#define mips_set_fcr31( _x )
+
+#endif
 
 /*
  *  Manipulate interrupt mask 
@@ -271,3 +280,4 @@ extern "C" {
 #endif
 
 #endif /* ! _INCLUDE_MIPS_h */
+/* end of include file */