PR 730

	* cpu_asm.S: Collected PR 601 changes for commit to cvshead
	for rtems-4.7

15 files changed, 658 insertions, 216 deletions

diff --git a/cpukit/libnetworking/netinet/tcp_input.c b/cpukit/libnetworking/netinet/tcp_input.c
index a33f9593c4..5c83e5b091 100644
--- a/cpukit/libnetworking/netinet/tcp_input.c
+++ b/cpukit/libnetworking/netinet/tcp_input.c
@@ -201,7 +201,7 @@ tcp_reass(tp, ti, m)
 	}
 	tcpstat.tcps_rcvoopack++;
 	tcpstat.tcps_rcvoobyte += ti->ti_len;
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
     STR32_UNALGN(ti,m);
 #else
 	REASS_MBUF(ti) = m;		/* XXX */
@@ -217,7 +217,7 @@ tcp_reass(tp, ti, m)
 		if (i < q->ti_len) {
 			q->ti_seq += i;
 			q->ti_len -= i;
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
             LD32_UNALGN(q,m);
             m_adj(m, i);
 #else
@@ -226,7 +226,7 @@ tcp_reass(tp, ti, m)
 			break;
 		}
 		q = (struct tcpiphdr *)q->ti_next;
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
         LD32_UNALGN((struct tcpiphdr *)q->ti_prev,m);
 #else
 		m = REASS_MBUF((struct tcpiphdr *)q->ti_prev);
@@ -254,7 +254,7 @@ present:
 		tp->rcv_nxt += ti->ti_len;
 		flags = ti->ti_flags & TH_FIN;
 		remque(ti);
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
         LD32_UNALGN(ti,m);
 #else
 		m = REASS_MBUF(ti);
diff --git a/cpukit/libnetworking/netinet/tcp_subr.c b/cpukit/libnetworking/netinet/tcp_subr.c
index 5802ccc465..e879d855be 100644
--- a/cpukit/libnetworking/netinet/tcp_subr.c
+++ b/cpukit/libnetworking/netinet/tcp_subr.c
@@ -399,7 +399,7 @@ tcp_close(tp)
 	t = tp->seg_next;
 	while (t != (struct tcpiphdr *)tp) {
 		t = (struct tcpiphdr *)t->ti_next;
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
         LD32_UNALGN((struct tcpiphdr *)t->ti_prev,m);
 #else
 		m = REASS_MBUF((struct tcpiphdr *)t->ti_prev);
diff --git a/cpukit/libnetworking/netinet/tcp_var.h b/cpukit/libnetworking/netinet/tcp_var.h
index 6c772b5053..0c05b03c56 100644
--- a/cpukit/libnetworking/netinet/tcp_var.h
+++ b/cpukit/libnetworking/netinet/tcp_var.h
@@ -225,7 +225,7 @@ struct rmxp_tao {
  * port numbers (which are no longer needed once we've located the
  * tcpcb) are overlayed with an mbuf pointer.
  */
-#if (defined(__GNUC__) && defined(__arm__))
+#if (defined(__GNUC__) && (defined(__arm__) || defined(__mips__)))
 #define STR32_UNALGN(ti,m) \
         (ti)->ti_sport = (unsigned short)(((unsigned int) m & 0xffff0000) >> 16); \
          (ti)->ti_dport = (unsigned short) ((unsigned int) m & 0x0000ffff);
diff --git a/cpukit/libnetworking/sys/queue.h b/cpukit/libnetworking/sys/queue.h
index 6ff47d9fe2..3c42406df6 100644
--- a/cpukit/libnetworking/sys/queue.h
+++ b/cpukit/libnetworking/sys/queue.h
@@ -568,7 +568,7 @@ struct {								\
 #ifdef	__GNUC__
 
 struct quehead {
-#if defined(__arm__)
+#if (defined(__arm__) || defined(__mips__))
     struct quehead *qh_link  __attribute__((packed));
     struct quehead *qh_rlink __attribute__((packed));
 #else /* !defined(__arm__)) */
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index c20d1643fc..216153ea8f 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,43 +1,18 @@
-2004-11-21	Ralf Corsepius <ralf.corsepius@rtems.org>
-
-	* rtems/score/types.h: Use __rtems_score_types_h as preprocessor
-	guard.
-
-2004-11-21	Ralf Corsepius <ralf.corsepius@rtems.org>
-
-	* asm.h: Add doxygen preamble.
-
-2004-10-02	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* rtems/score/cpu.h: Add doxygen preamble.
-	* rtems/score/mips.h: Add doxygen preamble.
-	* rtems/score/types.h: Add doxygen preamble.
-
-2004-09-29	Joel Sherrill <joel@OARcorp.com>
-
-	* rtems/score/cpu.h: i960 obsoleted and all references removed.
-
-2004-07-25	Joel Sherrill <joel@OARcorp.com>
-
-	* cpu_asm.S: Remove use of C++ style comments and make this compile
-	again.
-
-2004-04-14	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	PR 605/bsps
-	* cpu.c: Remove further c++ style comments having been missed in
-	previous patch. Remove printf's entirely.
+2004-12-02	Greg Menke <gregory.menke@gsfc.nasa.gov>
+	PR 730 
+	* cpu_asm.S: Collected PR 601 changes for commit to cvshead
+	for rtems-4.7
 
 2004-04-09	Joel Sherrill <joel@OARcorp.com>
 
 	PR 605/bsps
 	* cpu.c: Do not use C++ style comments.
 
-2004-04-06	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* configure.ac: Remove (Merged into $(top_srcdir)/configure.ac).
-	* Makefile.am: Don't include multilib.am.
-	Reflect merging configure.ac into $(top_srcdir)/configure.ac.
+2004-04-07	Greg Menke <gregory.menke@gsfc.nasa.gov>
+	PR 601
+	* cpu_asm.S: Added __mips==32 support for R4000 processors running
+	32 bit code.  Fixed #define problems that caused fpu code to
+	always be included even when no fpu is present.
 
 2004-04-03	Art Ferrer <arturo.b.ferrer@nasa.gov>
 
@@ -46,92 +21,6 @@
 	status/control register on context switches. Missing this register
 	was causing intermittent floating point errors.
 
-2004-04-02	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* Makefile.am: Install iregdefs.h and idtcpu.h to 
-	$(includedir)/rtems/mips.
-	* cpu_asm.S: Include <rtems/mips/iregdef.h> instead of <iregdef.h>.
-	* rtems/score/mips.h, cpu_asm.S: Include <rtems/mips/idtcpu.h>
-	instead of <idtcpu.h>.
-
-2004-04-01	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* Makefile.am: Install asm.h to $(includedir)/rtems.
-
-2004-04-01	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
-
-2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
-
-2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
-
-	* configure.ac: RTEMS_TOP([../../../..]).
-
-2004-01-21	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Move RTEMS_TOP one subdir down.
-
-2004-01-19	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Add PREINSTALL_DIRS.
-
-2004-01-14	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
-	Add PREINSTALL_FILES to CLEANFILES.
-
-2004-01-12	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Requires automake >= 1.8.1.
-
-2004-01-11	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Include compile.am, again.
-
-2004-01-11	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Convert to using automake compilation rules.
-
-2004-01-07	Joel Sherrill <joel@OARcorp.com>
-
-	* rtems/score/mips.h: Removed junk revision line.
-
-2003-12-12	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
-
-2003-12-12	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Require automake >= 1.8, autoconf >= 2.59.
-
-2003-12-01	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Remove TMPINSTALL_FILES.
-
-2003-11-30	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Add $(dirstamp) to preinstallation rules.
-
-2003-11-23	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* Makefile.am: Don't use gmake rules for preinstallation.
-
-2003-10-21	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Remove RTEMS_CANONICAL_HOST.
-
-2003-10-21	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
-	* configure.ac: Remove RTEMS_CHECK_CPU.
-
-2003-09-26	Joel Sherrill <joel@OARcorp.com>
-
-	* rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
-	references.
-
 2003-09-04	Joel Sherrill <joel@OARcorp.com>
 
 	* cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
diff --git a/cpukit/score/cpu/mips/asm.h b/cpukit/score/cpu/mips/asm.h
index 0460d34eff..c060bb8091 100644
--- a/cpukit/score/cpu/mips/asm.h
+++ b/cpukit/score/cpu/mips/asm.h
@@ -157,3 +157,5 @@ _##name:
 #define R_FP31 	31
 
 #endif
+/* end of include file */
+
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index c84b738cf2..5cf43917f0 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -99,9 +99,11 @@ uint32_t   _CPU_ISR_Get_level( void )
 
   mips_get_sr(sr);
 
-#if __mips == 3
-/* EXL bit and shift down hardware ints into bits 1 thru 6 */
-  sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9);
+  /* printf("current sr=%08X, ",sr); */
+
+#if (__mips == 3) || (__mips == 32)
+/* IE bit and shift down hardware ints into bits 1 thru 6 */
+  sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
 
 #elif __mips == 1
 /* IEC bit and shift down hardware ints into bits 1 thru 6 */
@@ -131,14 +133,14 @@ void _CPU_ISR_Set_level( uint32_t   new_level )
 
   mips_get_sr(sr);
 
-#if __mips == 3
+#if (__mips == 3) || (__mips == 32)
   mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
 
-  srbits = sr & ~(0xfc00 | SR_EXL | SR_IE);
+   srbits = sr & ~(0xfc00 | SR_IE);
 
-  sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \
+   sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
 		 (((new_level<<9) & 0xfc00) | \
-		  (new_level & 1)?(SR_EXL | SR_IE):0));
+                   ((new_level & 1)?SR_IE:0)));
 /*
   if ( (new_level & SR_EXL) == (sr & SR_EXL) )
     return;
@@ -263,7 +265,7 @@ void _CPU_Install_interrupt_stack( void )
 
 void _CPU_Thread_Idle_body( void )
 {
-#if __mips == 3
+#if (__mips == 3) || (__mips == 32)
    for( ; ; )
      asm volatile("wait"); /* use wait to enter low power mode */
 #elif __mips == 1
diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S
index c0ad608486..081883fb7a 100644
--- a/cpukit/score/cpu/mips/cpu_asm.S
+++ b/cpukit/score/cpu/mips/cpu_asm.S
@@ -35,6 +35,10 @@
  *    2004: 24March, Art Ferrer, NASA/GSFC, added save of FP status/control
  *          register to fix intermittent FP error encountered on ST5 mission
  *          implementation on Mongoose V processor.
+ *    2004: April 7, Greg Menke <gregory.menke@gsfc.nasa.gov> Added __mips==32
+ *          support for R4000 processors running 32 bit code.  Fixed #define
+ *          problems that caused fpu code to always be included even when no
+ *          fpu is present.
  *  
  *  COPYRIGHT (c) 1989-2002.
  *  On-Line Applications Research Corporation (OAR).
@@ -53,6 +57,23 @@
 #define ASSEMBLY_ONLY
 #include <rtems/score/cpu.h>
 
+#if TRUE
+#else
+#error TRUE is not true
+#endif
+#if FALSE
+#error FALSE is not false
+#else
+#endif
+
+/*		
+#if ( CPU_HARDWARE_FP == TRUE )
+#warning CPU_HARDWARE_FP == TRUE
+#else
+#warning CPU_HARDWARE_FP != TRUE
+#endif
+*/
+	
 		
 /* enable debugging shadow writes to misc ram, this is a vestigal
 * Mongoose-ism debug tool- but may be handy in the future so we
@@ -70,12 +91,17 @@
 
 #if __mips == 3
 /* 64 bit register operations */
-#define NOP	
+#define NOP	nop
+/*
 #define ADD	dadd
-#define STREG	sd
-#define LDREG	ld
 #define MFCO	dmfc0
 #define MTCO	dmtc0
+*/
+#define ADD	add	
+#define MFCO	mfc0
+#define MTCO	mtc0
+#define STREG	sd
+#define LDREG	ld
 #define ADDU	addu
 #define ADDIU	addiu
 #define R_SZ	8
@@ -85,7 +111,7 @@
 
 /* XXX if we don't always want 64 bit register ops, then another ifdef */
 
-#elif __mips == 1
+#elif (__mips == 1 ) || (__mips == 32)
 /* 32 bit register operations*/
 #define NOP	nop
 #define ADD	add
@@ -385,8 +411,8 @@ FRAME(_CPU_Context_switch,sp,0,ra)
         .set noreorder
 
         MFC0	t0,C0_SR
-#if __mips == 3
-	li	t1,SR_EXL | SR_IE
+#if (__mips == 3) || (__mips == 32)
+	li	t1,SR_IE
 #elif __mips == 1
 	li	t1,SR_IEC
 #endif
@@ -450,44 +476,67 @@ _CPU_Context_switch_restore:
 
         LDREG t0, C0_SR_OFFSET*R_SZ(a1)
 	
+/*	NOP */
+/*#if __mips == 3 */
+/*        andi  t0,SR_EXL */
+/*        bnez  t0,_CPU_Context_1 */   /* set exception level from restore context */
+/*        li    t0,~SR_EXL */
+/*        MFC0  t1,C0_SR */
+/*        NOP */
+/*        and   t1,t0 */
+/*        MTC0  t1,C0_SR */
+/* */
+/*#elif __mips == 1 */
+/* */
+/*        andi  t0,(SR_INTERRUPT_ENABLE_BITS) */ /* we know 0 disabled */
+/*        beq   t0,$0,_CPU_Context_1  */         /* set level from restore context */
+/*        MFC0  t0,C0_SR */
+/*        NOP */
+/*        or    t0,(SR_INTERRUPT_ENABLE_BITS) */ /* new_sr = old sr with enabled  */
+/*        MTC0  t0,C0_SR */                     /* set with enabled */
+/*	  NOP */
+
 
 /*
- * Incorporate the incoming task's FP coprocessor state and interrupt
- * mask/enable into the status register.  We jump thru the requisite hoops
- * to ensure we maintain all other SR bits as global values.
- *
- * Get the task's FPU enable, int mask & int enable bits.  Although we keep the 
- * software int enables on a per-task basis, the rtems_task_create
- * Interrupt Level & int level manipulation functions cannot enable/disable
- * them, so they are automatically enabled for all tasks.  To turn them off,
- * a task must itself manipulate the SR register.  
- *
- * Although something of a hack on this processor, we treat the SR register
- * int enables as the RTEMS interrupt level.  We use the int level
- * value as a bitmask, not as any sort of greater than/less than metric.
- * Manipulation of a task's interrupt level directly corresponds to manipulation
- * of that task's SR bits, as seen in cpu.c
- *
- * Note, interrupts are disabled before context is saved, though the task's
- * interrupt enable state is recorded.  The task swapping in will apply its
- * specific SR bits, including interrupt enable.  If further task-specific
- * SR bits are arranged, it is this code, the cpu.c interrupt level stuff and
- * cpu.h task initialization code that will be affected.  
- */
+** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
+** into the status register.  We jump thru the requisite hoops to ensure we 
+** maintain all other SR bits as global values.
+**
+** Get the task's FPU enable, int mask & int enable bits.  Although we keep the 
+** software int enables on a per-task basis, the rtems_task_create
+** Interrupt Level & int level manipulation functions cannot enable/disable them, 
+** so they are automatically enabled for all tasks.  To turn them off, a task  
+** must itself manipulate the SR register.  
+**
+** Although something of a hack on this processor, we treat the SR register
+** int enables as the RTEMS interrupt level.  We use the int level
+** value as a bitmask, not as any sort of greater than/less than metric.
+** Manipulation of a task's interrupt level corresponds directly to manipulation
+** of that task's SR bits, as seen in cpu.c
+**
+** Note, interrupts are disabled before context is saved, though the task's
+** interrupt enable state is recorded.  The task swapping in will apply its
+** specific SR bits, including interrupt enable.  If further task-specific
+** SR bits are arranged, it is this code, the cpu.c interrupt level stuff and
+** cpu.h task initialization code that will be affected.  
+*/
 
 	li	t2,SR_CU1
 	or	t2,SR_IMASK
 
 	/* int enable bits */
-#if __mips == 3
-	or	t2,SR_EXL + SR_IE
+#if (__mips == 3) || (__mips == 32)
+	/* 
+	** Save IE
+	*/
+	or	t2, SR_IE
 #elif __mips == 1
 	/* 
 	** Save current, previous & old int enables.  This is key because
 	** we can dispatch from within the stack frame used by an
 	** interrupt service.  The int enables nest, but not beyond
 	** previous and old because of the dispatch interlock seen
-	** in the interrupt processing code
+	** in the interrupt processing code.
 	*/
 	or	t2,SR_IEC + SR_IEP + SR_IEO
 #endif
@@ -495,7 +544,7 @@ _CPU_Context_switch_restore:
 		
 	MFC0	t1,C0_SR	/* grab the current SR */
 	not	t2		
-	and	t1,t2		/* mask off the old task's bits */
+	and	t1,t2		/* mask off the old task's per-task bits */
 	or	t1,t0		/* or in the new task's bits */
         MTC0	t1,C0_SR	/* and load the new SR */
 	NOP
@@ -687,7 +736,7 @@ _ISR_Handler_Exception:
         STREG    t1,R_BADVADDR*R_SZ(sp)
 	
 #if ( CPU_HARDWARE_FP == TRUE )
-        MFC0     t0,C0_SR                 /* FPU is enabled, save state */
+        MFC0     t0,C0_SR                 /* we have a FPU, save state if enabled */
 	NOP
         srl      t0,t0,16
         andi     t0,t0,(SR_CU1 >> 16)
@@ -711,7 +760,7 @@ _ISR_Handler_Exception:
 
 	
 	/* 
-	** note, if the exception vector returns, rely on it to have
+	** Note, if the exception vector returns, rely on it to have
 	** adjusted EPC so we will return to some correct address.  If
 	** this is not done, we might get stuck in an infinite loop because 
 	** we'll return to the instruction where the exception occured and
@@ -779,7 +828,7 @@ excreturn:
 	
 		
 #if ( CPU_HARDWARE_FP == TRUE )
-        MFC0     t0,C0_SR               /* FPU is enabled, restore state */
+        MFC0     t0,C0_SR               /* FPU is present, restore state if enabled */
 	NOP
         srl      t0,t0,16
         andi     t0,t0,(SR_CU1 >> 16)
@@ -935,12 +984,22 @@ _ISR_Handler_1:
 */
 
         MFC0    t0, C0_SR
-#if __mips == 3
-	li	t1,SR_EXL | SR_IE
-#elif __mips == 1
+#if __mips == 1
+	
 	li	t1,SR_IEC
-#endif
 	or	t0, t1
+	
+#elif (__mips == 3) || (__mips == 32)
+	
+	/* 
+	** clear XL and set IE so we can get interrupts.
+	*/
+	li	t1, SR_EXL
+	not	t1
+	and	t0,t1
+	or	t0, SR_IE
+	
+#endif
         MTC0    t0, C0_SR
 	NOP
 
@@ -951,40 +1010,56 @@ _ISR_Handler_1:
         jal     _Thread_Dispatch
         NOP
 
-	/* and make sure its clear in case we didn't dispatch.  if we did, its
-	** already cleared */
+	/* 
+	** And make sure its clear in case we didn't dispatch.  if we did, its
+	** already cleared 
+	*/
 	la	t0,__exceptionStackFrame
 	STREG	zero,(t0)
 	NOP
 
 /* 
 ** turn interrupts back off while we restore context so
-** a badly timed interrupt won't accidentally mess things up
+** a badly timed interrupt won't mess things up
 */
         MFC0    t0, C0_SR
-#if __mips == 3
-	li	t1,SR_EXL | SR_IE
-#elif __mips == 1
+
+#if __mips == 1
+ 
 	/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
 	li	t1,SR_IEC | SR_KUP | SR_KUC	
-#endif
 	not	t1
 	and	t0, t1
+        MTC0    t0, C0_SR
+ 	NOP
 
-#if __mips == 1
-	/* disabled 7/29, gregm, this tasks context was saved previously in an interrupt,
-	** so we'll just restore the task's previous interrupt enables.
+ #elif (__mips == 3) || (__mips == 32)
 
-	**
-	** make sure previous int enable is on  because we're returning from an interrupt
-	** which means interrupts have to be enabled
+ 	move	t2, t0
 	
-	li	t1,SR_IEP
-	or	t0,t1
-	*/
-#endif
-        MTC0    t0, C0_SR
+  /* make sure XL & IE are clear so ints are disabled & we can update EPC for the return */ 
+        li   t1,SR_EXL | SR_IE 
+        not  t1 
+        and  t0,t1 
+        MTC0 t0,C0_SR
+  	NOP
+  	
+ 	/* store new EPC value, which we can do since XL=0 */
+        LDREG   t0, R_EPC*R_SZ(sp)
 	NOP
+ 	MTC0	t0, C0_EPC
+ 	NOP
+ 	
+ 	/* apply task's SR with XL set so the eret will return properly */
+ 	or	t2, SR_EXL
+ 	MTC0	t2, C0_SR
+ 	NOP
+#endif
+ 
+ 
+ 
+ 
+ 
 	
 #ifdef INSTRUMENT_EXECUTING_THREAD
 	lw	t0,_Thread_Executing
@@ -1041,15 +1116,22 @@ _ISR_Handler_exit:
         LDREG v1, R_V1*R_SZ(sp)
         LDREG v0, R_V0*R_SZ(sp)
 	
-        LDREG     k1, R_EPC*R_SZ(sp)
-	
+#if __mips == 1
+	LDREG     k1, R_EPC*R_SZ(sp)
+#endif
+		
 	.set noat
         LDREG     AT, R_AT*R_SZ(sp)
         .set at
 
         ADDIU     sp,sp,EXCP_STACK_SIZE
-	j         k1
-	rfe
+
+#if (__mips == 3) || (__mips == 32)
+	eret
+#elif __mips == 1
+  	j         k1
+  	rfe
+#endif
         NOP
 
        .set    reorder
@@ -1066,3 +1148,4 @@ FRAME(mips_break,sp,0,ra)
         NOP
        .set    reorder
 ENDFRAME(mips_break)
+
diff --git a/cpukit/score/cpu/mips/idtcpu.h b/cpukit/score/cpu/mips/idtcpu.h
index 0e451e7f8f..e1df010d86 100644
--- a/cpukit/score/cpu/mips/idtcpu.h
+++ b/cpukit/score/cpu/mips/idtcpu.h
@@ -60,6 +60,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	UT_VEC	K0BASE			/* utlbmiss vector */
 #define DB_VEC  (K0BASE+0x40)           /* debug vector */
 #define E_VEC	(K0BASE+0x80)		/* exception vector */
+#elif  __mips == 32
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K0BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
 #elif  __mips == 3
 #define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
 #define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
@@ -91,6 +96,100 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	MINCACHE	0x200		/* 512       For 3041. */
 #define	MAXCACHE	0x40000		/* 256*1024   256k */	
 
+#if  __mips == 32
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00010000	/* 32 bit */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#ifndef WAIT
+#define WAIT .word 0x42000020
+#endif /* WAIT */
+
+/* Disabled by joel -- horrible overload of common word.
+#ifndef wait 
+#define wait .word 0x42000020
+#endif wait
+*/
+
+#endif
+
 #if  __mips == 3
 /* R4000 configuration register definitions */
 #define CFG_CM		0x80000000	/* Master-Checker mode */
@@ -253,6 +352,41 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define TLBPGMASK_MASK		0x01ffe000
 #endif
 
+#if  __mips == 32
+#define	N_TLB_ENTRIES	16
+
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define TLBLO_CSHIFT	3
+
+#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define TLBPGMASK_MASK		0x01ffe000
+#endif
+
 #if  __mips == 1
 
 
@@ -383,7 +517,58 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define SR_IE		0x00000001	/* Interrupts enabled */
 #endif
 
+#if  __mips == 32
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define SR_RP		0x08000000      /* Reduced power operation */
+#define SR_FR		0x04000000	/* Additional floating point registers */
+#define SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define SR_BEV		0x00400000	/* Use boot exception vectors */
+#define SR_TS		0x00200000	/* TLB shutdown */
+#define SR_SR		0x00100000	/* Soft reset */
+#define SR_CH		0x00040000	/* Cache hit */
+#define SR_CE		0x00020000	/* Use cache ECC  */
+#define SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
 
+#define SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define SR_KSUSER	0x00000010	/* User mode */
+#define SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define SR_ERL		0x00000004	/* Error level */
+#define SR_EXL		0x00000002	/* Exception level */
+#define SR_IE		0x00000001	/* Interrupts enabled */
+#endif
 
 /*
  * Cause Register
@@ -414,6 +599,12 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	C0_TLBLO1	$3		/* tlb entry low 1 */
 #endif
 
+#if  __mips == 32
+#define	C0_TLBLO0	$2		/* tlb entry low 0 */
+#define	C0_TLBLO1	$3		/* tlb entry low 1 */
+#endif
+
+
 #define	C0_CTXT		$4		/* tlb context */
 
 #if  __mips == 3
@@ -421,6 +612,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_WIRED	$6		/* number of wired tlb entries */
 #endif
 
+#if  __mips == 32
+#define C0_PAGEMASK	$5		/* tlb page mask */
+#define C0_WIRED	$6		/* number of wired tlb entries */
+#endif
+
 #if  __mips == 1
 #define C0_TAR          $6
 #endif
@@ -430,6 +626,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if  __mips == 3
 #define C0_COUNT	$9		/* cycle count */
 #endif
+#if  __mips == 32
+#define C0_COUNT	$9		/* cycle count */
+#endif
 
 #define	C0_TLBHI	$10		/* tlb entry hi */
 
@@ -437,6 +636,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_COMPARE	$11		/* cyccle count comparator  */
 #endif
 
+#if  __mips == 32
+#define C0_COMPARE	$11		/* cyccle count comparator  */
+#endif
+
 #define	C0_SR		$12		/* status register */
 #define	C0_CAUSE	$13		/* exception cause */
 #define	C0_EPC		$14		/* exception pc */
@@ -459,6 +662,20 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_ERRPC	$30		/* cache error pc */
 #endif
 
+#if  __mips == 32
+#define C0_CONFIG	$16		/* configuration register */
+#define C0_LLADDR	$17		/* linked load address */
+#define C0_WATCHLO	$18		/* watchpoint trap register */
+#define C0_WATCHHI	$19		/* watchpoint trap register */
+#define C0_XCTXT    $20     /* extended tlb context */
+#define C0_ECC		$26		/* secondary cache ECC control */
+#define C0_CACHEERR	$27		/* cache error status */
+#define C0_TAGLO	$28		/* cache tag lo */
+#define C0_TAGHI	$29		/* cache tag hi */
+#define C0_ERRPC	$30		/* cache error pc */
+#endif
+
+
 #define C1_REVISION     $0
 #define C1_STATUS       $31
 
@@ -475,3 +692,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* _IDTCPU_H__ */
+
diff --git a/cpukit/score/cpu/mips/iregdef.h b/cpukit/score/cpu/mips/iregdef.h
index 7abb8d59ba..6b6f2e82f8 100644
--- a/cpukit/score/cpu/mips/iregdef.h
+++ b/cpukit/score/cpu/mips/iregdef.h
@@ -229,7 +229,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define	R_TLBLO		73
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO0	73
 #endif
 
@@ -243,7 +243,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define NREGS		81
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO1	81
 #define R_PAGEMASK	82
 #define R_WIRED		83
@@ -298,7 +298,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	R_SP		R_R29
 #define	R_FP		R_R30
 #define	R_RA		R_R31
-
+#define R_SZ 4
 /* disabled for RTEMS */
 #if 0
 /* Ketan added the following */
@@ -329,3 +329,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* __IREGDEF_H__ */
+
diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h
index 0460d34eff..c060bb8091 100644
--- a/cpukit/score/cpu/mips/rtems/asm.h
+++ b/cpukit/score/cpu/mips/rtems/asm.h
@@ -157,3 +157,5 @@ _##name:
 #define R_FP31 	31
 
 #endif
+/* end of include file */
+
diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
index 0e451e7f8f..e1df010d86 100644
--- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
@@ -60,6 +60,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	UT_VEC	K0BASE			/* utlbmiss vector */
 #define DB_VEC  (K0BASE+0x40)           /* debug vector */
 #define E_VEC	(K0BASE+0x80)		/* exception vector */
+#elif  __mips == 32
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K0BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
 #elif  __mips == 3
 #define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
 #define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
@@ -91,6 +96,100 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	MINCACHE	0x200		/* 512       For 3041. */
 #define	MAXCACHE	0x40000		/* 256*1024   256k */	
 
+#if  __mips == 32
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00010000	/* 32 bit */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#ifndef WAIT
+#define WAIT .word 0x42000020
+#endif /* WAIT */
+
+/* Disabled by joel -- horrible overload of common word.
+#ifndef wait 
+#define wait .word 0x42000020
+#endif wait
+*/
+
+#endif
+
 #if  __mips == 3
 /* R4000 configuration register definitions */
 #define CFG_CM		0x80000000	/* Master-Checker mode */
@@ -253,6 +352,41 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define TLBPGMASK_MASK		0x01ffe000
 #endif
 
+#if  __mips == 32
+#define	N_TLB_ENTRIES	16
+
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define TLBLO_CSHIFT	3
+
+#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define TLBPGMASK_MASK		0x01ffe000
+#endif
+
 #if  __mips == 1
 
 
@@ -383,7 +517,58 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define SR_IE		0x00000001	/* Interrupts enabled */
 #endif
 
+#if  __mips == 32
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define SR_RP		0x08000000      /* Reduced power operation */
+#define SR_FR		0x04000000	/* Additional floating point registers */
+#define SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define SR_BEV		0x00400000	/* Use boot exception vectors */
+#define SR_TS		0x00200000	/* TLB shutdown */
+#define SR_SR		0x00100000	/* Soft reset */
+#define SR_CH		0x00040000	/* Cache hit */
+#define SR_CE		0x00020000	/* Use cache ECC  */
+#define SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
 
+#define SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define SR_KSUSER	0x00000010	/* User mode */
+#define SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define SR_ERL		0x00000004	/* Error level */
+#define SR_EXL		0x00000002	/* Exception level */
+#define SR_IE		0x00000001	/* Interrupts enabled */
+#endif
 
 /*
  * Cause Register
@@ -414,6 +599,12 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	C0_TLBLO1	$3		/* tlb entry low 1 */
 #endif
 
+#if  __mips == 32
+#define	C0_TLBLO0	$2		/* tlb entry low 0 */
+#define	C0_TLBLO1	$3		/* tlb entry low 1 */
+#endif
+
+
 #define	C0_CTXT		$4		/* tlb context */
 
 #if  __mips == 3
@@ -421,6 +612,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_WIRED	$6		/* number of wired tlb entries */
 #endif
 
+#if  __mips == 32
+#define C0_PAGEMASK	$5		/* tlb page mask */
+#define C0_WIRED	$6		/* number of wired tlb entries */
+#endif
+
 #if  __mips == 1
 #define C0_TAR          $6
 #endif
@@ -430,6 +626,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if  __mips == 3
 #define C0_COUNT	$9		/* cycle count */
 #endif
+#if  __mips == 32
+#define C0_COUNT	$9		/* cycle count */
+#endif
 
 #define	C0_TLBHI	$10		/* tlb entry hi */
 
@@ -437,6 +636,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_COMPARE	$11		/* cyccle count comparator  */
 #endif
 
+#if  __mips == 32
+#define C0_COMPARE	$11		/* cyccle count comparator  */
+#endif
+
 #define	C0_SR		$12		/* status register */
 #define	C0_CAUSE	$13		/* exception cause */
 #define	C0_EPC		$14		/* exception pc */
@@ -459,6 +662,20 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define C0_ERRPC	$30		/* cache error pc */
 #endif
 
+#if  __mips == 32
+#define C0_CONFIG	$16		/* configuration register */
+#define C0_LLADDR	$17		/* linked load address */
+#define C0_WATCHLO	$18		/* watchpoint trap register */
+#define C0_WATCHHI	$19		/* watchpoint trap register */
+#define C0_XCTXT    $20     /* extended tlb context */
+#define C0_ECC		$26		/* secondary cache ECC control */
+#define C0_CACHEERR	$27		/* cache error status */
+#define C0_TAGLO	$28		/* cache tag lo */
+#define C0_TAGHI	$29		/* cache tag hi */
+#define C0_ERRPC	$30		/* cache error pc */
+#endif
+
+
 #define C1_REVISION     $0
 #define C1_STATUS       $31
 
@@ -475,3 +692,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* _IDTCPU_H__ */
+
diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
index 7abb8d59ba..6b6f2e82f8 100644
--- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h
+++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
@@ -229,7 +229,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define	R_TLBLO		73
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO0	73
 #endif
 
@@ -243,7 +243,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #if __mips == 1
 #define NREGS		81
 #endif
-#if  __mips == 3
+#if  (__mips == 3 ) || ( __mips == 32)
 #define	R_TLBLO1	81
 #define R_PAGEMASK	82
 #define R_WIRED		83
@@ -298,7 +298,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define	R_SP		R_R29
 #define	R_FP		R_R30
 #define	R_RA		R_R31
-
+#define R_SZ 4
 /* disabled for RTEMS */
 #if 0
 /* Ketan added the following */
@@ -329,3 +329,4 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #endif
 
 #endif /* __IREGDEF_H__ */
+
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index a91e8307cd..279e06eb2f 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -1,7 +1,3 @@
-/**
- * @file rtems/score/cpu.h
- */
-
 /*
  *  Mips CPU Dependent Header File
  *
@@ -52,6 +48,16 @@ extern "C" {
 #include <rtems/score/types.h>
 #endif
 
+#ifndef TRUE
+#define TRUE 1
+#warning "TRUE was not defined, assuming default of 1"
+#endif
+#ifndef FALSE
+#define FALSE 0
+#warning "FALSE was not defined, assuming default of 0"
+#endif
+
+
 /* conditional compilation parameters */
 
 /*
@@ -187,6 +193,13 @@ extern "C" {
  *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
  *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
+ *  So far, the only CPU in which this option has been used is the
+ *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
+ *  floating point registers to perform integer multiplies.  If
+ *  a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
  *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  */
 
@@ -314,7 +327,10 @@ extern "C" {
 #define CPU_MODES_INTERRUPT_MASK   0x000000ff
 
 /*
- *  Processor defined structures required for cpukit/score.
+ *  Processor defined structures
+ *
+ *  Examples structures include the descriptor tables from the i386
+ *  and the processor control structure on the i960ca.
  */
 
 /* may need to put some structures here.  */
@@ -357,7 +373,7 @@ extern "C" {
 #ifndef ASSEMBLY_ONLY
 
 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
-#if __mips == 1
+#if (__mips == 1) || (__mips == 32)
 #define __MIPS_REGISTER_TYPE     uint32_t  
 #define __MIPS_FPU_REGISTER_TYPE uint32_t  
 #elif __mips == 3
@@ -534,7 +550,7 @@ typedef struct
   __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
                                   /*         all MIPS CPUs (at least MGV) */
 #endif
-#if  __mips == 3
+#if  (__mips == 3) || (__mips == 32)
   __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
                                   /*         all MIPS CPUs (at least MGV) */
 #endif
@@ -550,7 +566,7 @@ typedef struct
   __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
   __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
   /* end of __mips == 1 so NREGS == 81 */
-#if  __mips == 3
+#if  (__mips == 3) || (__mips == 32)
   __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
   __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
   __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
@@ -685,7 +701,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
  *  that a "reasonable" small application should not have any problems.
  */
 
-#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(uint32_t  ))
+#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
 
 
 /*
@@ -848,8 +864,8 @@ void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
  */
 
 
-#if __mips == 3
-#define _INTON	(SR_EXL | SR_IE)
+#if (__mips == 3) || (__mips == 32)
+#define _INTON	        SR_IE
 #define _EXTRABITS      0
 #endif
 #if __mips == 1
@@ -865,7 +881,7 @@ void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
   	_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
   	(_the_context)->sp = _stack_tmp; \
   	(_the_context)->fp = _stack_tmp; \
-	(_the_context)->ra = (uint64_t  )_entry_point; \
+	(_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
 	(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
 						       0x300 | \
 						       ((_intlvl & 1)?_INTON:0)) ) | \
diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h
index 341dd89d3e..ab75c9a8d1 100644
--- a/cpukit/score/cpu/mips/rtems/score/mips.h
+++ b/cpukit/score/cpu/mips/rtems/score/mips.h
@@ -30,7 +30,7 @@ extern "C" {
  *  NOTE: XXX what about SR_ERL?
  */
 
-#if __mips == 3
+#if (__mips == 3) || (__mips == 32)
 #ifdef ASM
 #define SR_INTERRUPT_ENABLE_BITS 0x01
 #else
@@ -59,9 +59,10 @@ extern "C" {
 #define MIPS_HAS_FPU 1
 #endif 
 
+
 #if (__mips == 1)
 #define CPU_MODEL_NAME  "ISA Level 1 or 2"
-#elif (__mips == 3)
+#elif (__mips == 3) || (__mips == 32)
 #if defined(__mips64)
 #define CPU_MODEL_NAME  "ISA Level 4"
 #else
@@ -218,6 +219,8 @@ extern "C" {
  *  Access FCR31
  */
 
+#if ( MIPS_HAS_FPU == 1 )
+
 #define mips_get_fcr31( _x ) \
   do { \
     asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
@@ -230,6 +233,12 @@ extern "C" {
     asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
   } while(0)
 
+#else
+
+#define mips_get_fcr31( _x )
+#define mips_set_fcr31( _x )
+
+#endif
 
 /*
  *  Manipulate interrupt mask 
@@ -271,3 +280,4 @@ extern "C" {
 #endif
 
 #endif /* ! _INCLUDE_MIPS_h */
+/* end of include file */