diff options
author | Hesham ALMatary <heshamelmatary@gmail.com> | 2021-09-30 16:33:48 -0500 |
---|---|---|
committer | Joel Sherrill <joel@rtems.org> | 2021-10-13 14:45:37 -0500 |
commit | 0f62af0ef88606773582643fdc6eae01e26a103c (patch) | |
tree | 7eb0ebab1c46e57e92934d1322b86d4e9ef2e0df /cpukit/score/cpu/microblaze/cpu.c | |
parent | score: Add MicroBlaze port (diff) | |
download | rtems-0f62af0ef88606773582643fdc6eae01e26a103c.tar.bz2 |
bsps: Add MicroBlaze FPGA BSP
Diffstat (limited to 'cpukit/score/cpu/microblaze/cpu.c')
-rw-r--r-- | cpukit/score/cpu/microblaze/cpu.c | 47 |
1 files changed, 40 insertions, 7 deletions
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c index 27dd69b9fb..ca4a3ec2f6 100644 --- a/cpukit/score/cpu/microblaze/cpu.c +++ b/cpukit/score/cpu/microblaze/cpu.c @@ -1,14 +1,28 @@ /* - * MicroBlaze CPU Dependent Source - * + * Copyright (c) 2015, Hesham Almatary * COPYRIGHT (c) 1989-2011. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id: cpu.c,v 1.24 2010/03/27 15:02:26 joel Exp $ + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifdef HAVE_CONFIG_H @@ -42,6 +56,25 @@ void _CPU_Initialize(void) /* FP context initialization support goes here */ } +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +) +{ + uint32_t stack = ((uint32_t) stack_area_begin); + uint32_t stack_high = stack + stack_area_size; + + memset(context, 0, sizeof(*context)); + + context->r[0] = stack_high; + context->r[3] = (uint32_t) entry_point; +} + /*PAGE * * _CPU_ISR_Get_level |