bsps: Add MicroBlaze FPGA BSP

5 files changed, 238 insertions, 79 deletions

diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
index 27dd69b9fb..ca4a3ec2f6 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -1,14 +1,28 @@
 /*
- *  MicroBlaze CPU Dependent Source
- *
+ *  Copyright (c) 2015, Hesham Almatary
  *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id: cpu.c,v 1.24 2010/03/27 15:02:26 joel Exp $
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifdef HAVE_CONFIG_H
@@ -42,6 +56,25 @@ void _CPU_Initialize(void)
   /* FP context initialization support goes here */
 }
 
+void _CPU_Context_Initialize(
+  Context_Control *context,
+  void *stack_area_begin,
+  size_t stack_area_size,
+  uint32_t new_level,
+  void (*entry_point)( void ),
+  bool is_fp,
+  void *tls_area
+)
+{
+  uint32_t stack = ((uint32_t) stack_area_begin);
+  uint32_t stack_high = stack + stack_area_size;
+
+  memset(context, 0, sizeof(*context));
+
+  context->r[0] = stack_high;
+  context->r[3] = (uint32_t) entry_point;
+}
+
 /*PAGE
  *
  *  _CPU_ISR_Get_level
diff --git a/cpukit/score/cpu/microblaze/microblaze-context-switch.S b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
new file mode 100644
index 0000000000..e2ec760080
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
@@ -0,0 +1,88 @@
+/*
+ *  Copyright (c) 2015, Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_switch)
+PUBLIC(_CPU_Context_restore)
+PUBLIC(_CPU_Context_restore_fp)
+PUBLIC(_CPU_Context_save_fp)
+
+SYM(_CPU_Context_switch):
+    swi     r1,  r5, 0
+    swi     r13, r5, 4
+    swi     r14, r5, 8
+    swi     r15, r5, 12
+    swi     r16, r5, 16
+    swi     r17, r5, 20
+    swi     r18, r5, 24
+    swi     r19, r5, 28
+    swi     r20, r5, 32
+    swi     r21, r5, 36
+    swi     r22, r5, 40
+    swi     r23, r5, 44
+    swi     r24, r5, 48
+    swi     r25, r5, 52
+    swi     r26, r5, 56
+    swi     r27, r5, 60
+    swi     r28, r5, 64
+    swi     r29, r5, 68
+    swi     r30, r5, 72
+    swi     r31, r5, 76
+
+SYM(restore):
+    lwi     r1,  r6, 0
+    lwi     r13, r6, 4
+    lwi     r14, r6, 8
+    lwi     r15, r6, 12
+    lwi     r16, r6, 16
+    lwi     r17, r6, 20
+    lwi     r18, r6, 24
+    lwi     r19, r6, 28
+    lwi     r20, r6, 32
+    lwi     r21, r6, 36
+    lwi     r22, r6, 40
+    lwi     r23, r6, 44
+    lwi     r24, r6, 48
+    lwi     r25, r6, 52
+    lwi     r26, r6, 56
+    lwi     r27, r6, 60
+    lwi     r28, r6, 64
+    lwi     r29, r6, 68
+    lwi     r30, r6, 72
+    lwi     r31, r6, 76
+
+    rtsd    r15, 8
+
+SYM(_CPU_Context_restore):
+    add   r6, r5, r0
+    brai  restore
diff --git a/cpukit/score/cpu/microblaze/rtems/asm.h b/cpukit/score/cpu/microblaze/rtems/asm.h
index 13609d2d70..b5a8702f02 100644
--- a/cpukit/score/cpu/microblaze/rtems/asm.h
+++ b/cpukit/score/cpu/microblaze/rtems/asm.h
@@ -19,6 +19,7 @@
  *  notice.  This file is freely distributable as long as the source
  *  of the file is noted.  This file is:
  *
+ *  Copyright (c) 2015, Hesham Almatary
  *  COPYRIGHT (c) 1994-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -36,7 +37,6 @@
 #define ASM
 #endif
 #include <rtems/score/cpuopts.h>
-#include <rtems/score/no_cpu.h>
 
 #ifndef __USER_LABEL_PREFIX__
 /**
diff --git a/cpukit/score/cpu/microblaze/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/rtems/score/cpu.h
index 4947045c2c..d9f9e8add5 100644
--- a/cpukit/score/cpu/microblaze/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/rtems/score/cpu.h
@@ -1,3 +1,30 @@
+/*
+ *  Copyright (c) 2015, Hesham Almatary
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
 /**
  * @file rtems/score/cpu.h
  */
@@ -19,17 +46,6 @@
  *    add CPU family specific information in this section
  */
 
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id: cpu.h,v 1.35 2010/10/21 22:14:20 joel Exp $
- */
-
 #ifndef _RTEMS_SCORE_CPU_H
 #define _RTEMS_SCORE_CPU_H
 
@@ -464,19 +480,7 @@ extern "C" {
  *  to another.
  */
 typedef struct {
-    /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved at a context switch.
-     */
-    uint32_t   some_integer_register;
-    /** This field is a hint that a port will have a number of system
-     *  registers that need to be saved at a context switch.
-     */
-    uint32_t   some_system_register;
-
-    /** This field is a hint that a port will have a register that
-     *  is the stack pointer.
-     */
-    uint32_t   stack_pointer;
+    uint32_t r[32];
 } Context_Control;
 
 /**
@@ -489,7 +493,7 @@ typedef struct {
  *  @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
-  (_context)->stack_pointer
+  (_context)->r[0]
 
 /**
  *  @ingroup CPUContext Management
@@ -799,43 +803,32 @@ uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
-/* Context handler macros */
-
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
-                                 _isr, _entry_point, _is_fp ) \
-  { \
-  }
+ * @brief Initializes the CPU context.
+ *
+ * The following steps are performed:
+ *  - setting a starting address
+ *  - preparing the stack
+ *  - preparing the stack and frame pointers
+ *  - setting the proper interrupt level in the context
+ *
+ * @param[in] context points to the context area
+ * @param[in] stack_area_begin is the low address of the allocated stack area
+ * @param[in] stack_area_size is the size of the stack area in bytes
+ * @param[in] new_level is the interrupt level for the task
+ * @param[in] entry_point is the task's entry point
+ * @param[in] is_fp is set to @c true if the task is a floating point task
+ * @param[in] tls_area is the thread-local storage (TLS) area
+ */
+void _CPU_Context_Initialize(
+  Context_Control *context,
+  void *stack_area_begin,
+  size_t stack_area_size,
+  uint32_t new_level,
+  void (*entry_point)( void ),
+  bool is_fp,
+  void *tls_area
+);
 
 /**
  *  This routine is responsible for somehow restarting the currently
@@ -916,9 +909,9 @@ uint32_t   _CPU_ISR_Get_level( void );
  *
  *  XXX document implementation including references if appropriate
  */
-#define _CPU_Fatal_halt( _error ) \
-  { \
-  }
+#define _CPU_Fatal_halt(_source, _error ) \
+        printk("Fatal Error %d.%d Halted\n",_source, _error); \
+        for(;;)
 
 /* end of Fatal Error manager macros */
 
@@ -1059,6 +1052,21 @@ uint32_t   _CPU_ISR_Get_level( void );
 
 #endif
 
+#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
+#define CPU_TIMESTAMP_USE_INT64 TRUE
+#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
+
+typedef struct {
+/* There is no CPU specific per-CPU state */
+} CPU_Per_CPU_control;
+
+#define CPU_SIZEOF_POINTER 4
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
+typedef struct {
+  uint32_t r[32];
+} CPU_Exception_frame;
+
 /* end of Priority handler macros */
 
 /* functions */
@@ -1256,6 +1264,15 @@ static inline uint32_t CPU_swap_u32(
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
 
+typedef uint32_t CPU_Counter_ticks;
+
+CPU_Counter_ticks _CPU_Counter_read( void );
+
+CPU_Counter_ticks _CPU_Counter_difference(
+  CPU_Counter_ticks second,
+  CPU_Counter_ticks first
+);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h b/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
index 3878d411c4..19e26314e8 100644
--- a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
+++ b/cpukit/score/cpu/microblaze/rtems/score/microblaze.h
@@ -1,20 +1,41 @@
 /*
+ *  Copyright (c) 2015, Hesham Almatary
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
  *  This file sets up basic CPU dependency settings based on
  *  compiler settings.  For example, it can determine if
  *  floating point is available.  This particular implementation
  *  is specified to the NO CPU port.
  *
- *  COPYRIGHT (c) 1989-2011.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
  *  $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $
  *
  */
 
+
 #ifndef _RTEMS_SCORE_NO_CPU_H
 #define _RTEMS_SCORE_NO_CPU_H