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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-06-05 14:30:07 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-06-05 14:30:07 +0000 |
| commit | 2fd427c7926495b3e1ad3c7aaaa489f8cde95573 (patch) | |
| tree | 7ff7f4fc896909274f626ceaf23693571cf3cd4e /cpukit/score/cpu/c4x | |
| parent | 2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
| download | rtems-2fd427c7926495b3e1ad3c7aaaa489f8cde95573.tar.bz2 | |
2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>
* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
parameter to indicate that the port uses the Simple Vectored
Interrupt model or the Programmable Interrupt Controller Model. The
PIC model is implemented primarily in the BSP and it is responsible
for all memory allocation.
Diffstat (limited to 'cpukit/score/cpu/c4x')
| -rw-r--r-- | cpukit/score/cpu/c4x/ChangeLog | 8 | ||||
| -rw-r--r-- | cpukit/score/cpu/c4x/rtems/score/cpu.h | 13 |
2 files changed, 21 insertions, 0 deletions
diff --git a/cpukit/score/cpu/c4x/ChangeLog b/cpukit/score/cpu/c4x/ChangeLog index ba86673678..ec0d81bc7a 100644 --- a/cpukit/score/cpu/c4x/ChangeLog +++ b/cpukit/score/cpu/c4x/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu.h b/cpukit/score/cpu/c4x/rtems/score/cpu.h index 612d6c5668..9d49590f25 100644 --- a/cpukit/score/cpu/c4x/rtems/score/cpu.h +++ b/cpukit/score/cpu/c4x/rtems/score/cpu.h @@ -110,6 +110,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * C4x Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. |