diff options
22 files changed, 227 insertions, 1 deletions
diff --git a/cpukit/score/cpu/avr/ChangeLog b/cpukit/score/cpu/avr/ChangeLog index 1cdcfe8e74..ab5d0a6981 100644 --- a/cpukit/score/cpu/avr/ChangeLog +++ b/cpukit/score/cpu/avr/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h index b993c336d5..d92cfb1c9d 100644 --- a/cpukit/score/cpu/avr/rtems/score/cpu.h +++ b/cpukit/score/cpu/avr/rtems/score/cpu.h @@ -156,6 +156,19 @@ extern "C" { #define CPU_ISR_PASSES_FRAME_POINTER 0 /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * AVR Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does the CPU have hardware floating point? * * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. diff --git a/cpukit/score/cpu/bfin/ChangeLog b/cpukit/score/cpu/bfin/ChangeLog index 347d9c486e..710bddb153 100644 --- a/cpukit/score/cpu/bfin/ChangeLog +++ b/cpukit/score/cpu/bfin/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-20 Joel Sherrill <joel.sherrill@OARcorp.com> * rtems/score/cpu.h: Use correct register name. diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h index dc9cba2cde..eab64595ce 100644 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h @@ -107,6 +107,19 @@ extern "C" { */ #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * BFIN Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + /** * Does this CPU have hardware support for a dedicated interrupt stack? * diff --git a/cpukit/score/cpu/c4x/ChangeLog b/cpukit/score/cpu/c4x/ChangeLog index ba86673678..ec0d81bc7a 100644 --- a/cpukit/score/cpu/c4x/ChangeLog +++ b/cpukit/score/cpu/c4x/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu.h b/cpukit/score/cpu/c4x/rtems/score/cpu.h index 612d6c5668..9d49590f25 100644 --- a/cpukit/score/cpu/c4x/rtems/score/cpu.h +++ b/cpukit/score/cpu/c4x/rtems/score/cpu.h @@ -110,6 +110,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * C4x Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. diff --git a/cpukit/score/cpu/h8300/ChangeLog b/cpukit/score/cpu/h8300/ChangeLog index 3e318a434a..5d61ee2840 100644 --- a/cpukit/score/cpu/h8300/ChangeLog +++ b/cpukit/score/cpu/h8300/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h index 4843e09871..2957e38608 100644 --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h +++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h @@ -110,6 +110,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * H8300 Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. diff --git a/cpukit/score/cpu/m68k/ChangeLog b/cpukit/score/cpu/m68k/ChangeLog index e7615cca4e..5b57dfea94 100644 --- a/cpukit/score/cpu/m68k/ChangeLog +++ b/cpukit/score/cpu/m68k/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2008-01-22 Joel Sherrill <joel.sherrill@OARcorp.com> * cpu_asm.S: Spacing and comment alignment. diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h index 1d55b8bb68..fcdfeffd31 100644 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h @@ -34,6 +34,19 @@ extern "C" { #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * M68K Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Use the m68k's hardware interrupt stack support and have the * interrupt manager allocate the memory for it. */ diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index da56fd86ea..5689ee26a9 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2008-06-04 Joel Sherrill <joel.sherrill@OARcorp.com> * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index 863866fc3d..7c676d2a4a 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -124,6 +124,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * MIPS Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. @@ -675,7 +688,6 @@ extern unsigned int mips_interrupt_number_of_vectors; #define CPU_STACK_MINIMUM_SIZE (8 * 1024) - /* * CPU's worst alignment requirement for data types on a byte boundary. This * alignment does not take into account the requirements for the stack. diff --git a/cpukit/score/cpu/nios2/ChangeLog b/cpukit/score/cpu/nios2/ChangeLog index 948d5719d6..a652068ea2 100644 --- a/cpukit/score/cpu/nios2/ChangeLog +++ b/cpukit/score/cpu/nios2/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h index 1372fb9dd7..f35f8844ab 100644 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h @@ -119,6 +119,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE /** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. diff --git a/cpukit/score/cpu/no_cpu/ChangeLog b/cpukit/score/cpu/no_cpu/ChangeLog index 3403063650..c4a42eb055 100644 --- a/cpukit/score/cpu/no_cpu/ChangeLog +++ b/cpukit/score/cpu/no_cpu/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2008-01-29 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Remove most doxygen warnings. diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h index d97800d5ac..73d063aad1 100644 --- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h +++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @@ -120,6 +120,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE /** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. diff --git a/cpukit/score/cpu/sh/ChangeLog b/cpukit/score/cpu/sh/ChangeLog index d06990665c..c884c71720 100644 --- a/cpukit/score/cpu/sh/ChangeLog +++ b/cpukit/score/cpu/sh/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h index 8870833857..2294a57c6d 100644 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ b/cpukit/score/cpu/sh/rtems/score/cpu.h @@ -83,6 +83,19 @@ extern "C" { #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * SH Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does RTEMS manage a dedicated interrupt stack in software? * * If TRUE, then a stack is allocated in _ISR_Handler_initialization. diff --git a/cpukit/score/cpu/sparc/ChangeLog b/cpukit/score/cpu/sparc/ChangeLog index 293e4d5fc8..997fc6774a 100644 --- a/cpukit/score/cpu/sparc/ChangeLog +++ b/cpukit/score/cpu/sparc/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2008-02-20 Alexandru Bugnar <a-bugnar@criticalsoftware.com> PR 1278/cpukit diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index e9678420af..3d3e04a185 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -69,6 +69,19 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * SPARC Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. diff --git a/cpukit/score/cpu/unix/ChangeLog b/cpukit/score/cpu/unix/ChangeLog index c582284e9f..571f638759 100644 --- a/cpukit/score/cpu/unix/ChangeLog +++ b/cpukit/score/cpu/unix/ChangeLog @@ -1,3 +1,11 @@ +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. diff --git a/cpukit/score/cpu/unix/rtems/score/cpu.h b/cpukit/score/cpu/unix/rtems/score/cpu.h index 567a52bddf..925bc8e5f4 100644 --- a/cpukit/score/cpu/unix/rtems/score/cpu.h +++ b/cpukit/score/cpu/unix/rtems/score/cpu.h @@ -106,6 +106,15 @@ extern "C" { #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE /* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. |