Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC.  Other
architectures need more work.

1 files changed, 44 insertions, 0 deletions

diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
new file mode 100644
index 0000000000..afdfd99d8b
--- /dev/null
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/score/thread.h>
+#include <rtems/score/percpu.h>
+
+#ifndef RTEMS_SMP
+
+void __attribute__((naked)) __aeabi_read_tp(void);
+
+void __attribute__((naked)) __aeabi_read_tp(void)
+{
+  __asm__ volatile (
+    "ldr r0, =_Per_CPU_Information\n"
+    "ldr r0, [r0, %[executingoff]]\n"
+#if defined(__thumb__) && !defined(__thumb2__)
+    "add r0, %[tlsareaoff]\n"
+    "ldr r0, [r0]\n"
+#else
+    "ldr r0, [r0, %[tlsareaoff]]\n"
+#endif
+    "bx lr\n"
+    :
+    : [executingoff] "I" (offsetof(Per_CPU_Control, executing)),
+      [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area))
+  );
+}
+
+#endif /* RTEMS_SMP */