Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC.  Other
architectures need more work.

8 files changed, 131 insertions, 3 deletions

diff --git a/cpukit/score/cpu/arm/Makefile.am b/cpukit/score/cpu/arm/Makefile.am
index edd72480bd..fe97e03e29 100644
--- a/cpukit/score/cpu/arm/Makefile.am
+++ b/cpukit/score/cpu/arm/Makefile.am
@@ -15,6 +15,8 @@ include_rtems_score_HEADERS += rtems/score/cpusmplock.h
 noinst_LIBRARIES = libscorecpu.a
 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
 libscorecpu_a_SOURCES =
+libscorecpu_a_SOURCES += __aeabi_read_tp.c
+libscorecpu_a_SOURCES += __tls_get_addr.c
 libscorecpu_a_SOURCES += cpu.c
 libscorecpu_a_SOURCES += cpu_asm.S
 libscorecpu_a_SOURCES += arm-context-validate.S
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
new file mode 100644
index 0000000000..afdfd99d8b
--- /dev/null
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/score/thread.h>
+#include <rtems/score/percpu.h>
+
+#ifndef RTEMS_SMP
+
+void __attribute__((naked)) __aeabi_read_tp(void);
+
+void __attribute__((naked)) __aeabi_read_tp(void)
+{
+  __asm__ volatile (
+    "ldr r0, =_Per_CPU_Information\n"
+    "ldr r0, [r0, %[executingoff]]\n"
+#if defined(__thumb__) && !defined(__thumb2__)
+    "add r0, %[tlsareaoff]\n"
+    "ldr r0, [r0]\n"
+#else
+    "ldr r0, [r0, %[tlsareaoff]]\n"
+#endif
+    "bx lr\n"
+    :
+    : [executingoff] "I" (offsetof(Per_CPU_Control, executing)),
+      [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area))
+  );
+}
+
+#endif /* RTEMS_SMP */
diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c
new file mode 100644
index 0000000000..cd046518e1
--- /dev/null
+++ b/cpukit/score/cpu/arm/__tls_get_addr.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/score/thread.h>
+#include <rtems/score/tls.h>
+
+#include <assert.h>
+
+void *__tls_get_addr(const TLS_Index *ti);
+
+void *__tls_get_addr(const TLS_Index *ti)
+{
+  const Thread_Control *executing = _Thread_Get_executing();
+  void *tls_block = (char *) executing->Start.tls_area
+    + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+
+  assert(ti->module == 1);
+
+  return (char *) tls_block + ti->offset;
+}
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
index 892df4d8c8..13aa0a9b19 100644
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
@@ -26,6 +26,7 @@
 
 #include <rtems/score/armv7m.h>
 #include <rtems/score/thread.h>
+#include <rtems/score/tls.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
@@ -35,7 +36,8 @@ void _CPU_Context_Initialize(
   size_t stack_area_size,
   uint32_t new_level,
   void (*entry_point)( void ),
-  bool is_fp
+  bool is_fp,
+  void *tls_area
 )
 {
   char *stack_area_end = (char *) stack_area_begin + stack_area_size;
@@ -44,6 +46,10 @@ void _CPU_Context_Initialize(
 
   context->register_lr = entry_point;
   context->register_sp = stack_area_end;
+
+  if ( tls_area != NULL ) {
+    _TLS_TCB_at_area_begin_initialize( tls_area );
+  }
 }
 
 #endif /* ARM_MULTILIB_ARCH_V7M */
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index 1c1fe5d3de..c3f071df55 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -32,6 +32,7 @@
 #include <rtems/score/isr.h>
 #include <rtems/score/wkspace.h>
 #include <rtems/score/thread.h>
+#include <rtems/score/tls.h>
 #include <rtems/score/cpu.h>
 
 #ifdef ARM_MULTILIB_VFP_D32
@@ -41,6 +42,14 @@
   );
 #endif
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+  RTEMS_STATIC_ASSERT(
+    offsetof( Context_Control, thread_id )
+      == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
+    ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
+  );
+#endif
+
 RTEMS_STATIC_ASSERT(
   sizeof( CPU_Exception_frame ) == ARM_EXCEPTION_FRAME_SIZE,
   ARM_EXCEPTION_FRAME_SIZE
@@ -71,13 +80,22 @@ void _CPU_Context_Initialize(
   size_t stack_area_size,
   uint32_t new_level,
   void (*entry_point)( void ),
-  bool is_fp
+  bool is_fp,
+  void *tls_area
 )
 {
   the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
   the_context->register_lr = (uint32_t) entry_point;
   the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
     | arm_cpu_mode;
+
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+  the_context->thread_id = (uint32_t) tls_area;
+#endif
+
+  if ( tls_area != NULL ) {
+    _TLS_TCB_at_area_begin_initialize( tls_area );
+  }
 }
 
 /* Preprocessor magic for stringification of x */
diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index 7fb4062d50..1771ddd661 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -62,12 +62,22 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch)
 	vstm	r3, {d8-d15}
 #endif
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+	mrc	p15, 0, r3, c13, c0, 3
+	str	r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
+#endif
+
 /* Start restoring context */
 _restore:
 #ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
 	clrex
 #endif
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+	ldr	r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
+	mcr	p15, 0, r3, c13, c0, 3
+#endif
+
 #ifdef ARM_MULTILIB_VFP_D32
 	add	r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
 	vldm	r3, {d8-d15}
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
index 608f753d11..3e428f9201 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -44,6 +44,11 @@ extern "C" {
   #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
 #endif
 
+#if defined(__ARM_ARCH_7A__) \
+  || defined(__ARM_ARCH_7R__)
+  #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+#endif
+
 #if defined(__ARM_NEON__)
   #define ARM_MULTILIB_VFP_D32
 #elif !defined(__SOFTFP__)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 2d9b5d50b6..216f39f862 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -212,6 +212,10 @@
 
 /** @} */
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
+#endif
+
 #ifdef ARM_MULTILIB_VFP_D32
   #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
 #endif
@@ -267,6 +271,9 @@ typedef struct {
 #else
   void *register_sp;
 #endif
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+  uint32_t thread_id;
+#endif
 #ifdef ARM_MULTILIB_VFP_D32
   uint64_t register_d8;
   uint64_t register_d9;
@@ -400,7 +407,8 @@ void _CPU_Context_Initialize(
   size_t stack_area_size,
   uint32_t new_level,
   void (*entry_point)( void ),
-  bool is_fp
+  bool is_fp,
+  void *tls_area
 );
 
 #define _CPU_Context_Get_SP( _context ) \