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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2020-09-22 08:31:34 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2020-10-05 16:11:39 -0500 |
| commit | 8387c52e476e18c42d5f3986e01cbb1916f13a2c (patch) | |
| tree | ca9219330ea133ec66de05c7fe56fa59903ec3ad /cpukit/include/rtems/score/tls.h | |
| parent | spmsgq_err01: Use correct max values and fix 64bit (diff) | |
| download | rtems-8387c52e476e18c42d5f3986e01cbb1916f13a2c.tar.bz2 | |
score: Add AArch64 port
This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
Diffstat (limited to 'cpukit/include/rtems/score/tls.h')
| -rw-r--r-- | cpukit/include/rtems/score/tls.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h index 65a49d87be..57063990e7 100644 --- a/cpukit/include/rtems/score/tls.h +++ b/cpukit/include/rtems/score/tls.h @@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block { struct TLS_Thread_control_block *tcb; #else /* !__i386__ */ TLS_Dynamic_thread_vector *dtv; -#if CPU_SIZEOF_POINTER == 4 +/* + * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS + * data segment and indexes into it accordingly for TLS variable addresses. + */ +#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8) uintptr_t reserved; #endif #endif /* __i386__ */ |