From 8387c52e476e18c42d5f3986e01cbb1916f13a2c Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Tue, 22 Sep 2020 08:31:34 -0500 Subject: score: Add AArch64 port This adds a CPU port for AArch64(ARMv8) with support for exceptions and interrupts. --- cpukit/include/rtems/score/tls.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'cpukit/include/rtems/score/tls.h') diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h index 65a49d87be..57063990e7 100644 --- a/cpukit/include/rtems/score/tls.h +++ b/cpukit/include/rtems/score/tls.h @@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block { struct TLS_Thread_control_block *tcb; #else /* !__i386__ */ TLS_Dynamic_thread_vector *dtv; -#if CPU_SIZEOF_POINTER == 4 +/* + * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS + * data segment and indexes into it accordingly for TLS variable addresses. + */ +#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8) uintptr_t reserved; #endif #endif /* __i386__ */ -- cgit v1.2.3