dev/sc16is752: Add name space for field names.

The field names for the registers generated a name collision (MSR_RI on
the power pc). This patch adds a SC16IS752_ prefix for all field names.

Closes #3501.

1 files changed, 54 insertions, 54 deletions

diff --git a/cpukit/dev/serial/sc16is752-regs.h b/cpukit/dev/serial/sc16is752-regs.h
index 21d425a118..b07e489a3e 100644
--- a/cpukit/dev/serial/sc16is752-regs.h
+++ b/cpukit/dev/serial/sc16is752-regs.h
@@ -52,76 +52,76 @@ extern "C" {
 #define SC16IS752_XOFF2 0x7
 
 /* FCR */
-#define FCR_FIFO_EN        0x01
-#define FCR_RX_FIFO_RST    0x02
-#define FCR_TX_FIFO_RST    0x04
-#define FCR_TX_FIFO_TRG_8  0x00
-#define FCR_TX_FIFO_TRG_16 0x10
-#define FCR_TX_FIFO_TRG_32 0x20
-#define FCR_TX_FIFO_TRG_56 0x30
-#define FCR_RX_FIFO_TRG_8  0x00
-#define FCR_RX_FIFO_TRG_16 0x40
-#define FCR_RX_FIFO_TRG_56 0x80
-#define FCR_RX_FIFO_TRG_60 0xc0
+#define SC16IS752_FCR_FIFO_EN        0x01
+#define SC16IS752_FCR_RX_FIFO_RST    0x02
+#define SC16IS752_FCR_TX_FIFO_RST    0x04
+#define SC16IS752_FCR_TX_FIFO_TRG_8  0x00
+#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10
+#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20
+#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30
+#define SC16IS752_FCR_RX_FIFO_TRG_8  0x00
+#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40
+#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80
+#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0
 
 /* EFCR */
-#define EFCR_RS485_ENABLE (1u << 0)
-#define EFCR_RX_DISABLE (1u << 1)
-#define EFCR_TX_DISABLE (1u << 2)
+#define SC16IS752_EFCR_RS485_ENABLE (1u << 0)
+#define SC16IS752_EFCR_RX_DISABLE (1u << 1)
+#define SC16IS752_EFCR_TX_DISABLE (1u << 2)
 
 /* IER */
-#define IER_RHR (1u << 0)
-#define IER_THR (1u << 1)
-#define IER_RECEIVE_LINE_STATUS (1u << 2)
-#define IER_MODEM_STATUS (1u << 3)
-#define IER_SLEEP_MODE (1u << 4)
-#define IER_XOFF (1u << 5)
-#define IER_RTS (1u << 6)
-#define IER_CTS (1u << 7)
+#define SC16IS752_IER_RHR (1u << 0)
+#define SC16IS752_IER_THR (1u << 1)
+#define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2)
+#define SC16IS752_IER_MODEM_STATUS (1u << 3)
+#define SC16IS752_IER_SLEEP_MODE (1u << 4)
+#define SC16IS752_IER_XOFF (1u << 5)
+#define SC16IS752_IER_RTS (1u << 6)
+#define SC16IS752_IER_CTS (1u << 7)
 
 /* IIR */
-#define IIR_TX_INTERRUPT (1u << 1)
-#define IIR_RX_INTERRUPT (1u << 2)
+#define SC16IS752_IIR_TX_INTERRUPT (1u << 1)
+#define SC16IS752_IIR_RX_INTERRUPT (1u << 2)
 
 /* LCR */
-#define LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
-#define LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
-#define LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
-#define LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
-#define LCR_2_STOP_BIT (1u << 2)
-#define LCR_SET_PARITY (1u << 3)
-#define LCR_EVEN_PARITY (1u << 4)
-#define LCR_ENABLE_DIVISOR (1u << 7)
+#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
+#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
+#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
+#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
+#define SC16IS752_LCR_2_STOP_BIT (1u << 2)
+#define SC16IS752_LCR_SET_PARITY (1u << 3)
+#define SC16IS752_LCR_EVEN_PARITY (1u << 4)
+#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)
 
 /* LSR */
-#define LSR_TXEMPTY (1u << 5)
-#define LSR_RXRDY (1u << 0)
-#define LSR_ERROR_BITS (7u << 2)
+#define SC16IS752_LSR_TXEMPTY (1u << 5)
+#define SC16IS752_LSR_RXRDY (1u << 0)
+#define SC16IS752_LSR_ERROR_BITS (7u << 2)
 
 /* MCR */
-#define MCR_DTR             (1u << 0)
-#define MCR_RTS             (1u << 1)
-#define MCR_TCR_TLR         (1u << 2)
-#define MCR_LOOPBACK        (1u << 4)
-#define MCR_XON_ANY         (1u << 5)
-#define MCR_IRDA_ENABLE     (1u << 6)
-#define MCR_PRESCALE_NEEDED (1u << 7)
+#define SC16IS752_MCR_DTR             (1u << 0)
+#define SC16IS752_MCR_RTS             (1u << 1)
+#define SC16IS752_MCR_TCR_TLR         (1u << 2)
+#define SC16IS752_MCR_LOOPBACK        (1u << 4)
+#define SC16IS752_MCR_XON_ANY         (1u << 5)
+#define SC16IS752_MCR_IRDA_ENABLE     (1u << 6)
+#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)
 
 /* MSR */
-#define MSR_dCTS (1u << 0)
-#define MSR_dDSR (1u << 1)
-#define MSR_dRI  (1u << 2)
-#define MSR_dCD  (1u << 3)
-#define MSR_CTS  (1u << 4)
-#define MSR_DSR  (1u << 5)
-#define MSR_RI   (1u << 6)
-#define MSR_CD   (1u << 7)
+#define SC16IS752_MSR_dCTS (1u << 0)
+#define SC16IS752_MSR_dDSR (1u << 1)
+#define SC16IS752_MSR_dRI  (1u << 2)
+#define SC16IS752_MSR_dCD  (1u << 3)
+#define SC16IS752_MSR_CTS  (1u << 4)
+#define SC16IS752_MSR_DSR  (1u << 5)
+#define SC16IS752_MSR_RI   (1u << 6)
+#define SC16IS752_MSR_CD   (1u << 7)
 
 /* EFR */
-#define EFR_ENHANCED_FUNC_ENABLE (1u << 4)
-#define EFR_SPECIAL_CHAR_DETECT (1u << 5)
-#define EFR_RTS_FLOW_CTRL_EN (1u << 6)
-#define EFR_CTS_FLOW_CTRL_EN (1u << 7)
+#define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4)
+#define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5)
+#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)
+#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)
 
 /* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */