diff options
| -rw-r--r-- | cpukit/dev/serial/sc16is752-regs.h | 108 | ||||
| -rw-r--r-- | cpukit/dev/serial/sc16is752.c | 85 |
2 files changed, 98 insertions, 95 deletions
diff --git a/cpukit/dev/serial/sc16is752-regs.h b/cpukit/dev/serial/sc16is752-regs.h index 21d425a118..b07e489a3e 100644 --- a/cpukit/dev/serial/sc16is752-regs.h +++ b/cpukit/dev/serial/sc16is752-regs.h @@ -52,76 +52,76 @@ extern "C" { #define SC16IS752_XOFF2 0x7 /* FCR */ -#define FCR_FIFO_EN 0x01 -#define FCR_RX_FIFO_RST 0x02 -#define FCR_TX_FIFO_RST 0x04 -#define FCR_TX_FIFO_TRG_8 0x00 -#define FCR_TX_FIFO_TRG_16 0x10 -#define FCR_TX_FIFO_TRG_32 0x20 -#define FCR_TX_FIFO_TRG_56 0x30 -#define FCR_RX_FIFO_TRG_8 0x00 -#define FCR_RX_FIFO_TRG_16 0x40 -#define FCR_RX_FIFO_TRG_56 0x80 -#define FCR_RX_FIFO_TRG_60 0xc0 +#define SC16IS752_FCR_FIFO_EN 0x01 +#define SC16IS752_FCR_RX_FIFO_RST 0x02 +#define SC16IS752_FCR_TX_FIFO_RST 0x04 +#define SC16IS752_FCR_TX_FIFO_TRG_8 0x00 +#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10 +#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20 +#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30 +#define SC16IS752_FCR_RX_FIFO_TRG_8 0x00 +#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40 +#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80 +#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0 /* EFCR */ -#define EFCR_RS485_ENABLE (1u << 0) -#define EFCR_RX_DISABLE (1u << 1) -#define EFCR_TX_DISABLE (1u << 2) +#define SC16IS752_EFCR_RS485_ENABLE (1u << 0) +#define SC16IS752_EFCR_RX_DISABLE (1u << 1) +#define SC16IS752_EFCR_TX_DISABLE (1u << 2) /* IER */ -#define IER_RHR (1u << 0) -#define IER_THR (1u << 1) -#define IER_RECEIVE_LINE_STATUS (1u << 2) -#define IER_MODEM_STATUS (1u << 3) -#define IER_SLEEP_MODE (1u << 4) -#define IER_XOFF (1u << 5) -#define IER_RTS (1u << 6) -#define IER_CTS (1u << 7) +#define SC16IS752_IER_RHR (1u << 0) +#define SC16IS752_IER_THR (1u << 1) +#define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2) +#define SC16IS752_IER_MODEM_STATUS (1u << 3) +#define SC16IS752_IER_SLEEP_MODE (1u << 4) +#define SC16IS752_IER_XOFF (1u << 5) +#define SC16IS752_IER_RTS (1u << 6) +#define SC16IS752_IER_CTS (1u << 7) /* IIR */ -#define IIR_TX_INTERRUPT (1u << 1) -#define IIR_RX_INTERRUPT (1u << 2) +#define SC16IS752_IIR_TX_INTERRUPT (1u << 1) +#define SC16IS752_IIR_RX_INTERRUPT (1u << 2) /* LCR */ -#define LCR_CHRL_5_BIT (0u << 1) | (0u << 0) -#define LCR_CHRL_6_BIT (0u << 1) | (1u << 0) -#define LCR_CHRL_7_BIT (1u << 1) | (0u << 0) -#define LCR_CHRL_8_BIT (1u << 1) | (1u << 0) -#define LCR_2_STOP_BIT (1u << 2) -#define LCR_SET_PARITY (1u << 3) -#define LCR_EVEN_PARITY (1u << 4) -#define LCR_ENABLE_DIVISOR (1u << 7) +#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0) +#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0) +#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0) +#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0) +#define SC16IS752_LCR_2_STOP_BIT (1u << 2) +#define SC16IS752_LCR_SET_PARITY (1u << 3) +#define SC16IS752_LCR_EVEN_PARITY (1u << 4) +#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7) /* LSR */ -#define LSR_TXEMPTY (1u << 5) -#define LSR_RXRDY (1u << 0) -#define LSR_ERROR_BITS (7u << 2) +#define SC16IS752_LSR_TXEMPTY (1u << 5) +#define SC16IS752_LSR_RXRDY (1u << 0) +#define SC16IS752_LSR_ERROR_BITS (7u << 2) /* MCR */ -#define MCR_DTR (1u << 0) -#define MCR_RTS (1u << 1) -#define MCR_TCR_TLR (1u << 2) -#define MCR_LOOPBACK (1u << 4) -#define MCR_XON_ANY (1u << 5) -#define MCR_IRDA_ENABLE (1u << 6) -#define MCR_PRESCALE_NEEDED (1u << 7) +#define SC16IS752_MCR_DTR (1u << 0) +#define SC16IS752_MCR_RTS (1u << 1) +#define SC16IS752_MCR_TCR_TLR (1u << 2) +#define SC16IS752_MCR_LOOPBACK (1u << 4) +#define SC16IS752_MCR_XON_ANY (1u << 5) +#define SC16IS752_MCR_IRDA_ENABLE (1u << 6) +#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7) /* MSR */ -#define MSR_dCTS (1u << 0) -#define MSR_dDSR (1u << 1) -#define MSR_dRI (1u << 2) -#define MSR_dCD (1u << 3) -#define MSR_CTS (1u << 4) -#define MSR_DSR (1u << 5) -#define MSR_RI (1u << 6) -#define MSR_CD (1u << 7) +#define SC16IS752_MSR_dCTS (1u << 0) +#define SC16IS752_MSR_dDSR (1u << 1) +#define SC16IS752_MSR_dRI (1u << 2) +#define SC16IS752_MSR_dCD (1u << 3) +#define SC16IS752_MSR_CTS (1u << 4) +#define SC16IS752_MSR_DSR (1u << 5) +#define SC16IS752_MSR_RI (1u << 6) +#define SC16IS752_MSR_CD (1u << 7) /* EFR */ -#define EFR_ENHANCED_FUNC_ENABLE (1u << 4) -#define EFR_SPECIAL_CHAR_DETECT (1u << 5) -#define EFR_RTS_FLOW_CTRL_EN (1u << 6) -#define EFR_CTS_FLOW_CTRL_EN (1u << 7) +#define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4) +#define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5) +#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6) +#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7) /* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */ diff --git a/cpukit/dev/serial/sc16is752.c b/cpukit/dev/serial/sc16is752.c index ac88c8389f..0dcf21765a 100644 --- a/cpukit/dev/serial/sc16is752.c +++ b/cpukit/dev/serial/sc16is752.c @@ -57,15 +57,15 @@ static void read_2_reg( static bool is_sleep_mode_enabled(sc16is752_context *ctx) { - return (ctx->ier & IER_SLEEP_MODE) != 0; + return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0; } static void set_sleep_mode(sc16is752_context *ctx, bool enable) { if (enable) { - ctx->ier |= IER_SLEEP_MODE; + ctx->ier |= SC16IS752_IER_SLEEP_MODE; } else { - ctx->ier &= ~IER_SLEEP_MODE; + ctx->ier &= ~SC16IS752_IER_SLEEP_MODE; } write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); @@ -85,14 +85,14 @@ static void set_mcr_dll_dlh( set_sleep_mode(ctx, false); } - ctx->lcr |= LCR_ENABLE_DIVISOR; + ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR; write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); write_reg(ctx, SC16IS752_MCR, &mcr, 1); write_reg(ctx, SC16IS752_DLH, &dlh, 1); write_reg(ctx, SC16IS752_DLL, &dll, 1); - ctx->lcr &= ~LCR_ENABLE_DIVISOR; + ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR; write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); if (sleep_mode) { @@ -127,10 +127,10 @@ static bool set_baud(sc16is752_context *ctx, rtems_termios_baud_t baud) if (divisor > 0xFFFF){ return false; } else { - mcr |= MCR_PRESCALE_NEEDED; + mcr |= SC16IS752_MCR_PRESCALE_NEEDED; } } else { - mcr &= ~MCR_PRESCALE_NEEDED; + mcr &= ~SC16IS752_MCR_PRESCALE_NEEDED; } set_mcr_dll_dlh(ctx, mcr, divisor); @@ -155,42 +155,42 @@ static bool sc16is752_set_attributes( } if ((term->c_cflag & CREAD) == 0){ - ctx->efcr |= EFCR_RX_DISABLE; + ctx->efcr |= SC16IS752_EFCR_RX_DISABLE; } else { - ctx->efcr &= ~EFCR_RX_DISABLE; + ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE; } write_reg(ctx, SC16IS752_EFCR, &ctx->efcr, 1); switch (term->c_cflag & CSIZE) { case CS5: - ctx->lcr |= LCR_CHRL_5_BIT; + ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT; break; case CS6: - ctx->lcr |= LCR_CHRL_6_BIT; + ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT; break; case CS7: - ctx->lcr |= LCR_CHRL_7_BIT; + ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT; break; case CS8: - ctx->lcr |= LCR_CHRL_8_BIT; + ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT; break; } if ((term->c_cflag & PARENB) != 0){ if ((term->c_cflag & PARODD) != 0) { - ctx->lcr &= ~LCR_EVEN_PARITY; + ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY; } else { - ctx->lcr |= LCR_EVEN_PARITY; + ctx->lcr |= SC16IS752_LCR_EVEN_PARITY; } } else { - ctx->lcr &= ~LCR_SET_PARITY; + ctx->lcr &= ~SC16IS752_LCR_SET_PARITY; } if ((term->c_cflag & CSTOPB) != 0) { - ctx->lcr |= LCR_2_STOP_BIT; + ctx->lcr |= SC16IS752_LCR_2_STOP_BIT; } else { - ctx->lcr &= ~LCR_2_STOP_BIT; + ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT; } write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1); @@ -218,20 +218,23 @@ static bool sc16is752_first_open( } if (ctx->mode == SC16IS752_MODE_RS485) { - ctx->efcr = EFCR_RS485_ENABLE; + ctx->efcr = SC16IS752_EFCR_RS485_ENABLE; } else { ctx->efcr = 0; } write_reg(ctx, SC16IS752_FCR, &ctx->efcr, 1); - fcr = FCR_FIFO_EN | FCR_RX_FIFO_RST | FCR_TX_FIFO_RST - | FCR_RX_FIFO_TRG_16 | FCR_TX_FIFO_TRG_32; + fcr = SC16IS752_FCR_FIFO_EN + | SC16IS752_FCR_RX_FIFO_RST + | SC16IS752_FCR_TX_FIFO_RST + | SC16IS752_FCR_RX_FIFO_TRG_16 + | SC16IS752_FCR_TX_FIFO_TRG_32; write_reg(ctx, SC16IS752_FCR, &fcr, 1); - ctx->ier = IER_RHR; + ctx->ier = SC16IS752_IER_RHR; write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); - set_efr(ctx, EFR_ENHANCED_FUNC_ENABLE); + set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_ENABLE); rtems_termios_set_initial_baud(tty, 115200); ok = sc16is752_set_attributes(base, term); @@ -265,14 +268,14 @@ static void sc16is752_write( sc16is752_context *ctx = (sc16is752_context *)base; if (len > 0) { - ctx->ier |= IER_THR; + ctx->ier |= SC16IS752_IER_THR; len = MIN(len, 32); ctx->tx_in_progress = (uint8_t)len; write_reg(ctx, SC16IS752_THR, (const uint8_t *)&buf[0], len); write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); } else { ctx->tx_in_progress = 0; - ctx->ier &= ~IER_THR; + ctx->ier &= ~SC16IS752_IER_THR; write_reg(ctx, SC16IS752_IER, &ctx->ier, 1); } } @@ -286,22 +289,22 @@ static void sc16is752_get_modem_bits(sc16is752_context *ctx, int *bits) read_reg(ctx, SC16IS752_MSR, &msr, 1); read_reg(ctx, SC16IS752_MCR, &mcr, 1); - if (msr & MSR_CTS) { + if (msr & SC16IS752_MSR_CTS) { *bits |= TIOCM_CTS; } - if (msr & MSR_DSR) { + if (msr & SC16IS752_MSR_DSR) { *bits |= TIOCM_DSR; } - if (msr & MSR_RI) { + if (msr & SC16IS752_MSR_RI) { *bits |= TIOCM_RI; } - if (msr & MSR_CD) { + if (msr & SC16IS752_MSR_CD) { *bits |= TIOCM_CD; } - if ((mcr & MCR_DTR) == 0) { + if ((mcr & SC16IS752_MCR_DTR) == 0) { *bits |= TIOCM_DTR; } - if ((mcr & MCR_RTS) == 0) { + if ((mcr & SC16IS752_MCR_RTS) == 0) { *bits |= TIOCM_RTS; } } @@ -316,29 +319,29 @@ static void sc16is752_set_modem_bits( if (bits != NULL) { if ((*bits & TIOCM_DTR) == 0) { - mcr |= MCR_DTR; + mcr |= SC16IS752_MCR_DTR; } else { - mcr &= ~MCR_DTR; + mcr &= ~SC16IS752_MCR_DTR; } if ((*bits & TIOCM_RTS) == 0) { - mcr |= MCR_RTS; + mcr |= SC16IS752_MCR_RTS; } else { - mcr &= ~MCR_RTS; + mcr &= ~SC16IS752_MCR_RTS; } } if ((set & TIOCM_DTR) != 0) { - mcr &= ~MCR_DTR; + mcr &= ~SC16IS752_MCR_DTR; } if ((set & TIOCM_RTS) != 0) { - mcr &= ~MCR_RTS; + mcr &= ~SC16IS752_MCR_RTS; } if ((clear & TIOCM_DTR) != 0) { - mcr |= MCR_DTR; + mcr |= SC16IS752_MCR_DTR; } if ((clear & TIOCM_RTS) != 0) { - mcr |= MCR_RTS; + mcr |= SC16IS752_MCR_RTS; } write_reg(ctx, SC16IS752_MCR, &mcr, 1); @@ -416,11 +419,11 @@ void sc16is752_interrupt_handler(void *arg) read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data); iir = data[0]; - if ((iir & IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) { + if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) { rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress); } - if ((iir & IIR_RX_INTERRUPT) != 0) { + if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) { uint8_t buf[SC16IS752_FIFO_DEPTH]; uint8_t rxlvl = data[1]; |