diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c index 13e2d674df..29e5f9f9fa 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @@ -483,6 +483,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) m8260.sipnr_h |= SIU_MaskBit[irq].mask_h; m8260.sipnr_l |= SIU_MaskBit[irq].mask_l; + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* re-enable external exceptions */ _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; @@ -494,6 +500,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) /* disable exceptions again */ _CPU_MSR_SET(msr); + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* restore interrupt masks */ m8260.simr_h = old_simr_h; m8260.simr_l = old_simr_l; |