diff options
| author | Daniel Cederman <cederman@gaisler.com> | 2014-07-11 16:09:41 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-08-22 13:10:59 +0200 |
| commit | bba83e5191eaed493bd619a5458ac5f22501f59b (patch) | |
| tree | 84611778cf7105ed7a8c78d015bd78a95f98a874 /c/src | |
| parent | bsp/sparc: Flush icache before first time enabling interrupts (diff) | |
| download | rtems-bba83e5191eaed493bd619a5458ac5f22501f59b.tar.bz2 | |
score/sparc: Add comment on icache flush after trap table update
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
Diffstat (limited to 'c/src')
0 files changed, 0 insertions, 0 deletions