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| author | Daniel Cederman <cederman@gaisler.com> | 2014-07-03 11:18:55 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-08-22 13:10:59 +0200 |
| commit | 54f3476e2493a957efb0e30c77226d496e7fc5a1 (patch) | |
| tree | fb80dacd4bc89121ccc648f905d0e88fde1bafc3 /c/src | |
| parent | score: Rename SMP broadcast message function (diff) | |
| download | rtems-54f3476e2493a957efb0e30c77226d496e7fc5a1.tar.bz2 | |
bsp/sparc: Flush icache before first time enabling interrupts
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
Diffstat (limited to 'c/src')
| -rw-r--r-- | c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c index 567eecc819..9166ad5630 100644 --- a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c +++ b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c @@ -15,6 +15,7 @@ #include <bsp.h> #include <bsp/bootcard.h> +#include <cache_.h> #include <leon.h> #include <rtems/bspIo.h> #include <rtems/score/smpimpl.h> @@ -80,3 +81,11 @@ void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) /* send interrupt to destination CPU */ LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_MP_IRQ; } + +void _BSP_Start_multitasking( + Context_Control *heir +) +{ + _CPU_cache_invalidate_entire_instruction(); + _CPU_Context_Restart_self( heir ); +} |