diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-27 14:37:51 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-31 12:49:09 +0100 |
| commit | 4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c (patch) | |
| tree | 8ce105a37991b79f38da9da31c1cb6ce13ef6beb /c/src/lib/libcpu | |
| parent | bsps: Move network define to source files (diff) | |
| download | rtems-4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c.tar.bz2 | |
bsps: Rework cache manager implementation
The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.
Use the following directories and files:
* bsps/shared/cache
* bsps/@RTEMS_CPU@/shared/cache
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c
Update #3285.
Diffstat (limited to 'c/src/lib/libcpu')
38 files changed, 0 insertions, 2657 deletions
diff --git a/c/src/lib/libcpu/Makefile.am b/c/src/lib/libcpu/Makefile.am index 9cc2ece050..693f50b2b8 100644 --- a/c/src/lib/libcpu/Makefile.am +++ b/c/src/lib/libcpu/Makefile.am @@ -1,6 +1,4 @@ EXTRA_DIST = -EXTRA_DIST += shared/include/cache.h -EXTRA_DIST += shared/src/cache_manager.c _SUBDIRS = @libcpu_cpu_subdir@ DIST_SUBDIRS = @libcpu_cpu_subdir@ diff --git a/c/src/lib/libcpu/arm/shared/include/cache_.h b/c/src/lib/libcpu/arm/shared/include/cache_.h deleted file mode 100644 index 9db399edf7..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/cache_.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * - * @ingroup arm - * - * @brief ARM cache dummy include for chips without cache - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_ARM_CACHE__H -#define LIBCPU_ARM_CACHE__H - -/* - * The ARM targets equipped by cache should include - * which kind and implementation they support. - * Next options are available - * - * c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h - * basic ARM cache integrated on the CPU core directly - * which requires only CP15 oparations - * - * c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h - * support for case where ARM L2C-310 cache controller - * is used. It is accessible as mmaped peripheral. - * - * c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h - * Cortex-M specific cache support - * - * Cache support should be included in BSP Makefile.am - * - * Example how to include cache support - * - * # Cache - * libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c - * libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h - * libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h - * libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache - */ - -#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__) -#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache -#warning change BSP to include appropriate cache implementation -#endif - -#endif /* LIBCPU_ARM_CACHE__H */ diff --git a/c/src/lib/libcpu/bfin/Makefile.am b/c/src/lib/libcpu/bfin/Makefile.am index 9b7ee0c26e..8d484480a9 100644 --- a/c/src/lib/libcpu/bfin/Makefile.am +++ b/c/src/lib/libcpu/bfin/Makefile.am @@ -22,12 +22,6 @@ endif # endof bf52x ############ -noinst_PROGRAMS += cache.rel -cache_rel_SOURCES = cache/cache.c \ - ../shared/src/cache_manager.c cache/cache_.h -cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/cache -cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - noinst_PROGRAMS += mmu.rel mmu_rel_SOURCES = mmu/mmu.c mmu_rel_CPPFLAGS = $(AM_CPPFLAGS) diff --git a/c/src/lib/libcpu/bfin/cache/cache.c b/c/src/lib/libcpu/bfin/cache/cache.c deleted file mode 100644 index cc60904f8c..0000000000 --- a/c/src/lib/libcpu/bfin/cache/cache.c +++ /dev/null @@ -1,125 +0,0 @@ -/* Blackfin Cache Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include <rtems.h> -#include <bsp.h> -#include <libcpu/memoryRegs.h> -#include "cache_.h" - - -/* There are many syncs in the following code because they should be - harmless except for wasting time, and this is easier than figuring out - exactly where they're needed to protect from the effects of write - buffers and queued reads. Many of them are likely unnecessary. */ - - -void _CPU_cache_flush_1_data_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr)); -} - -/* Blackfins can't just invalidate cache; they can only do flush + - invalidate. If the line isn't dirty then this is equivalent to - just an invalidate. Even if it is dirty, this should still be - okay since with a pure invalidate method the caller would have no - way to insure the dirty line hadn't been written out anyway prior - to the invalidate. */ -void _CPU_cache_invalidate_1_data_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr)); -} - -void _CPU_cache_freeze_data(void) { -} - -void _CPU_cache_unfreeze_data(void) { -} - -void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr)); -} - -void _CPU_cache_freeze_instruction(void) { -} - -void _CPU_cache_unfreeze_instruction(void) { -} - -/* incredibly inefficient... It would be better to make use of the - DTEST_COMMAND/DTEST_DATAx registers to find the addresses in each - cache line and flush just those. However the documentation I've - seen on those is a bit sketchy, and I sure wouldn't want to get it - wrong. */ -void _CPU_cache_flush_entire_data(void) { - uint32_t i; - - i = 0; - __asm__ __volatile__ ("ssync"); - do { - __asm__ __volatile__ ("flush [%0]" :: "a" (i)); - i += CPU_DATA_CACHE_ALIGNMENT; - } while (i); - __asm__ __volatile__ ("ssync"); -} - -void _CPU_cache_invalidate_entire_data(void) { - uint32_t dmemControl; - - __asm__ __volatile__ ("ssync"); - dmemControl = *(uint32_t volatile *) DMEM_CONTROL; - *(uint32_t volatile *) DMEM_CONTROL = dmemControl & ~DMEM_CONTROL_DMC_MASK; - *(uint32_t volatile *) DMEM_CONTROL = dmemControl; - __asm__ __volatile__ ("ssync"); -} - -/* this does not actually enable data cache unless CPLBs are also enabled. - LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */ -void _CPU_cache_enable_data(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG; - __asm__ __volatile__ ("ssync"); -} - -void _CPU_cache_disable_data(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK; - __asm__ __volatile__ ("ssync"); -} - -void _CPU_cache_invalidate_entire_instruction(void) { - uint32_t imemControl; - - __asm__ __volatile__ ("ssync"); - imemControl = *(uint32_t volatile *) IMEM_CONTROL; - *(uint32_t volatile *) IMEM_CONTROL = imemControl & ~IMEM_CONTROL_IMC; - *(uint32_t volatile *) IMEM_CONTROL = imemControl; - __asm__ __volatile__ ("ssync"); -} - -/* this only actually enables the instruction cache if the CPLBs are also - enabled. */ -void _CPU_cache_enable_instruction(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC; - __asm__ __volatile__ ("ssync"); -} - -void _CPU_cache_disable_instruction(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC; - __asm__ __volatile__ ("ssync"); -} - diff --git a/c/src/lib/libcpu/bfin/cache/cache_.h b/c/src/lib/libcpu/bfin/cache/cache_.h deleted file mode 100644 index f739976b51..0000000000 --- a/c/src/lib/libcpu/bfin/cache/cache_.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Blackfin Cache Manager Support - */ - -#ifndef _cache__h_ -#define _cache__h_ - -#include "../../shared/include/cache.h" - -#define CPU_DATA_CACHE_ALIGNMENT 32 -#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 - -#ifdef BSP_DATA_CACHE_CONFIG -#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG -#else -/* use 16K of each SRAM bank */ -#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT) -#endif - -#endif /* _cache__h_ */ - diff --git a/c/src/lib/libcpu/i386/Makefile.am b/c/src/lib/libcpu/i386/Makefile.am index 6f1e9fe3ec..ec7a4c4a48 100644 --- a/c/src/lib/libcpu/i386/Makefile.am +++ b/c/src/lib/libcpu/i386/Makefile.am @@ -4,12 +4,6 @@ noinst_PROGRAMS = include $(top_srcdir)/../../../automake/compile.am -noinst_PROGRAMS += cache.rel -cache_rel_SOURCES = cache.c cache_.h \ - ../shared/src/cache_manager.c ../shared/include/cache.h -cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - noinst_PROGRAMS += score.rel score_rel_SOURCES = displayCpu.c cpuModel.S cpuModel.h idtr.S cpu.h score_rel_CPPFLAGS = $(AM_CPPFLAGS) diff --git a/c/src/lib/libcpu/i386/cache.c b/c/src/lib/libcpu/i386/cache.c deleted file mode 100644 index da31a38bee..0000000000 --- a/c/src/lib/libcpu/i386/cache.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Cache Management Support Routines for the i386 - */ - -#include <rtems.h> -#include "cache_.h" -#include <rtems/score/cpu.h> -#include <libcpu/page.h> - -void _CPU_disable_cache(void) -{ - unsigned int regCr0; - - regCr0 = i386_get_cr0(); - regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE; - regCr0 |= CR0_NO_WRITE_THROUGH; - i386_set_cr0( regCr0 ); - rtems_cache_flush_entire_data(); -} - -/* - * Enable the entire cache - */ - -void _CPU_enable_cache(void) -{ - unsigned int regCr0; - - regCr0 = i386_get_cr0(); - regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE); - regCr0 &= ~(CR0_NO_WRITE_THROUGH); - i386_set_cr0( regCr0 ); - /*rtems_cache_flush_entire_data();*/ -} - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: The routines below should be implemented per CPU, - * to accomodate the capabilities of each. - */ - -#if defined(I386_CACHE_ALIGNMENT) -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_invalidate_1_data_line(const void *d_addr) {} -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -void _CPU_cache_flush_entire_data(void) -{ - __asm__ volatile ("wbinvd"); -} -void _CPU_cache_invalidate_entire_data(void) -{ - __asm__ volatile ("invd"); -} - -void _CPU_cache_enable_data(void) -{ - _CPU_enable_cache(); -} - -void _CPU_cache_disable_data(void) -{ - _CPU_disable_cache(); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - __asm__ volatile ("invd"); -} - -void _CPU_cache_enable_instruction(void) -{ - _CPU_enable_cache(); -} - -void _CPU_cache_disable_instruction( void ) -{ - _CPU_disable_cache(); -} -#endif diff --git a/c/src/lib/libcpu/i386/cache_.h b/c/src/lib/libcpu/i386/cache_.h deleted file mode 100644 index cefd39f3ad..0000000000 --- a/c/src/lib/libcpu/i386/cache_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * i386 Cache Manager Wrapper - */ - -#ifndef __i386_CACHE_h -#define __i386_CACHE_h - -#define I386_CACHE_ALIGNMENT 16 -#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT -#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT - -#include "../shared/include/cache.h" - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/lm32/Makefile.am b/c/src/lib/libcpu/lm32/Makefile.am index 1e609cabf6..7c1ce064d5 100644 --- a/c/src/lib/libcpu/lm32/Makefile.am +++ b/c/src/lib/libcpu/lm32/Makefile.am @@ -7,13 +7,6 @@ DISTCLEANFILES = noinst_PROGRAMS = if shared - -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h \ - ../shared/src/cache_manager.c -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - ## shared/misc noinst_PROGRAMS += shared/misc.rel shared_misc_rel_SOURCES = shared/misc/memcpy.c diff --git a/c/src/lib/libcpu/lm32/shared/cache/cache_.h b/c/src/lib/libcpu/lm32/shared/cache/cache_.h deleted file mode 100644 index 2a303b7db7..0000000000 --- a/c/src/lib/libcpu/lm32/shared/cache/cache_.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * LM32 Cache Manager Support - */ - -#ifndef __LM32_CACHE_h -#define __LM32_CACHE_h - -#include "../../../shared/include/cache.h" - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am index 2800e421c4..ed07940257 100644 --- a/c/src/lib/libcpu/m68k/Makefile.am +++ b/c/src/lib/libcpu/m68k/Makefile.am @@ -6,13 +6,6 @@ noinst_PROGRAMS = if shared -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = shared/cache/cache.c -shared_cache_rel_SOURCES += shared/cache/cache_.h -shared_cache_rel_SOURCES += ../shared/src/cache_manager.c -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - ## shared/misc # gcc doesn't recognize difference between the cpu32 and cpu32+ so we have to @@ -92,46 +85,6 @@ mcf5206_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) mcf5206_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -if mcf5223x -## mcf5223x/include -## mcf5223x/cache -noinst_PROGRAMS += mcf5223x/cachepd.rel -mcf5223x_cachepd_rel_SOURCES = mcf5223x/cache/cachepd.c -mcf5223x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -mcf5223x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - -if mcf5225x -## mcf5225x/include -# mcf5225x/cache -noinst_PROGRAMS += mcf5225x/cachepd.rel -mcf5225x_cachepd_rel_SOURCES = mcf5225x/cache/cachepd.c -mcf5225x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -mcf5225x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -# Network -if HAS_NETWORKING -endif ## HAS_NETWORKING -endif - -if mcf5235 -## mcf5235/include -## mcf5235/cache -noinst_PROGRAMS += mcf5235/cachepd.rel -mcf5235_cachepd_rel_SOURCES = mcf5235/cache/cachepd.c -mcf5235_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -mcf5235_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - -if mcf532x -## mcf532x/include -## mcf532x/cache -noinst_PROGRAMS += mcf532x/cachepd.rel -mcf532x_cachepd_rel_SOURCES = mcf532x/cache/cachepd.c -mcf532x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -mcf532x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - if mcf5272 ## mcf5272/include ## clock @@ -147,14 +100,6 @@ mcf5272_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) mcf5272_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -if mcf5282 -## mcf5282/include -noinst_PROGRAMS += mcf5282/cachepd.rel -mcf5282_cachepd_rel_SOURCES = mcf5282/cache/cachepd.c -mcf5282_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -mcf5282_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - if mcf548x ## mcf548x/include ## mcf548x/mcdma diff --git a/c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c deleted file mode 100644 index c18cf94c9f..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5223x/cache/cachepd.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems.h> -#include <mcf5223x/mcf5223x.h> -#include "cache_.h" - -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) {} -void _CPU_cache_disable_instruction(void) {} -void _CPU_cache_invalidate_entire_instruction(void) {} -void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} - -void _CPU_cache_enable_data(void) {} -void _CPU_cache_disable_data(void) {} -void _CPU_cache_invalidate_entire_data(void) {} -void _CPU_cache_invalidate_1_data_line(const void *addr) {} diff --git a/c/src/lib/libcpu/m68k/mcf5225x/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5225x/cache/cachepd.c deleted file mode 100644 index 031f02b601..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5225x/cache/cachepd.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file - * - * Cache Management Support Routines for the MCF5225x - */ - -#include <rtems.h> -#include "cache_.h" - -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) {} -void _CPU_cache_disable_instruction(void) {} -void _CPU_cache_invalidate_entire_instruction(void) {} -void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} - -void _CPU_cache_enable_data(void) {} -void _CPU_cache_disable_data(void) {} -void _CPU_cache_invalidate_entire_data(void) {} -void _CPU_cache_invalidate_1_data_line(const void *addr) {} diff --git a/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c deleted file mode 100644 index 043908c0e7..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems.h> -#include <mcf5235/mcf5235.h> -#include "cache_.h" - -/* - * Default value for the cacr is set by the BSP - */ -extern uint32_t cacr_mode; - -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - /* - * Top half of cache is I-space - */ - addr = (void *)((int)addr | 0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - -void _CPU_cache_enable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - /* - * Bottom half of cache is D-space - */ - addr = (void *)((int)addr & ~0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} diff --git a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c deleted file mode 100644 index e59f213236..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - * @file - * - * Cache Management Support Routines for the MCF5282 - */ - -#include <rtems.h> -#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ -#include "cache_.h" - -/* - * CPU-space access - */ -#define m68k_set_acr0(_acr0) \ - __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) \ - __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) - -#define NOP __asm__ volatile ("nop"); - -/* - * DEFAULT WHEN mcf5xxx_initialize_cacr not called - * Read/write copy of common cache - * Split I/D cache - * Allow CPUSHL to invalidate a cache line - * Enable buffered writes - * No burst transfers on non-cacheable accesses - * Default cache mode is *disabled* (cache only ACRx areas) - */ -static uint32_t cacr_mode = MCF5XXX_CACR_CENB | - MCF5XXX_CACR_DBWE | - MCF5XXX_CACR_DCM; - -void mcf5xxx_initialize_cacr(uint32_t cacr) -{ - cacr_mode = cacr; - m68k_set_cacr( cacr_mode ); -} - -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} - -/* - * Write-through data cache -- flushes are unnecessary - */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI ); - NOP; - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); - NOP; -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - /* - * Top half of cache is I-space - */ - addr = (void *)((int)addr | 0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - -void _CPU_cache_enable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - /* - * Bottom half of cache is D-space - */ - addr = (void *)((int)addr & ~0x400); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} diff --git a/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c b/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c deleted file mode 100644 index 5a93ea9d6c..0000000000 --- a/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file - * - * Cache Management Support Routines for the MCF532x - */ - -#include <rtems.h> -#include <mcf532x/mcf532x.h> -#include "cache_.h" - -#define m68k_set_cacr(_cacr) \ - __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) - -/* - * Read/write copy of common cache - * Default cache mode is *disabled* (cache only ACRx areas) - * Allow CPUSHL to invalidate a cache line - * Enable store buffer - */ -static uint32_t cacr_mode = MCF_CACR_ESB | - MCF_CACR_DCM(3); - -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) -{ -} - -void _CPU_cache_unfreeze_data(void) -{ -} - -void _CPU_cache_freeze_instruction(void) -{ -} - -void _CPU_cache_unfreeze_instruction(void) -{ -} - -void _CPU_cache_flush_1_data_line(const void *d_addr) -{ - register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4; - - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); -} - -void _CPU_cache_flush_entire_data(void) -{ - register unsigned long set, adr; - - for(set = 0; set < 256; ++set) { - adr = (set << 4); - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - } -} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - if(!(cacr_mode & MCF_CACR_CENB)) - { - cacr_mode |= MCF_CACR_CENB; - m68k_set_cacr(cacr_mode); - } - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - if((cacr_mode & MCF_CACR_CENB)) - { - cacr_mode &= ~MCF_CACR_CENB; - m68k_set_cacr(cacr_mode); - } - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr(cacr_mode | MCF_CACR_CINVA); -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4; - - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); - adr += 1; - __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); -} - -void _CPU_cache_enable_data(void) -{ - /* - * The 532x has a unified data and instruction cache, so we call through - * to enable instruction. - */ - _CPU_cache_enable_instruction(); -} - -void _CPU_cache_disable_data(void) -{ - /* - * The 532x has a unified data and instruction cache, so we call through - * to disable instruction. - */ - _CPU_cache_disable_instruction(); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - _CPU_cache_invalidate_entire_instruction(); -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - _CPU_cache_invalidate_1_instruction_line(addr); -} diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache.c b/c/src/lib/libcpu/m68k/shared/cache/cache.c deleted file mode 100644 index 5039ea59ed..0000000000 --- a/c/src/lib/libcpu/m68k/shared/cache/cache.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Cache Management Support Routines for the MC68040 - */ - -#include <rtems.h> -#include "cache_.h" - -/* - * Since the cacr is common to all mc680x0, provide macros - * for masking values in that register. - */ - -/* - * Used to clear bits in the cacr. - */ -#define _CPU_CACR_AND(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ - andl %2, %0; /* and with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * Used to set bits in the cacr. - */ -#define _CPU_CACR_OR(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ - orl %2, %0; /* or with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - */ -#if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) ) - -#if defined(__mc68030__) - -/* Only the mc68030 has a data cache; it is writethrough only. */ - -void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} -void _CPU_cache_flush_entire_data ( void ) {} - -void _CPU_cache_invalidate_1_data_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR(0x00000400); -} - -void _CPU_cache_invalidate_entire_data ( void ) -{ - _CPU_CACR_OR( 0x00000800 ); -} - -void _CPU_cache_freeze_data ( void ) -{ - _CPU_CACR_OR( 0x00000200 ); -} - -void _CPU_cache_unfreeze_data ( void ) -{ - _CPU_CACR_AND( 0xFFFFFDFF ); -} - -void _CPU_cache_enable_data ( void ) -{ - _CPU_CACR_OR( 0x00000100 ); -} -void _CPU_cache_disable_data ( void ) -{ - _CPU_CACR_AND( 0xFFFFFEFF ); -} -#endif - - -/* Both the 68020 and 68030 have instruction caches */ - -void _CPU_cache_invalidate_1_instruction_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR( 0x00000004 ); -} - -void _CPU_cache_invalidate_entire_instruction ( void ) -{ - _CPU_CACR_OR( 0x00000008 ); -} - -void _CPU_cache_freeze_instruction ( void ) -{ - _CPU_CACR_OR( 0x00000002); -} - -void _CPU_cache_unfreeze_instruction ( void ) -{ - _CPU_CACR_AND( 0xFFFFFFFD ); -} - -void _CPU_cache_enable_instruction ( void ) -{ - _CPU_CACR_OR( 0x00000001 ); -} - -void _CPU_cache_disable_instruction ( void ) -{ - _CPU_CACR_AND( 0xFFFFFFFE ); -} - - -#elif ( defined(__mc68040__) || defined (__mc68060__) ) - -/* Cannot be frozen */ -void _CPU_cache_freeze_data ( void ) {} -void _CPU_cache_unfreeze_data ( void ) {} -void _CPU_cache_freeze_instruction ( void ) {} -void _CPU_cache_unfreeze_instruction ( void ) {} - -void _CPU_cache_flush_1_data_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); -} - -void _CPU_cache_invalidate_1_data_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); -} - -void _CPU_cache_flush_entire_data ( void ) -{ - asm volatile ( "cpusha %%dc" :: ); -} - -void _CPU_cache_invalidate_entire_data ( void ) -{ - asm volatile ( "cinva %%dc" :: ); -} - -void _CPU_cache_enable_data ( void ) -{ - _CPU_CACR_OR( 0x80000000 ); -} - -void _CPU_cache_disable_data ( void ) -{ - _CPU_CACR_AND( 0x7FFFFFFF ); -} - -void _CPU_cache_invalidate_1_instruction_line ( - const void * i_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); - __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); -} - -void _CPU_cache_invalidate_entire_instruction ( void ) -{ - asm volatile ( "cinva %%ic" :: ); -} - -void _CPU_cache_enable_instruction ( void ) -{ - _CPU_CACR_OR( 0x00008000 ); -} - -void _CPU_cache_disable_instruction ( void ) -{ - _CPU_CACR_AND( 0xFFFF7FFF ); -} -#endif -/* end of file */ diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache_.h b/c/src/lib/libcpu/m68k/shared/cache/cache_.h deleted file mode 100644 index af4bef638a..0000000000 --- a/c/src/lib/libcpu/m68k/shared/cache/cache_.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * M68K Cache Manager Support - */ - -#ifndef __M68K_CACHE_h -#define __M68K_CACHE_h - -#if (defined(__mc68020__) && !defined(__mcpu32__)) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -#elif defined(__mc68030__) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#elif ( defined(__mc68040__) || defined (__mc68060__) ) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#elif ( defined(__mcf5200__) ) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# if ( defined(__mcf528x__) ) -# define M68K_DATA_CACHE_ALIGNMENT 16 -# endif -#elif ( defined(__mcf5300__) ) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#elif defined(__mcfv4e__) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#endif - -#if defined(M68K_DATA_CACHE_ALIGNMENT) -#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT -#endif - -#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT) -#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT -#endif - -#include "../../../shared/include/cache.h" - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/mips/Makefile.am b/c/src/lib/libcpu/mips/Makefile.am index 84dc521fac..8ae999dd28 100644 --- a/c/src/lib/libcpu/mips/Makefile.am +++ b/c/src/lib/libcpu/mips/Makefile.am @@ -6,13 +6,6 @@ EXTRA_DIST = noinst_PROGRAMS = -## cache -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = shared/cache/cache.c \ - ../shared/src/cache_manager.c shared/cache/cache_.h -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - ## interrupts if rm52xx diff --git a/c/src/lib/libcpu/mips/shared/cache/cache.c b/c/src/lib/libcpu/mips/shared/cache/cache.c deleted file mode 100644 index 384e7c8c19..0000000000 --- a/c/src/lib/libcpu/mips/shared/cache/cache.c +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Cache Management Support Routines for the MIPS - */ - -#include <rtems.h> -#include "cache_.h" - -/* TBD */ diff --git a/c/src/lib/libcpu/mips/shared/cache/cache_.h b/c/src/lib/libcpu/mips/shared/cache/cache_.h deleted file mode 100644 index a81c5a098a..0000000000 --- a/c/src/lib/libcpu/mips/shared/cache/cache_.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * MIPS Cache Manager Support - */ - -#ifndef __MIPS_CACHE_h -#define __MIPS_CACHE_h - -#include "../../../shared/include/cache.h" - -/* TBD */ - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/nios2/Makefile.am b/c/src/lib/libcpu/nios2/Makefile.am index 7641afb335..d5bfc578c3 100644 --- a/c/src/lib/libcpu/nios2/Makefile.am +++ b/c/src/lib/libcpu/nios2/Makefile.am @@ -7,14 +7,6 @@ DISTCLEANFILES = noinst_PROGRAMS = if shared - -## shared/cache -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h \ - ../shared/src/cache_manager.c -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - ## shared/misc noinst_PROGRAMS += shared/misc.rel shared_misc_rel_SOURCES = shared/misc/memcpy.c diff --git a/c/src/lib/libcpu/nios2/shared/cache/cache_.h b/c/src/lib/libcpu/nios2/shared/cache/cache_.h deleted file mode 100644 index 1a83b8eb23..0000000000 --- a/c/src/lib/libcpu/nios2/shared/cache/cache_.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * M68K Cache Manager Support - */ - -#ifndef __M68K_CACHE_h -#define __M68K_CACHE_h - -#if (defined(__mc68020__) && !defined(__mcpu32__)) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -#elif defined(__mc68030__) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#elif ( defined(__mc68040__) || defined (__mc68060__) ) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# define M68K_DATA_CACHE_ALIGNMENT 16 -#elif ( defined(__mcf5200__) ) -# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 -# if ( defined(__mcf528x__) ) -# define M68K_DATA_CACHE_ALIGNMENT 16 -# endif -#endif - -#if defined(M68K_DATA_CACHE_ALIGNMENT) -#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT -#endif - -#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT) -#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT -#endif - -#include "../../../shared/include/cache.h" - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am deleted file mode 100644 index e34d580982..0000000000 --- a/c/src/lib/libcpu/or1k/Makefile.am +++ /dev/null @@ -1,16 +0,0 @@ -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/compile.am - -CLEANFILES = -DISTCLEANFILES = -noinst_PROGRAMS = - -## shared/cache -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = shared/cache/cache.c ../shared/src/cache_manager.c -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/or1k/configure.ac b/c/src/lib/libcpu/or1k/configure.ac deleted file mode 100644 index 80c67b63c3..0000000000 --- a/c/src/lib/libcpu/or1k/configure.ac +++ /dev/null @@ -1,33 +0,0 @@ -## Process this file with autoconf to produce a configure script. - -AC_PREREQ([2.69]) -AC_INIT([rtems-c-src-lib-libcpu-or1k],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) -RTEMS_TOP([../../../../..],[../../..]) -RTEMS_SOURCE_TOP -RTEMS_BUILD_TOP - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSBSP - -RTEMS_PROJECT_ROOT - -RTEMS_PROG_CC_FOR_TARGET -AM_PROG_CC_C_O -RTEMS_CANONICALIZE_TOOLS -RTEMS_PROG_CCAS - -# At this time all models should use the shared directory so do this -AM_CONDITIONAL(shared, true) - -AC_PATH_PROG([AMPOLISH3],[ampolish3],[]) - -RTEMS_AMPOLISH3 - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile -]) -AC_OUTPUT diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c deleted file mode 100644 index 898955f041..0000000000 --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * COPYRIGHT (c) 2014, 2016 ÅAC Microtec AB <www.aacmicrotec.com> - * Contributor(s): - * Karol Gugala <kgugala@antmicro.com> - * Martin Werner <martin.werner@aacmicrotec.com> - * - * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> - * - * COPYRIGHT (c) 1989-2006 - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/score/cpu.h> -#include <rtems/score/interr.h> -#include <rtems/score/or1k-utility.h> -#include <rtems/score/percpu.h> -#include "cache_.h" - -static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -static inline void _CPU_OR1K_Cache_instruction_block_prefetch -(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -static inline void _CPU_OR1K_Cache_instruction_block_lock -(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -/* Implement RTEMS cache manager functions */ - -void _CPU_cache_flush_1_data_line(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); - - //__asm__ volatile("l.csync"); - - _ISR_Local_enable(level); -} - -void _CPU_cache_invalidate_1_data_line(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -void _CPU_cache_freeze_data(void) -{ - /* Do nothing */ -} - -void _CPU_cache_unfreeze_data(void) -{ - /* Do nothing */ -} - -void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) -{ - ISR_Level level; - - _ISR_Local_disable (level); - - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr); - - _ISR_Local_enable(level); -} - -void _CPU_cache_freeze_instruction(void) -{ - /* Do nothing */ -} - -void _CPU_cache_unfreeze_instruction(void) -{ - /* Do nothing */ -} - -void _CPU_cache_flush_entire_data(void) -{ - size_t addr; - ISR_Level level; - - _ISR_Local_disable (level); - - /* We have only 0 level cache so we do not need to invalidate others */ - for ( - addr = _CPU_cache_get_data_cache_size(0); - addr > 0; - addr -= CPU_DATA_CACHE_ALIGNMENT - ) { - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) addr); - } - - _ISR_Local_enable (level); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - size_t addr; - ISR_Level level; - - _ISR_Local_disable (level); - - /* We have only 0 level cache so we do not need to invalidate others */ - for ( - addr = _CPU_cache_get_data_cache_size(0); - addr > 0; - addr -= CPU_DATA_CACHE_ALIGNMENT - ) { - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) addr); - } - - _ISR_Local_enable (level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - size_t addr; - ISR_Level level; - - _ISR_Local_disable (level); - - /* We have only 0 level cache so we do not need to invalidate others */ - for ( - addr = _CPU_cache_get_instruction_cache_size(0); - addr > 0; - addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT - ) { - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) addr); - } - - /* Flush instructions out of instruction buffer */ - __asm__ volatile("l.nop"); - __asm__ volatile("l.nop"); - __asm__ volatile("l.nop"); - __asm__ volatile("l.nop"); - __asm__ volatile("l.nop"); - - _ISR_Local_enable (level); -} - -/* - * The range functions are copied almost verbatim from the generic - * implementations in c/src/lib/libcpu/shared/src/cache_manager.c. The main - * modification here is avoiding reapeated off/on toggling of the ISR for each - * cache line operation. - */ - -void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes) -{ - const void * final_address; - ISR_Level level; - - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be pushed. Increment d_addr and push - * the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to flush is zero */ - return; - - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); - - if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { - /* - * Avoid iterating over the whole cache multiple times if the range is - * larger than the cache size. - */ - _CPU_cache_flush_entire_data(); - return; - } - - _ISR_Local_disable (level); - - while( d_addr <= final_address ) { - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); - d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); - } - - _ISR_Local_enable (level); -} - -void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes) -{ - const void * final_address; - ISR_Level level; - - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be pushed. Increment d_addr and push - * the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to flush is zero */ - return; - - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); - - if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { - /* - * Avoid iterating over the whole cache multiple times if the range is - * larger than the cache size. - */ - _CPU_cache_invalidate_entire_data(); - return; - } - - _ISR_Local_disable (level); - - while( d_addr <= final_address ) { - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); - d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); - } - - _ISR_Local_enable (level); -} - -void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes) -{ - const void * final_address; - ISR_Level level; - - /* - * Set i_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be pushed. Increment i_addr and push - * the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to flush is zero */ - return; - - final_address = (void *)((size_t)i_addr + n_bytes - 1); - i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); - - if( final_address - i_addr > _CPU_cache_get_data_cache_size(0) ) { - /* - * Avoid iterating over the whole cache multiple times if the range is - * larger than the cache size. - */ - _CPU_cache_invalidate_entire_instruction(); - return; - } - - _ISR_Local_disable (level); - - while( i_addr <= final_address ) { - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) i_addr); - i_addr = (void *)((size_t)i_addr + CPU_DATA_CACHE_ALIGNMENT); - } - - _ISR_Local_enable (level); -} - -void _CPU_cache_enable_data(void) -{ - uint32_t sr; - ISR_Level level; - - _ISR_Local_disable (level); - - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE); - - _ISR_Local_enable(level); -} - -void _CPU_cache_disable_data(void) -{ - uint32_t sr; - ISR_Level level; - - _ISR_Local_disable (level); - - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE)); - - _ISR_Local_enable(level); -} - -void _CPU_cache_enable_instruction(void) -{ - uint32_t sr; - ISR_Level level; - - _ISR_Local_disable (level); - - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE); - - _ISR_Local_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - uint32_t sr; - ISR_Level level; - - _ISR_Local_disable (level); - - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE)); - - _ISR_Local_enable(level); -} diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h deleted file mode 100644 index ea379580d5..0000000000 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * or1k Cache Manager Support - */ - -#ifndef __OR1K_CACHE_H -#define __OR1K_CACHE_H - -#include <bsp/cache_.h> -#include "../../../shared/include/cache.h" - -#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1 - -void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes); -void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes); -void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes); - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am index 514c93db37..6cf77130f1 100644 --- a/c/src/lib/libcpu/powerpc/Makefile.am +++ b/c/src/lib/libcpu/powerpc/Makefile.am @@ -51,14 +51,6 @@ shared_cpuIdent_rel_SOURCES = shared/include/cpuIdent.c shared/include/cpuIdent. shared_cpuIdent_rel_CPPFLAGS = $(AM_CPPFLAGS) shared_cpuIdent_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -# shared/cache -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = shared/src/cache_.h \ - ../shared/src/cache_manager.c \ - ../shared/include/cache.h -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/src -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - # shared/stack noinst_PROGRAMS += shared/stack.rel shared_stack_rel_SOURCES = shared/src/stack.c shared/include/spr.h shared/src/stackTrace.h diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache_.h b/c/src/lib/libcpu/powerpc/shared/src/cache_.h deleted file mode 100644 index 17758947e0..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/src/cache_.h +++ /dev/null @@ -1,322 +0,0 @@ -/** - * @file - * - * #ingroup powerpc_shared - * - * @brief Header file for the Cache Manager PowerPC support. - */ - -/* - * Cache Management Support Routines for the MC68040 - * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited (SSTL), 2001 - */ - -#ifndef LIBCPU_POWERPC_CACHE_H -#define LIBCPU_POWERPC_CACHE_H - -#include <rtems.h> -#include <rtems/powerpc/powerpc.h> -#include <rtems/powerpc/registers.h> - -/* Provide the CPU defines only if we have a cache */ -#if PPC_CACHE_ALIGNMENT != PPC_NO_CACHE_ALIGNMENT - #define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - #define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#endif - -#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS - -static inline size_t _CPU_cache_get_data_cache_size(uint32_t level) -{ - switch (level) { - case 0: - /* Fall through */ -#ifdef PPC_CACHE_DATA_L3_SIZE - case 3: - return PPC_CACHE_DATA_L3_SIZE; -#endif -#ifdef PPC_CACHE_DATA_L2_SIZE - case 2: - return PPC_CACHE_DATA_L2_SIZE; -#endif -#ifdef PPC_CACHE_DATA_L1_SIZE - case 1: - return PPC_CACHE_DATA_L1_SIZE; -#endif - default: - return 0; - } -} - -static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level) -{ - switch (level) { - case 0: - /* Fall through */ -#ifdef PPC_CACHE_INSTRUCTION_L3_SIZE - case 3: - return PPC_CACHE_INSTRUCTION_L3_SIZE; -#endif -#ifdef PPC_CACHE_INSTRUCTION_L2_SIZE - case 2: - return PPC_CACHE_INSTRUCTION_L2_SIZE; -#endif -#ifdef PPC_CACHE_INSTRUCTION_L1_SIZE - case 1: - return PPC_CACHE_INSTRUCTION_L1_SIZE; -#endif - default: - return 0; - } -} - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */ - -/* Helpful macros */ -#define PPC_Get_HID0( _value ) \ - do { \ - _value = 0; /* to avoid warnings */ \ - __asm__ volatile( \ - "mfspr %0, 0x3f0;" /* get HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -#define PPC_Set_HID0( _value ) \ - do { \ - __asm__ volatile( \ - "isync;" \ - "mtspr 0x3f0, %0;" /* load HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -static inline void _CPU_cache_enable_data(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= HID0_DCE; /* set DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_disable_data(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value &= ~HID0_DCE; /* clear DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_invalidate_entire_data(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= HID0_DCI; /* set data flash invalidate bit */ - PPC_Set_HID0( value ); - value &= ~HID0_DCI; /* clear data flash invalidate bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_freeze_data(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= HID0_DLOCK; /* set data cache lock bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_unfreeze_data(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value &= ~HID0_DLOCK; /* set data cache lock bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_flush_entire_data(void) -{ - /* - * FIXME: how can we do this? - */ -} - -static inline void _CPU_cache_enable_instruction(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= 0x00008000; /* Set ICE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_disable_instruction(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value &= 0xFFFF7FFF; /* Clear ICE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_invalidate_entire_instruction(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= HID0_ICFI; /* set data flash invalidate bit */ - PPC_Set_HID0( value ); - value &= ~HID0_ICFI; /* clear data flash invalidate bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_freeze_instruction(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value |= HID0_ILOCK; /* set instruction cache lock bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_cache_unfreeze_instruction(void) -{ - uint32_t value; - PPC_Get_HID0( value ); - value &= ~HID0_ILOCK; /* set instruction cache lock bit */ - PPC_Set_HID0( value ); -} - -#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) ) - -#define mtspr(_spr,_reg) \ - __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) -#define isync \ - __asm__ volatile ("isync\n"::) - -static inline void _CPU_cache_flush_entire_data(void) {} -static inline void _CPU_cache_invalidate_entire_data(void) {} -static inline void _CPU_cache_freeze_data(void) {} -static inline void _CPU_cache_unfreeze_data(void) {} - -static inline void _CPU_cache_enable_data(void) -{ - uint32_t r1; - r1 = (0x2<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_cache_disable_data(void) -{ - uint32_t r1; - r1 = (0x4<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_cache_invalidate_entire_instruction(void) {} -static inline void _CPU_cache_freeze_instruction(void) {} -static inline void _CPU_cache_unfreeze_instruction(void) {} - -static inline void _CPU_cache_enable_instruction(void) -{ - uint32_t r1; - r1 = (0x2<<24); - mtspr( 560, r1 ); - isync; -} - -static inline void _CPU_cache_disable_instruction(void) -{ - uint32_t r1; - r1 = (0x4<<24); - mtspr( 560, r1 ); - isync; -} - -#else - -static inline void _CPU_cache_flush_entire_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_invalidate_entire_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_freeze_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_unfreeze_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_enable_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_disable_data(void) -{ - /* Void */ -} - -static inline void _CPU_cache_invalidate_entire_instruction(void) -{ - /* Void */ -} - -static inline void _CPU_cache_freeze_instruction(void) -{ - /* Void */ -} - -static inline void _CPU_cache_unfreeze_instruction(void) -{ - /* Void */ -} - -static inline void _CPU_cache_enable_instruction(void) -{ - /* Void */ -} - -static inline void _CPU_cache_disable_instruction(void) -{ - /* Void */ -} - -#endif - -static inline void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - __asm__ volatile ( "dcbi 0,%0" :: "r" (addr) : "memory" ); -} - -static inline void _CPU_cache_flush_1_data_line(const void *addr) -{ - __asm__ volatile ( "dcbf 0,%0" :: "r" (addr) : "memory" ); -} - - -static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - __asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory"); -} - -#endif /* LIBCPU_POWERPC_CACHE_H */ diff --git a/c/src/lib/libcpu/shared/include/cache.h b/c/src/lib/libcpu/shared/include/cache.h deleted file mode 100644 index 9220a20d28..0000000000 --- a/c/src/lib/libcpu/shared/include/cache.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * libcpu Cache Manager Support - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * The functions declared in this file are implemented for - * each processor in the cache.c file under libcpu/CPU/. - * They provide the processor specific actions to take for - * implementing most of the RTEMS Cache Manager directives, - * and should only ever be called by these directives. - * - * The API for the RTEMS Cache Manager can be found in - * c/src/exec/rtems/include/rtems/rtems/cache.h - */ - -#ifndef __LIBCPU_CACHE_h -#define __LIBCPU_CACHE_h - -void _CPU_cache_flush_1_data_line(const void *d_addr); -void _CPU_cache_invalidate_1_data_line(const void *d_addr); -void _CPU_cache_freeze_data(void); -void _CPU_cache_unfreeze_data(void); -void _CPU_cache_invalidate_1_instruction_line(const void *d_addr); -void _CPU_cache_freeze_instruction(void); -void _CPU_cache_unfreeze_instruction(void); -void _CPU_cache_flush_entire_data(void); -void _CPU_cache_invalidate_entire_data(void); -void _CPU_cache_enable_data(void); -void _CPU_cache_disable_data(void); -void _CPU_cache_invalidate_entire_instruction(void); -void _CPU_cache_enable_instruction(void); -void _CPU_cache_disable_instruction(void); - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c deleted file mode 100644 index 3201c319b8..0000000000 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * Cache Manager - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * The functions in this file implement the API to the RTEMS Cache Manager and - * are divided into data cache and instruction cache functions. Data cache - * functions only have bodies if a data cache is supported. Instruction - * cache functions only have bodies if an instruction cache is supported. - * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is - * defined, where x E {DATA, INSTRUCTION}. These definitions are found in - * the Cache Manager Wrapper header files, often - * - * rtems/c/src/lib/libcpu/CPU/cache_.h - * - * The cache implementation header file can define - * - * #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS - * - * if it provides cache maintenance functions which operate on multiple lines. - * Otherwise a generic loop with single line operations will be used. It is - * strongly recommended to provide the implementation in terms of static - * inline functions for performance reasons. - * - * The functions below are implemented with CPU dependent inline routines - * found in the cache.c files for each CPU. In the event that a CPU does - * not support a specific function for a cache it has, the CPU dependent - * routine does nothing (but does exist). - * - * At this point, the Cache Manager makes no considerations, and provides no - * support for BSP specific issues such as a secondary cache. In such a system, - * the CPU dependent routines would have to be modified, or a BSP layer added - * to this Manager. - */ - -#include <rtems.h> -#include "cache_.h" - -#if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES -#error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" -#endif - -#if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES -#error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" -#endif - -#if defined(RTEMS_SMP) - -#include <rtems/score/smpimpl.h> - -typedef struct { - const void *addr; - size_t size; -} smp_cache_area; - -#if defined(CPU_DATA_CACHE_ALIGNMENT) - -static void smp_cache_data_flush(void *arg) -{ - smp_cache_area *area = arg; - - rtems_cache_flush_multiple_data_lines(area->addr, area->size); -} - -static void smp_cache_data_inv(void *arg) -{ - smp_cache_area *area = arg; - - rtems_cache_invalidate_multiple_data_lines(area->addr, area->size); -} - -static void smp_cache_data_flush_all(void *arg) -{ - rtems_cache_flush_entire_data(); -} - -static void smp_cache_data_inv_all(void *arg) -{ - rtems_cache_invalidate_entire_data(); -} - -#endif /* defined(CPU_DATA_CACHE_ALIGNMENT) */ - -void -rtems_cache_flush_multiple_data_lines_processor_set( - const void *addr, - size_t size, - const size_t setsize, - const cpu_set_t *set -) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - smp_cache_area area = { addr, size }; - - _SMP_Multicast_action( setsize, set, smp_cache_data_flush, &area ); -#endif -} - -void -rtems_cache_invalidate_multiple_data_lines_processor_set( - const void *addr, - size_t size, - const size_t setsize, - const cpu_set_t *set -) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - smp_cache_area area = { addr, size }; - - _SMP_Multicast_action( setsize, set, smp_cache_data_inv, &area ); -#endif -} - -void -rtems_cache_flush_entire_data_processor_set( - const size_t setsize, - const cpu_set_t *set -) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _SMP_Multicast_action( setsize, set, smp_cache_data_flush_all, NULL ); -#endif -} - -void -rtems_cache_invalidate_entire_data_processor_set( - const size_t setsize, - const cpu_set_t *set -) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _SMP_Multicast_action( setsize, set, smp_cache_data_inv_all, NULL ); -#endif -} - -#endif /* defined(RTEMS_SMP) */ - -/* - * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE - */ - -/* - * This function is called to flush the data cache by performing cache - * copybacks. It must determine how many cache lines need to be copied - * back and then perform the copybacks. - */ -void -rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) -#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) - _CPU_cache_flush_data_range( d_addr, n_bytes ); -#else - const void * final_address; - - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be pushed. Increment d_addr and push - * the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to flush is zero */ - return; - - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); - while( d_addr <= final_address ) { - _CPU_cache_flush_1_data_line( d_addr ); - d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); - } -#endif -#endif -} - - -/* - * This function is responsible for performing a data cache invalidate. - * It must determine how many cache lines need to be invalidated and then - * perform the invalidations. - */ - -void -rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) -#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) - _CPU_cache_invalidate_data_range( d_addr, n_bytes ); -#else - const void * final_address; - - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be invalidated. Increment d_addr and - * invalidate the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to invalidate is zero */ - return; - - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); - while( final_address >= d_addr ) { - _CPU_cache_invalidate_1_data_line( d_addr ); - d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); - } -#endif -#endif -} - - -/* - * This function is responsible for performing a data cache flush. - * It flushes the entire cache. - */ -void -rtems_cache_flush_entire_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - /* - * Call the CPU-specific routine - */ - _CPU_cache_flush_entire_data(); -#endif -} - - -/* - * This function is responsible for performing a data cache - * invalidate. It invalidates the entire cache. - */ -void -rtems_cache_invalidate_entire_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - /* - * Call the CPU-specific routine - */ - - _CPU_cache_invalidate_entire_data(); -#endif -} - - -/* - * This function returns the data cache granularity. - */ -size_t -rtems_cache_get_data_line_size( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - return CPU_DATA_CACHE_ALIGNMENT; -#else - return 0; -#endif -} - - -size_t -rtems_cache_get_data_cache_size( uint32_t level ) -{ -#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) - return _CPU_cache_get_data_cache_size( level ); -#else - return 0; -#endif -} - -/* - * This function freezes the data cache; cache lines - * are not replaced. - */ -void -rtems_cache_freeze_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _CPU_cache_freeze_data(); -#endif -} - - -/* - * This function unfreezes the instruction cache. - */ -void rtems_cache_unfreeze_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _CPU_cache_unfreeze_data(); -#endif -} - - -/* Turn on the data cache. */ -void -rtems_cache_enable_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _CPU_cache_enable_data(); -#endif -} - - -/* Turn off the data cache. */ -void -rtems_cache_disable_data( void ) -{ -#if defined(CPU_DATA_CACHE_ALIGNMENT) - _CPU_cache_disable_data(); -#endif -} - - - -/* - * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE - */ - -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ - && defined(RTEMS_SMP) \ - && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) - -static void smp_cache_inst_inv(void *arg) -{ - smp_cache_area *area = arg; - - _CPU_cache_invalidate_instruction_range(area->addr, area->size); -} - -static void smp_cache_inst_inv_all(void *arg) -{ - _CPU_cache_invalidate_entire_instruction(); -} - -#endif - -/* - * This function is responsible for performing an instruction cache - * invalidate. It must determine how many cache lines need to be invalidated - * and then perform the invalidations. - */ - -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ - && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) -static void -_CPU_cache_invalidate_instruction_range( - const void * i_addr, - size_t n_bytes -) -{ - const void * final_address; - - /* - * Set i_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be invalidated. Increment i_addr and - * invalidate the resulting line until final_address is passed. - */ - - if( n_bytes == 0 ) - /* Do nothing if number of bytes to invalidate is zero */ - return; - - final_address = (void *)((size_t)i_addr + n_bytes - 1); - i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); - while( final_address >= i_addr ) { - _CPU_cache_invalidate_1_instruction_line( i_addr ); - i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); - } -} -#endif - -void -rtems_cache_invalidate_multiple_instruction_lines( - const void * i_addr, - size_t n_bytes -) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) -#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) - smp_cache_area area = { i_addr, n_bytes }; - - _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv, &area ); -#else - _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); -#endif -#endif -} - - -/* - * This function is responsible for performing an instruction cache - * invalidate. It invalidates the entire cache. - */ -void -rtems_cache_invalidate_entire_instruction( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) -#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) - _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv_all, NULL ); -#else - _CPU_cache_invalidate_entire_instruction(); -#endif -#endif -} - - -/* - * This function returns the instruction cache granularity. - */ -size_t -rtems_cache_get_instruction_line_size( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - return CPU_INSTRUCTION_CACHE_ALIGNMENT; -#else - return 0; -#endif -} - - -size_t -rtems_cache_get_instruction_cache_size( uint32_t level ) -{ -#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) - return _CPU_cache_get_instruction_cache_size( level ); -#else - return 0; -#endif -} - - -/* - * This function freezes the instruction cache; cache lines - * are not replaced. - */ -void -rtems_cache_freeze_instruction( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - _CPU_cache_freeze_instruction(); -#endif -} - - -/* - * This function unfreezes the instruction cache. - */ -void rtems_cache_unfreeze_instruction( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - _CPU_cache_unfreeze_instruction(); -#endif -} - - -/* Turn on the instruction cache. */ -void -rtems_cache_enable_instruction( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - _CPU_cache_enable_instruction(); -#endif -} - - -/* Turn off the instruction cache. */ -void -rtems_cache_disable_instruction( void ) -{ -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - _CPU_cache_disable_instruction(); -#endif -} - -/* Returns the maximal cache line size of all cache kinds in bytes. */ -size_t rtems_cache_get_maximal_line_size( void ) -{ -#if defined(CPU_MAXIMAL_CACHE_ALIGNMENT) - return CPU_MAXIMAL_CACHE_ALIGNMENT; -#endif - size_t max_line_size = 0; -#if defined(CPU_DATA_CACHE_ALIGNMENT) - { - size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT; - if ( max_line_size < data_line_size ) - max_line_size = data_line_size; - } -#endif -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) - { - size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT; - if ( max_line_size < instruction_line_size ) - max_line_size = instruction_line_size; - } -#endif - return max_line_size; -} - -/* - * Purpose is to synchronize caches after code has been loaded - * or self modified. Actual implementation is simple only - * but it can and should be repaced by optimized version - * which does not need flush and invalidate all cache levels - * when code is changed. - */ -void -rtems_cache_instruction_sync_after_code_change( const void * code_addr, size_t n_bytes ) -{ -#if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION) - _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes ); -#else - rtems_cache_flush_multiple_data_lines( code_addr, n_bytes ); - rtems_cache_invalidate_multiple_instruction_lines( code_addr, n_bytes ); -#endif -} diff --git a/c/src/lib/libcpu/shared/src/no_cache.c b/c/src/lib/libcpu/shared/src/no_cache.c deleted file mode 100644 index 3f869fcd60..0000000000 --- a/c/src/lib/libcpu/shared/src/no_cache.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * STUB Cache Management Support Routines - */ - -#include <rtems.h> -#include "cache_.h" - -/* - * CACHE MANAGER: The following functions should be implemented - * properly for each CPU if it has a cache. These provide the basic - * implementation for the rtems_* cache management routines. If a given - * function has no meaning for the CPU, then just let your implementation - * do nothing. - * - * This is just a series of stubs. - */ - -void _CPU_cache_freeze_data ( void ) {} -void _CPU_cache_unfreeze_data ( void ) {} -void _CPU_cache_freeze_instruction ( void ) {} -void _CPU_cache_unfreeze_instruction ( void ) {} - -void _CPU_cache_flush_1_data_line ( - const void * d_addr ) -{ -} - -void _CPU_cache_invalidate_1_data_line ( - const void * d_addr ) -{ -} - -void _CPU_cache_flush_entire_data ( void ) -{ -} - -void _CPU_cache_invalidate_entire_data ( void ) -{ -} - -void _CPU_cache_enable_data ( void ) -{ -} - -void _CPU_cache_disable_data ( void ) -{ -} - -void _CPU_cache_invalidate_1_instruction_line ( - const void * i_addr ) -{ -} - -void _CPU_cache_invalidate_entire_instruction ( void ) -{ -} - -void _CPU_cache_enable_instruction ( void ) -{ -} - -void _CPU_cache_disable_instruction ( void ) -{ -} -/* end of file */ diff --git a/c/src/lib/libcpu/sparc/Makefile.am b/c/src/lib/libcpu/sparc/Makefile.am index 4d957dac04..95e473d622 100644 --- a/c/src/lib/libcpu/sparc/Makefile.am +++ b/c/src/lib/libcpu/sparc/Makefile.am @@ -4,16 +4,6 @@ include $(top_srcdir)/../../../automake/compile.am noinst_PROGRAMS = -noinst_PROGRAMS += cache.rel -cache_rel_SOURCES = cache/cache_.h \ - ../shared/src/cache_manager.c -cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/cache -cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -if has_instruction_cache -cache_rel_CPPFLAGS += -DHAS_INSTRUCTION_CACHE -endif - noinst_PROGRAMS += syscall.rel syscall_rel_SOURCES = syscall/syscall.S syscall/syscall.h syscall_rel_CPPFLAGS = $(AM_CPPFLAGS) diff --git a/c/src/lib/libcpu/sparc/cache/cache_.h b/c/src/lib/libcpu/sparc/cache/cache_.h deleted file mode 100644 index 3d4ea69f8b..0000000000 --- a/c/src/lib/libcpu/sparc/cache/cache_.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * SPARC Cache Manager Support - */ - -#ifndef __SPARC_CACHE_h -#define __SPARC_CACHE_h - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -/* This define is set in a Makefile */ -#if defined(HAS_INSTRUCTION_CACHE) - -#define CPU_INSTRUCTION_CACHE_ALIGNMENT 0 - -#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS - -static inline void _CPU_cache_invalidate_entire_instruction ( void ) -{ - __asm__ volatile ("flush"); -} - -static inline void _CPU_cache_invalidate_instruction_range( - const void *i_addr, - size_t n_bytes -) -{ - __asm__ volatile ("flush"); -} - -/* XXX these need to be addressed */ - -static inline void _CPU_cache_freeze_instruction ( void ) -{ -} - -static inline void _CPU_cache_unfreeze_instruction ( void ) -{ -} - -static inline void _CPU_cache_enable_instruction ( void ) -{ -} - -static inline void _CPU_cache_disable_instruction ( void ) -{ -} - -#endif /* defined(HAS_INSTRUCTION_CACHE) */ - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/sparc/configure.ac b/c/src/lib/libcpu/sparc/configure.ac index 98b2ce8c4b..7107f971a9 100644 --- a/c/src/lib/libcpu/sparc/configure.ac +++ b/c/src/lib/libcpu/sparc/configure.ac @@ -21,9 +21,6 @@ AM_PROG_CC_C_O RTEMS_CANONICALIZE_TOOLS RTEMS_PROG_CCAS -AM_CONDITIONAL(has_instruction_cache, test "$RTEMS_CPU_MODEL" = "leon1" \ -|| test "$RTEMS_CPU_MODEL" = "leon2" || test "$RTEMS_CPU_MODEL" = "leon3" ) - RTEMS_AMPOLISH3 # Explicitly list all Makefiles here diff --git a/c/src/lib/libcpu/sparc64/Makefile.am b/c/src/lib/libcpu/sparc64/Makefile.am index 81d07d4617..d5883f5bd4 100644 --- a/c/src/lib/libcpu/sparc64/Makefile.am +++ b/c/src/lib/libcpu/sparc64/Makefile.am @@ -21,20 +21,8 @@ shared_sparc64_syscall_rel_SOURCES = shared/syscall/sparc64-syscall.S \ shared/syscall/sparc64-syscall.h shared_sparc64_syscall_rel_CPPFLAGS = $(AM_CPPFLAGS) shared_sparc64_syscall_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += shared/cache.rel -shared_cache_rel_SOURCES = shared/cache/cache.c shared/cache/cache_.h \ - ../shared/src/cache_manager.c -shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache -shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -#if has_instruction_cache -#cache_rel_CPPFLAGS += -DHAS_INSTRUCTION_CACHE -#endif - - - ### This is an example of how to define a separate score implementation. ## NOTE: Unlike other CPUs, we install into a subdirectory to avoid ## file name conflicts (See sh CPU for simexampleilar approach) diff --git a/c/src/lib/libcpu/sparc64/shared/cache/cache.c b/c/src/lib/libcpu/sparc64/shared/cache/cache.c deleted file mode 100644 index 63b6bb1cc6..0000000000 --- a/c/src/lib/libcpu/sparc64/shared/cache/cache.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Cache Management Support Routines for the SPARC 64 - */ - -#include <rtems.h> -#include "cache_.h" - - -#if defined(HAS_INSTRUCTION_CACHE) - -void _CPU_cache_invalidate_entire_instruction ( void ) -{ - __asm__ volatile ("flush"); -} - -/* XXX these need to be addressed */ -void _CPU_cache_freeze_instruction ( void ) -{ -} - -void _CPU_cache_unfreeze_instruction ( void ) -{ -} - -void _CPU_cache_enable_instruction ( void ) -{ -} - -void _CPU_cache_disable_instruction ( void ) -{ -} - -#endif -/* end of file */ diff --git a/c/src/lib/libcpu/sparc64/shared/cache/cache_.h b/c/src/lib/libcpu/sparc64/shared/cache/cache_.h deleted file mode 100644 index fc3600f380..0000000000 --- a/c/src/lib/libcpu/sparc64/shared/cache/cache_.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * SPARC64 Cache Manager Support - */ - -#ifndef __SPARC_CACHE_h -#define __SPARC_CACHE_h - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -#if defined(HAS_INSTRUCTION_CACHE) -#define CPU_INSTRUCTION_CACHE_ALIGNMENT 0 -#endif - -#include "../../../shared/include/cache.h" - -#endif -/* end of include file */ |