blob: da31a38bee7de81cffeb94fc201cc29af57b32a4 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
|
/*
* Cache Management Support Routines for the i386
*/
#include <rtems.h>
#include "cache_.h"
#include <rtems/score/cpu.h>
#include <libcpu/page.h>
void _CPU_disable_cache(void)
{
unsigned int regCr0;
regCr0 = i386_get_cr0();
regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
regCr0 |= CR0_NO_WRITE_THROUGH;
i386_set_cr0( regCr0 );
rtems_cache_flush_entire_data();
}
/*
* Enable the entire cache
*/
void _CPU_enable_cache(void)
{
unsigned int regCr0;
regCr0 = i386_get_cr0();
regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
regCr0 &= ~(CR0_NO_WRITE_THROUGH);
i386_set_cr0( regCr0 );
/*rtems_cache_flush_entire_data();*/
}
/*
* CACHE MANAGER: The following functions are CPU-specific.
* They provide the basic implementation for the rtems_* cache
* management routines. If a given function has no meaning for the CPU,
* it does nothing by default.
*
* FIXME: The routines below should be implemented per CPU,
* to accomodate the capabilities of each.
*/
#if defined(I386_CACHE_ALIGNMENT)
void _CPU_cache_flush_1_data_line(const void *d_addr) {}
void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
void _CPU_cache_freeze_data(void) {}
void _CPU_cache_unfreeze_data(void) {}
void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
void _CPU_cache_freeze_instruction(void) {}
void _CPU_cache_unfreeze_instruction(void) {}
void _CPU_cache_flush_entire_data(void)
{
__asm__ volatile ("wbinvd");
}
void _CPU_cache_invalidate_entire_data(void)
{
__asm__ volatile ("invd");
}
void _CPU_cache_enable_data(void)
{
_CPU_enable_cache();
}
void _CPU_cache_disable_data(void)
{
_CPU_disable_cache();
}
void _CPU_cache_invalidate_entire_instruction(void)
{
__asm__ volatile ("invd");
}
void _CPU_cache_enable_instruction(void)
{
_CPU_enable_cache();
}
void _CPU_cache_disable_instruction( void )
{
_CPU_disable_cache();
}
#endif
|