score: Rename _ISR_Disable() and _ISR_Enable()

Rename _ISR_Disable() into _ISR_Local_disable().  Rename _ISR_Enable()
into _ISR_Local_enable().  Remove _Debug_Is_owner_of_giant().

This is a preparation to remove the Giant lock.

Update #2555.

7 files changed, 54 insertions, 54 deletions

diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2dde..54728e1e1d 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -20,11 +20,11 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_disable_data(void)
@@ -32,12 +32,12 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_enable_instruction(void)
@@ -45,12 +45,12 @@ static inline void _CPU_OR1K_Cache_enable_instruction(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_disable_instruction(void)
@@ -58,96 +58,96 @@ static inline void _CPU_OR1K_Cache_disable_instruction(void)
   uint32_t sr;
   ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 {
   ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_prefetch
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_invalidate
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_lock
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 /* Implement RTEMS cache manager functions */
@@ -155,23 +155,23 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_flush(d_addr);
 
   //asm volatile("l.csync");
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_invalidate(d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_freeze_data(void)
@@ -187,11 +187,11 @@ void _CPU_cache_unfreeze_data(void)
 void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_freeze_instruction(void)
diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
index 4e6202ed79..8b74a9759c 100644
--- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
+++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
@@ -57,7 +57,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
    * form, but this routine is probably being run as part of an
    * initialization sequence so the effect shouldn't be too severe.
    */
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
     /*
@@ -85,7 +85,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
     }
   }
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 
   if (blockp == NULL)
     rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
index 94fcaa61c8..4f6cb6d94a 100644
--- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
+++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
@@ -55,7 +55,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
    * form, but this routine is probably being run as part of an
    * initialization sequence so the effect shouldn't be too severe.
    */
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
     /*
@@ -83,7 +83,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
     }
   }
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 
   if (blockp == NULL)
     rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
index 649c89de89..99d9cc9a6a 100644
--- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
@@ -111,14 +111,14 @@ unsigned int sh_set_irq_priority(
   /*
    * Set the interrupt priority register
    */
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
     temp16 = read16( prioreg);
     temp16 &= ~( 15 << shiftcount);
     temp16 |= prio << shiftcount;
     write16( temp16, prioreg);
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return 0;
 }
@@ -131,7 +131,7 @@ void __ISR_Handler( uint32_t   vector)
 {
   ISR_Level level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_disable();
 
@@ -147,13 +147,13 @@ void __ISR_Handler( uint32_t   vector)
 
   _ISR_Nest_level++;
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   /* call isp */
   if ( _ISR_Vector_table[ vector])
     (*_ISR_Vector_table[ vector ])( vector );
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_unnest( _Per_CPU_Get() );
 
@@ -166,7 +166,7 @@ void __ISR_Handler( uint32_t   vector)
     stack_ptr = _old_stack_ptr;
 #endif
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   if ( _ISR_Nest_level )
     return;
diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
index f7534269a6..47bc859dbd 100644
--- a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
@@ -112,14 +112,14 @@ unsigned int sh_set_irq_priority(
   /*
    * Set the interrupt priority register
    */
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
     temp16 = read16( prioreg);
     temp16 &= ~( 15 << shiftcount);
     temp16 |= prio << shiftcount;
     write16( temp16, prioreg);
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return 0;
 }
@@ -132,7 +132,7 @@ void __ISR_Handler( uint32_t   vector)
 {
   ISR_Level level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_disable();
 
@@ -148,13 +148,13 @@ void __ISR_Handler( uint32_t   vector)
 
   _ISR_Nest_level++;
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   /* call isp */
   if ( _ISR_Vector_table[ vector])
     (*_ISR_Vector_table[ vector ])( vector );
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_unnest( _Per_CPU_Get() );
 
@@ -167,7 +167,7 @@ void __ISR_Handler( uint32_t   vector)
     stack_ptr = _old_stack_ptr;
 #endif
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   if ( _ISR_Nest_level )
     return;
diff --git a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
index f47e360d51..52a033bb75 100644
--- a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
@@ -56,7 +56,7 @@ void __ISR_Handler( uint32_t   vector)
 {
   ISR_Level level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
    _Thread_Dispatch_disable();
 
@@ -72,13 +72,13 @@ void __ISR_Handler( uint32_t   vector)
 
   _ISR_Nest_level++;
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   /* call isp */
   if ( _ISR_Vector_table[ vector])
     (*_ISR_Vector_table[ vector ])( vector );
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_enable( _Per_CPU_Get() );
 
@@ -90,7 +90,7 @@ void __ISR_Handler( uint32_t   vector)
     stack_ptr = _old_stack_ptr;
 #endif
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   if ( _ISR_Nest_level )
     return;
diff --git a/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c b/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
index cb93c5ab3b..2ca8926a24 100644
--- a/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
@@ -33,7 +33,7 @@ void __ISR_Handler( uint32_t   vector)
 {
   ISR_Level level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_disable();
 
@@ -49,13 +49,13 @@ void __ISR_Handler( uint32_t   vector)
 
   _ISR_Nest_level++;
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   /* call isp */
   if ( _ISR_Vector_table[ vector])
     (*_ISR_Vector_table[ vector ])( vector );
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   _Thread_Dispatch_unnest( _Per_CPU_Get() );
 
@@ -68,7 +68,7 @@ void __ISR_Handler( uint32_t   vector)
     stack_ptr = _old_stack_ptr;
 #endif
 
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   if ( _ISR_Nest_level )
     return;