1 files changed, 30 insertions, 30 deletions

diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2dde..54728e1e1d 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -20,11 +20,11 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_disable_data(void)
@@ -32,12 +32,12 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_enable_instruction(void)
@@ -45,12 +45,12 @@ static inline void _CPU_OR1K_Cache_enable_instruction(void)
   uint32_t sr;
    ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_disable_instruction(void)
@@ -58,96 +58,96 @@ static inline void _CPU_OR1K_Cache_disable_instruction(void)
   uint32_t sr;
   ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 {
   ISR_Level level;
 
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_prefetch
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_invalidate
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 static inline void _CPU_OR1K_Cache_instruction_block_lock
 (const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 /* Implement RTEMS cache manager functions */
@@ -155,23 +155,23 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_flush(d_addr);
 
   //asm volatile("l.csync");
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_invalidate(d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_freeze_data(void)
@@ -187,11 +187,11 @@ void _CPU_cache_unfreeze_data(void)
 void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
    ISR_Level level;
-  _ISR_Disable (level);
+  _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
 
-  _ISR_Enable(level);
+  _ISR_Local_enable(level);
 }
 
 void _CPU_cache_freeze_instruction(void)