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author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-14 08:46:06 +0000 |
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committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-14 08:46:06 +0000 |
commit | 3c6fe2e7f95f6bff53123df9377b114cadeac874 (patch) | |
tree | fef9ad7a4cd45497a1a84c1b7f9cd103eb258c43 /c/src/lib/libcpu/powerpc/ppc403/include | |
parent | corrections in display driver (diff) | |
download | rtems-3c6fe2e7f95f6bff53123df9377b114cadeac874.tar.bz2 |
added haleakala BSP contributed by Michael Hamel
Diffstat (limited to 'c/src/lib/libcpu/powerpc/ppc403/include')
-rw-r--r-- | c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h | 158 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h | 146 |
2 files changed, 304 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h new file mode 100644 index 0000000000..e64fc2d936 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h @@ -0,0 +1,158 @@ + +/* + +Constants for manipulating system registers of PPC 405EX in C + +Michael Hamel ADInstruments May 2008 + +*/ + +#include <libcpu/powerpc-utility.h> +/* Indirect access to Clocking/Power-On registers */ +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ + } while (0) + +#define mfcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ + } while (0) + + +/* Indirect access to System registers */ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define mtsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ + } while (0) + +#define mfsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ + } while (0) + +/* Indirect access to EBC registers */ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +#define mtebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ + } while (0) + +#define mfebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ + } while (0) + +/* EBC DCRs */ +enum { + /* + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_BEAR = 0x20, + EBC0_BESR = 0x21, + EBC0_CFG = 0x23, + */ + EBC0_CID = 0x24 +}; + +enum { + SDR0_UART0 = 0x120, + SDR0_UART1 = 0x121, + SDR0_C405 = 0x180, + SDR0_MALTBL = 0x280, + SDR0_MALRBL = 0x2A0, + SDR0_MALTBS = 0x2C0, + SDR0_MALRBS = 0x2E0 +}; + + +/* Memory-mapped registers */ + + +/*======================= Ethernet =================== */ + + +typedef struct EthernetRegisters_EX { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t multicastAddr[2]; + uint32_t multicastMask[2]; + uint32_t unused[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermark; + uint32_t bytesXmtd; + uint32_t bytesRcvd; + uint32_t unused2; + uint32_t revID; + uint32_t unused3[2]; + uint32_t indivHash[8]; + uint32_t groupHash[8]; + uint32_t xmtPause; +} EthernetRegisters_EX; + +enum { + EMAC0Address = 0xEF600900, + EMAC1Address = 0xEF600A00 +}; + + +typedef struct GPIORegisters { + uint32_t OR; + uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ + uint32_t OSRL; + uint32_t OSRH; + uint32_t TSRL; + uint32_t TSRH; + uint32_t ODR; + uint32_t IR; + uint32_t RR1; + uint32_t RR2; + uint32_t RR3; + uint32_t unknown; + uint32_t ISR1L; + uint32_t ISR1H; + uint32_t ISR2L; + uint32_t ISR2H; + uint32_t ISR3L; + uint32_t ISR3H; +} GPIORegisters; + +enum { GPIOAddress = 0xEF600800 }; + diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h new file mode 100644 index 0000000000..814f18d046 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h @@ -0,0 +1,146 @@ + + +/* SDRAM DCRs */ +enum { + SDRAM0_BESR0 = 0, + SDRAM0_BESR1 = 8, + SDRAM0_BEAR = 0x10, + SDRAM0_CFG = 0x20, + SDRAM0_STATUS = 0x24, + SDRAM0_RTR = 0x30, + SDRAM0_PMIT = 0x34, + SDRAM0_TR = 0x80 +}; + + +/* EBC DCRs */ +enum { + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B4CR = 4, + EBC0_B5CR = 5, + EBC0_B6CR = 6, + EBC0_B7CR = 7, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_B4AP = 0x14, + EBC0_B5AP = 0x15, + EBC0_B6AP = 0x16, + EBC0_B7AP = 0x17, + EBC0_BEAR = 0x20, + EBC0_BESR0 = 0x21, + EBC0_BESR1 = 0x22, + EBC0_CFG = 0x23 +}; + +/* Memory-mapped registers */ + +typedef struct EthernetRegisters_GP { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t indivHash[4]; + uint32_t groupHash[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermark; + uint32_t bytesXmtd; + uint32_t bytesRcvd; +} EthernetRegisters_GP; + +enum { EMACAddress = 0xEF600800 }; + +enum { + // Mode 0 bits + kEMACRxIdle = 0x80000000, + kEMACTxIdle = 0x40000000, + kEMACSoftRst = 0x20000000, + kEMACTxEnable = 0x10000000, + kEMACRxEnable = 0x08000000, + + // Mode 1 bits + kEMACFullDuplex = 0x80000000, + kEMACIgnoreSQE = 0x01000000, + kEMAC100MBbps = 0x00400000, + kEMAC4KRxFIFO = 0x00300000, + kEMAC2KTxFIFO = 0x00080000, + kEMACTx0Multi = 0x00008000, + kEMACTxDependent= 0x00014000, + + // Tx mode bits + kEMACNewPacket0 = 0x80000000, + kEMACNewPacket1 = 0x40000000, + + // Receive mode bits + kEMACStripPadding = 0x80000000, + kEMACStripFCS = 0x40000000, + kEMACRcvRunts = 0x20000000, + kEMACRcvFCSErrs = 0x10000000, + kEMACRcvOversize = 0x08000000, + kEMACPromiscRcv = 0x01000000, + kEMACPromMultRcv = 0x00800000, + kEMACIndivRcv = 0x00400000, + kEMACHashRcv = 0x00200000, + kEMACBrcastRcv = 0x00100000, + kEMACMultcastRcv = 0x00080000, + + // Buffer descriptor control bits + kMALTxReady = 0x8000, + kMALRxEmpty = 0x8000, + kMALWrap = 0x4000, + kMALContinuous = 0x2000, + kMALLast = 0x1000, + kMALRxFirst = 0x0800, + kMALInterrupt = 0x0400, + + // EMAC Tx descriptor bits sent + kEMACGenFCS = 0x200, + kEMACGenPad = 0x100, + kEMACInsSrcAddr = 0x080, + kEMACRepSrcAddr = 0x040, + kEMACInsVLAN = 0x020, + kEMACRepVLAN = 0x010, + + // EMAC TX descriptor bits returned + kEMACErrMask = 0x3FF, + kEMACFCSWrong = 0x200, + kEMACBadPrev = 0x100, + kEMACLostCarrier = 0x080, + kEMACDeferred = 0x040, + kEMACCollFail = 0x020, + kEMACLateColl = 0x010, + kEMACMultColl = 0x008, + kEMACOneColl = 0x004, + kEMACUnderrun = 0x002, + kEMACSQEFail = 0x001, + + // EMAC Rx descriptor bits returned + kEMACOverrun = 0x200, + kEMACPausePkt = 0x100, + kEMACBadPkt = 0x080, + kEMACRuntPkt = 0x040, + kEMACShortEvt = 0x020, + kEMACAlignErr = 0x010, + kEMACBadFCS = 0x008, + kEMACPktLong = 0x004, + kEMACPktOOR = 0x002, + kEMACPktIRL = 0x001 +}; + + |