diff options
| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-14 08:46:06 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-14 08:46:06 +0000 |
| commit | 3c6fe2e7f95f6bff53123df9377b114cadeac874 (patch) | |
| tree | fef9ad7a4cd45497a1a84c1b7f9cd103eb258c43 | |
| parent | corrections in display driver (diff) | |
| download | rtems-3c6fe2e7f95f6bff53123df9377b114cadeac874.tar.bz2 | |
added haleakala BSP contributed by Michael Hamel
40 files changed, 2659 insertions, 81 deletions
@@ -1,7 +1,12 @@ +2008-07-14 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * make/custom/haleakala.cfg: + added PPC405 haleakala BSP contributed by Michael Hamel + 2008-07-09 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> * aclocal/bsp-alias.m4, aclocal/check-bsps.m4, - make/custom/m5484FireEngine.cfg: + * make/custom/m5484FireEngine.cfg: added pgh360 BSP variant added m5484FireEngine BSP diff --git a/c/src/lib/libbsp/powerpc/ChangeLog b/c/src/lib/libbsp/powerpc/ChangeLog index edd3ee28d2..4d118f49d0 100644 --- a/c/src/lib/libbsp/powerpc/ChangeLog +++ b/c/src/lib/libbsp/powerpc/ChangeLog @@ -1,3 +1,6 @@ +2008-07-14 Thomas Doefler <Thomas.Doerfler@embedded-brains.de> + * haleakala: added new BSP + 2008-07-11 Sebastian Huber <sebastian.huber@embedded-brains.de> * ep1a/startup/bspstart.c, mvme3100/startup/bspstart.c, diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4 b/c/src/lib/libbsp/powerpc/acinclude.m4 index e3e9fecc16..0c46a901b4 100644 --- a/c/src/lib/libbsp/powerpc/acinclude.m4 +++ b/c/src/lib/libbsp/powerpc/acinclude.m4 @@ -8,6 +8,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR], AC_CONFIG_SUBDIRS([gen5200]);; gen83xx ) AC_CONFIG_SUBDIRS([gen83xx]);; + haleakala ) + AC_CONFIG_SUBDIRS([haleakala]);; mbx8xx ) AC_CONFIG_SUBDIRS([mbx8xx]);; motorola_powerpc ) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c index e4d35dbfd5..141fdb679c 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c @@ -18,11 +18,7 @@ \*===============================================================*/ /* -<<<<<<< bspstart.c * $Id$ -======= - * $Id$ ->>>>>>> 1.11 */ #include <bsp.h> diff --git a/c/src/lib/libbsp/powerpc/haleakala/ChangeLog b/c/src/lib/libbsp/powerpc/haleakala/ChangeLog new file mode 100644 index 0000000000..91a7b1bad8 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/ChangeLog @@ -0,0 +1,13 @@ +2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de> + + * README, bsp_specs, INSTALL, bsp_specs.dl, configure.ac, + * Makefile.am, preinstall.am, dlentry/dlentry.S, + * include/bsp.h, include/coverhd.h, include/tm27.h + * irq/irq.c, irq/irq.h, irq/irq_init.c, + * startup/bspclean.c, startup/bspstart.c, startup/linkcmds: + + Added BSP contributed by Michael Hamel + + + + diff --git a/c/src/lib/libbsp/powerpc/haleakala/INSTALL b/c/src/lib/libbsp/powerpc/haleakala/INSTALL new file mode 100644 index 0000000000..91626b3a89 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/INSTALL @@ -0,0 +1 @@ +<to be filled in > diff --git a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am new file mode 100644 index 0000000000..be74e8d2a5 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am @@ -0,0 +1,96 @@ +## +## $Id$ +## + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am +include $(top_srcdir)/../../bsp.am + +dist_project_lib_DATA = bsp_specs + +include_HEADERS = include/bsp.h +include_HEADERS += include/tm27.h + +nodist_include_HEADERS = include/bspopts.h +DISTCLEANFILES = include/bspopts.h + +noinst_PROGRAMS = + +include_bspdir = $(includedir)/bsp + +include_HEADERS += include/coverhd.h + +EXTRA_DIST = ../../powerpc/shared/start/rtems_crti.S +rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S + $(CPPASCOMPILE) -o $@ -c $< +project_lib_DATA = rtems_crti.$(OBJEXT) + +dist_project_lib_DATA += startup/linkcmds + + +noinst_PROGRAMS += startup.rel +startup_rel_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \ + ../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \ + ../../shared/sbrk.c startup/setvec.c \ + ../../shared/gnatinstallhandler.c +startup_rel_CPPFLAGS = $(AM_CPPFLAGS) +startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + + +noinst_PROGRAMS += dlentry.rel +dlentry_rel_SOURCES = dlentry/dlentry.S +dlentry_rel_CPPFLAGS = $(AM_CPPFLAGS) +dlentry_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +include_bsp_HEADERS = ../../powerpc/shared/console/uart.h +include_bsp_HEADERS += ../../powerpc/shared/console/consoleIo.h + +noinst_PROGRAMS += console.rel +console_rel_SOURCES = ../../powerpc/shared/console/uart.c \ + ../../powerpc/shared/console/console.c +console_rel_CPPFLAGS = $(AM_CPPFLAGS) +console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +include_bsp_HEADERS += irq/irq.h \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h + +noinst_PROGRAMS += irq.rel +irq_rel_SOURCES = irq/irq_init.c irq/irq.c +irq_rel_CPPFLAGS = $(AM_CPPFLAGS) +irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + + +if HAS_NETWORKING +network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ +noinst_PROGRAMS += network.rel +network_rel_SOURCES = network/network.c +network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS) +network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) +endif + + +noinst_LIBRARIES = libbsp.a +libbsp_a_SOURCES = + +libbsp_a_LIBADD = startup.rel dlentry.rel console.rel irq.rel + +if HAS_NETWORKING +libbsp_a_LIBADD += network.rel +endif + +libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \ + ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ + ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \ + ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel + + +EXTRA_DIST += times + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/powerpc/haleakala/README b/c/src/lib/libbsp/powerpc/haleakala/README new file mode 100644 index 0000000000..a17e582721 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/README @@ -0,0 +1,55 @@ +# +# $Id$ +# + +# Adapted from Virtex BSP + +BSP NAME: Haleakala +BOARD: AMCC/UDTech Haleakala 405Exr eval board +BUS: N/A +CPU FAMILY: ppc +CPU: PowerPC 405EXr +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: + +PERIPHERALS +=========== +TIMERS: 405EXr internal +SERIAL PORTS: 405EXr internal +REAL-TIME CLOCK: DS1338 +DMA: 405EXr internal +VIDEO: none +SCSI: none +NETWORKING: 405EXr internal + +DRIVER INFORMATION +================== +CLOCK DRIVER: PPC Decrementer +IOSUPP DRIVER: N/A +SHMSUPP: N/A +TIMER DRIVER: N/A +TTY DRIVER: shared + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: RS-232 +BAUD: 9600-115200 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +Notes +===== + +Board description +----------------- +clock rate: 400 MHz +ROM: 64MByte FLASH +RAM: 256MByte DDR DRAM + + +Porting +------- diff --git a/c/src/lib/libbsp/powerpc/haleakala/bsp_specs b/c/src/lib/libbsp/powerpc/haleakala/bsp_specs new file mode 100644 index 0000000000..9102ad7442 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s}} + +*endfile: +%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -u download_entry -N } + diff --git a/c/src/lib/libbsp/powerpc/haleakala/bsp_specs.dl b/c/src/lib/libbsp/powerpc/haleakala/bsp_specs.dl new file mode 100644 index 0000000000..24804479a0 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/bsp_specs.dl @@ -0,0 +1,23 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} %{qrtems: ecrti%O%s --start-group \ +%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \ +-lc -lgcc --end-group \ +%{!qnolinkcmds: -T linkcmds%s}} + +*startfile: +%{!qrtems: %(old_startfile)} %{qrtems: \ +%{!qrtems_debug: } \ +%{qrtems_debug: }} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -u download_entry -N } + diff --git a/c/src/lib/libbsp/powerpc/haleakala/configure.ac b/c/src/lib/libbsp/powerpc/haleakala/configure.ac new file mode 100644 index 0000000000..f3e5214ca5 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/configure.ac @@ -0,0 +1,40 @@ +dnl Process this file with autoconf to produce a configure script. +dnl +dnl $Id$ + +AC_PREREQ(2.59) +AC_INIT([rtems-c-src-lib-libbsp-powerpc-haleakala],[_RTEMS_VERSION],[rtems-bugs@rtems.com]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_NETWORKING + +AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") + +RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[1]) +RTEMS_BSPOPTS_HELP([PPC_USE_SPRG], +[If defined, then the PowerPC specific code in RTEMS will use some + of the special purpose registers to slightly optimize interrupt + response time. The use of these registers can conflict with + other tools like debuggers.]) + +RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100]) +RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE], +[This defines the base address of the exception table. + NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.]) + + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) + +RTEMS_PPC_EXCEPTIONS + +AC_OUTPUT diff --git a/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S new file mode 100644 index 0000000000..3eb321432b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S @@ -0,0 +1,245 @@ +/* dlentry.s + * + * This file contains the entry code for RTEMS programs starting + * after download to RAM + * + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + * + * derived from "helas403/dlentry.S": + * + * Further changes to derive for the PPC405CR/GP/GPr/EX/EXr + * by Michael Hamel ADInstruments Ltd 2008 + * + * + * Id: dlentry.S,v 1.2 2000/08/02 16:30:57 joel Exp + */ + +#include <rtems/asm.h> + +/* + * The virtex ELF link scripts support three special sections: + * .entry The actual entry point + * .vectors The section containing the interrupt entry veneers. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .text + * .data + * .bss + * see linker command file for section placement + * + * The initial stack is set to stack.end + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here was some DWARF information. IMD removed it, because we + * could not check, whether it was still correct. Sorry. + + */ + + + .section .entry + + PUBLIC_VAR (start) + PUBLIC_VAR (download_entry) + PUBLIC_VAR (__rtems_entry_point) + +SYM(start): +SYM(download_entry): +SYM(__rtems_entry_point): + + .extern SYM (boot_card) + + bl .startup /* First word is branch to reset_entry */ + + +/*--------------------------------------------------------------------------- + * Parameters from linker + *--------------------------------------------------------------------------*/ + +base_addr: +toc_pointer: + .long s.got +bss_length: + .long bss.size +bss_addr: + .long bss.start +sbss_length: + .long sbss.size +sbss_addr: + .long sbss.start +stack_top: + .long stack.end +PUBLIC_VAR (text_addr) +text_addr: + .long text.start +PUBLIC_VAR (text_length) +text_length: + .long text.size + +/*--------------------------------------------------------------------------- + * Reset_entry. + *--------------------------------------------------------------------------*/ +.startup: + /* Get entrypoint address in R1 so we can find linker variables */ + mflr r1 + + /* Initialise procesor registers generally */ + bl init405 + + /* Clear .bss and .sbss */ + bl bssclr + + /*------------------------------------------------------------------- + * C_setup. + *------------------------------------------------------------------*/ + lwz r1,stack_top - base_addr(r1) /* Now set R1 to stack_top */ + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + li r3,0 + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + + bl __eabi /* Initialise EABI: sets up r2 & r13 */ + + lis r5,environ@ha + la r5,environ@l(r5) /* environp */ + li r4, 0 /* argv */ + li r3, 0 /* argc */ + + b SYM (boot_card) /* call the first C routine */ + +/*--------------------------------------------------------------------------- + * bssclr. + *--------------------------------------------------------------------------*/ +bssclr: lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + srwi. r3,r3,2 /* div 4 to get # of words */ + li r0,0 + beq dosbss /* no bss */ + mtctr r3 /* set ctr reg */ + subi r2,r2,4 +clear_bss: stwu r0,4(r2) + bdnz clear_bss /* decrement counter and loop */ + +dosbss: lwz r2,sbss_addr-base_addr(r1) /* start of sbss set by loader */ + lwz r3,sbss_length-base_addr(r1) /* sbss length */ + slwi. r3,r3,2 /* div 4 to get # of words */ + subi r2,r2,4 + beqlr /* no sbss */ + mtctr r3 /* set ctr reg */ +clear_sbss: stwu r0,4(r2) + bdnz clear_sbss /* decrement counter and loop */ + + blr /* return */ + + +/*--------------------------------------------------------------------------- + * Generic 405 register setup + *--------------------------------------------------------------------------*/ +init405: + li r0, 0 + mtmsr r0 + mticcr r0 + mtdccr r0 + + li r3,0x7FFC # 405EX-specific + mtsgr r3 # Clear guarded mode on all storage except PCIe region + + mtsler r0 # Storage is all big-endian + mtsu0r r0 # and uncompressed + + iccci r3,0 # Invalidate the instruction cache + li r3,1 # Enable F800 0000 to FFFF FFFF + oris r3,r3,0xC000 # Enable 0000 0000 to 0FFF FFFF + mticcr r3 + isync + + li r3,0 + li r4,256 # 405 has 128 or 256 32-byte lines: do 256 + mtctr r4 # set loop ctr +dcloop: dccci 0,r3 # invalidate line + addi r3,r3,0x20 # bump to next line + bdnz dcloop + mtdcwr r0 # Select write-back caching + lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF + # mtdccr r3 # Enable data cache + + mtevpr r0 + mtesr r0 + mtxer r0 + + lwarx r3,r0,r0 # get some data/set resv bit + stwcx. r3,r0,r0 # store out and clear resv bit + + lis r3,0xDEAD + ori r3,r3,0xBEEF # Make distintive uninitialised value + mr r4, r3 + mr r5, r3 + mr r6, r3 + mr r7, r3 + mr r8, r3 + mr r9, r3 + mr r10, r3 + mr r11, r3 + mr r12, r3 + mr r13, r3 + mr r14, r3 + mr r15, r3 + mr r16, r3 + mr r17, r3 + mr r18, r3 + mr r19, r3 + mr r20, r3 + mr r21, r3 + mr r22, r3 + mr r23, r3 + mr r24, r3 + mr r25, r3 + mr r26, r3 + mr r27, r3 + mr r28, r3 + mr r29, r3 + mr r30, r3 + mr r31, r3 + + blr + +.L_text_e: + + .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h b/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h new file mode 100644 index 0000000000..784e21c696 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h @@ -0,0 +1,103 @@ +/* bsp.h + * + * Generic 405EX bsp.h + * derived from virtex/include/bsp.h + * by Michael Hamel ADInstruments Ltd 2008 + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * + * + * $Id$ + * + */ + +#ifndef _BSP_H +#define _BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <bspopts.h> + +#ifdef ASM + + /* Definition of where to store registers in alignment handler */ + #define ALIGN_REGS 0x0140 + +#else + + #include <rtems.h> + #include <rtems/console.h> + #include <rtems/clockdrv.h> + #include <libcpu/io.h> + #include <rtems/console.h> + #include <rtems/iosupp.h> + #include <bsp/irq.h> + #include <bsp/vectors.h> + + /* Network Defines */ + #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + + struct rtems_bsdnet_ifconfig; + int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching); + #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach + + /* Definitions for the shared console/UART driver */ + #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 + + #define BSP_UART_IOBASE_COM1 0xEF600200 /* PPC405EX */ + #define BSP_UART_IOBASE_COM2 0xEF600300 + + #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ + + #define BSP_UART_BAUD_BASE (11059200 / 16) /* Kilauea ext clock, max speed */ + + /* functions */ + + rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ + ); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_H */ diff --git a/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h b/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h new file mode 100644 index 0000000000..f39d324eaa --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h @@ -0,0 +1,133 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +/* + * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> + * + * Units are 100ns. + * + * These numbers are of questionable use, as they are developed by calling + * the routine many times, thus getting its entry veneer into the (small) + * cache on the 403GA. This in general is not true of the RTEMS timing + * tests, which usually call a routine only once, thus having no cache loaded + * advantage. + * + * Whether the directive times are useful after deducting the function call + * overhead is also questionable. The user is more interested generally + * in the total cost of a directive, not the cost if the procedure call + * is inlined! (In general this is not true). + * + * Andrew Bray 18/08/1995 + * + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 +#define CALLING_OVERHEAD_TASK_CREATE 3 +#define CALLING_OVERHEAD_TASK_IDENT 1 +#define CALLING_OVERHEAD_TASK_START 1 +#define CALLING_OVERHEAD_TASK_RESTART 1 +#define CALLING_OVERHEAD_TASK_DELETE 1 +#define CALLING_OVERHEAD_TASK_SUSPEND 1 +#define CALLING_OVERHEAD_TASK_RESUME 1 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 +#define CALLING_OVERHEAD_TASK_MODE 1 +#define CALLING_OVERHEAD_TASK_GET_NOTE 1 +#define CALLING_OVERHEAD_TASK_SET_NOTE 1 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 +#define CALLING_OVERHEAD_CLOCK_GET 4 +#define CALLING_OVERHEAD_CLOCK_SET 3 +#define CALLING_OVERHEAD_CLOCK_TICK 1 + +#define CALLING_OVERHEAD_TIMER_CREATE 1 +#define CALLING_OVERHEAD_TIMER_IDENT 1 +#define CALLING_OVERHEAD_TIMER_DELETE 1 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 +#define CALLING_OVERHEAD_TIMER_RESET 1 +#define CALLING_OVERHEAD_TIMER_CANCEL 1 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 + +#define CALLING_OVERHEAD_EVENT_SEND 1 +#define CALLING_OVERHEAD_EVENT_RECEIVE 2 +#define CALLING_OVERHEAD_SIGNAL_CATCH 1 +#define CALLING_OVERHEAD_SIGNAL_SEND 1 +#define CALLING_OVERHEAD_PARTITION_CREATE 3 +#define CALLING_OVERHEAD_PARTITION_IDENT 1 +#define CALLING_OVERHEAD_PARTITION_DELETE 1 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 +#define CALLING_OVERHEAD_REGION_CREATE 3 +#define CALLING_OVERHEAD_REGION_IDENT 1 +#define CALLING_OVERHEAD_REGION_DELETE 1 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 +#define CALLING_OVERHEAD_PORT_CREATE 2 +#define CALLING_OVERHEAD_PORT_IDENT 1 +#define CALLING_OVERHEAD_PORT_DELETE 1 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 + +#define CALLING_OVERHEAD_IO_INITIALIZE 2 +#define CALLING_OVERHEAD_IO_OPEN 2 +#define CALLING_OVERHEAD_IO_CLOSE 2 +#define CALLING_OVERHEAD_IO_READ 2 +#define CALLING_OVERHEAD_IO_WRITE 2 +#define CALLING_OVERHEAD_IO_CONTROL 2 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/powerpc/haleakala/include/tm27.h b/c/src/lib/libbsp/powerpc/haleakala/include/tm27.h new file mode 100644 index 0000000000..18f3b6b32b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/include/tm27.h @@ -0,0 +1,32 @@ +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), PPC_IRQ_SCALL, 1 ) + +#define Cause_tm27_intr() asm volatile ("sc") + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c new file mode 100644 index 0000000000..dd20e93b90 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c @@ -0,0 +1,212 @@ +/* + * + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * Middleware support for PPC405 by M.Hamel ADInstruments Ltd 2008 + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/irq_supp.h> +#include <libcpu/raw_exception.h> +#include <libcpu/powerpc-utility.h> + + +/* PPC405EX UIC numbers */ +#define UIC_DCR_BASE 0xc0 +#define UIC0_SR (UIC_DCR_BASE+0x0) /* UIC status */ +#define UIC0_SRS (UIC_DCR_BASE+0x1) /* UIC status set */ +#define UIC0_ER (UIC_DCR_BASE+0x2) /* UIC enable */ +#define UIC0_CR (UIC_DCR_BASE+0x3) /* UIC critical */ +#define UIC0_PR (UIC_DCR_BASE+0x4) /* UIC polarity */ +#define UIC0_TR (UIC_DCR_BASE+0x5) /* UIC triggering */ +#define UIC0_MSR (UIC_DCR_BASE+0x6) /* UIC masked status */ +#define UIC0_VR (UIC_DCR_BASE+0x7) /* UIC vector */ +#define UIC0_VCR (UIC_DCR_BASE+0x8) /* UIC vector configuration */ + +#define UIC1_SR (UIC_DCR_BASE+0x10) /* UIC status */ +#define UIC1_SRS (UIC_DCR_BASE+0x11) /* UIC status set */ +#define UIC1_ER (UIC_DCR_BASE+0x12) /* UIC enable */ +#define UIC1_CR (UIC_DCR_BASE+0x13) /* UIC critical */ +#define UIC1_PR (UIC_DCR_BASE+0x14) /* UIC polarity */ +#define UIC1_TR (UIC_DCR_BASE+0x15) /* UIC triggering */ +#define UIC1_MSR (UIC_DCR_BASE+0x16) /* UIC masked status */ +#define UIC1_VR (UIC_DCR_BASE+0x17) /* UIC vector */ +#define UIC1_VCR (UIC_DCR_BASE+0x18) /* UIC vector configuration */ + +#define UIC2_SR (UIC_DCR_BASE+0x20) /* UIC status */ +#define UIC2_SRS (UIC_DCR_BASE+0x21) /* UIC status set */ +#define UIC2_ER (UIC_DCR_BASE+0x22) /* UIC enable */ +#define UIC2_CR (UIC_DCR_BASE+0x23) /* UIC critical */ +#define UIC2_PR (UIC_DCR_BASE+0x24) /* UIC polarity */ +#define UIC2_TR (UIC_DCR_BASE+0x25) /* UIC triggering */ +#define UIC2_MSR (UIC_DCR_BASE+0x26) /* UIC masked status */ +#define UIC2_VR (UIC_DCR_BASE+0x27) /* UIC vector */ +#define UIC2_VCR (UIC_DCR_BASE+0x28) /* UIC vector configuration */ + +enum { kUICWords = 3 }; + +static rtems_irq_connect_data* rtems_hdl_tblP; +static rtems_irq_connect_data dflt_entry; + +static uint32_t gEnabledInts[kUICWords]; /* 1-bits mean enabled */ +static uint32_t gIntInhibited[kUICWords]; /* 1-bits disable, overriding gEnabledInts because the interrupt + is being processed in C_dispatch_irq_handler */ + +static inline int IsUICIRQ(const rtems_irq_number irqLine) +{ + return (((int) irqLine <= BSP_UIC_IRQ_MAX_OFFSET) && + ((int) irqLine >= BSP_UIC_IRQ_LOWEST_OFFSET) + ); +} + +static void WriteIState() +/* Write the gEnabledInts state masked by gIntInhibited to the hardware */ +{ + mtdcr(UIC0_ER, gEnabledInts[0] & ~gIntInhibited[0]); + mtdcr(UIC1_ER, gEnabledInts[1] & ~gIntInhibited[1]); + mtdcr(UIC2_ER, gEnabledInts[2] & ~gIntInhibited[2]); +} + +void +BSP_enable_irq_at_pic(const rtems_irq_number irq) +/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ +{ + if (IsUICIRQ(irq)) { + /* Set relevant bit in the state, write state to the UIC */ + gEnabledInts[irq>>5] |= (0x80000000 >> (irq & 0x1F)); + WriteIState(); + } +} + +int +BSP_disable_irq_at_pic(const rtems_irq_number irq) +/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ +{ + if (IsUICIRQ(irq)) { + uint32_t oldState; + int iword = irq>>5; + uint32_t mask = (0x80000000 >> (irq & 0x1F)); + + oldState = gEnabledInts[iword] & mask; + gEnabledInts[iword] &= ~mask; + WriteIState(); + return oldState ? 1 : 0; + } else + return -1; +} + +int +BSP_setup_the_pic(rtems_irq_global_settings* config) +{ + int i; + + dflt_entry = config->defaultEntry; + rtems_hdl_tblP = config->irqHdlTbl; + for (i=0; i<kUICWords; i++) + gIntInhibited[i] = 0; + + mtdcr (UIC2_ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2_CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2_PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2_TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2_SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC1_ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1_CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1_PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1_TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1_SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC0_ER, 0x0000000a); /* Disable all interrupts except cascade UIC0 and UIC1 */ + mtdcr (UIC0_CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0_PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0_TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0_SR, 0xffffffff); /* clear all interrupts */ + + return 1; +} + + +/* + * High level IRQ handler called from shared_raw_irq_code_entry; decode and + * dispatch. Note that this routine needs to be re-entrant + * + * No support for critical interrupts here yet + */ + +int +C_dispatch_irq_handler( struct _BSP_Exception_frame* frame, unsigned int excNum ) +{ + if (excNum == ASM_EXT_VECTOR) { + uint32_t active[kUICWords]; + + /* Fetch the masked flags that tell us what external ints are active. + Likely to be only one, but we need to handle more than one, + OR the flags into gIntInhibited */ + active[0] = mfdcr(UIC0_MSR); + active[1] = mfdcr(UIC1_MSR); + active[2] = mfdcr(UIC2_MSR); + gIntInhibited[0] |= active[0]; + gIntInhibited[1] |= active[1]; + gIntInhibited[2] |= active[2]; + + /* ...and update the hardware so the active interrupts are disabled */ + WriteIState(); + + /* Loop, calling bsp_irq_dispatch_list for each active interrupt */ + while ((active[0] | active[1] | active[2]) != 0) { + uint32_t index = -1; + uint32_t bit, bmask; + + /* Find an active interrupt, searching 0..2, bit 0..bit 31 (IBM order) */ + do { + index++; + asm volatile (" cntlzw %0, %1":"=r" (bit):"r" (active[index])); + } while (bit==32); + + /* Call the matching handler */ + bsp_irq_dispatch_list(rtems_hdl_tblP, (index*32)+bit, dflt_entry.hdl); + + /* Write a 1-bit to the appropriate status register to clear it */ + bmask = 0x80000000 >> bit; + switch (index) { + case 0: mtdcr(UIC0_SR, bmask); break; + case 1: mtdcr(UIC1_SR, bmask); break; + case 2: mtdcr(UIC2_SR, bmask); break; + } + + /* Clear in the active record and gIntInhibited */ + active[index] &= ~bmask; + gIntInhibited[index] &= ~bmask; + }; + + /* Update the hardware again so the interrupts we have handled are unmasked */ + WriteIState(); + return 0; + + } else if (excNum == ASM_DEC_VECTOR) { /* 0x1000 remapped by C_dispatch_dec_handler_bookE */ + bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl); + return 0; + + } else if (excNum == ASM_BOOKE_FIT_VECTOR) { /* 0x1010 mapped to 0x13 by ppc_get_vector_addr */ + bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl); + return 0; + + } else if (excNum == ASM_BOOKE_WDOG_VECTOR) { /* 0x1020 mapped to 0x14 by ppc_get_vector_addr */ + bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl); + return 0; + + } else + return -1; /* unhandled interrupt, panic time */ +} + diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h new file mode 100644 index 0000000000..fcb33e0b3e --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h @@ -0,0 +1,166 @@ +/*===============================================================*\ +| Project: RTEMS Haleakala BSP | +| by Michael Hamel ADInstruments Ltd 2008 | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | +\*===============================================================*/ + + +#ifndef Haleakala_IRQ_IRQ_H +#define Haleakala_IRQ_IRQ_H + +/* Implemented for us in bsp_irq_dispatch_list */ +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#include <rtems/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. + These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ + + /* + + #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC_IRQ_NUMBER (32) + + */ + /* PPC405EX interrupt vectors */ + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) + #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) + + #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) + #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) + + #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) + + #define BSP_UIC_IRQ_NUMBER (95) + + + #define BSP_UIC_IRQ_LOWEST_OFFSET 0 + #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) + + #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ + #define BSP_UART_COM2_IRQ BSP_UIC_UART1 + + /* Define processor IRQ numbers; IRQs that are handled by the raw_exception vectors */ + + #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ + #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 + #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + + #define BSP_PROCESSOR_IRQ_NUMBER (3) + #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) + #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* Summary and totals */ + + #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) + #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) + #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c + #include <bsp/irq_supp.h> + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* Haleakala_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c b/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c new file mode 100644 index 0000000000..088b15ecaa --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c @@ -0,0 +1,89 @@ +/*===============================================================*\ +| Project: RTEMS Haleakala BSP | +| * by Michael Hamel ADInstruments Ltd 2008 | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the irq controller handler | +\*===============================================================*/ +#include <libcpu/spr.h> +#include <bsp/irq.h> +#include <bsp.h> +#include <libcpu/raw_exception.h> +#include <rtems/bspIo.h> +#include <rtems/powerpc/powerpc.h> + + +/* + * default on/off function + */ +static void nop_func() +{ +} + +/* + * default isOn function + */ +static int not_connected() +{ + return 0; +} + +static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; +static rtems_irq_global_settings initial_config; +static rtems_irq_connect_data defaultIrq = { + /* name, hdl , handle , on , off , isOn */ + 0, nop_func , NULL , nop_func , nop_func , not_connected +}; + +static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ + /* + * Processor exceptions handled as interrupts + */ + 0 +}; + + /* + * This code assumes the exceptions management setup has already + * been done. We just need to replace the exceptions that will + * be handled like interrupt. On mcp750/mpc750 and many PPC processors + * this means the decrementer exception and the external exception. + */ + +void BSP_rtems_irq_mng_init(unsigned cpuId) +{ + int i; + + /* + * re-init the rtemsIrq table + */ + for (i = 0; i < BSP_IRQ_NUMBER; i++) { + rtemsIrq[i] = defaultIrq; + rtemsIrq[i].name = i; + } + /* + * Init initial Interrupt management config + */ + initial_config.irqNb = BSP_IRQ_NUMBER; + initial_config.defaultEntry = defaultIrq; + initial_config.irqHdlTbl = rtemsIrq; + initial_config.irqBase = BSP_LOWEST_OFFSET; + initial_config.irqPrioTbl = irqPrioTable; + + if (!BSP_rtems_irq_mngt_set(&initial_config)) { + /* + * put something here that will show the failure... + */ + BSP_panic( + "Unable to initialize RTEMS interrupt management!!! System locked\n" + ); + } + + #ifdef TRACE_IRQ_INIT + printk("RTEMS IRQ management is now operational\n"); + #endif +} diff --git a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am new file mode 100644 index 0000000000..85a77e1029 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am @@ -0,0 +1,87 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds + +$(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h + +$(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h + +$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h + +$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h + +$(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h + diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/bspclean.c b/c/src/lib/libbsp/powerpc/haleakala/startup/bspclean.c new file mode 100644 index 0000000000..56699da354 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/startup/bspclean.c @@ -0,0 +1,43 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspclean.c: + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +void bsp_cleanup( void ) +{ + rtems_fatal_error_occurred(0); +} diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c new file mode 100644 index 0000000000..2bf2f18c1b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c @@ -0,0 +1,315 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Modifications for spooling console driver and control of memory layout + * with linker command file by + * Thomas Doerfler <td@imd.m.isar.de> + * for these modifications: + * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies. IMD makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * + * Modifications for PPC405GP by Dennis Ehlin + * + * Further modified for the PPC405EX Haleakala board by + * Michael Hamel ADInstruments Ltd May 2008 + * + * $Id$ + */ +#include <string.h> +#include <fcntl.h> + +#include <bsp.h> +#include <bsp/uart.h> +#include <rtems/libio.h> +#include <rtems/libcsupport.h> +#include <bsp/irq.h> +#include <rtems/bspIo.h> +#include <libcpu/cpuIdent.h> +#include <libcpu/spr.h> +#include <rtems/powerpc/powerpc.h> +#include <ppc4xx/ppc405gp.h> +#include <ppc4xx/ppc405ex.h> + +SPR_RW(SPRG0) +SPR_RW(SPRG1) + +#include <stdio.h> + +/* + * Driver configuration parameters + */ + +/* Expected by clock.c */ +uint32_t bsp_clicks_per_usec; +boolean bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ +uint32_t bsp_timer_least_valid; +uint32_t bsp_timer_average_overhead; + + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + +void bsp_postdriver_hook(void); +void bsp_libc_init( void *, uint32_t, int ); + +/* + * + * bsp_predriver_hook + * + * Before drivers are setup. + */ + +void bsp_predriver_hook(void) +{ + +} + +/* + * Function: bsp_pretasking_hook + * Created: 95/03/10 + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + + +extern uint8_t _RAMEnd; /* Defined in linkcmds */ + +void bsp_pretasking_hook(void) +/* Initialise libc with the address and size of the heap, which runs + from the end of the RTEMS workspace to the top of RAM */ +{ + uint32_t heap_start; + + heap_start = ( (uint32_t)Configuration.work_space_start + + rtems_configuration_get_work_space_size() ); + + bsp_libc_init((void *)heap_start, (uint32_t)(&_RAMEnd) - heap_start, 0); + + #ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); + #endif +} + +/*-------------------- Haleakala-specific UART setup -------------------------*/ + +static void +EarlyUARTInit(int baudRate) +{ + uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1); + int divider = BSP_UART_BAUD_BASE / baudRate; + up[LCR] = DLAB; /* Access DLM/DLL */ + up[DLL] = divider & 0x0FF; + up[DLM] = divider >> 8; + up[LCR] = CHR_8_BITS; + up[MCR] = DTR | RTS; + up[FCR] = FIFO_EN | XMIT_RESET | RCV_RESET; + up[THR] = '+'; +} + + +static void +InitUARTClock() +{ + uint32_t reg; + mfsdr(SDR0_UART0,reg); + reg &= ~0x008000FF; + reg |= 0x00800001; /* Ext clock, div 1 */ + mtsdr(SDR0_UART0,reg); +} + +void GPIO_AlternateSelect(int bitnum, int source) +/* PPC405EX: select a GPIO function for the specified pin */ +{ + int shift; + unsigned long value, mask; + GPIORegisters* gpioPtr = (GPIORegisters*)(GPIOAddress); + + shift = (31 - bitnum) & 0xF; + value = (source & 3) << (shift*2); + mask = 3 << (shift*2); + if (bitnum <= 15) { + gpioPtr->OSRL = (gpioPtr->OSRL & ~mask) | value; + gpioPtr->TSRL = (gpioPtr->TSRL & ~mask) | value; + } else { + gpioPtr->OSRH = (gpioPtr->OSRH & ~mask) | value; + gpioPtr->TSRH = (gpioPtr->TSRH & ~mask) | value; + } +} + +void Init_FPGA() +{ + /* Have to write to the FPGA to enable the UART drivers */ + /* Have to enable CS2 as an output in GPIO to get the FPGA working */ + mtebc(EBC0_B2CR,0xF0018000); /* Set up CS2 at 0xF0000000 */ + mtebc(EBC0_B2AP,0x9400C800); + GPIO_AlternateSelect(9,1); /* GPIO9 = PerCS2 */ + { + unsigned long *fpgaPtr = (unsigned long*)(0xF0000000); + unsigned long n; + n = *(fpgaPtr); + n &= ~0x00100; /* User LEDs on */ + n |= 0x30000; /* UART 0 and 1 transcievers on! */ + *fpgaPtr = n; + } +} + +/*===================================================================*/ + +static void +DirectUARTWrite(const char c) +{ + uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1); + while ((up[LSR] & THRE) == 0) { ; } + up[THR] = c; + if (c=='\n') + DirectUARTWrite('\r'); +} + +/* We will provide our own printk output function as it may get used early */ +BSP_output_char_function_type BSP_output_char = DirectUARTWrite; + + +/*===================================================================*/ + + +/* + * bsp_start + * + * This routine does the bulk of the system initialization. + */ + + +void bsp_start( void ) +{ + extern unsigned long *intrStackPtr; + register unsigned char* intrStack; + ppc_cpu_id_t myCpu; + ppc_cpu_revision_t myCpuRevision; + + /* Get the UART clock initialized first in case we call printk */ + + InitUARTClock(); + Init_FPGA(); + EarlyUARTInit(115200); + + /* + * Get CPU identification dynamically. Note that the get_ppc_cpu_type() + * function store the result in global variables + * so that it can be used later... + */ + myCpu = get_ppc_cpu_type(); + myCpuRevision = get_ppc_cpu_revision(); + + /* + * initialize the device driver parameters + */ + + /* Set globals visible to clock.c */ + bsp_clicks_per_usec = 400; /* timebase register ticks/microsecond = CPU Clk in MHz */ + bsp_timer_internal_clock = TRUE; + bsp_timer_average_overhead = 2; + bsp_timer_least_valid = 3; + + /* + * Initialize some SPRG registers related to irq handling + */ + + intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); + _write_SPRG1((unsigned int)intrStack); + /* signal them that we have fixed PR288 - eventually, this should go away */ + /* + * Initialize default raw exception handlers. + */ + initialize_exceptions(); + + /* + * Install our own set of exception vectors + */ + BSP_rtems_irq_mng_init(0); + + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ + /* In this case we allocate space at an address defined in linkcmds + which points to a block above the stack and below the heap */ + { + extern uint8_t _WorkspaceStart; + Configuration.work_space_start = &_WorkspaceStart; + } + +} + +void BSP_ask_for_reset(void) +{ + printk("system stopped, press RESET"); + while(1) {}; +} + +void BSP_panic(char *s) +{ + printk("%s PANIC %s\n",_RTEMS_version, s); + BSP_ask_for_reset(); +} + +void _BSP_Fatal_error(unsigned int v) +{ + printk("%s PANIC ERROR %x\n",_RTEMS_version, v); + BSP_ask_for_reset(); +} + + diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds b/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds new file mode 100644 index 0000000000..abd15dab60 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds @@ -0,0 +1,255 @@ +/* + * This file contains directives for the GNU linker which are specific + * to the 405GP/EX + * This file is intended to be used together with dlentry.s + * it will generate downloadable code + * + * Modifications for gen405 by Dennis Ehlin + * Modifications for virtex by Keith, Greg, and Bob + * Modifications for 405GP/EX by Michael Hamel + * + * $Id$ + */ + +OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc") +OUTPUT_ARCH(powerpc) +ENTRY(download_entry) + +kIntrStackSize = 16K; +kMainStackSize = 64K; + +MEMORY { + RAM : ORIGIN = 0, LENGTH = 256M + /*FLASH : ORIGIN = 0xFFE00000, LENGTH = 16M*/ +} + + +SECTIONS +{ + /* First 16K is occupied by exception vectors and anything else we want to put there */ + .text 0x4000: + { + text.start = . ; + *(.entry) + *(.entry2) + *(.text*) + *(.rodata*) + *(.rodata1) + + /* + * Special FreeBSD sysctl sections. + */ + . = ALIGN (16); + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = ABSOLUTE(.); + *(set_domain_*); + *(set_pseudo_*); + + /* C++ constructors/destructors */ + *(.gnu.linkonce.t*) + + /* Initialization and finalization code. + * + * Various files can provide initialization and finalization functions. + * The bodies of these functions are in .init and .fini sections. We + * accumulate the bodies here, and prepend function prologues from + * ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked + * first; ecrtn.o must be linked last. Because these are wildcards, it + * doesn't matter if the user does not actually link against ecrti.o and + * ecrtn.o; the linker won't look for a file to match a wildcard. The + * wildcard also means that it doesn't matter which directory ecrti.o + * and ecrtn.o are in. + */ + PROVIDE (_init = .); + *ecrti.o(.init) + *(.init) + *ecrtn.o(.init) + + PROVIDE (_fini = .); + *ecrti.o(.fini) + *(.fini) + *ecrtn.o(.init) + + /* + * C++ constructors and destructors for static objects. + * PowerPC EABI does not use crtstuff yet, so we build "old-style" + * constructor and destructor lists that begin with the list lenght + * end terminate with a NULL entry. + */ + + PROVIDE (__CTOR_LIST__ = .); + *crtbegin.o(.ctors) + *(.ctors) + *crtend.o(.ctors) + LONG(0) + PROVIDE (__CTOR_END__ = .); + + PROVIDE (__DTOR_LIST__ = .); + *crtbegin.o(.dtors) + *(.dtors) + *crtend.o(.dtors) + LONG(0) + PROVIDE (__DTOR_END__ = .); + + /* Exception frame info */ + *(.eh_frame) + /* Miscellaneous read-only data */ + _rodata_start = . ; + *(.gnu.linkonce.r*) + *(.lit) + *(.shdata) + *(.rodata) + *(.rodata1) + *(.descriptors) + *(rom_ver) + _erodata = .; + + PROVIDE (__EXCEPT_START__ = .); + *(.gcc_except_table*) + PROVIDE (__EXCEPT_END__ = .); + __GOT_START__ = .; + s.got = .; + *(.got.plt) + *(.got) + *(.got1) + PROVIDE (__GOT2_START__ = .); + PROVIDE (_GOT2_START_ = .); + *(.got2) + PROVIDE (__GOT2_END__ = .); + PROVIDE (_GOT2_END_ = .); + + PROVIDE (__FIXUP_START__ = .); + PROVIDE (_FIXUP_START_ = .); + *(.fixup) + PROVIDE (_FIXUP_END_ = .); + PROVIDE (__FIXUP_END__ = .); + + + /* Various possible names for the end of the .text section */ + etext = ALIGN(0x10); + _etext = .; + + *(.lit) + *(.shdata) + _endtext = ALIGN(0x10); + text.end = .; + text.size = text.end - text.start; + } >RAM + + text.size = text.end - text.start; + + .jcr : { KEEP (*(.jcr)) } >RAM + + .rel.dyn : { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + } >RAM + .rela.dyn : { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.got1) + *(.rela.got2) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } >RAM + + + /* Initialised large data */ + .data ( . ) : + { + . = ALIGN (4); + data.start = .; + *(.data) + *(.data1) + *(.data.* .gnu.linkonce.d.*) + data.end = .; + } > RAM + + /* Initialised small data addressed as offsets from r13 */ + .sdata : { + . = ALIGN (4); + PROVIDE (__SDATA_START__ = .); + sdata.start = .; + *(.sdata*) + *(.gnu.linkonce.s.*) + sdata.end = .; + } > RAM + + /* Zeroed small data addressed as offsets from r13 */ + .sbss : { + . = ALIGN (4); + PROVIDE(__SBSS_START__ = .); + sbss.start = .; + *(.sbss*) + *(.gnu.linkonce.sb.*); + sbss.end = .; + } > RAM + PROVIDE(__SBSS_END__ = .); + + /* Zeroed large data */ + .bss : { + . = ALIGN (4); + bss.start = .; + *(.bss .bss* .gnu.linkonce.b*) + . = ALIGN(4); + bss.end = .; + } > RAM + + bss.size = bss.end - bss.start; + sbss.size = sbss.end - sbss.start; + + /* Interrupt stack: align to a cache-line boundary */ + IntrStack_start = ALIGN(0x20); + . += kIntrStackSize; + intrStack = .; + PROVIDE(intrStackPtr = intrStack); + + /* Main stack: align to a cache-line boundary */ + stack.start = ALIGN(0x20); + . += kMainStackSize; + stack.end = .; + + /* RTEMS workspace: size specified by application */ + _WorkspaceStart = ALIGN(0x20); + + /* Heap: from end of the workspace to _RAMEnd */ + _RAMEnd = ORIGIN(RAM) + LENGTH(RAM); + + /* Debugging information */ + .line 0 : { *(.line) } + .debug 0 : { *(.debug) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_aregion 0 : { *(.debug_aregion) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } +} diff --git a/c/src/lib/libbsp/powerpc/shared/console/uart.c b/c/src/lib/libbsp/powerpc/shared/console/uart.c index ea47aa8313..dd63c6781b 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/uart.c +++ b/c/src/lib/libbsp/powerpc/shared/console/uart.c @@ -74,15 +74,13 @@ static struct uart_data uart_data[2] = { static inline unsigned char uread(int uart, unsigned int reg) { - - return in_8((unsigned char*)(uart_data[uart].ioBase + reg)); - + return in_8((unsigned char*)(uart_data[uart].ioBase + reg)); } static inline void uwrite(int uart, int reg, unsigned int val) { - out_8((unsigned char*)(uart_data[uart].ioBase + reg), val); + out_8((unsigned char*)(uart_data[uart].ioBase + reg), val); } diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index 25f2fa5cf8..dd2928fc5b 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,13 @@ +2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de> + + * Makefile.am, new-exceptions/raw_exception.c, + * new-exceptions/bspsupport/irq.c, ppc403/clock/clock_4xx.c, + * ppc403/include/ppc405ex.h, ppc403/include/ppc405gp.h, + * ppc403/timer/timer.c, rtems/powerpc/powerpc.h, + * shared/include/cpuIdent.c, shared/include/cpuIdent.h, + * shared/include/powerpc-utility.h: + Added support for PPC405EX (contributed by Michael Hamel) + 2008-07-11 Sebastian Huber <sebastian.huber@embedded-brains.de> * Makefile.am: Install powerpc-utility.h. @@ -15,13 +25,14 @@ ppc_exc_vector_base for CPUs with IVPR register. * new-exceptions/bspsupport/ppc_exc.S, - new-exceptions/bspsupport/ppc_exc_asm_macros.h, - new-exceptions/bspsupport/ppc_exc_bspsupp.h, - new-exceptions/bspsupport/ppc_exc_hdl.c, - new-exceptions/bspsupport/vectors.h, - new-exceptions/bspsupport/vectors_init.c: Conistent code layout in most - assember code sections and usage of defines for registers. Usage of - standard header files to avoid multiple definitions. + * new-exceptions/bspsupport/ppc_exc_asm_macros.h, + * new-exceptions/bspsupport/ppc_exc_bspsupp.h, + * new-exceptions/bspsupport/ppc_exc_hdl.c, + * new-exceptions/bspsupport/vectors.h, + * new-exceptions/bspsupport/vectors_init.c: + Conistent code layout in most assember code sections and usage of + defines for registers. Usage of standard header files to avoid + multiple definitions. Optimized exception code: Removed many branches and exploit branch prediction for asynchronous exceptions, moved common wrap code into diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am index 8a071a2dd9..6c75b46a83 100644 --- a/c/src/lib/libcpu/powerpc/Makefile.am +++ b/c/src/lib/libcpu/powerpc/Makefile.am @@ -126,8 +126,19 @@ ppc403_tty_drv_rel_CPPFLAGS = $(AM_CPPFLAGS) ppc403_tty_drv_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -endif +endif # ppc403 + +if ppc405 + +## ppc4xx/include +include_ppc4xxdir = $(includedir)/ppc4xx +include_ppc4xx_HEADERS = ppc403/include/ppc405gp.h \ + ppc403/include/ppc405ex.h +endif # ppc405 + + +## mpc5xx EXTRA_DIST += mpc5xx/README if mpc5xx include_mpc5xxdir = $(includedir)/mpc5xx @@ -341,6 +352,7 @@ mpc8260_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if mpc83xx + include_mpc83xxdir = $(includedir)/mpc83xx include_mpc83xx_HEADERS = mpc83xx/include/mpc83xx.h include_mpc83xx_HEADERS += mpc83xx/network/tsec.h diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c index 1b9dcafefe..6b3d218e60 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c @@ -38,6 +38,7 @@ static rtems_irq_connect_data* rtems_hdl_tbl; SPR_RW(BOOKE_TSR) +SPR_RW(PPC405_TSR) /* legacy mode for bookE DEC exception; * to avoid the double layer of function calls @@ -52,8 +53,12 @@ int C_dispatch_dec_handler_bookE (BSP_Exception_frame *frame, unsigned int excNu /* clear interrupt; we must do this * before C_dispatch_irq_handler() * re-enables MSR_EE. + * Note that PPC405 uses a different SPR# for TSR */ - _write_BOOKE_TSR( BOOKE_TSR_DIS ); + if ( ppc_cpu_is_bookE()==PPC_BOOKE_405) + _write_PPC405_TSR( BOOKE_TSR_DIS ); + else + _write_BOOKE_TSR( BOOKE_TSR_DIS ); return C_dispatch_irq_handler(frame, ASM_DEC_VECTOR); } diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c b/c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c index e330d80921..06ed62423d 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c @@ -162,7 +162,8 @@ static const cat_ini_t mpc_5xx_vector_categories[LAST_VALID_EXC + 1] = { static const cat_ini_t ppc_405_vector_categories[LAST_VALID_EXC + 1] = { [ ASM_EXT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, - [ ASM_BOOKE_DEC_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, + [ ASM_BOOKE_DEC_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* PIT */ + [ ASM_BOOKE_FIT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* FIT */ [ ASM_PROT_VECTOR ] = PPC_EXC_CLASSIC, [ ASM_ISI_VECTOR ] = PPC_EXC_CLASSIC, @@ -371,6 +372,8 @@ ppc_raw_exception_category rval = PPC_EXC_INVALID; rval = mpc_860_vector_categories[vector]; break; case PPC_405: + case PPC_405GP: + case PPC_405EX: rval = ppc_405_vector_categories[vector]; break; default: diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c new file mode 100644 index 0000000000..890e75509d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c @@ -0,0 +1,251 @@ +/* clock.c + * + * This routine initializes the interval timer on the + * PowerPC 405 CPU. The tick frequency is specified by the bsp. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: + * + * Modifications for deriving timer clock from cpu system clock by + * Thomas Doerfler <td@imd.m.isar.de> + * for these modifications: + * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. + * + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * Modifications for PPC405GP by Dennis Ehlin + * + * Further modifications for PPC405GP/EX by Michael Hamel + * + * $Id$ + */ + +#include <rtems.h> +#include <rtems/clockdrv.h> +#include <rtems/libio.h> +#include <stdlib.h> /* for atexit() */ +#include <rtems/bspIo.h> +#include <ppc405common.h> +#include <libcpu/cpuIdent.h> +#include <bsp/irq.h> + + + +/* PPC405GP */ +#define CPC0_CR1 0xB2 + #define CR1_CETE 0x00800000 + +/* PPC405EX */ +#define SDR0_C405 0x180 + #define SDR_CETE 0x02000000 + +volatile uint32_t Clock_driver_ticks; +static uint32_t pit_value, tick_time; + +void Clock_exit( void ); + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +/* Defined in bspstart.c */ +extern uint32_t bsp_clicks_per_usec; +extern boolean bsp_timer_internal_clock; + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * ISR Handler + */ + +void Clock_isr(void* handle) +{ + Clock_driver_ticks++; + rtems_clock_tick(); +} + +int ClockIsOn(const rtems_irq_connect_data* unused) +{ + return ((mfspr(TCR) & PIE) != 0); +} + + +void ClockOff(const rtems_irq_connect_data* unused) +{ + register uint32_t r; + + r = mfspr(TCR); + mtspr(TCR, r & ~(PIE | ARE) ); +} + +void ClockOn(const rtems_irq_connect_data* unused) +{ + uint32_t iocr, r; + ppc_cpu_id_t cpu; + Clock_driver_ticks = 0; + + cpu = get_ppc_cpu_type(); + if (cpu==PPC_405GP) { + iocr = mfdcr(CPC0_CR1); + if (bsp_timer_internal_clock) iocr &= ~CR1_CETE ;/* timer clocked from system clock */ + else iocr |= CR1_CETE; /* select external timer clock */ + mtdcr(CPC0_CR1,iocr); + } else if (cpu==PPC_405EX) { + mfsdr(SDR0_C405,iocr); + if (bsp_timer_internal_clock) iocr &= ~SDR_CETE ;/* timer clocked from system clock */ + else iocr |= SDR_CETE; /* select external timer clock */ + mtsdr(SDR0_C405,iocr); + } else { + printk("clock.c:unrecognised CPU"); + rtems_fatal_error_occurred(1); + } + + pit_value = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec; + mtspr(PIT,pit_value); + + tick_time = mfspr(TBL) + pit_value; + r = mfspr(TCR); + mtspr(TCR, r | PIE | ARE); +} + + + +void Install_clock(void (*clock_isr)(void *)) +{ + + /* + * initialize the interval here + * First tick is set to right amount of time in the future + * Future ticks will be incremented over last value set + * in order to provide consistent clicks in the face of + * interrupt overhead + */ + + rtems_irq_connect_data clockIrqConnData; + + Clock_driver_ticks = 0; + clockIrqConnData.on = ClockOn; + clockIrqConnData.off = ClockOff; + clockIrqConnData.isOn = ClockIsOn; + clockIrqConnData.name = BSP_PIT; + clockIrqConnData.hdl = clock_isr; + if ( ! BSP_install_rtems_irq_handler (&clockIrqConnData)) { + printk("Unable to connect Clock Irq handler\n"); + rtems_fatal_error_occurred(1); + } + atexit(Clock_exit); +} + +void +ReInstall_clock(void (*new_clock_isr)(void *)) +{ + uint32_t isrlevel = 0; + rtems_irq_connect_data clockIrqConnData; + + rtems_interrupt_disable(isrlevel); + clockIrqConnData.name = BSP_PIT; + if ( ! BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { + printk("Unable to stop system clock\n"); + rtems_fatal_error_occurred(1); + } + + BSP_remove_rtems_irq_handler (&clockIrqConnData); + clockIrqConnData.on = ClockOn; + clockIrqConnData.off = ClockOff; + clockIrqConnData.isOn = ClockIsOn; + clockIrqConnData.name = BSP_PIT; + clockIrqConnData.hdl = new_clock_isr; + if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) { + printk("Unable to connect Clock Irq handler\n"); + rtems_fatal_error_occurred(1); + } + rtems_interrupt_enable(isrlevel); +} + + +/* + * Called via atexit() + * Remove the clock interrupt handler by setting handler to NULL + * + * This will not work on the 405GP because + * when bit's are set in TCR they can only be unset by a reset + */ + +void Clock_exit(void) +{ + rtems_irq_connect_data clockIrqConnData; + + clockIrqConnData.name = BSP_PIT; + if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { + printk("Unable to stop system clock\n"); + rtems_fatal_error_occurred(1); + } + BSP_remove_rtems_irq_handler (&clockIrqConnData); +} + + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_libio_ioctl_args_t* args = pargp; + + if (args!=NULL) { + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) + Clock_isr(NULL); + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) + ReInstall_clock(args->buffer); + } + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h new file mode 100644 index 0000000000..e64fc2d936 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h @@ -0,0 +1,158 @@ + +/* + +Constants for manipulating system registers of PPC 405EX in C + +Michael Hamel ADInstruments May 2008 + +*/ + +#include <libcpu/powerpc-utility.h> +/* Indirect access to Clocking/Power-On registers */ +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ + } while (0) + +#define mfcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ + } while (0) + + +/* Indirect access to System registers */ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define mtsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ + } while (0) + +#define mfsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ + } while (0) + +/* Indirect access to EBC registers */ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +#define mtebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ + } while (0) + +#define mfebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ + } while (0) + +/* EBC DCRs */ +enum { + /* + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_BEAR = 0x20, + EBC0_BESR = 0x21, + EBC0_CFG = 0x23, + */ + EBC0_CID = 0x24 +}; + +enum { + SDR0_UART0 = 0x120, + SDR0_UART1 = 0x121, + SDR0_C405 = 0x180, + SDR0_MALTBL = 0x280, + SDR0_MALRBL = 0x2A0, + SDR0_MALTBS = 0x2C0, + SDR0_MALRBS = 0x2E0 +}; + + +/* Memory-mapped registers */ + + +/*======================= Ethernet =================== */ + + +typedef struct EthernetRegisters_EX { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t multicastAddr[2]; + uint32_t multicastMask[2]; + uint32_t unused[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermark; + uint32_t bytesXmtd; + uint32_t bytesRcvd; + uint32_t unused2; + uint32_t revID; + uint32_t unused3[2]; + uint32_t indivHash[8]; + uint32_t groupHash[8]; + uint32_t xmtPause; +} EthernetRegisters_EX; + +enum { + EMAC0Address = 0xEF600900, + EMAC1Address = 0xEF600A00 +}; + + +typedef struct GPIORegisters { + uint32_t OR; + uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ + uint32_t OSRL; + uint32_t OSRH; + uint32_t TSRL; + uint32_t TSRH; + uint32_t ODR; + uint32_t IR; + uint32_t RR1; + uint32_t RR2; + uint32_t RR3; + uint32_t unknown; + uint32_t ISR1L; + uint32_t ISR1H; + uint32_t ISR2L; + uint32_t ISR2H; + uint32_t ISR3L; + uint32_t ISR3H; +} GPIORegisters; + +enum { GPIOAddress = 0xEF600800 }; + diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h new file mode 100644 index 0000000000..814f18d046 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h @@ -0,0 +1,146 @@ + + +/* SDRAM DCRs */ +enum { + SDRAM0_BESR0 = 0, + SDRAM0_BESR1 = 8, + SDRAM0_BEAR = 0x10, + SDRAM0_CFG = 0x20, + SDRAM0_STATUS = 0x24, + SDRAM0_RTR = 0x30, + SDRAM0_PMIT = 0x34, + SDRAM0_TR = 0x80 +}; + + +/* EBC DCRs */ +enum { + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B4CR = 4, + EBC0_B5CR = 5, + EBC0_B6CR = 6, + EBC0_B7CR = 7, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_B4AP = 0x14, + EBC0_B5AP = 0x15, + EBC0_B6AP = 0x16, + EBC0_B7AP = 0x17, + EBC0_BEAR = 0x20, + EBC0_BESR0 = 0x21, + EBC0_BESR1 = 0x22, + EBC0_CFG = 0x23 +}; + +/* Memory-mapped registers */ + +typedef struct EthernetRegisters_GP { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t indivHash[4]; + uint32_t groupHash[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermark; + uint32_t bytesXmtd; + uint32_t bytesRcvd; +} EthernetRegisters_GP; + +enum { EMACAddress = 0xEF600800 }; + +enum { + // Mode 0 bits + kEMACRxIdle = 0x80000000, + kEMACTxIdle = 0x40000000, + kEMACSoftRst = 0x20000000, + kEMACTxEnable = 0x10000000, + kEMACRxEnable = 0x08000000, + + // Mode 1 bits + kEMACFullDuplex = 0x80000000, + kEMACIgnoreSQE = 0x01000000, + kEMAC100MBbps = 0x00400000, + kEMAC4KRxFIFO = 0x00300000, + kEMAC2KTxFIFO = 0x00080000, + kEMACTx0Multi = 0x00008000, + kEMACTxDependent= 0x00014000, + + // Tx mode bits + kEMACNewPacket0 = 0x80000000, + kEMACNewPacket1 = 0x40000000, + + // Receive mode bits + kEMACStripPadding = 0x80000000, + kEMACStripFCS = 0x40000000, + kEMACRcvRunts = 0x20000000, + kEMACRcvFCSErrs = 0x10000000, + kEMACRcvOversize = 0x08000000, + kEMACPromiscRcv = 0x01000000, + kEMACPromMultRcv = 0x00800000, + kEMACIndivRcv = 0x00400000, + kEMACHashRcv = 0x00200000, + kEMACBrcastRcv = 0x00100000, + kEMACMultcastRcv = 0x00080000, + + // Buffer descriptor control bits + kMALTxReady = 0x8000, + kMALRxEmpty = 0x8000, + kMALWrap = 0x4000, + kMALContinuous = 0x2000, + kMALLast = 0x1000, + kMALRxFirst = 0x0800, + kMALInterrupt = 0x0400, + + // EMAC Tx descriptor bits sent + kEMACGenFCS = 0x200, + kEMACGenPad = 0x100, + kEMACInsSrcAddr = 0x080, + kEMACRepSrcAddr = 0x040, + kEMACInsVLAN = 0x020, + kEMACRepVLAN = 0x010, + + // EMAC TX descriptor bits returned + kEMACErrMask = 0x3FF, + kEMACFCSWrong = 0x200, + kEMACBadPrev = 0x100, + kEMACLostCarrier = 0x080, + kEMACDeferred = 0x040, + kEMACCollFail = 0x020, + kEMACLateColl = 0x010, + kEMACMultColl = 0x008, + kEMACOneColl = 0x004, + kEMACUnderrun = 0x002, + kEMACSQEFail = 0x001, + + // EMAC Rx descriptor bits returned + kEMACOverrun = 0x200, + kEMACPausePkt = 0x100, + kEMACBadPkt = 0x080, + kEMACRuntPkt = 0x040, + kEMACShortEvt = 0x020, + kEMACAlignErr = 0x010, + kEMACBadFCS = 0x008, + kEMACPktLong = 0x004, + kEMACPktOOR = 0x002, + kEMACPktIRL = 0x001 +}; + + diff --git a/c/src/lib/libcpu/powerpc/ppc403/timer/timer.c b/c/src/lib/libcpu/powerpc/ppc403/timer/timer.c index 25bd3659d6..8eed54468e 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/ppc403/timer/timer.c @@ -1,6 +1,6 @@ /* timer.c * - * This file manages the interval timer on the PowerPC 403*. + * This file manages the interval timer on the PowerPC 405. * We shall use the bottom 32 bits of the timebase register, * * NOTE: It is important that the timer start/stop overhead be @@ -32,85 +32,47 @@ * * Modifications for PPC405GP by Dennis Ehlin * + * Further mods for PPC405EX/EXr by Michael Hamel + * * $Id$ * */ #include <rtems.h> +#include <libcpu/powerpc-utility.h> -static volatile uint32_t Timer_starting; -static rtems_boolean Timer_driver_Find_average_overhead; - -/* - * This is so small that this code will be reproduced where needed. - */ -static inline uint32_t get_itimer(void) -{ - uint32_t ret; - -#ifndef ppc405 - asm volatile ("mfspr %0, 0x3dd" : "=r" ((ret))); /* TBLO */ -#else /* ppc405 */ -/* asm volatile ("mfspr %0, 0x3dd" : "=r" ((ret))); TBLO */ - - asm volatile ("mfspr %0, 0x10c" : "=r" ((ret))); /* 405GP TBL */ -#endif /* ppc405 */ +extern uint32_t bsp_timer_least_valid; +extern uint32_t bsp_timer_average_overhead; - return ret; -} +static volatile uint32_t startedAt; +static rtems_boolean subtractOverhead; void Timer_initialize() { - uint32_t iocr; - -#ifndef ppc405 - asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ - iocr &= ~4; - iocr |= 4; /* Select external timer clock */ - asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ -#else /* ppc405 */ - asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */ -/* asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); IOCR */ - - /* iocr |= 0x800000; select external timer clock CETE*/ - iocr &= ~0x800000; /* timer clocked from system clock CETE*/ - - asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */ -/* asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); IOCR */ -#endif /* ppc405 */ - - Timer_starting = get_itimer(); + /* We are going to rely on clock.c to sort out where the clock comes from */ + startedAt = ppc_time_base(); } int Read_timer() { - uint32_t clicks; - uint32_t total; - extern uint32_t bsp_timer_least_valid; - extern uint32_t bsp_timer_average_overhead; - - clicks = get_itimer(); - - total = clicks - Timer_starting; - - if ( Timer_driver_Find_average_overhead == 1 ) - return total; /* in XXX microsecond units */ - - else { - if ( total < bsp_timer_least_valid ) - return 0; /* below timer resolution */ - return (total - bsp_timer_average_overhead); - } + uint32_t clicks, total; + + clicks = ppc_time_base(); + total = clicks - startedAt; + if ( ! subtractOverhead ) + return total; /* in XXX microsecond units */ + else if ( total < bsp_timer_least_valid ) + return 0; /* below timer resolution */ + else + return (total - bsp_timer_average_overhead); } rtems_status_code Empty_function( void ) { - return RTEMS_SUCCESSFUL; + return RTEMS_SUCCESSFUL; } -void Set_find_average_overhead( - rtems_boolean find_flag -) +void Set_find_average_overhead( rtems_boolean find_flag) { - Timer_driver_Find_average_overhead = find_flag; + subtractOverhead = find_flag; } diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 44d82ee075..35fb2467ff 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -45,6 +45,10 @@ $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) +$(PROJECT_INCLUDE)/libcpu/powerpc-utility.h: shared/include/powerpc-utility.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/powerpc-utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/powerpc-utility.h + if !mpc5xx $(PROJECT_INCLUDE)/libcpu/raw_exception.h: new-exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h @@ -93,7 +97,21 @@ $(PROJECT_INCLUDE)/tty_drv.h: ppc403/tty_drv/tty_drv.h $(PROJECT_INCLUDE)/$(dirs $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tty_drv.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/tty_drv.h endif -endif +endif # ppc403 +if ppc405 +$(PROJECT_INCLUDE)/ppc4xx/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/ppc4xx + @: > $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) + +$(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h: ppc403/include/ppc405gp.h $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h + +$(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h: ppc403/include/ppc405ex.h $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h +endif # ppc405 if mpc5xx $(PROJECT_INCLUDE)/mpc5xx/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc5xx diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h index 9d9db55bc5..2a0b9bb547 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @@ -115,6 +115,17 @@ extern "C" { #define PPC_HAS_EXCEPTION_PREFIX 0 #define PPC_HAS_EVPR 1 +#elif defined (ppc405) + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 /* except GP/CR */ +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + #elif defined(mpc555) /* Copied from mpc505 */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c index cd5d97ec6f..3f02a710f2 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c @@ -31,6 +31,8 @@ char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu) { switch (cpu) { case PPC_405: return "PPC405"; + case PPC_405GP: return "PPC405GP"; + case PPC_405EX: return "PPC405EX"; case PPC_601: return "MPC601"; case PPC_5XX: return "MPC5XX"; case PPC_603: return "MPC603"; @@ -69,6 +71,8 @@ ppc_cpu_id_t get_ppc_cpu_type() switch (pvr) { case PPC_405: + case PPC_405GP: + case PPC_405EX: case PPC_601: case PPC_5XX: case PPC_603: @@ -128,6 +132,8 @@ ppc_cpu_id_t get_ppc_cpu_type() switch ( current_ppc_cpu ) { case PPC_405: + case PPC_405GP: + case PPC_405EX: current_ppc_features.is_bookE = PPC_BOOKE_405; break; case PPC_8540: diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h index 2ee0ca0709..2d3ce95d00 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h @@ -32,6 +32,11 @@ typedef enum PPC_604r = 0xA, PPC_7400 = 0xC, PPC_405 = 0x2001, + PPC_405EX = 0x1291, /* + 405EXr */ + PPC_405GP = 0x4011, /* + 405CR */ + PPC_405GPr = 0x5091, + PPC_405EZ = 0x4151, + PPC_405EP = 0x5121, PPC_7455 = 0x8001, /* Kate Feng */ PPC_7457 = 0x8002, PPC_620 = 0x16, diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h index 1867ecfbac..02a4544341 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @@ -14,6 +14,9 @@ * D-82178 Puchheim * Germany * rtems@embedded-brains.de + * + * access function for Device Control Registers inspired by "ppc405common.h" + * from Michael Hamel ADInstruments May 2008 * * The license and distribution terms for this file may be found in the file * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. @@ -189,6 +192,7 @@ static inline void ppc_write_word( uint32_t value, volatile void *dest) ); } + static inline void *ppc_stack_pointer() { void *sp; @@ -301,6 +305,8 @@ static inline void ppc_set_decrementer_register( uint32_t dec) PPC_Set_decrementer( dec); } +#define PPC_STRINGOF(x) #x + /* Do not use the following macros. Use the inline functions instead. */ #define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \ @@ -324,6 +330,20 @@ static inline void ppc_set_decrementer_register( uint32_t dec) #define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \ PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) +/* + * PPC4xx have Device Control Registers... + */ +#define PPC_DEVICE_CONTROL_REGISTER(dcr) \ + ({uint32_t val;asm volatile ("mfspr %0," PPC_STRINGOF(dcr) \ + : "=r" (val)); val;}) + +#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr,val) \ + do { \ + asm volatile ("mtspr " PPC_STRINGOF(dcr)",%0" \ + :: "r" (val)); \ + } while (0) + + static inline uint32_t ppc_special_purpose_register_0() { PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0); diff --git a/cpukit/preinstall.am b/cpukit/preinstall.am index 7e13481738..7c5cc69b3f 100644 --- a/cpukit/preinstall.am +++ b/cpukit/preinstall.am @@ -126,6 +126,10 @@ $(PROJECT_INCLUDE)/rtems/tar.h: include/rtems/tar.h $(PROJECT_INCLUDE)/rtems/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/tar.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/tar.h +$(PROJECT_INCLUDE)/rtems/status-checks.h: include/rtems/status-checks.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/status-checks.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/status-checks.h + $(PROJECT_INCLUDE)/rtems/endian.h: include/rtems/endian.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/endian.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/endian.h @@ -134,6 +138,10 @@ $(PROJECT_INCLUDE)/rtems/irq.h: include/rtems/irq.h $(PROJECT_INCLUDE)/rtems/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/irq.h +$(PROJECT_INCLUDE)/rtems/irq-extension.h: include/rtems/irq-extension.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/irq-extension.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/irq-extension.h + $(PROJECT_INCLUDE)/rtems/imfs.h: libfs/src/imfs/imfs.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/imfs.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/imfs.h diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index 431492b5a7..4d83efb6b8 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de> + * rtems/powerpc/registers.h: + + Added PPC405EX support contributed by Michael Hamel + 2008-07-10 Sebastian Huber <sebastian.huber@embedded-brains.de> * rtems/asm.h: Added defines for save and restore registers and diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h index 05d429e239..312dbcc75a 100644 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @@ -292,12 +292,14 @@ lidate */ #define BOOKE_DECAR 54 +#define PPC405_TSR 0x3D8 #define BOOKE_TSR 336 #define BOOKE_TSR_ENW (1<<31) #define BOOKE_TSR_WIS (1<<30) #define BOOKE_TSR_DIS (1<<27) #define BOOKE_TSR_FIS (1<<26) +#define PPC405_TCR 0x3DA #define BOOKE_TCR 340 #define BOOKE_TCR_WP(x) (((x)&3)<<30) #define BOOKE_TCR_WRC(x) (((x)&3)<<28) diff --git a/make/custom/haleakala.cfg b/make/custom/haleakala.cfg new file mode 100644 index 0000000000..a26df72565 --- /dev/null +++ b/make/custom/haleakala.cfg @@ -0,0 +1,30 @@ +# +# Config file for a PowerPC 405 based card +# mhamel +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU=powerpc +RTEMS_CPU_MODEL=ppc405 + +# This is the actual bsp directory used during the build process. +RTEMS_BSP_FAMILY=haleakala + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +# +CPU_CFLAGS = -mcpu=405 -Dppc405 + +# optimize flag: typically -0, could use -O4 or -fast +# -O4 is ok for RTEMS +# NOTE: some level of -O may be actually required by inline assembler +CFLAGS_OPTIMIZE_V = -O1 -g + +# No start file +START_BASE= + +define bsp-post-link + $(default-bsp-post-link) + $(OBJCOPY) -O srec $(basename $@).exe $(basename $@)$(DOWNEXT) +endef |