Remove stray white spaces.

4 files changed, 52 insertions, 52 deletions

diff --git a/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c
index 77f10642a8..11ddae9bf6 100644
--- a/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c
+++ b/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c
@@ -93,7 +93,7 @@ void _CPU_Initialize(
    * Store Msr Value in the IRQ info structure.
    */
    _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
-  
+
 #if (PPC_USE_SPRG)
   i = _CPU_IRQ_info.msr_initial;
   asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
@@ -111,7 +111,7 @@ void _CPU_Initialize(
  *
  *  Complete initialization since the table is now allocated.
  */
- 
+
 void _CPU_Initialize_vectors(void)
 {
   int i;
@@ -126,7 +126,7 @@ void _CPU_Initialize_vectors(void)
     _ISR_Vector_table[i] = handler;
 
 }
- 
+
 /*PAGE
  *
  *  _CPU_ISR_Calculate_level
@@ -137,7 +137,7 @@ void _CPU_Initialize_vectors(void)
  *  is why it was necessary to adopt a scheme which allowed the user
  *  to specify specifically which interrupt sources were enabled.
  */
- 
+
 uint32_t   _CPU_ISR_Calculate_level(
   uint32_t   new_level
 )
@@ -189,7 +189,7 @@ void _CPU_ISR_Set_level(
  *
  *  _CPU_ISR_Get_level
  *
- *  This routine gets the current interrupt level from the MSR and 
+ *  This routine gets the current interrupt level from the MSR and
  *  converts it to an RTEMS interrupt level.
  */
 
@@ -197,9 +197,9 @@ uint32_t   _CPU_ISR_Get_level( void )
 {
   uint32_t   level = 0;
   uint32_t   msr;
- 
+
   asm volatile("mfmsr %0" : "=r" ((msr)));
- 
+
   msr &= PPC_MSR_DISABLE_MASK;
 
   /*
@@ -246,12 +246,12 @@ void _CPU_Context_Initialize(
   sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
   *((uint32_t*)sp) = 0;
   the_context->gpr1 = sp;
-   
+
   the_context->msr = _CPU_ISR_Calculate_level( new_level );
 
   /*
    *  The FP bit of the MSR should only be enabled if this is a floating
-   *  point task.  Unfortunately, the vfprintf_r routine in newlib 
+   *  point task.  Unfortunately, the vfprintf_r routine in newlib
    *  ends up pushing a floating point register regardless of whether or
    *  not a floating point number is being printed.  Serious restructuring
    *  of vfprintf.c will be required to avoid this behavior.  At this
@@ -266,7 +266,7 @@ void _CPU_Context_Initialize(
    *
    *     + Set the exception prefix bit to point to the exception table
    *     + Force the RI bit
-   *     + Use the DR and IR bits 
+   *     + Use the DR and IR bits
    */
   _CPU_MSR_Value( msr_value );
   the_context->msr |= (msr_value & PPC_MSR_EP);
@@ -284,7 +284,7 @@ void _CPU_Context_Initialize(
 #if (PPC_ABI == PPC_ABI_SVR4)
   { unsigned    r13 = 0;
     asm volatile ("mr %0, 13" : "=r" ((r13)));
-   
+
     the_context->pc = (uint32_t)entry_point;
     the_context->gpr13 = r13;
   }
@@ -294,7 +294,7 @@ void _CPU_Context_Initialize(
   { uint32_t    r2 = 0;
     unsigned    r13 = 0;
     asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
- 
+
     the_context->pc = (uint32_t)entry_point;
     the_context->gpr2 = r2;
     the_context->gpr13 = r13;
@@ -335,7 +335,7 @@ void _CPU_ISR_install_vector(
    /*
     * Install the wrapper so this ISR can be invoked properly.
     */
-   if (_CPU_Table.exceptions_in_RAM) 
+   if (_CPU_Table.exceptions_in_RAM)
       _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
 
    /*
@@ -344,7 +344,7 @@ void _CPU_ISR_install_vector(
     */
 
     _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
-       _CPU_Table.spurious_handler ? 
+       _CPU_Table.spurious_handler ?
           (ISR_Handler_entry)_CPU_Table.spurious_handler :
           (ISR_Handler_entry)ppc_spurious;
 }
@@ -440,7 +440,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
 };
 #endif /* mpc860 */
 
-uint32_t    ppc_exception_vector_addr( 
+uint32_t    ppc_exception_vector_addr(
   uint32_t   vector
 );
 
@@ -453,24 +453,24 @@ uint32_t    ppc_exception_vector_addr(
  *  supported trap handler (a.k.a. interrupt service routine).
  *
  *  Input Parameters:
- *    vector      - trap table entry number plus synchronous 
+ *    vector      - trap table entry number plus synchronous
  *                    vs. asynchronous information
  *    new_handler - address of the handler to be installed
  *    old_handler - pointer to an address of the handler previously installed
  *
  *  Output Parameters: NONE
  *    *new_handler - address of the handler previously installed
- * 
- *  NOTE: 
+ *
+ *  NOTE:
  *
  *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
- *  Install a software trap handler as an executive interrupt handler 
+ *  Install a software trap handler as an executive interrupt handler
  *  (which is desirable since RTEMS takes care of window and register issues),
- *  then the executive needs to know that the return address is to the trap 
+ *  then the executive needs to know that the return address is to the trap
  *  rather than the instruction following the trap.
  *
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
@@ -506,8 +506,8 @@ void _CPU_ISR_install_raw_handler(
 #define LOW_BITS_MASK    0x000003FF
 
   if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
-    /* 
-     * Set u32_handler = to target address  
+    /*
+     * Set u32_handler = to target address
      */
     u32_handler = slot->b_Handler & 0x03fffffc;
 
@@ -518,15 +518,15 @@ void _CPU_ISR_install_raw_handler(
 
     *old_handler =  (proc_ptr) u32_handler;
   } else
-/* There are two kinds of handlers for the MPC860. One is the 'standard' 
+/* There are two kinds of handlers for the MPC860. One is the 'standard'
  *  one like above. The other is for the cascaded interrupts from the SIU
  *  and CPM. Therefore we must check for the alternate one if the standard
  *  one is not present
  */
 #if defined(mpc860) || defined(mpc821)
   if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
-    /* 
-     * Set u32_handler = to target address  
+    /*
+     * Set u32_handler = to target address
      */
     u32_handler = slot->b_Handler & 0x03fffffc;
     *old_handler =  (proc_ptr) u32_handler;
@@ -547,9 +547,9 @@ void _CPU_ISR_install_raw_handler(
 
   u32_handler = (uint32_t) new_handler;
 
-  /* 
-   * IMD FIX: insert address fragment only (bits 6..29) 
-   *          therefore check for proper address range 
+  /*
+   * IMD FIX: insert address fragment only (bits 6..29)
+   *          therefore check for proper address range
    *          and remove unwanted bits
    */
   if ((u32_handler & 0xfc000000) == 0xfc000000) {
@@ -568,7 +568,7 @@ void _CPU_ISR_install_raw_handler(
   _CPU_Data_Cache_Block_Flush( slot );
 }
 
-uint32_t    ppc_exception_vector_addr( 
+uint32_t    ppc_exception_vector_addr(
   uint32_t   vector
 )
 {
@@ -632,7 +632,7 @@ uint32_t    ppc_exception_vector_addr(
       break;
 
 #if defined(ppc403) || defined(ppc405)
-                                  
+
 /*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
     case PPC_IRQ_CRIT:
       Offset = 0x00100;
diff --git a/c/src/lib/libcpu/powerpc/old-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/old-exceptions/cpu_asm.S
index 1aed87b6ac..cd35eb02af 100644
--- a/c/src/lib/libcpu/powerpc/old-exceptions/cpu_asm.S
+++ b/c/src/lib/libcpu/powerpc/old-exceptions/cpu_asm.S
@@ -38,7 +38,7 @@
 
 #include <rtems/asm.h>
 #include <rtems/score/ppc_offs.h>
-	
+
 	BEGIN_CODE
 /*
  *  _CPU_Context_save_fp_context
@@ -365,7 +365,7 @@ PROC (_CPU_Context_switch):
 	stw	r7, GP_PC-GP_26(r3)
 	mfmsr	r8
 	stw	r8, GP_MSR-GP_26(r3)
-	
+
 #if ( PPC_USE_DATA_CACHE )
 	dcbt	r5, r4
 #endif
diff --git a/c/src/lib/libcpu/powerpc/old-exceptions/irq_stub.S b/c/src/lib/libcpu/powerpc/old-exceptions/irq_stub.S
index 71c6332a41..6a0dd00342 100644
--- a/c/src/lib/libcpu/powerpc/old-exceptions/irq_stub.S
+++ b/c/src/lib/libcpu/powerpc/old-exceptions/irq_stub.S
@@ -74,7 +74,7 @@
 	slwi	r4,r0,2
 	lwz	r28, Nest_level(r11)
 	add	r4, r4, r30
-	
+
 	lwz	r30, 0(r28)
 	mr	r3, r0
 	lwz	r31, Stack(r11)
@@ -86,14 +86,14 @@
    */
 	/* Switch stacks, here we must prevent ALL interrupts */
 #if (PPC_USE_SPRG)
-	mfmsr	r5          
-	mfspr   r6, sprg2   
-#else	
+	mfmsr	r5
+	mfspr   r6, sprg2
+#else
         lwz	r6,msr_initial(r11)
 	lis     r5,~PPC_MSR_DISABLE_MASK@ha
         ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
 	and	r6,r6,r5
-	mfmsr	r5          
+	mfmsr	r5
 #endif
 	mtmsr	r6
 	cmpwi	r30, 0
@@ -154,10 +154,10 @@ LABEL (nested):
 	/*	We must re-disable the interrupts */
 #if (PPC_USE_SPRG)
 	mfspr	r11, sprg3
-	mfspr	r0, sprg2  
+	mfspr	r0, sprg2
 #else
 	lis     r11,_CPU_IRQ_info@ha
-	addi	r11,r11,_CPU_IRQ_info@l	
+	addi	r11,r11,_CPU_IRQ_info@l
         lwz	r0,msr_initial(r11)
 	lis     r30,~PPC_MSR_DISABLE_MASK@ha
         ori     r30,r30,~PPC_MSR_DISABLE_MASK@l
@@ -190,8 +190,8 @@ LABEL (nested):
 	bne	LABEL (easy_exit)
 	lwz	r30, 0(r30)
 	lwz	r31, Signal(r11)
-	
-  /*  
+
+  /*
    *  if ( _Context_Switch_necessary )
    *    goto switch
    */
@@ -199,7 +199,7 @@ LABEL (nested):
 	lwz	r28, 0(r31)
 	li	r6,0
 	bne	LABEL (switch)
-  /*  
+  /*
    *  if ( !_ISR_Signals_to_thread_executing )
    *    goto easy_exit
    *  _ISR_Signals_to_thread_executing = 0;
@@ -232,14 +232,14 @@ LABEL (switch):
 	mfspr   r0, sprg2
 #else
 	lis     r11,_CPU_IRQ_info@ha
-	addi	r11,r11,_CPU_IRQ_info@l	
+	addi	r11,r11,_CPU_IRQ_info@l
         lwz	r0,msr_initial(r11)
 	lis     r5,~PPC_MSR_DISABLE_MASK@ha
         ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
 	and	r0,r0,r5
 #endif
 	mtmsr   r0
-	
+
   /*
    *  easy_exit:
    *  prepare to get out of interrupt
diff --git a/c/src/lib/libcpu/powerpc/old-exceptions/rtems/score/ppc_offs.h b/c/src/lib/libcpu/powerpc/old-exceptions/rtems/score/ppc_offs.h
index d319107aaa..05a4fddb8f 100644
--- a/c/src/lib/libcpu/powerpc/old-exceptions/rtems/score/ppc_offs.h
+++ b/c/src/lib/libcpu/powerpc/old-exceptions/rtems/score/ppc_offs.h
@@ -104,7 +104,7 @@
 	.set	FP_31, (FP_30 + 4)
 	.set	FP_FPSCR, (FP_31 + 4)
 #endif
-	
+
 	.set	IP_LINK, 0
 #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
 	.set	IP_0, (IP_LINK + 56)
@@ -117,12 +117,12 @@
 	.set	IP_4, (IP_3 + 4)
 	.set	IP_5, (IP_4 + 4)
 	.set	IP_6, (IP_5 + 4)
-	
+
 	.set	IP_7, (IP_6 + 4)
 	.set	IP_8, (IP_7 + 4)
 	.set	IP_9, (IP_8 + 4)
 	.set	IP_10, (IP_9 + 4)
-	
+
 	.set	IP_11, (IP_10 + 4)
 	.set	IP_12, (IP_11 + 4)
 	.set	IP_13, (IP_12 + 4)
@@ -132,15 +132,15 @@
 	.set	IP_30, (IP_29 + 4)
 	.set	IP_31, (IP_30 + 4)
 	.set	IP_CR, (IP_31 + 4)
-	
+
 	.set	IP_CTR, (IP_CR + 4)
 	.set	IP_XER, (IP_CTR + 4)
 	.set	IP_LR, (IP_XER + 4)
 	.set	IP_PC, (IP_LR + 4)
-	
+
 	.set	IP_MSR, (IP_PC + 4)
 	.set	IP_END, (IP_MSR + 16)
-	
+
 	/* _CPU_IRQ_info offsets */
 
 	/* These must be in this order */
@@ -162,5 +162,5 @@
 #endif
 	.set	Signal, Switch_necessary + 4
         .set    msr_initial, Signal + 4
-	
+
 #endif  /* __PPC_OFFS_H */