Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier

<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:

  + BSPs for many variations on the Motorola MBX8xx board series
  + Cache Manager including initial support for m68040
    and PowerPC
  + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
    same code base.
  + Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

1 files changed, 34 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c
new file mode 100644
index 0000000000..235e4bafc3
--- /dev/null
+++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c
@@ -0,0 +1,34 @@
+/*
+ * cp.c
+ *
+ * MPC8xx CPM RISC Communication Processor routines.
+ * 
+ * Based on code (alloc860.c in eth_comm port) by
+ * Jay Monkman (jmonkman@frasca.com),
+ * which, in turn, is based on code by
+ * W. Eric Norum (eric@skatter.usask.ca).
+ *
+ * Modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
+ * Copyright (c) 1999, National Research Council of Canada
+ */
+
+#include <bsp.h>
+#include <rtems/rtems/intr.h>
+#include <rtems/error.h>
+
+/*
+ * Send a command to the CPM RISC processer
+ */
+void m8xx_cp_execute_cmd( unsigned16 command )
+{
+  rtems_unsigned16 lvl;
+  
+  rtems_interrupt_disable(lvl);
+  while (m8xx.cpcr & M8xx_CR_FLG) {
+    continue;
+  }
+
+  m8xx.cpcr = command | M8xx_CR_FLG;
+  rtems_interrupt_enable (lvl);
+}
+