From 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 12 Jun 2000 19:57:02 +0000 Subject: Patch from John Cotton , Charles-Antoine Gauthier , and Darlene A. Stewart to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860 --- c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c (limited to 'c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c') diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c new file mode 100644 index 0000000000..235e4bafc3 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c @@ -0,0 +1,34 @@ +/* + * cp.c + * + * MPC8xx CPM RISC Communication Processor routines. + * + * Based on code (alloc860.c in eth_comm port) by + * Jay Monkman (jmonkman@frasca.com), + * which, in turn, is based on code by + * W. Eric Norum (eric@skatter.usask.ca). + * + * Modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca): + * Copyright (c) 1999, National Research Council of Canada + */ + +#include +#include +#include + +/* + * Send a command to the CPM RISC processer + */ +void m8xx_cp_execute_cmd( unsigned16 command ) +{ + rtems_unsigned16 lvl; + + rtems_interrupt_disable(lvl); + while (m8xx.cpcr & M8xx_CR_FLG) { + continue; + } + + m8xx.cpcr = command | M8xx_CR_FLG; + rtems_interrupt_enable (lvl); +} + -- cgit v1.2.3